1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
17 #include "StatepointLowering.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 #include "llvm/IR/CallSite.h"
24 #include "llvm/IR/Statepoint.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Target/TargetLowering.h"
32 class AddrSpaceCastInst;
40 class ExtractElementInst;
41 class ExtractValueInst;
48 class FunctionLoweringInfo;
49 class GetElementPtrInst;
55 class InsertElementInst;
56 class InsertValueInst;
59 class MachineBasicBlock;
61 class MachineRegisterInfo;
70 class ShuffleVectorInst;
75 class TargetLibraryInfo;
79 class UnreachableInst;
83 //===----------------------------------------------------------------------===//
84 /// SelectionDAGBuilder - This is the common target-independent lowering
85 /// implementation that is parameterized by a TargetLowering object.
87 class SelectionDAGBuilder {
88 /// CurInst - The current instruction being visited
89 const Instruction *CurInst;
91 DenseMap<const Value*, SDValue> NodeMap;
93 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
94 /// to preserve debug information for incoming arguments.
95 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
97 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
98 class DanglingDebugInfo {
99 const DbgValueInst* DI;
101 unsigned SDNodeOrder;
103 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
104 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
105 DI(di), dl(DL), SDNodeOrder(SDNO) { }
106 const DbgValueInst* getDI() { return DI; }
107 DebugLoc getdl() { return dl; }
108 unsigned getSDNodeOrder() { return SDNodeOrder; }
111 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
112 /// yet seen the referent. We defer handling these until we do see it.
113 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
116 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
117 /// them up and then emit token factor nodes when possible. This allows us to
118 /// get simple disambiguation between loads without worrying about alias
120 SmallVector<SDValue, 8> PendingLoads;
122 /// State used while lowering a statepoint sequence (gc_statepoint,
123 /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
124 StatepointLoweringState StatepointLowering;
127 /// PendingExports - CopyToReg nodes that copy values to virtual registers
128 /// for export to other blocks need to be emitted before any terminator
129 /// instruction, but they have no other ordering requirements. We bunch them
130 /// up and the emit a single tokenfactor for them just before terminator
132 SmallVector<SDValue, 8> PendingExports;
134 /// SDNodeOrder - A unique monotonically increasing number used to order the
135 /// SDNodes we create.
136 unsigned SDNodeOrder;
138 enum CaseClusterKind {
139 /// A cluster of adjacent case labels with the same destination, or just one
142 /// A cluster of cases suitable for jump table lowering.
144 /// A cluster of cases suitable for bit test lowering.
148 /// A cluster of case labels.
150 CaseClusterKind Kind;
151 const ConstantInt *Low, *High;
153 MachineBasicBlock *MBB;
154 unsigned JTCasesIndex;
155 unsigned BTCasesIndex;
159 static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
160 MachineBasicBlock *MBB, uint32_t Weight) {
170 static CaseCluster jumpTable(const ConstantInt *Low,
171 const ConstantInt *High, unsigned JTCasesIndex,
174 C.Kind = CC_JumpTable;
177 C.JTCasesIndex = JTCasesIndex;
182 static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
183 unsigned BTCasesIndex, uint32_t Weight) {
185 C.Kind = CC_BitTests;
188 C.BTCasesIndex = BTCasesIndex;
194 typedef std::vector<CaseCluster> CaseClusterVector;
195 typedef CaseClusterVector::iterator CaseClusterIt;
199 MachineBasicBlock* BB;
201 uint32_t ExtraWeight;
203 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
205 Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
207 CaseBits() : Mask(0), BB(nullptr), Bits(0), ExtraWeight(0) {}
210 typedef std::vector<CaseBits> CaseBitsVector;
212 /// Sort Clusters and merge adjacent cases.
213 void sortAndRangeify(CaseClusterVector &Clusters);
215 /// CaseBlock - This structure is used to communicate between
216 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
217 /// blocks needed by multi-case switch statements.
219 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
220 const Value *cmpmiddle,
221 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
222 MachineBasicBlock *me,
223 uint32_t trueweight = 0, uint32_t falseweight = 0)
224 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
225 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
226 TrueWeight(trueweight), FalseWeight(falseweight) { }
228 // CC - the condition code to use for the case block's setcc node
231 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
232 // Emit by default LHS op RHS. MHS is used for range comparisons:
233 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
234 const Value *CmpLHS, *CmpMHS, *CmpRHS;
236 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
237 MachineBasicBlock *TrueBB, *FalseBB;
239 // ThisBB - the block into which to emit the code for the setcc and branches
240 MachineBasicBlock *ThisBB;
242 // TrueWeight/FalseWeight - branch weights.
243 uint32_t TrueWeight, FalseWeight;
247 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
248 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
250 /// Reg - the virtual register containing the index of the jump table entry
253 /// JTI - the JumpTableIndex for this jump table in the function.
255 /// MBB - the MBB into which to emit the code for the indirect jump.
256 MachineBasicBlock *MBB;
257 /// Default - the MBB of the default bb, which is a successor of the range
258 /// check MBB. This is when updating PHI nodes in successors.
259 MachineBasicBlock *Default;
261 struct JumpTableHeader {
262 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
264 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
268 MachineBasicBlock *HeaderBB;
271 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
274 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
276 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
278 MachineBasicBlock *ThisBB;
279 MachineBasicBlock *TargetBB;
280 uint32_t ExtraWeight;
283 typedef SmallVector<BitTestCase, 3> BitTestInfo;
285 struct BitTestBlock {
286 BitTestBlock(APInt F, APInt R, const Value* SV,
287 unsigned Rg, MVT RgVT, bool E, bool CR,
288 MachineBasicBlock* P, MachineBasicBlock* D,
290 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
291 ContiguousRange(CR), Parent(P), Default(D), Cases(std::move(C)) { }
298 bool ContiguousRange;
299 MachineBasicBlock *Parent;
300 MachineBasicBlock *Default;
304 /// Minimum jump table density, in percent.
305 enum { MinJumpTableDensity = 40 };
307 /// Check whether a range of clusters is dense enough for a jump table.
308 bool isDense(const CaseClusterVector &Clusters, unsigned *TotalCases,
309 unsigned First, unsigned Last);
311 /// Build a jump table cluster from Clusters[First..Last]. Returns false if it
312 /// decides it's not a good idea.
313 bool buildJumpTable(CaseClusterVector &Clusters, unsigned First,
314 unsigned Last, const SwitchInst *SI,
315 MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
317 /// Find clusters of cases suitable for jump table lowering.
318 void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
319 MachineBasicBlock *DefaultMBB);
321 /// Check whether the range [Low,High] fits in a machine word.
322 bool rangeFitsInWord(const APInt &Low, const APInt &High);
324 /// Check whether these clusters are suitable for lowering with bit tests based
325 /// on the number of destinations, comparison metric, and range.
326 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
327 const APInt &Low, const APInt &High);
329 /// Build a bit test cluster from Clusters[First..Last]. Returns false if it
330 /// decides it's not a good idea.
331 bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
332 const SwitchInst *SI, CaseCluster &BTCluster);
334 /// Find clusters of cases suitable for bit test lowering.
335 void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
337 struct SwitchWorkListItem {
338 MachineBasicBlock *MBB;
339 CaseClusterIt FirstCluster;
340 CaseClusterIt LastCluster;
341 const ConstantInt *GE;
342 const ConstantInt *LT;
344 typedef SmallVector<SwitchWorkListItem, 4> SwitchWorkList;
346 /// Determine the rank by weight of CC in [First,Last]. If CC has more weight
347 /// than each cluster in the range, its rank is 0.
348 static unsigned caseClusterRank(const CaseCluster &CC, CaseClusterIt First,
351 /// Emit comparison and split W into two subtrees.
352 void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
353 Value *Cond, MachineBasicBlock *SwitchMBB);
356 void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
357 MachineBasicBlock *SwitchMBB,
358 MachineBasicBlock *DefaultMBB);
361 /// A class which encapsulates all of the information needed to generate a
362 /// stack protector check and signals to isel via its state being initialized
363 /// that a stack protector needs to be generated.
365 /// *NOTE* The following is a high level documentation of SelectionDAG Stack
366 /// Protector Generation. The reason that it is placed here is for a lack of
367 /// other good places to stick it.
369 /// High Level Overview of SelectionDAG Stack Protector Generation:
371 /// Previously, generation of stack protectors was done exclusively in the
372 /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
373 /// splitting basic blocks at the IR level to create the success/failure basic
374 /// blocks in the tail of the basic block in question. As a result of this,
375 /// calls that would have qualified for the sibling call optimization were no
376 /// longer eligible for optimization since said calls were no longer right in
377 /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
380 /// Then it was noticed that since the sibling call optimization causes the
381 /// callee to reuse the caller's stack, if we could delay the generation of
382 /// the stack protector check until later in CodeGen after the sibling call
383 /// decision was made, we get both the tail call optimization and the stack
386 /// A few goals in solving this problem were:
388 /// 1. Preserve the architecture independence of stack protector generation.
390 /// 2. Preserve the normal IR level stack protector check for platforms like
391 /// OpenBSD for which we support platform-specific stack protector
394 /// The main problem that guided the present solution is that one can not
395 /// solve this problem in an architecture independent manner at the IR level
396 /// only. This is because:
398 /// 1. The decision on whether or not to perform a sibling call on certain
399 /// platforms (for instance i386) requires lower level information
400 /// related to available registers that can not be known at the IR level.
402 /// 2. Even if the previous point were not true, the decision on whether to
403 /// perform a tail call is done in LowerCallTo in SelectionDAG which
404 /// occurs after the Stack Protector Pass. As a result, one would need to
405 /// put the relevant callinst into the stack protector check success
406 /// basic block (where the return inst is placed) and then move it back
407 /// later at SelectionDAG/MI time before the stack protector check if the
408 /// tail call optimization failed. The MI level option was nixed
409 /// immediately since it would require platform-specific pattern
410 /// matching. The SelectionDAG level option was nixed because
411 /// SelectionDAG only processes one IR level basic block at a time
412 /// implying one could not create a DAG Combine to move the callinst.
414 /// To get around this problem a few things were realized:
416 /// 1. While one can not handle multiple IR level basic blocks at the
417 /// SelectionDAG Level, one can generate multiple machine basic blocks
418 /// for one IR level basic block. This is how we handle bit tests and
421 /// 2. At the MI level, tail calls are represented via a special return
422 /// MIInst called "tcreturn". Thus if we know the basic block in which we
423 /// wish to insert the stack protector check, we get the correct behavior
424 /// by always inserting the stack protector check right before the return
425 /// statement. This is a "magical transformation" since no matter where
426 /// the stack protector check intrinsic is, we always insert the stack
427 /// protector check code at the end of the BB.
429 /// Given the aforementioned constraints, the following solution was devised:
431 /// 1. On platforms that do not support SelectionDAG stack protector check
432 /// generation, allow for the normal IR level stack protector check
433 /// generation to continue.
435 /// 2. On platforms that do support SelectionDAG stack protector check
438 /// a. Use the IR level stack protector pass to decide if a stack
439 /// protector is required/which BB we insert the stack protector check
440 /// in by reusing the logic already therein. If we wish to generate a
441 /// stack protector check in a basic block, we place a special IR
442 /// intrinsic called llvm.stackprotectorcheck right before the BB's
443 /// returninst or if there is a callinst that could potentially be
444 /// sibling call optimized, before the call inst.
446 /// b. Then when a BB with said intrinsic is processed, we codegen the BB
447 /// normally via SelectBasicBlock. In said process, when we visit the
448 /// stack protector check, we do not actually emit anything into the
449 /// BB. Instead, we just initialize the stack protector descriptor
450 /// class (which involves stashing information/creating the success
451 /// mbbb and the failure mbb if we have not created one for this
452 /// function yet) and export the guard variable that we are going to
455 /// c. After we finish selecting the basic block, in FinishBasicBlock if
456 /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
457 /// initialized, we first find a splice point in the parent basic block
458 /// before the terminator and then splice the terminator of said basic
459 /// block into the success basic block. Then we code-gen a new tail for
460 /// the parent basic block consisting of the two loads, the comparison,
461 /// and finally two branches to the success/failure basic blocks. We
462 /// conclude by code-gening the failure basic block if we have not
463 /// code-gened it already (all stack protector checks we generate in
464 /// the same function, use the same failure basic block).
465 class StackProtectorDescriptor {
467 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
468 FailureMBB(nullptr), Guard(nullptr),
471 /// Returns true if all fields of the stack protector descriptor are
472 /// initialized implying that we should/are ready to emit a stack protector.
473 bool shouldEmitStackProtector() const {
474 return ParentMBB && SuccessMBB && FailureMBB && Guard;
477 /// Initialize the stack protector descriptor structure for a new basic
479 void initialize(const BasicBlock *BB,
480 MachineBasicBlock *MBB,
481 const CallInst &StackProtCheckCall) {
482 // Make sure we are not initialized yet.
483 assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
484 "already initialized!");
486 SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
487 FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
489 Guard = StackProtCheckCall.getArgOperand(0);
492 /// Reset state that changes when we handle different basic blocks.
494 /// This currently includes:
496 /// 1. The specific basic block we are generating a
497 /// stack protector for (ParentMBB).
499 /// 2. The successor machine basic block that will contain the tail of
500 /// parent mbb after we create the stack protector check (SuccessMBB). This
501 /// BB is visited only on stack protector check success.
502 void resetPerBBState() {
504 SuccessMBB = nullptr;
507 /// Reset state that only changes when we switch functions.
509 /// This currently includes:
511 /// 1. FailureMBB since we reuse the failure code path for all stack
512 /// protector checks created in an individual function.
514 /// 2.The guard variable since the guard variable we are checking against is
516 void resetPerFunctionState() {
517 FailureMBB = nullptr;
522 MachineBasicBlock *getParentMBB() { return ParentMBB; }
523 MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
524 MachineBasicBlock *getFailureMBB() { return FailureMBB; }
525 const Value *getGuard() { return Guard; }
527 unsigned getGuardReg() const { return GuardReg; }
528 void setGuardReg(unsigned R) { GuardReg = R; }
531 /// The basic block for which we are generating the stack protector.
533 /// As a result of stack protector generation, we will splice the
534 /// terminators of this basic block into the successor mbb SuccessMBB and
535 /// replace it with a compare/branch to the successor mbbs
536 /// SuccessMBB/FailureMBB depending on whether or not the stack protector
538 MachineBasicBlock *ParentMBB;
540 /// A basic block visited on stack protector check success that contains the
541 /// terminators of ParentMBB.
542 MachineBasicBlock *SuccessMBB;
544 /// This basic block visited on stack protector check failure that will
545 /// contain a call to __stack_chk_fail().
546 MachineBasicBlock *FailureMBB;
548 /// The guard variable which we will compare against the stored value in the
549 /// stack protector stack slot.
552 /// The virtual register holding the stack guard value.
555 /// Add a successor machine basic block to ParentMBB. If the successor mbb
556 /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
557 /// block will be created. Assign a large weight if IsLikely is true.
558 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
559 MachineBasicBlock *ParentMBB,
561 MachineBasicBlock *SuccMBB = nullptr);
565 const TargetMachine &TM;
567 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
568 /// nodes without a corresponding SDNode.
569 static const unsigned LowestSDNodeOrder = 1;
572 const DataLayout *DL;
574 const TargetLibraryInfo *LibInfo;
576 /// SwitchCases - Vector of CaseBlock structures used to communicate
577 /// SwitchInst code generation information.
578 std::vector<CaseBlock> SwitchCases;
579 /// JTCases - Vector of JumpTable structures used to communicate
580 /// SwitchInst code generation information.
581 std::vector<JumpTableBlock> JTCases;
582 /// BitTestCases - Vector of BitTestBlock structures used to communicate
583 /// SwitchInst code generation information.
584 std::vector<BitTestBlock> BitTestCases;
585 /// A StackProtectorDescriptor structure used to communicate stack protector
586 /// information in between SelectBasicBlock and FinishBasicBlock.
587 StackProtectorDescriptor SPDescriptor;
589 // Emit PHI-node-operand constants only once even if used by multiple
591 DenseMap<const Constant *, unsigned> ConstantsOut;
593 /// FuncInfo - Information about the function as a whole.
595 FunctionLoweringInfo &FuncInfo;
597 /// OptLevel - What optimization level we're generating code for.
599 CodeGenOpt::Level OptLevel;
601 /// GFI - Garbage collection metadata for the function.
604 /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
605 DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
607 /// HasTailCall - This is set to true if a call in the current
608 /// block has been translated as a tail call. In this case,
609 /// no subsequent DAG nodes should be created.
613 LLVMContext *Context;
615 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
616 CodeGenOpt::Level ol)
617 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
618 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
622 void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
623 const TargetLibraryInfo *li);
625 /// clear - Clear out the current SelectionDAG and the associated
626 /// state and prepare this SelectionDAGBuilder object to be used
627 /// for a new block. This doesn't clear out information about
628 /// additional blocks that are needed to complete switch lowering
629 /// or PHI node updating; that information is cleared out as it is
633 /// clearDanglingDebugInfo - Clear the dangling debug information
634 /// map. This function is separated from the clear so that debug
635 /// information that is dangling in a basic block can be properly
636 /// resolved in a different basic block. This allows the
637 /// SelectionDAG to resolve dangling debug information attached
639 void clearDanglingDebugInfo();
641 /// getRoot - Return the current virtual root of the Selection DAG,
642 /// flushing any PendingLoad items. This must be done before emitting
643 /// a store or any other node that may need to be ordered after any
644 /// prior load instructions.
648 /// getControlRoot - Similar to getRoot, but instead of flushing all the
649 /// PendingLoad items, flush all the PendingExports items. It is necessary
650 /// to do this before emitting a terminator instruction.
652 SDValue getControlRoot();
654 SDLoc getCurSDLoc() const {
655 return SDLoc(CurInst, SDNodeOrder);
658 DebugLoc getCurDebugLoc() const {
659 return CurInst ? CurInst->getDebugLoc() : DebugLoc();
662 unsigned getSDNodeOrder() const { return SDNodeOrder; }
664 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
666 void visit(const Instruction &I);
668 void visit(unsigned Opcode, const User &I);
670 /// getCopyFromRegs - If there was virtual register allocated for the value V
671 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
672 SDValue getCopyFromRegs(const Value *V, Type *Ty);
674 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
675 // generate the debug data structures now that we've seen its definition.
676 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
677 SDValue getValue(const Value *V);
678 bool findValue(const Value *V) const;
680 SDValue getNonRegisterValue(const Value *V);
681 SDValue getValueImpl(const Value *V);
683 void setValue(const Value *V, SDValue NewN) {
684 SDValue &N = NodeMap[V];
685 assert(!N.getNode() && "Already set a value for this node!");
689 void setUnusedArgValue(const Value *V, SDValue NewN) {
690 SDValue &N = UnusedArgNodeMap[V];
691 assert(!N.getNode() && "Already set a value for this node!");
695 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
696 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
697 MachineBasicBlock *SwitchBB,
698 Instruction::BinaryOps Opc,
699 uint32_t TW, uint32_t FW);
700 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
701 MachineBasicBlock *FBB,
702 MachineBasicBlock *CurBB,
703 MachineBasicBlock *SwitchBB,
704 uint32_t TW, uint32_t FW);
705 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
706 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
707 void CopyToExportRegsIfNeeded(const Value *V);
708 void ExportFromCurrentBlock(const Value *V);
709 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
710 MachineBasicBlock *LandingPad = nullptr);
712 std::pair<SDValue, SDValue> lowerCallOperands(
713 ImmutableCallSite CS,
718 MachineBasicBlock *LandingPad = nullptr,
719 bool IsPatchPoint = false);
721 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
722 /// references that need to refer to the last resulting block.
723 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
725 // This function is responsible for the whole statepoint lowering process.
726 // It uniformly handles invoke and call statepoints.
727 void LowerStatepoint(ImmutableStatepoint Statepoint,
728 MachineBasicBlock *LandingPad = nullptr);
730 std::pair<SDValue, SDValue> lowerInvokable(
731 TargetLowering::CallLoweringInfo &CLI,
732 MachineBasicBlock *LandingPad);
734 // Terminator instructions.
735 void visitRet(const ReturnInst &I);
736 void visitBr(const BranchInst &I);
737 void visitSwitch(const SwitchInst &I);
738 void visitIndirectBr(const IndirectBrInst &I);
739 void visitUnreachable(const UnreachableInst &I);
740 void visitCleanupRet(const CleanupReturnInst &I);
741 void visitCatchEndPad(const CatchEndPadInst &I);
742 void visitCatchRet(const CatchReturnInst &I);
743 void visitCatchPad(const CatchPadInst &I);
744 void visitTerminatePad(const TerminatePadInst &TPI);
745 void visitCleanupPad(const CleanupPadInst &CPI);
747 uint32_t getEdgeWeight(const MachineBasicBlock *Src,
748 const MachineBasicBlock *Dst) const;
749 void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
750 uint32_t Weight = 0);
752 void visitSwitchCase(CaseBlock &CB,
753 MachineBasicBlock *SwitchBB);
754 void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
755 MachineBasicBlock *ParentBB);
756 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
757 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
758 void visitBitTestCase(BitTestBlock &BB,
759 MachineBasicBlock* NextMBB,
760 uint32_t BranchWeightToNext,
763 MachineBasicBlock *SwitchBB);
764 void visitJumpTable(JumpTable &JT);
765 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
766 MachineBasicBlock *SwitchBB);
769 // These all get lowered before this pass.
770 void visitInvoke(const InvokeInst &I);
771 void visitResume(const ResumeInst &I);
773 void visitBinary(const User &I, unsigned OpCode);
774 void visitShift(const User &I, unsigned Opcode);
775 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
776 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
777 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
778 void visitFSub(const User &I);
779 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
780 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
781 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
782 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
783 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
784 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
785 void visitSDiv(const User &I);
786 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
787 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
788 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
789 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
790 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
791 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
792 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
793 void visitICmp(const User &I);
794 void visitFCmp(const User &I);
795 // Visit the conversion instructions
796 void visitTrunc(const User &I);
797 void visitZExt(const User &I);
798 void visitSExt(const User &I);
799 void visitFPTrunc(const User &I);
800 void visitFPExt(const User &I);
801 void visitFPToUI(const User &I);
802 void visitFPToSI(const User &I);
803 void visitUIToFP(const User &I);
804 void visitSIToFP(const User &I);
805 void visitPtrToInt(const User &I);
806 void visitIntToPtr(const User &I);
807 void visitBitCast(const User &I);
808 void visitAddrSpaceCast(const User &I);
810 void visitExtractElement(const User &I);
811 void visitInsertElement(const User &I);
812 void visitShuffleVector(const User &I);
814 void visitExtractValue(const ExtractValueInst &I);
815 void visitInsertValue(const InsertValueInst &I);
816 void visitLandingPad(const LandingPadInst &I);
818 void visitGetElementPtr(const User &I);
819 void visitSelect(const User &I);
821 void visitAlloca(const AllocaInst &I);
822 void visitLoad(const LoadInst &I);
823 void visitStore(const StoreInst &I);
824 void visitMaskedLoad(const CallInst &I);
825 void visitMaskedStore(const CallInst &I);
826 void visitMaskedGather(const CallInst &I);
827 void visitMaskedScatter(const CallInst &I);
828 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
829 void visitAtomicRMW(const AtomicRMWInst &I);
830 void visitFence(const FenceInst &I);
831 void visitPHI(const PHINode &I);
832 void visitCall(const CallInst &I);
833 bool visitMemCmpCall(const CallInst &I);
834 bool visitMemChrCall(const CallInst &I);
835 bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
836 bool visitStrCmpCall(const CallInst &I);
837 bool visitStrLenCall(const CallInst &I);
838 bool visitStrNLenCall(const CallInst &I);
839 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
840 bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
841 void visitAtomicLoad(const LoadInst &I);
842 void visitAtomicStore(const StoreInst &I);
844 void visitInlineAsm(ImmutableCallSite CS);
845 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
846 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
848 void visitVAStart(const CallInst &I);
849 void visitVAArg(const VAArgInst &I);
850 void visitVAEnd(const CallInst &I);
851 void visitVACopy(const CallInst &I);
852 void visitStackmap(const CallInst &I);
853 void visitPatchpoint(ImmutableCallSite CS,
854 MachineBasicBlock *LandingPad = nullptr);
856 // These three are implemented in StatepointLowering.cpp
857 void visitStatepoint(const CallInst &I);
858 void visitGCRelocate(const CallInst &I);
859 void visitGCResult(const CallInst &I);
861 void visitUserOp1(const Instruction &I) {
862 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
864 void visitUserOp2(const Instruction &I) {
865 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
868 void processIntegerCallValue(const Instruction &I,
869 SDValue Value, bool IsSigned);
871 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
873 /// EmitFuncArgumentDbgValue - If V is an function argument then create
874 /// corresponding DBG_VALUE machine instruction for it now. At the end of
875 /// instruction selection, they will be inserted to the entry BB.
876 bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
877 DIExpression *Expr, DILocation *DL,
878 int64_t Offset, bool IsIndirect,
881 /// Return the next block after MBB, or nullptr if there is none.
882 MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
884 /// Update the DAG and DAG builder with the relevant information after
885 /// a new root node has been created which could be a tail call.
886 void updateDAGForMaybeTailCall(SDValue MaybeTC);
889 /// RegsForValue - This struct represents the registers (physical or virtual)
890 /// that a particular set of values is assigned, and the type information about
891 /// the value. The most common situation is to represent one value at a time,
892 /// but struct or array values are handled element-wise as multiple values. The
893 /// splitting of aggregates is performed recursively, so that we never have
894 /// aggregate-typed registers. The values at this point do not necessarily have
895 /// legal types, so each value may require one or more registers of some legal
898 struct RegsForValue {
899 /// ValueVTs - The value types of the values, which may not be legal, and
900 /// may need be promoted or synthesized from one or more registers.
902 SmallVector<EVT, 4> ValueVTs;
904 /// RegVTs - The value types of the registers. This is the same size as
905 /// ValueVTs and it records, for each value, what the type of the assigned
906 /// register or registers are. (Individual values are never synthesized
907 /// from more than one type of register.)
909 /// With virtual registers, the contents of RegVTs is redundant with TLI's
910 /// getRegisterType member function, however when with physical registers
911 /// it is necessary to have a separate record of the types.
913 SmallVector<MVT, 4> RegVTs;
915 /// Regs - This list holds the registers assigned to the values.
916 /// Each legal or promoted value requires one register, and each
917 /// expanded value requires multiple registers.
919 SmallVector<unsigned, 4> Regs;
923 RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt);
925 RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
926 const DataLayout &DL, unsigned Reg, Type *Ty);
928 /// append - Add the specified values to this one.
929 void append(const RegsForValue &RHS) {
930 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
931 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
932 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
935 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
936 /// this value and returns the result as a ValueVTs value. This uses
937 /// Chain/Flag as the input and updates them for the output Chain/Flag.
938 /// If the Flag pointer is NULL, no flag is used.
939 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
941 SDValue &Chain, SDValue *Flag,
942 const Value *V = nullptr) const;
944 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified
945 /// value into the registers specified by this object. This uses Chain/Flag
946 /// as the input and updates them for the output Chain/Flag. If the Flag
947 /// pointer is nullptr, no flag is used. If V is not nullptr, then it is used
948 /// in printing better diagnostic messages on error.
950 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
951 SDValue *Flag, const Value *V = nullptr,
952 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
954 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
955 /// operand list. This adds the code marker, matching input operand index
956 /// (if applicable), and includes the number of values added into it.
957 void AddInlineAsmOperands(unsigned Kind,
958 bool HasMatching, unsigned MatchingIdx, SDLoc dl,
960 std::vector<SDValue> &Ops) const;
963 } // end namespace llvm