1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 llvm_unreachable("should never codegen catchpads");
1166 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1167 // Update machine-CFG edge.
1168 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1169 FuncInfo.MBB->addSuccessor(TargetMBB);
1171 // Create the terminator node.
1172 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1173 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1177 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1178 llvm_unreachable("should never codegen catchendpads");
1181 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1182 // Don't emit any special code for the cleanuppad instruction. It just marks
1183 // the start of a funclet.
1184 FuncInfo.MBB->setIsEHFuncletEntry();
1187 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1188 /// many places it could ultimately go. In the IR, we have a single unwind
1189 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1190 /// This function skips over imaginary basic blocks that hold catchpad,
1191 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1192 /// basic block destinations.
1194 findUnwindDestinations(FunctionLoweringInfo &FuncInfo,
1195 const BasicBlock *EHPadBB,
1196 SmallVectorImpl<MachineBasicBlock *> &UnwindDests) {
1197 bool IsMSVCCXX = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()) ==
1198 EHPersonality::MSVC_CXX;
1200 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1201 if (isa<LandingPadInst>(Pad)) {
1202 // Stop on landingpads. They are not funclets.
1203 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1205 } else if (isa<CleanupPadInst>(Pad) || isa<LandingPadInst>(Pad)) {
1206 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1208 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1209 UnwindDests.back()->setIsEHFuncletEntry();
1211 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1212 // Add the catchpad handler to the possible destinations.
1213 UnwindDests.push_back(FuncInfo.MBBMap[CPI->getNormalDest()]);
1214 // In MSVC C++, catchblocks are funclets and need prologues.
1216 UnwindDests.back()->setIsEHFuncletEntry();
1217 EHPadBB = CPI->getUnwindDest();
1218 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
1219 EHPadBB = CEPI->getUnwindDest();
1220 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
1221 EHPadBB = CEPI->getUnwindDest();
1226 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1227 // Update successor info.
1228 // FIXME: The weights for catchpads will be wrong.
1229 SmallVector<MachineBasicBlock *, 1> UnwindDests;
1230 findUnwindDestinations(FuncInfo, I.getUnwindDest(), UnwindDests);
1231 for (MachineBasicBlock *UnwindDest : UnwindDests) {
1232 UnwindDest->setIsEHPad();
1233 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest);
1236 // Create the terminator node.
1238 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1242 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1243 report_fatal_error("visitCleanupEndPad not yet implemented!");
1246 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1247 report_fatal_error("visitTerminatePad not yet implemented!");
1250 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1251 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1252 auto &DL = DAG.getDataLayout();
1253 SDValue Chain = getControlRoot();
1254 SmallVector<ISD::OutputArg, 8> Outs;
1255 SmallVector<SDValue, 8> OutVals;
1257 if (!FuncInfo.CanLowerReturn) {
1258 unsigned DemoteReg = FuncInfo.DemoteRegister;
1259 const Function *F = I.getParent()->getParent();
1261 // Emit a store of the return value through the virtual register.
1262 // Leave Outs empty so that LowerReturn won't try to load return
1263 // registers the usual way.
1264 SmallVector<EVT, 1> PtrValueVTs;
1265 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1268 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1269 SDValue RetOp = getValue(I.getOperand(0));
1271 SmallVector<EVT, 4> ValueVTs;
1272 SmallVector<uint64_t, 4> Offsets;
1273 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1274 unsigned NumValues = ValueVTs.size();
1276 SmallVector<SDValue, 4> Chains(NumValues);
1277 for (unsigned i = 0; i != NumValues; ++i) {
1278 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1279 RetPtr.getValueType(), RetPtr,
1280 DAG.getIntPtrConstant(Offsets[i],
1283 DAG.getStore(Chain, getCurSDLoc(),
1284 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1285 // FIXME: better loc info would be nice.
1286 Add, MachinePointerInfo(), false, false, 0);
1289 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1290 MVT::Other, Chains);
1291 } else if (I.getNumOperands() != 0) {
1292 SmallVector<EVT, 4> ValueVTs;
1293 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1294 unsigned NumValues = ValueVTs.size();
1296 SDValue RetOp = getValue(I.getOperand(0));
1298 const Function *F = I.getParent()->getParent();
1300 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1301 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1303 ExtendKind = ISD::SIGN_EXTEND;
1304 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1306 ExtendKind = ISD::ZERO_EXTEND;
1308 LLVMContext &Context = F->getContext();
1309 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1312 for (unsigned j = 0; j != NumValues; ++j) {
1313 EVT VT = ValueVTs[j];
1315 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1316 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1318 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1319 MVT PartVT = TLI.getRegisterType(Context, VT);
1320 SmallVector<SDValue, 4> Parts(NumParts);
1321 getCopyToParts(DAG, getCurSDLoc(),
1322 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1323 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1325 // 'inreg' on function refers to return value
1326 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1330 // Propagate extension type if any
1331 if (ExtendKind == ISD::SIGN_EXTEND)
1333 else if (ExtendKind == ISD::ZERO_EXTEND)
1336 for (unsigned i = 0; i < NumParts; ++i) {
1337 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1338 VT, /*isfixed=*/true, 0, 0));
1339 OutVals.push_back(Parts[i]);
1345 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1346 CallingConv::ID CallConv =
1347 DAG.getMachineFunction().getFunction()->getCallingConv();
1348 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1349 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1351 // Verify that the target's LowerReturn behaved as expected.
1352 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1353 "LowerReturn didn't return a valid chain!");
1355 // Update the DAG with the new chain value resulting from return lowering.
1359 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1360 /// created for it, emit nodes to copy the value into the virtual
1362 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1364 if (V->getType()->isEmptyTy())
1367 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1368 if (VMI != FuncInfo.ValueMap.end()) {
1369 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1370 CopyValueToVirtualRegister(V, VMI->second);
1374 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1375 /// the current basic block, add it to ValueMap now so that we'll get a
1377 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1378 // No need to export constants.
1379 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1381 // Already exported?
1382 if (FuncInfo.isExportedInst(V)) return;
1384 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1385 CopyValueToVirtualRegister(V, Reg);
1388 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1389 const BasicBlock *FromBB) {
1390 // The operands of the setcc have to be in this block. We don't know
1391 // how to export them from some other block.
1392 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1393 // Can export from current BB.
1394 if (VI->getParent() == FromBB)
1397 // Is already exported, noop.
1398 return FuncInfo.isExportedInst(V);
1401 // If this is an argument, we can export it if the BB is the entry block or
1402 // if it is already exported.
1403 if (isa<Argument>(V)) {
1404 if (FromBB == &FromBB->getParent()->getEntryBlock())
1407 // Otherwise, can only export this if it is already exported.
1408 return FuncInfo.isExportedInst(V);
1411 // Otherwise, constants can always be exported.
1415 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1416 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1417 const MachineBasicBlock *Dst) const {
1418 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1421 const BasicBlock *SrcBB = Src->getBasicBlock();
1422 const BasicBlock *DstBB = Dst->getBasicBlock();
1423 return BPI->getEdgeWeight(SrcBB, DstBB);
1426 void SelectionDAGBuilder::
1427 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1428 uint32_t Weight /* = 0 */) {
1430 Weight = getEdgeWeight(Src, Dst);
1431 Src->addSuccessor(Dst, Weight);
1435 static bool InBlock(const Value *V, const BasicBlock *BB) {
1436 if (const Instruction *I = dyn_cast<Instruction>(V))
1437 return I->getParent() == BB;
1441 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1442 /// This function emits a branch and is used at the leaves of an OR or an
1443 /// AND operator tree.
1446 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1447 MachineBasicBlock *TBB,
1448 MachineBasicBlock *FBB,
1449 MachineBasicBlock *CurBB,
1450 MachineBasicBlock *SwitchBB,
1453 const BasicBlock *BB = CurBB->getBasicBlock();
1455 // If the leaf of the tree is a comparison, merge the condition into
1457 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1458 // The operands of the cmp have to be in this block. We don't know
1459 // how to export them from some other block. If this is the first block
1460 // of the sequence, no exporting is needed.
1461 if (CurBB == SwitchBB ||
1462 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1463 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1464 ISD::CondCode Condition;
1465 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1466 Condition = getICmpCondCode(IC->getPredicate());
1468 const FCmpInst *FC = cast<FCmpInst>(Cond);
1469 Condition = getFCmpCondCode(FC->getPredicate());
1470 if (TM.Options.NoNaNsFPMath)
1471 Condition = getFCmpCodeWithoutNaN(Condition);
1474 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1475 TBB, FBB, CurBB, TWeight, FWeight);
1476 SwitchCases.push_back(CB);
1481 // Create a CaseBlock record representing this branch.
1482 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1483 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1484 SwitchCases.push_back(CB);
1487 /// Scale down both weights to fit into uint32_t.
1488 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1489 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1490 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1491 NewTrue = NewTrue / Scale;
1492 NewFalse = NewFalse / Scale;
1495 /// FindMergedConditions - If Cond is an expression like
1496 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1497 MachineBasicBlock *TBB,
1498 MachineBasicBlock *FBB,
1499 MachineBasicBlock *CurBB,
1500 MachineBasicBlock *SwitchBB,
1501 Instruction::BinaryOps Opc,
1504 // If this node is not part of the or/and tree, emit it as a branch.
1505 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1506 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1507 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1508 BOp->getParent() != CurBB->getBasicBlock() ||
1509 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1510 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1511 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1516 // Create TmpBB after CurBB.
1517 MachineFunction::iterator BBI = CurBB;
1518 MachineFunction &MF = DAG.getMachineFunction();
1519 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1520 CurBB->getParent()->insert(++BBI, TmpBB);
1522 if (Opc == Instruction::Or) {
1523 // Codegen X | Y as:
1532 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1533 // The requirement is that
1534 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1535 // = TrueProb for original BB.
1536 // Assuming the original weights are A and B, one choice is to set BB1's
1537 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1539 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1540 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1541 // TmpBB, but the math is more complicated.
1543 uint64_t NewTrueWeight = TWeight;
1544 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1545 ScaleWeights(NewTrueWeight, NewFalseWeight);
1546 // Emit the LHS condition.
1547 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1548 NewTrueWeight, NewFalseWeight);
1550 NewTrueWeight = TWeight;
1551 NewFalseWeight = 2 * (uint64_t)FWeight;
1552 ScaleWeights(NewTrueWeight, NewFalseWeight);
1553 // Emit the RHS condition into TmpBB.
1554 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1555 NewTrueWeight, NewFalseWeight);
1557 assert(Opc == Instruction::And && "Unknown merge op!");
1558 // Codegen X & Y as:
1566 // This requires creation of TmpBB after CurBB.
1568 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1569 // The requirement is that
1570 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1571 // = FalseProb for original BB.
1572 // Assuming the original weights are A and B, one choice is to set BB1's
1573 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1575 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1577 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1578 uint64_t NewFalseWeight = FWeight;
1579 ScaleWeights(NewTrueWeight, NewFalseWeight);
1580 // Emit the LHS condition.
1581 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1582 NewTrueWeight, NewFalseWeight);
1584 NewTrueWeight = 2 * (uint64_t)TWeight;
1585 NewFalseWeight = FWeight;
1586 ScaleWeights(NewTrueWeight, NewFalseWeight);
1587 // Emit the RHS condition into TmpBB.
1588 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1589 NewTrueWeight, NewFalseWeight);
1593 /// If the set of cases should be emitted as a series of branches, return true.
1594 /// If we should emit this as a bunch of and/or'd together conditions, return
1597 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1598 if (Cases.size() != 2) return true;
1600 // If this is two comparisons of the same values or'd or and'd together, they
1601 // will get folded into a single comparison, so don't emit two blocks.
1602 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1603 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1604 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1605 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1609 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1610 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1611 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1612 Cases[0].CC == Cases[1].CC &&
1613 isa<Constant>(Cases[0].CmpRHS) &&
1614 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1615 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1617 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1624 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1625 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1627 // Update machine-CFG edges.
1628 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1630 if (I.isUnconditional()) {
1631 // Update machine-CFG edges.
1632 BrMBB->addSuccessor(Succ0MBB);
1634 // If this is not a fall-through branch or optimizations are switched off,
1636 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1637 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1638 MVT::Other, getControlRoot(),
1639 DAG.getBasicBlock(Succ0MBB)));
1644 // If this condition is one of the special cases we handle, do special stuff
1646 const Value *CondVal = I.getCondition();
1647 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1649 // If this is a series of conditions that are or'd or and'd together, emit
1650 // this as a sequence of branches instead of setcc's with and/or operations.
1651 // As long as jumps are not expensive, this should improve performance.
1652 // For example, instead of something like:
1665 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1666 Instruction::BinaryOps Opcode = BOp->getOpcode();
1667 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1668 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1669 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1670 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1671 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1672 getEdgeWeight(BrMBB, Succ1MBB));
1673 // If the compares in later blocks need to use values not currently
1674 // exported from this block, export them now. This block should always
1675 // be the first entry.
1676 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1678 // Allow some cases to be rejected.
1679 if (ShouldEmitAsBranches(SwitchCases)) {
1680 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1681 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1682 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1685 // Emit the branch for this block.
1686 visitSwitchCase(SwitchCases[0], BrMBB);
1687 SwitchCases.erase(SwitchCases.begin());
1691 // Okay, we decided not to do this, remove any inserted MBB's and clear
1693 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1694 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1696 SwitchCases.clear();
1700 // Create a CaseBlock record representing this branch.
1701 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1702 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1704 // Use visitSwitchCase to actually insert the fast branch sequence for this
1706 visitSwitchCase(CB, BrMBB);
1709 /// visitSwitchCase - Emits the necessary code to represent a single node in
1710 /// the binary search tree resulting from lowering a switch instruction.
1711 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1712 MachineBasicBlock *SwitchBB) {
1714 SDValue CondLHS = getValue(CB.CmpLHS);
1715 SDLoc dl = getCurSDLoc();
1717 // Build the setcc now.
1719 // Fold "(X == true)" to X and "(X == false)" to !X to
1720 // handle common cases produced by branch lowering.
1721 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1722 CB.CC == ISD::SETEQ)
1724 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1725 CB.CC == ISD::SETEQ) {
1726 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1727 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1729 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1731 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1733 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1734 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1736 SDValue CmpOp = getValue(CB.CmpMHS);
1737 EVT VT = CmpOp.getValueType();
1739 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1740 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1743 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1744 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1745 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1746 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1750 // Update successor info
1751 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1752 // TrueBB and FalseBB are always different unless the incoming IR is
1753 // degenerate. This only happens when running llc on weird IR.
1754 if (CB.TrueBB != CB.FalseBB)
1755 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1757 // If the lhs block is the next block, invert the condition so that we can
1758 // fall through to the lhs instead of the rhs block.
1759 if (CB.TrueBB == NextBlock(SwitchBB)) {
1760 std::swap(CB.TrueBB, CB.FalseBB);
1761 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1762 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1765 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1766 MVT::Other, getControlRoot(), Cond,
1767 DAG.getBasicBlock(CB.TrueBB));
1769 // Insert the false branch. Do this even if it's a fall through branch,
1770 // this makes it easier to do DAG optimizations which require inverting
1771 // the branch condition.
1772 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1773 DAG.getBasicBlock(CB.FalseBB));
1775 DAG.setRoot(BrCond);
1778 /// visitJumpTable - Emit JumpTable node in the current MBB
1779 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1780 // Emit the code for the jump table
1781 assert(JT.Reg != -1U && "Should lower JT Header first!");
1782 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1783 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1785 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1786 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1787 MVT::Other, Index.getValue(1),
1789 DAG.setRoot(BrJumpTable);
1792 /// visitJumpTableHeader - This function emits necessary code to produce index
1793 /// in the JumpTable from switch case.
1794 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1795 JumpTableHeader &JTH,
1796 MachineBasicBlock *SwitchBB) {
1797 SDLoc dl = getCurSDLoc();
1799 // Subtract the lowest switch case value from the value being switched on and
1800 // conditional branch to default mbb if the result is greater than the
1801 // difference between smallest and largest cases.
1802 SDValue SwitchOp = getValue(JTH.SValue);
1803 EVT VT = SwitchOp.getValueType();
1804 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1805 DAG.getConstant(JTH.First, dl, VT));
1807 // The SDNode we just created, which holds the value being switched on minus
1808 // the smallest case value, needs to be copied to a virtual register so it
1809 // can be used as an index into the jump table in a subsequent basic block.
1810 // This value may be smaller or larger than the target's pointer type, and
1811 // therefore require extension or truncating.
1812 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1813 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1815 unsigned JumpTableReg =
1816 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1817 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1818 JumpTableReg, SwitchOp);
1819 JT.Reg = JumpTableReg;
1821 // Emit the range check for the jump table, and branch to the default block
1822 // for the switch statement if the value being switched on exceeds the largest
1823 // case in the switch.
1824 SDValue CMP = DAG.getSetCC(
1825 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1826 Sub.getValueType()),
1827 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1829 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1830 MVT::Other, CopyTo, CMP,
1831 DAG.getBasicBlock(JT.Default));
1833 // Avoid emitting unnecessary branches to the next block.
1834 if (JT.MBB != NextBlock(SwitchBB))
1835 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1836 DAG.getBasicBlock(JT.MBB));
1838 DAG.setRoot(BrCond);
1841 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1842 /// tail spliced into a stack protector check success bb.
1844 /// For a high level explanation of how this fits into the stack protector
1845 /// generation see the comment on the declaration of class
1846 /// StackProtectorDescriptor.
1847 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1848 MachineBasicBlock *ParentBB) {
1850 // First create the loads to the guard/stack slot for the comparison.
1851 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1852 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1854 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1855 int FI = MFI->getStackProtectorIndex();
1857 const Value *IRGuard = SPD.getGuard();
1858 SDValue GuardPtr = getValue(IRGuard);
1859 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1861 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1864 SDLoc dl = getCurSDLoc();
1866 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1867 // guard value from the virtual register holding the value. Otherwise, emit a
1868 // volatile load to retrieve the stack guard value.
1869 unsigned GuardReg = SPD.getGuardReg();
1871 if (GuardReg && TLI.useLoadStackGuardNode())
1872 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1875 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1876 GuardPtr, MachinePointerInfo(IRGuard, 0),
1877 true, false, false, Align);
1879 SDValue StackSlot = DAG.getLoad(
1880 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1881 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1882 false, false, Align);
1884 // Perform the comparison via a subtract/getsetcc.
1885 EVT VT = Guard.getValueType();
1886 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1888 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1890 Sub.getValueType()),
1891 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1893 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1894 // branch to failure MBB.
1895 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1896 MVT::Other, StackSlot.getOperand(0),
1897 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1898 // Otherwise branch to success MBB.
1899 SDValue Br = DAG.getNode(ISD::BR, dl,
1901 DAG.getBasicBlock(SPD.getSuccessMBB()));
1906 /// Codegen the failure basic block for a stack protector check.
1908 /// A failure stack protector machine basic block consists simply of a call to
1909 /// __stack_chk_fail().
1911 /// For a high level explanation of how this fits into the stack protector
1912 /// generation see the comment on the declaration of class
1913 /// StackProtectorDescriptor.
1915 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1916 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1918 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1919 nullptr, 0, false, getCurSDLoc(), false, false).second;
1923 /// visitBitTestHeader - This function emits necessary code to produce value
1924 /// suitable for "bit tests"
1925 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1926 MachineBasicBlock *SwitchBB) {
1927 SDLoc dl = getCurSDLoc();
1929 // Subtract the minimum value
1930 SDValue SwitchOp = getValue(B.SValue);
1931 EVT VT = SwitchOp.getValueType();
1932 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1933 DAG.getConstant(B.First, dl, VT));
1936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1937 SDValue RangeCmp = DAG.getSetCC(
1938 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1939 Sub.getValueType()),
1940 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1942 // Determine the type of the test operands.
1943 bool UsePtrType = false;
1944 if (!TLI.isTypeLegal(VT))
1947 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1948 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1949 // Switch table case range are encoded into series of masks.
1950 // Just use pointer type, it's guaranteed to fit.
1956 VT = TLI.getPointerTy(DAG.getDataLayout());
1957 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1960 B.RegVT = VT.getSimpleVT();
1961 B.Reg = FuncInfo.CreateReg(B.RegVT);
1962 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1964 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1966 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1967 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1969 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1970 MVT::Other, CopyTo, RangeCmp,
1971 DAG.getBasicBlock(B.Default));
1973 // Avoid emitting unnecessary branches to the next block.
1974 if (MBB != NextBlock(SwitchBB))
1975 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1976 DAG.getBasicBlock(MBB));
1978 DAG.setRoot(BrRange);
1981 /// visitBitTestCase - this function produces one "bit test"
1982 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1983 MachineBasicBlock* NextMBB,
1984 uint32_t BranchWeightToNext,
1987 MachineBasicBlock *SwitchBB) {
1988 SDLoc dl = getCurSDLoc();
1990 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1992 unsigned PopCount = countPopulation(B.Mask);
1993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1994 if (PopCount == 1) {
1995 // Testing for a single bit; just compare the shift count with what it
1996 // would need to be to shift a 1 bit in that position.
1998 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1999 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2001 } else if (PopCount == BB.Range) {
2002 // There is only one zero bit in the range, test for it directly.
2004 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2005 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2008 // Make desired shift
2009 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2010 DAG.getConstant(1, dl, VT), ShiftOp);
2012 // Emit bit tests and jumps
2013 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2014 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2016 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2017 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2020 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2021 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2022 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2023 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2025 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2026 MVT::Other, getControlRoot(),
2027 Cmp, DAG.getBasicBlock(B.TargetBB));
2029 // Avoid emitting unnecessary branches to the next block.
2030 if (NextMBB != NextBlock(SwitchBB))
2031 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2032 DAG.getBasicBlock(NextMBB));
2037 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2038 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2040 // Retrieve successors. Look through artificial IR level blocks like catchpads
2041 // and catchendpads for successors.
2042 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2043 const BasicBlock *EHPadBB = I.getSuccessor(1);
2045 const Value *Callee(I.getCalledValue());
2046 const Function *Fn = dyn_cast<Function>(Callee);
2047 if (isa<InlineAsm>(Callee))
2049 else if (Fn && Fn->isIntrinsic()) {
2050 switch (Fn->getIntrinsicID()) {
2052 llvm_unreachable("Cannot invoke this intrinsic");
2053 case Intrinsic::donothing:
2054 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2056 case Intrinsic::experimental_patchpoint_void:
2057 case Intrinsic::experimental_patchpoint_i64:
2058 visitPatchpoint(&I, EHPadBB);
2060 case Intrinsic::experimental_gc_statepoint:
2061 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2065 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2067 // If the value of the invoke is used outside of its defining block, make it
2068 // available as a virtual register.
2069 // We already took care of the exported value for the statepoint instruction
2070 // during call to the LowerStatepoint.
2071 if (!isStatepoint(I)) {
2072 CopyToExportRegsIfNeeded(&I);
2075 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2076 findUnwindDestinations(FuncInfo, EHPadBB, UnwindDests);
2078 // Update successor info.
2079 // FIXME: The weights for catchpads will be wrong.
2080 addSuccessorWithWeight(InvokeMBB, Return);
2081 for (MachineBasicBlock *UnwindDest : UnwindDests) {
2082 UnwindDest->setIsEHPad();
2083 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2086 // Drop into normal successor.
2087 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2088 MVT::Other, getControlRoot(),
2089 DAG.getBasicBlock(Return)));
2092 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2093 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2096 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2097 assert(FuncInfo.MBB->isEHPad() &&
2098 "Call to landingpad not in landing pad!");
2100 MachineBasicBlock *MBB = FuncInfo.MBB;
2101 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2102 AddLandingPadInfo(LP, MMI, MBB);
2104 // If there aren't registers to copy the values into (e.g., during SjLj
2105 // exceptions), then don't bother to create these DAG nodes.
2106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2107 if (TLI.getExceptionPointerRegister() == 0 &&
2108 TLI.getExceptionSelectorRegister() == 0)
2111 SmallVector<EVT, 2> ValueVTs;
2112 SDLoc dl = getCurSDLoc();
2113 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2114 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2116 // Get the two live-in registers as SDValues. The physregs have already been
2117 // copied into virtual registers.
2119 if (FuncInfo.ExceptionPointerVirtReg) {
2120 Ops[0] = DAG.getZExtOrTrunc(
2121 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2122 FuncInfo.ExceptionPointerVirtReg,
2123 TLI.getPointerTy(DAG.getDataLayout())),
2126 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2128 Ops[1] = DAG.getZExtOrTrunc(
2129 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2130 FuncInfo.ExceptionSelectorVirtReg,
2131 TLI.getPointerTy(DAG.getDataLayout())),
2135 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2136 DAG.getVTList(ValueVTs), Ops);
2140 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2142 for (const CaseCluster &CC : Clusters)
2143 assert(CC.Low == CC.High && "Input clusters must be single-case");
2146 std::sort(Clusters.begin(), Clusters.end(),
2147 [](const CaseCluster &a, const CaseCluster &b) {
2148 return a.Low->getValue().slt(b.Low->getValue());
2151 // Merge adjacent clusters with the same destination.
2152 const unsigned N = Clusters.size();
2153 unsigned DstIndex = 0;
2154 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2155 CaseCluster &CC = Clusters[SrcIndex];
2156 const ConstantInt *CaseVal = CC.Low;
2157 MachineBasicBlock *Succ = CC.MBB;
2159 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2160 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2161 // If this case has the same successor and is a neighbour, merge it into
2162 // the previous cluster.
2163 Clusters[DstIndex - 1].High = CaseVal;
2164 Clusters[DstIndex - 1].Weight += CC.Weight;
2165 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2167 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2168 sizeof(Clusters[SrcIndex]));
2171 Clusters.resize(DstIndex);
2174 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2175 MachineBasicBlock *Last) {
2177 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2178 if (JTCases[i].first.HeaderBB == First)
2179 JTCases[i].first.HeaderBB = Last;
2181 // Update BitTestCases.
2182 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2183 if (BitTestCases[i].Parent == First)
2184 BitTestCases[i].Parent = Last;
2187 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2188 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2190 // Update machine-CFG edges with unique successors.
2191 SmallSet<BasicBlock*, 32> Done;
2192 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2193 BasicBlock *BB = I.getSuccessor(i);
2194 bool Inserted = Done.insert(BB).second;
2198 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2199 addSuccessorWithWeight(IndirectBrMBB, Succ);
2202 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2203 MVT::Other, getControlRoot(),
2204 getValue(I.getAddress())));
2207 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2208 if (DAG.getTarget().Options.TrapUnreachable)
2209 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2212 void SelectionDAGBuilder::visitFSub(const User &I) {
2213 // -0.0 - X --> fneg
2214 Type *Ty = I.getType();
2215 if (isa<Constant>(I.getOperand(0)) &&
2216 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2217 SDValue Op2 = getValue(I.getOperand(1));
2218 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2219 Op2.getValueType(), Op2));
2223 visitBinary(I, ISD::FSUB);
2226 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2227 SDValue Op1 = getValue(I.getOperand(0));
2228 SDValue Op2 = getValue(I.getOperand(1));
2235 if (const OverflowingBinaryOperator *OFBinOp =
2236 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2237 nuw = OFBinOp->hasNoUnsignedWrap();
2238 nsw = OFBinOp->hasNoSignedWrap();
2240 if (const PossiblyExactOperator *ExactOp =
2241 dyn_cast<const PossiblyExactOperator>(&I))
2242 exact = ExactOp->isExact();
2243 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2244 FMF = FPOp->getFastMathFlags();
2247 Flags.setExact(exact);
2248 Flags.setNoSignedWrap(nsw);
2249 Flags.setNoUnsignedWrap(nuw);
2250 if (EnableFMFInDAG) {
2251 Flags.setAllowReciprocal(FMF.allowReciprocal());
2252 Flags.setNoInfs(FMF.noInfs());
2253 Flags.setNoNaNs(FMF.noNaNs());
2254 Flags.setNoSignedZeros(FMF.noSignedZeros());
2255 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2257 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2259 setValue(&I, BinNodeValue);
2262 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2263 SDValue Op1 = getValue(I.getOperand(0));
2264 SDValue Op2 = getValue(I.getOperand(1));
2266 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2267 Op2.getValueType(), DAG.getDataLayout());
2269 // Coerce the shift amount to the right type if we can.
2270 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2271 unsigned ShiftSize = ShiftTy.getSizeInBits();
2272 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2273 SDLoc DL = getCurSDLoc();
2275 // If the operand is smaller than the shift count type, promote it.
2276 if (ShiftSize > Op2Size)
2277 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2279 // If the operand is larger than the shift count type but the shift
2280 // count type has enough bits to represent any shift value, truncate
2281 // it now. This is a common case and it exposes the truncate to
2282 // optimization early.
2283 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2284 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2285 // Otherwise we'll need to temporarily settle for some other convenient
2286 // type. Type legalization will make adjustments once the shiftee is split.
2288 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2295 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2297 if (const OverflowingBinaryOperator *OFBinOp =
2298 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2299 nuw = OFBinOp->hasNoUnsignedWrap();
2300 nsw = OFBinOp->hasNoSignedWrap();
2302 if (const PossiblyExactOperator *ExactOp =
2303 dyn_cast<const PossiblyExactOperator>(&I))
2304 exact = ExactOp->isExact();
2307 Flags.setExact(exact);
2308 Flags.setNoSignedWrap(nsw);
2309 Flags.setNoUnsignedWrap(nuw);
2310 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2315 void SelectionDAGBuilder::visitSDiv(const User &I) {
2316 SDValue Op1 = getValue(I.getOperand(0));
2317 SDValue Op2 = getValue(I.getOperand(1));
2320 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2321 cast<PossiblyExactOperator>(&I)->isExact());
2322 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2326 void SelectionDAGBuilder::visitICmp(const User &I) {
2327 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2328 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2329 predicate = IC->getPredicate();
2330 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2331 predicate = ICmpInst::Predicate(IC->getPredicate());
2332 SDValue Op1 = getValue(I.getOperand(0));
2333 SDValue Op2 = getValue(I.getOperand(1));
2334 ISD::CondCode Opcode = getICmpCondCode(predicate);
2336 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2338 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2341 void SelectionDAGBuilder::visitFCmp(const User &I) {
2342 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2343 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2344 predicate = FC->getPredicate();
2345 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2346 predicate = FCmpInst::Predicate(FC->getPredicate());
2347 SDValue Op1 = getValue(I.getOperand(0));
2348 SDValue Op2 = getValue(I.getOperand(1));
2349 ISD::CondCode Condition = getFCmpCondCode(predicate);
2351 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2352 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2353 // further optimization, but currently FMF is only applicable to binary nodes.
2354 if (TM.Options.NoNaNsFPMath)
2355 Condition = getFCmpCodeWithoutNaN(Condition);
2356 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2358 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2361 void SelectionDAGBuilder::visitSelect(const User &I) {
2362 SmallVector<EVT, 4> ValueVTs;
2363 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2365 unsigned NumValues = ValueVTs.size();
2366 if (NumValues == 0) return;
2368 SmallVector<SDValue, 4> Values(NumValues);
2369 SDValue Cond = getValue(I.getOperand(0));
2370 SDValue LHSVal = getValue(I.getOperand(1));
2371 SDValue RHSVal = getValue(I.getOperand(2));
2372 auto BaseOps = {Cond};
2373 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2374 ISD::VSELECT : ISD::SELECT;
2376 // Min/max matching is only viable if all output VTs are the same.
2377 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2378 EVT VT = ValueVTs[0];
2379 LLVMContext &Ctx = *DAG.getContext();
2380 auto &TLI = DAG.getTargetLoweringInfo();
2381 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2382 VT = TLI.getTypeToTransformTo(Ctx, VT);
2385 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2386 ISD::NodeType Opc = ISD::DELETED_NODE;
2387 switch (SPR.Flavor) {
2388 case SPF_UMAX: Opc = ISD::UMAX; break;
2389 case SPF_UMIN: Opc = ISD::UMIN; break;
2390 case SPF_SMAX: Opc = ISD::SMAX; break;
2391 case SPF_SMIN: Opc = ISD::SMIN; break;
2393 switch (SPR.NaNBehavior) {
2394 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2395 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2396 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2397 case SPNB_RETURNS_ANY:
2398 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2404 switch (SPR.NaNBehavior) {
2405 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2406 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2407 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2408 case SPNB_RETURNS_ANY:
2409 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2417 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2418 // If the underlying comparison instruction is used by any other instruction,
2419 // the consumed instructions won't be destroyed, so it is not profitable
2420 // to convert to a min/max.
2421 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2423 LHSVal = getValue(LHS);
2424 RHSVal = getValue(RHS);
2429 for (unsigned i = 0; i != NumValues; ++i) {
2430 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2431 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2432 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2433 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2434 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2438 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2439 DAG.getVTList(ValueVTs), Values));
2442 void SelectionDAGBuilder::visitTrunc(const User &I) {
2443 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2444 SDValue N = getValue(I.getOperand(0));
2445 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2447 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2450 void SelectionDAGBuilder::visitZExt(const User &I) {
2451 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2452 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2453 SDValue N = getValue(I.getOperand(0));
2454 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2456 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2459 void SelectionDAGBuilder::visitSExt(const User &I) {
2460 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2461 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2462 SDValue N = getValue(I.getOperand(0));
2463 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2465 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2468 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2469 // FPTrunc is never a no-op cast, no need to check
2470 SDValue N = getValue(I.getOperand(0));
2471 SDLoc dl = getCurSDLoc();
2472 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2473 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2474 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2475 DAG.getTargetConstant(
2476 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2479 void SelectionDAGBuilder::visitFPExt(const User &I) {
2480 // FPExt is never a no-op cast, no need to check
2481 SDValue N = getValue(I.getOperand(0));
2482 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2484 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2487 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2488 // FPToUI is never a no-op cast, no need to check
2489 SDValue N = getValue(I.getOperand(0));
2490 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2492 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2495 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2496 // FPToSI is never a no-op cast, no need to check
2497 SDValue N = getValue(I.getOperand(0));
2498 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2500 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2503 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2504 // UIToFP is never a no-op cast, no need to check
2505 SDValue N = getValue(I.getOperand(0));
2506 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2508 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2511 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2512 // SIToFP is never a no-op cast, no need to check
2513 SDValue N = getValue(I.getOperand(0));
2514 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2516 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2519 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2520 // What to do depends on the size of the integer and the size of the pointer.
2521 // We can either truncate, zero extend, or no-op, accordingly.
2522 SDValue N = getValue(I.getOperand(0));
2523 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2525 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2528 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2529 // What to do depends on the size of the integer and the size of the pointer.
2530 // We can either truncate, zero extend, or no-op, accordingly.
2531 SDValue N = getValue(I.getOperand(0));
2532 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2534 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2537 void SelectionDAGBuilder::visitBitCast(const User &I) {
2538 SDValue N = getValue(I.getOperand(0));
2539 SDLoc dl = getCurSDLoc();
2540 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2543 // BitCast assures us that source and destination are the same size so this is
2544 // either a BITCAST or a no-op.
2545 if (DestVT != N.getValueType())
2546 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2547 DestVT, N)); // convert types.
2548 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2549 // might fold any kind of constant expression to an integer constant and that
2550 // is not what we are looking for. Only regcognize a bitcast of a genuine
2551 // constant integer as an opaque constant.
2552 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2553 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2556 setValue(&I, N); // noop cast.
2559 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2560 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2561 const Value *SV = I.getOperand(0);
2562 SDValue N = getValue(SV);
2563 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2565 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2566 unsigned DestAS = I.getType()->getPointerAddressSpace();
2568 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2569 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2574 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2575 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2576 SDValue InVec = getValue(I.getOperand(0));
2577 SDValue InVal = getValue(I.getOperand(1));
2578 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2579 TLI.getVectorIdxTy(DAG.getDataLayout()));
2580 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2581 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2582 InVec, InVal, InIdx));
2585 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2586 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2587 SDValue InVec = getValue(I.getOperand(0));
2588 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2589 TLI.getVectorIdxTy(DAG.getDataLayout()));
2590 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2591 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2595 // Utility for visitShuffleVector - Return true if every element in Mask,
2596 // beginning from position Pos and ending in Pos+Size, falls within the
2597 // specified sequential range [L, L+Pos). or is undef.
2598 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2599 unsigned Pos, unsigned Size, int Low) {
2600 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2601 if (Mask[i] >= 0 && Mask[i] != Low)
2606 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2607 SDValue Src1 = getValue(I.getOperand(0));
2608 SDValue Src2 = getValue(I.getOperand(1));
2610 SmallVector<int, 8> Mask;
2611 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2612 unsigned MaskNumElts = Mask.size();
2614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2615 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2616 EVT SrcVT = Src1.getValueType();
2617 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2619 if (SrcNumElts == MaskNumElts) {
2620 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2625 // Normalize the shuffle vector since mask and vector length don't match.
2626 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2627 // Mask is longer than the source vectors and is a multiple of the source
2628 // vectors. We can use concatenate vector to make the mask and vectors
2630 if (SrcNumElts*2 == MaskNumElts) {
2631 // First check for Src1 in low and Src2 in high
2632 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2633 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2634 // The shuffle is concatenating two vectors together.
2635 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2639 // Then check for Src2 in low and Src1 in high
2640 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2641 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2642 // The shuffle is concatenating two vectors together.
2643 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2649 // Pad both vectors with undefs to make them the same length as the mask.
2650 unsigned NumConcat = MaskNumElts / SrcNumElts;
2651 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2652 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2653 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2655 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2656 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2660 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2661 getCurSDLoc(), VT, MOps1);
2662 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2663 getCurSDLoc(), VT, MOps2);
2665 // Readjust mask for new input vector length.
2666 SmallVector<int, 8> MappedOps;
2667 for (unsigned i = 0; i != MaskNumElts; ++i) {
2669 if (Idx >= (int)SrcNumElts)
2670 Idx -= SrcNumElts - MaskNumElts;
2671 MappedOps.push_back(Idx);
2674 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2679 if (SrcNumElts > MaskNumElts) {
2680 // Analyze the access pattern of the vector to see if we can extract
2681 // two subvectors and do the shuffle. The analysis is done by calculating
2682 // the range of elements the mask access on both vectors.
2683 int MinRange[2] = { static_cast<int>(SrcNumElts),
2684 static_cast<int>(SrcNumElts)};
2685 int MaxRange[2] = {-1, -1};
2687 for (unsigned i = 0; i != MaskNumElts; ++i) {
2693 if (Idx >= (int)SrcNumElts) {
2697 if (Idx > MaxRange[Input])
2698 MaxRange[Input] = Idx;
2699 if (Idx < MinRange[Input])
2700 MinRange[Input] = Idx;
2703 // Check if the access is smaller than the vector size and can we find
2704 // a reasonable extract index.
2705 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2707 int StartIdx[2]; // StartIdx to extract from
2708 for (unsigned Input = 0; Input < 2; ++Input) {
2709 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2710 RangeUse[Input] = 0; // Unused
2711 StartIdx[Input] = 0;
2715 // Find a good start index that is a multiple of the mask length. Then
2716 // see if the rest of the elements are in range.
2717 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2718 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2719 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2720 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2723 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2724 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2727 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2728 // Extract appropriate subvector and generate a vector shuffle
2729 for (unsigned Input = 0; Input < 2; ++Input) {
2730 SDValue &Src = Input == 0 ? Src1 : Src2;
2731 if (RangeUse[Input] == 0)
2732 Src = DAG.getUNDEF(VT);
2734 SDLoc dl = getCurSDLoc();
2736 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2737 DAG.getConstant(StartIdx[Input], dl,
2738 TLI.getVectorIdxTy(DAG.getDataLayout())));
2742 // Calculate new mask.
2743 SmallVector<int, 8> MappedOps;
2744 for (unsigned i = 0; i != MaskNumElts; ++i) {
2747 if (Idx < (int)SrcNumElts)
2750 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2752 MappedOps.push_back(Idx);
2755 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2761 // We can't use either concat vectors or extract subvectors so fall back to
2762 // replacing the shuffle with extract and build vector.
2763 // to insert and build vector.
2764 EVT EltVT = VT.getVectorElementType();
2765 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2766 SDLoc dl = getCurSDLoc();
2767 SmallVector<SDValue,8> Ops;
2768 for (unsigned i = 0; i != MaskNumElts; ++i) {
2773 Res = DAG.getUNDEF(EltVT);
2775 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2776 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2778 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2779 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2785 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2788 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2789 const Value *Op0 = I.getOperand(0);
2790 const Value *Op1 = I.getOperand(1);
2791 Type *AggTy = I.getType();
2792 Type *ValTy = Op1->getType();
2793 bool IntoUndef = isa<UndefValue>(Op0);
2794 bool FromUndef = isa<UndefValue>(Op1);
2796 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2798 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2799 SmallVector<EVT, 4> AggValueVTs;
2800 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2801 SmallVector<EVT, 4> ValValueVTs;
2802 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2804 unsigned NumAggValues = AggValueVTs.size();
2805 unsigned NumValValues = ValValueVTs.size();
2806 SmallVector<SDValue, 4> Values(NumAggValues);
2808 // Ignore an insertvalue that produces an empty object
2809 if (!NumAggValues) {
2810 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2814 SDValue Agg = getValue(Op0);
2816 // Copy the beginning value(s) from the original aggregate.
2817 for (; i != LinearIndex; ++i)
2818 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2819 SDValue(Agg.getNode(), Agg.getResNo() + i);
2820 // Copy values from the inserted value(s).
2822 SDValue Val = getValue(Op1);
2823 for (; i != LinearIndex + NumValValues; ++i)
2824 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2825 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2827 // Copy remaining value(s) from the original aggregate.
2828 for (; i != NumAggValues; ++i)
2829 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2830 SDValue(Agg.getNode(), Agg.getResNo() + i);
2832 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2833 DAG.getVTList(AggValueVTs), Values));
2836 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2837 const Value *Op0 = I.getOperand(0);
2838 Type *AggTy = Op0->getType();
2839 Type *ValTy = I.getType();
2840 bool OutOfUndef = isa<UndefValue>(Op0);
2842 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2845 SmallVector<EVT, 4> ValValueVTs;
2846 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2848 unsigned NumValValues = ValValueVTs.size();
2850 // Ignore a extractvalue that produces an empty object
2851 if (!NumValValues) {
2852 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2856 SmallVector<SDValue, 4> Values(NumValValues);
2858 SDValue Agg = getValue(Op0);
2859 // Copy out the selected value(s).
2860 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2861 Values[i - LinearIndex] =
2863 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2864 SDValue(Agg.getNode(), Agg.getResNo() + i);
2866 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2867 DAG.getVTList(ValValueVTs), Values));
2870 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2871 Value *Op0 = I.getOperand(0);
2872 // Note that the pointer operand may be a vector of pointers. Take the scalar
2873 // element which holds a pointer.
2874 Type *Ty = Op0->getType()->getScalarType();
2875 unsigned AS = Ty->getPointerAddressSpace();
2876 SDValue N = getValue(Op0);
2877 SDLoc dl = getCurSDLoc();
2879 // Normalize Vector GEP - all scalar operands should be converted to the
2881 unsigned VectorWidth = I.getType()->isVectorTy() ?
2882 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2884 if (VectorWidth && !N.getValueType().isVector()) {
2885 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2886 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2887 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2889 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2891 const Value *Idx = *OI;
2892 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2893 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2896 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2897 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2898 DAG.getConstant(Offset, dl, N.getValueType()));
2901 Ty = StTy->getElementType(Field);
2903 Ty = cast<SequentialType>(Ty)->getElementType();
2905 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2906 unsigned PtrSize = PtrTy.getSizeInBits();
2907 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2909 // If this is a scalar constant or a splat vector of constants,
2910 // handle it quickly.
2911 const auto *CI = dyn_cast<ConstantInt>(Idx);
2912 if (!CI && isa<ConstantDataVector>(Idx) &&
2913 cast<ConstantDataVector>(Idx)->getSplatValue())
2914 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2919 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2920 SDValue OffsVal = VectorWidth ?
2921 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2922 DAG.getConstant(Offs, dl, PtrTy);
2923 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2927 // N = N + Idx * ElementSize;
2928 SDValue IdxN = getValue(Idx);
2930 if (!IdxN.getValueType().isVector() && VectorWidth) {
2931 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2932 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2933 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2935 // If the index is smaller or larger than intptr_t, truncate or extend
2937 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2939 // If this is a multiply by a power of two, turn it into a shl
2940 // immediately. This is a very common case.
2941 if (ElementSize != 1) {
2942 if (ElementSize.isPowerOf2()) {
2943 unsigned Amt = ElementSize.logBase2();
2944 IdxN = DAG.getNode(ISD::SHL, dl,
2945 N.getValueType(), IdxN,
2946 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2948 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2949 IdxN = DAG.getNode(ISD::MUL, dl,
2950 N.getValueType(), IdxN, Scale);
2954 N = DAG.getNode(ISD::ADD, dl,
2955 N.getValueType(), N, IdxN);
2962 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2963 // If this is a fixed sized alloca in the entry block of the function,
2964 // allocate it statically on the stack.
2965 if (FuncInfo.StaticAllocaMap.count(&I))
2966 return; // getValue will auto-populate this.
2968 SDLoc dl = getCurSDLoc();
2969 Type *Ty = I.getAllocatedType();
2970 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2971 auto &DL = DAG.getDataLayout();
2972 uint64_t TySize = DL.getTypeAllocSize(Ty);
2974 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2976 SDValue AllocSize = getValue(I.getArraySize());
2978 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2979 if (AllocSize.getValueType() != IntPtr)
2980 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2982 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2984 DAG.getConstant(TySize, dl, IntPtr));
2986 // Handle alignment. If the requested alignment is less than or equal to
2987 // the stack alignment, ignore it. If the size is greater than or equal to
2988 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2989 unsigned StackAlign =
2990 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2991 if (Align <= StackAlign)
2994 // Round the size of the allocation up to the stack alignment size
2995 // by add SA-1 to the size.
2996 AllocSize = DAG.getNode(ISD::ADD, dl,
2997 AllocSize.getValueType(), AllocSize,
2998 DAG.getIntPtrConstant(StackAlign - 1, dl));
3000 // Mask out the low bits for alignment purposes.
3001 AllocSize = DAG.getNode(ISD::AND, dl,
3002 AllocSize.getValueType(), AllocSize,
3003 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3006 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3007 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3008 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3010 DAG.setRoot(DSA.getValue(1));
3012 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3015 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3017 return visitAtomicLoad(I);
3019 const Value *SV = I.getOperand(0);
3020 SDValue Ptr = getValue(SV);
3022 Type *Ty = I.getType();
3024 bool isVolatile = I.isVolatile();
3025 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3027 // The IR notion of invariant_load only guarantees that all *non-faulting*
3028 // invariant loads result in the same value. The MI notion of invariant load
3029 // guarantees that the load can be legally moved to any location within its
3030 // containing function. The MI notion of invariant_load is stronger than the
3031 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3032 // with a guarantee that the location being loaded from is dereferenceable
3033 // throughout the function's lifetime.
3035 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3036 isDereferenceablePointer(SV, DAG.getDataLayout());
3037 unsigned Alignment = I.getAlignment();
3040 I.getAAMetadata(AAInfo);
3041 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3043 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3044 SmallVector<EVT, 4> ValueVTs;
3045 SmallVector<uint64_t, 4> Offsets;
3046 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3047 unsigned NumValues = ValueVTs.size();
3052 bool ConstantMemory = false;
3053 if (isVolatile || NumValues > MaxParallelChains)
3054 // Serialize volatile loads with other side effects.
3056 else if (AA->pointsToConstantMemory(MemoryLocation(
3057 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3058 // Do not serialize (non-volatile) loads of constant memory with anything.
3059 Root = DAG.getEntryNode();
3060 ConstantMemory = true;
3062 // Do not serialize non-volatile loads against each other.
3063 Root = DAG.getRoot();
3066 SDLoc dl = getCurSDLoc();
3069 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3071 SmallVector<SDValue, 4> Values(NumValues);
3072 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3073 EVT PtrVT = Ptr.getValueType();
3074 unsigned ChainI = 0;
3075 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3076 // Serializing loads here may result in excessive register pressure, and
3077 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3078 // could recover a bit by hoisting nodes upward in the chain by recognizing
3079 // they are side-effect free or do not alias. The optimizer should really
3080 // avoid this case by converting large object/array copies to llvm.memcpy
3081 // (MaxParallelChains should always remain as failsafe).
3082 if (ChainI == MaxParallelChains) {
3083 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3084 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3085 makeArrayRef(Chains.data(), ChainI));
3089 SDValue A = DAG.getNode(ISD::ADD, dl,
3091 DAG.getConstant(Offsets[i], dl, PtrVT));
3092 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3093 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3094 isNonTemporal, isInvariant, Alignment, AAInfo,
3098 Chains[ChainI] = L.getValue(1);
3101 if (!ConstantMemory) {
3102 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3103 makeArrayRef(Chains.data(), ChainI));
3107 PendingLoads.push_back(Chain);
3110 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3111 DAG.getVTList(ValueVTs), Values));
3114 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3116 return visitAtomicStore(I);
3118 const Value *SrcV = I.getOperand(0);
3119 const Value *PtrV = I.getOperand(1);
3121 SmallVector<EVT, 4> ValueVTs;
3122 SmallVector<uint64_t, 4> Offsets;
3123 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3124 SrcV->getType(), ValueVTs, &Offsets);
3125 unsigned NumValues = ValueVTs.size();
3129 // Get the lowered operands. Note that we do this after
3130 // checking if NumResults is zero, because with zero results
3131 // the operands won't have values in the map.
3132 SDValue Src = getValue(SrcV);
3133 SDValue Ptr = getValue(PtrV);
3135 SDValue Root = getRoot();
3136 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3137 EVT PtrVT = Ptr.getValueType();
3138 bool isVolatile = I.isVolatile();
3139 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3140 unsigned Alignment = I.getAlignment();
3141 SDLoc dl = getCurSDLoc();
3144 I.getAAMetadata(AAInfo);
3146 unsigned ChainI = 0;
3147 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3148 // See visitLoad comments.
3149 if (ChainI == MaxParallelChains) {
3150 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3151 makeArrayRef(Chains.data(), ChainI));
3155 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3156 DAG.getConstant(Offsets[i], dl, PtrVT));
3157 SDValue St = DAG.getStore(Root, dl,
3158 SDValue(Src.getNode(), Src.getResNo() + i),
3159 Add, MachinePointerInfo(PtrV, Offsets[i]),
3160 isVolatile, isNonTemporal, Alignment, AAInfo);
3161 Chains[ChainI] = St;
3164 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3165 makeArrayRef(Chains.data(), ChainI));
3166 DAG.setRoot(StoreNode);
3169 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3170 SDLoc sdl = getCurSDLoc();
3172 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3173 Value *PtrOperand = I.getArgOperand(1);
3174 SDValue Ptr = getValue(PtrOperand);
3175 SDValue Src0 = getValue(I.getArgOperand(0));
3176 SDValue Mask = getValue(I.getArgOperand(3));
3177 EVT VT = Src0.getValueType();
3178 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3180 Alignment = DAG.getEVTAlignment(VT);
3183 I.getAAMetadata(AAInfo);
3185 MachineMemOperand *MMO =
3186 DAG.getMachineFunction().
3187 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3188 MachineMemOperand::MOStore, VT.getStoreSize(),
3190 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3192 DAG.setRoot(StoreNode);
3193 setValue(&I, StoreNode);
3196 // Get a uniform base for the Gather/Scatter intrinsic.
3197 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3198 // We try to represent it as a base pointer + vector of indices.
3199 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3200 // The first operand of the GEP may be a single pointer or a vector of pointers
3202 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3204 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3205 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3207 // When the first GEP operand is a single pointer - it is the uniform base we
3208 // are looking for. If first operand of the GEP is a splat vector - we
3209 // extract the spalt value and use it as a uniform base.
3210 // In all other cases the function returns 'false'.
3212 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3213 SelectionDAGBuilder* SDB) {
3215 SelectionDAG& DAG = SDB->DAG;
3216 LLVMContext &Context = *DAG.getContext();
3218 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3219 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3220 if (!GEP || GEP->getNumOperands() > 2)
3223 Value *GEPPtr = GEP->getPointerOperand();
3224 if (!GEPPtr->getType()->isVectorTy())
3226 else if (!(Ptr = getSplatValue(GEPPtr)))
3229 Value *IndexVal = GEP->getOperand(1);
3231 // The operands of the GEP may be defined in another basic block.
3232 // In this case we'll not find nodes for the operands.
3233 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3236 Base = SDB->getValue(Ptr);
3237 Index = SDB->getValue(IndexVal);
3239 // Suppress sign extension.
3240 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3241 if (SDB->findValue(Sext->getOperand(0))) {
3242 IndexVal = Sext->getOperand(0);
3243 Index = SDB->getValue(IndexVal);
3246 if (!Index.getValueType().isVector()) {
3247 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3248 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3249 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3250 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3255 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3256 SDLoc sdl = getCurSDLoc();
3258 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3259 Value *Ptr = I.getArgOperand(1);
3260 SDValue Src0 = getValue(I.getArgOperand(0));
3261 SDValue Mask = getValue(I.getArgOperand(3));
3262 EVT VT = Src0.getValueType();
3263 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3265 Alignment = DAG.getEVTAlignment(VT);
3266 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3269 I.getAAMetadata(AAInfo);
3273 Value *BasePtr = Ptr;
3274 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3276 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3277 MachineMemOperand *MMO = DAG.getMachineFunction().
3278 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3279 MachineMemOperand::MOStore, VT.getStoreSize(),
3282 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3283 Index = getValue(Ptr);
3285 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3286 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3288 DAG.setRoot(Scatter);
3289 setValue(&I, Scatter);
3292 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3293 SDLoc sdl = getCurSDLoc();
3295 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3296 Value *PtrOperand = I.getArgOperand(0);
3297 SDValue Ptr = getValue(PtrOperand);
3298 SDValue Src0 = getValue(I.getArgOperand(3));
3299 SDValue Mask = getValue(I.getArgOperand(2));
3301 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3302 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3303 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3305 Alignment = DAG.getEVTAlignment(VT);
3308 I.getAAMetadata(AAInfo);
3309 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3311 SDValue InChain = DAG.getRoot();
3312 if (AA->pointsToConstantMemory(MemoryLocation(
3313 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3315 // Do not serialize (non-volatile) loads of constant memory with anything.
3316 InChain = DAG.getEntryNode();
3319 MachineMemOperand *MMO =
3320 DAG.getMachineFunction().
3321 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3322 MachineMemOperand::MOLoad, VT.getStoreSize(),
3323 Alignment, AAInfo, Ranges);
3325 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3327 SDValue OutChain = Load.getValue(1);
3328 DAG.setRoot(OutChain);
3332 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3333 SDLoc sdl = getCurSDLoc();
3335 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3336 Value *Ptr = I.getArgOperand(0);
3337 SDValue Src0 = getValue(I.getArgOperand(3));
3338 SDValue Mask = getValue(I.getArgOperand(2));
3340 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3341 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3342 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3344 Alignment = DAG.getEVTAlignment(VT);
3347 I.getAAMetadata(AAInfo);
3348 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3350 SDValue Root = DAG.getRoot();
3353 Value *BasePtr = Ptr;
3354 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3355 bool ConstantMemory = false;
3357 AA->pointsToConstantMemory(MemoryLocation(
3358 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3360 // Do not serialize (non-volatile) loads of constant memory with anything.
3361 Root = DAG.getEntryNode();
3362 ConstantMemory = true;
3365 MachineMemOperand *MMO =
3366 DAG.getMachineFunction().
3367 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3368 MachineMemOperand::MOLoad, VT.getStoreSize(),
3369 Alignment, AAInfo, Ranges);
3372 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3373 Index = getValue(Ptr);
3375 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3376 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3379 SDValue OutChain = Gather.getValue(1);
3380 if (!ConstantMemory)
3381 PendingLoads.push_back(OutChain);
3382 setValue(&I, Gather);
3385 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3386 SDLoc dl = getCurSDLoc();
3387 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3388 AtomicOrdering FailureOrder = I.getFailureOrdering();
3389 SynchronizationScope Scope = I.getSynchScope();
3391 SDValue InChain = getRoot();
3393 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3394 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3395 SDValue L = DAG.getAtomicCmpSwap(
3396 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3397 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3398 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3399 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3401 SDValue OutChain = L.getValue(2);
3404 DAG.setRoot(OutChain);
3407 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3408 SDLoc dl = getCurSDLoc();
3410 switch (I.getOperation()) {
3411 default: llvm_unreachable("Unknown atomicrmw operation");
3412 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3413 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3414 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3415 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3416 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3417 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3418 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3419 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3420 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3421 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3422 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3424 AtomicOrdering Order = I.getOrdering();
3425 SynchronizationScope Scope = I.getSynchScope();
3427 SDValue InChain = getRoot();
3430 DAG.getAtomic(NT, dl,
3431 getValue(I.getValOperand()).getSimpleValueType(),
3433 getValue(I.getPointerOperand()),
3434 getValue(I.getValOperand()),
3435 I.getPointerOperand(),
3436 /* Alignment=*/ 0, Order, Scope);
3438 SDValue OutChain = L.getValue(1);
3441 DAG.setRoot(OutChain);
3444 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3445 SDLoc dl = getCurSDLoc();
3446 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3449 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3450 TLI.getPointerTy(DAG.getDataLayout()));
3451 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3452 TLI.getPointerTy(DAG.getDataLayout()));
3453 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3456 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3457 SDLoc dl = getCurSDLoc();
3458 AtomicOrdering Order = I.getOrdering();
3459 SynchronizationScope Scope = I.getSynchScope();
3461 SDValue InChain = getRoot();
3463 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3464 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3466 if (I.getAlignment() < VT.getSizeInBits() / 8)
3467 report_fatal_error("Cannot generate unaligned atomic load");
3469 MachineMemOperand *MMO =
3470 DAG.getMachineFunction().
3471 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3472 MachineMemOperand::MOVolatile |
3473 MachineMemOperand::MOLoad,
3475 I.getAlignment() ? I.getAlignment() :
3476 DAG.getEVTAlignment(VT));
3478 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3480 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3481 getValue(I.getPointerOperand()), MMO,
3484 SDValue OutChain = L.getValue(1);
3487 DAG.setRoot(OutChain);
3490 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3491 SDLoc dl = getCurSDLoc();
3493 AtomicOrdering Order = I.getOrdering();
3494 SynchronizationScope Scope = I.getSynchScope();
3496 SDValue InChain = getRoot();
3498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3500 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3502 if (I.getAlignment() < VT.getSizeInBits() / 8)
3503 report_fatal_error("Cannot generate unaligned atomic store");
3506 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3508 getValue(I.getPointerOperand()),
3509 getValue(I.getValueOperand()),
3510 I.getPointerOperand(), I.getAlignment(),
3513 DAG.setRoot(OutChain);
3516 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3518 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3519 unsigned Intrinsic) {
3520 bool HasChain = !I.doesNotAccessMemory();
3521 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3523 // Build the operand list.
3524 SmallVector<SDValue, 8> Ops;
3525 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3527 // We don't need to serialize loads against other loads.
3528 Ops.push_back(DAG.getRoot());
3530 Ops.push_back(getRoot());
3534 // Info is set by getTgtMemInstrinsic
3535 TargetLowering::IntrinsicInfo Info;
3536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3537 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3539 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3540 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3541 Info.opc == ISD::INTRINSIC_W_CHAIN)
3542 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3543 TLI.getPointerTy(DAG.getDataLayout())));
3545 // Add all operands of the call to the operand list.
3546 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3547 SDValue Op = getValue(I.getArgOperand(i));
3551 SmallVector<EVT, 4> ValueVTs;
3552 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3555 ValueVTs.push_back(MVT::Other);
3557 SDVTList VTs = DAG.getVTList(ValueVTs);
3561 if (IsTgtIntrinsic) {
3562 // This is target intrinsic that touches memory
3563 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3564 VTs, Ops, Info.memVT,
3565 MachinePointerInfo(Info.ptrVal, Info.offset),
3566 Info.align, Info.vol,
3567 Info.readMem, Info.writeMem, Info.size);
3568 } else if (!HasChain) {
3569 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3570 } else if (!I.getType()->isVoidTy()) {
3571 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3573 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3577 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3579 PendingLoads.push_back(Chain);
3584 if (!I.getType()->isVoidTy()) {
3585 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3586 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3587 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3590 setValue(&I, Result);
3594 /// GetSignificand - Get the significand and build it into a floating-point
3595 /// number with exponent of 1:
3597 /// Op = (Op & 0x007fffff) | 0x3f800000;
3599 /// where Op is the hexadecimal representation of floating point value.
3601 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3602 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3603 DAG.getConstant(0x007fffff, dl, MVT::i32));
3604 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3605 DAG.getConstant(0x3f800000, dl, MVT::i32));
3606 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3609 /// GetExponent - Get the exponent:
3611 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3613 /// where Op is the hexadecimal representation of floating point value.
3615 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3617 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3618 DAG.getConstant(0x7f800000, dl, MVT::i32));
3619 SDValue t1 = DAG.getNode(
3620 ISD::SRL, dl, MVT::i32, t0,
3621 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3622 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3623 DAG.getConstant(127, dl, MVT::i32));
3624 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3627 /// getF32Constant - Get 32-bit floating point constant.
3629 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3630 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3634 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3635 SelectionDAG &DAG) {
3636 // TODO: What fast-math-flags should be set on the floating-point nodes?
3638 // IntegerPartOfX = ((int32_t)(t0);
3639 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3641 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3642 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3643 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3645 // IntegerPartOfX <<= 23;
3646 IntegerPartOfX = DAG.getNode(
3647 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3648 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3649 DAG.getDataLayout())));
3651 SDValue TwoToFractionalPartOfX;
3652 if (LimitFloatPrecision <= 6) {
3653 // For floating-point precision of 6:
3655 // TwoToFractionalPartOfX =
3657 // (0.735607626f + 0.252464424f * x) * x;
3659 // error 0.0144103317, which is 6 bits
3660 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3661 getF32Constant(DAG, 0x3e814304, dl));
3662 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3663 getF32Constant(DAG, 0x3f3c50c8, dl));
3664 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3665 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3666 getF32Constant(DAG, 0x3f7f5e7e, dl));
3667 } else if (LimitFloatPrecision <= 12) {
3668 // For floating-point precision of 12:
3670 // TwoToFractionalPartOfX =
3673 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3675 // error 0.000107046256, which is 13 to 14 bits
3676 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3677 getF32Constant(DAG, 0x3da235e3, dl));
3678 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3679 getF32Constant(DAG, 0x3e65b8f3, dl));
3680 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3681 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3682 getF32Constant(DAG, 0x3f324b07, dl));
3683 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3684 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3685 getF32Constant(DAG, 0x3f7ff8fd, dl));
3686 } else { // LimitFloatPrecision <= 18
3687 // For floating-point precision of 18:
3689 // TwoToFractionalPartOfX =
3693 // (0.554906021e-1f +
3694 // (0.961591928e-2f +
3695 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3696 // error 2.47208000*10^(-7), which is better than 18 bits
3697 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3698 getF32Constant(DAG, 0x3924b03e, dl));
3699 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3700 getF32Constant(DAG, 0x3ab24b87, dl));
3701 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3702 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3703 getF32Constant(DAG, 0x3c1d8c17, dl));
3704 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3705 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3706 getF32Constant(DAG, 0x3d634a1d, dl));
3707 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3708 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3709 getF32Constant(DAG, 0x3e75fe14, dl));
3710 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3711 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3712 getF32Constant(DAG, 0x3f317234, dl));
3713 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3714 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3715 getF32Constant(DAG, 0x3f800000, dl));
3718 // Add the exponent into the result in integer domain.
3719 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3720 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3721 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3724 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3725 /// limited-precision mode.
3726 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3727 const TargetLowering &TLI) {
3728 if (Op.getValueType() == MVT::f32 &&
3729 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3731 // Put the exponent in the right bit position for later addition to the
3734 // #define LOG2OFe 1.4426950f
3735 // t0 = Op * LOG2OFe
3737 // TODO: What fast-math-flags should be set here?
3738 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3739 getF32Constant(DAG, 0x3fb8aa3b, dl));
3740 return getLimitedPrecisionExp2(t0, dl, DAG);
3743 // No special expansion.
3744 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3747 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3748 /// limited-precision mode.
3749 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3750 const TargetLowering &TLI) {
3752 // TODO: What fast-math-flags should be set on the floating-point nodes?
3754 if (Op.getValueType() == MVT::f32 &&
3755 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3756 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3758 // Scale the exponent by log(2) [0.69314718f].
3759 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3760 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3761 getF32Constant(DAG, 0x3f317218, dl));
3763 // Get the significand and build it into a floating-point number with
3765 SDValue X = GetSignificand(DAG, Op1, dl);
3767 SDValue LogOfMantissa;
3768 if (LimitFloatPrecision <= 6) {
3769 // For floating-point precision of 6:
3773 // (1.4034025f - 0.23903021f * x) * x;
3775 // error 0.0034276066, which is better than 8 bits
3776 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3777 getF32Constant(DAG, 0xbe74c456, dl));
3778 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3779 getF32Constant(DAG, 0x3fb3a2b1, dl));
3780 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3781 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3782 getF32Constant(DAG, 0x3f949a29, dl));
3783 } else if (LimitFloatPrecision <= 12) {
3784 // For floating-point precision of 12:
3790 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3792 // error 0.000061011436, which is 14 bits
3793 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3794 getF32Constant(DAG, 0xbd67b6d6, dl));
3795 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3796 getF32Constant(DAG, 0x3ee4f4b8, dl));
3797 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3798 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3799 getF32Constant(DAG, 0x3fbc278b, dl));
3800 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3801 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3802 getF32Constant(DAG, 0x40348e95, dl));
3803 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3804 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3805 getF32Constant(DAG, 0x3fdef31a, dl));
3806 } else { // LimitFloatPrecision <= 18
3807 // For floating-point precision of 18:
3815 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3817 // error 0.0000023660568, which is better than 18 bits
3818 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3819 getF32Constant(DAG, 0xbc91e5ac, dl));
3820 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3821 getF32Constant(DAG, 0x3e4350aa, dl));
3822 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3823 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3824 getF32Constant(DAG, 0x3f60d3e3, dl));
3825 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3826 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3827 getF32Constant(DAG, 0x4011cdf0, dl));
3828 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3829 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3830 getF32Constant(DAG, 0x406cfd1c, dl));
3831 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3832 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3833 getF32Constant(DAG, 0x408797cb, dl));
3834 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3835 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3836 getF32Constant(DAG, 0x4006dcab, dl));
3839 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3842 // No special expansion.
3843 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3846 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3847 /// limited-precision mode.
3848 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3849 const TargetLowering &TLI) {
3851 // TODO: What fast-math-flags should be set on the floating-point nodes?
3853 if (Op.getValueType() == MVT::f32 &&
3854 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3855 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3857 // Get the exponent.
3858 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3860 // Get the significand and build it into a floating-point number with
3862 SDValue X = GetSignificand(DAG, Op1, dl);
3864 // Different possible minimax approximations of significand in
3865 // floating-point for various degrees of accuracy over [1,2].
3866 SDValue Log2ofMantissa;
3867 if (LimitFloatPrecision <= 6) {
3868 // For floating-point precision of 6:
3870 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3872 // error 0.0049451742, which is more than 7 bits
3873 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3874 getF32Constant(DAG, 0xbeb08fe0, dl));
3875 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3876 getF32Constant(DAG, 0x40019463, dl));
3877 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3878 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3879 getF32Constant(DAG, 0x3fd6633d, dl));
3880 } else if (LimitFloatPrecision <= 12) {
3881 // For floating-point precision of 12:
3887 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3889 // error 0.0000876136000, which is better than 13 bits
3890 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3891 getF32Constant(DAG, 0xbda7262e, dl));
3892 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3893 getF32Constant(DAG, 0x3f25280b, dl));
3894 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3895 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3896 getF32Constant(DAG, 0x4007b923, dl));
3897 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3898 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3899 getF32Constant(DAG, 0x40823e2f, dl));
3900 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3901 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3902 getF32Constant(DAG, 0x4020d29c, dl));
3903 } else { // LimitFloatPrecision <= 18
3904 // For floating-point precision of 18:
3913 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3915 // error 0.0000018516, which is better than 18 bits
3916 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3917 getF32Constant(DAG, 0xbcd2769e, dl));
3918 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3919 getF32Constant(DAG, 0x3e8ce0b9, dl));
3920 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3921 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3922 getF32Constant(DAG, 0x3fa22ae7, dl));
3923 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3924 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3925 getF32Constant(DAG, 0x40525723, dl));
3926 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3927 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3928 getF32Constant(DAG, 0x40aaf200, dl));
3929 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3930 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3931 getF32Constant(DAG, 0x40c39dad, dl));
3932 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3933 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3934 getF32Constant(DAG, 0x4042902c, dl));
3937 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3940 // No special expansion.
3941 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3944 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3945 /// limited-precision mode.
3946 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3947 const TargetLowering &TLI) {
3949 // TODO: What fast-math-flags should be set on the floating-point nodes?
3951 if (Op.getValueType() == MVT::f32 &&
3952 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3953 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3955 // Scale the exponent by log10(2) [0.30102999f].
3956 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3957 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3958 getF32Constant(DAG, 0x3e9a209a, dl));
3960 // Get the significand and build it into a floating-point number with
3962 SDValue X = GetSignificand(DAG, Op1, dl);
3964 SDValue Log10ofMantissa;
3965 if (LimitFloatPrecision <= 6) {
3966 // For floating-point precision of 6:
3968 // Log10ofMantissa =
3970 // (0.60948995f - 0.10380950f * x) * x;
3972 // error 0.0014886165, which is 6 bits
3973 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3974 getF32Constant(DAG, 0xbdd49a13, dl));
3975 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3976 getF32Constant(DAG, 0x3f1c0789, dl));
3977 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3978 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3979 getF32Constant(DAG, 0x3f011300, dl));
3980 } else if (LimitFloatPrecision <= 12) {
3981 // For floating-point precision of 12:
3983 // Log10ofMantissa =
3986 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3988 // error 0.00019228036, which is better than 12 bits
3989 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3990 getF32Constant(DAG, 0x3d431f31, dl));
3991 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3992 getF32Constant(DAG, 0x3ea21fb2, dl));
3993 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3994 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3995 getF32Constant(DAG, 0x3f6ae232, dl));
3996 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3997 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3998 getF32Constant(DAG, 0x3f25f7c3, dl));
3999 } else { // LimitFloatPrecision <= 18
4000 // For floating-point precision of 18:
4002 // Log10ofMantissa =
4007 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4009 // error 0.0000037995730, which is better than 18 bits
4010 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4011 getF32Constant(DAG, 0x3c5d51ce, dl));
4012 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4013 getF32Constant(DAG, 0x3e00685a, dl));
4014 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4015 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4016 getF32Constant(DAG, 0x3efb6798, dl));
4017 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4018 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4019 getF32Constant(DAG, 0x3f88d192, dl));
4020 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4021 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4022 getF32Constant(DAG, 0x3fc4316c, dl));
4023 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4024 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4025 getF32Constant(DAG, 0x3f57ce70, dl));
4028 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4031 // No special expansion.
4032 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4035 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4036 /// limited-precision mode.
4037 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4038 const TargetLowering &TLI) {
4039 if (Op.getValueType() == MVT::f32 &&
4040 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4041 return getLimitedPrecisionExp2(Op, dl, DAG);
4043 // No special expansion.
4044 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4047 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4048 /// limited-precision mode with x == 10.0f.
4049 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4050 SelectionDAG &DAG, const TargetLowering &TLI) {
4051 bool IsExp10 = false;
4052 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4053 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4054 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4056 IsExp10 = LHSC->isExactlyValue(Ten);
4060 // TODO: What fast-math-flags should be set on the FMUL node?
4062 // Put the exponent in the right bit position for later addition to the
4065 // #define LOG2OF10 3.3219281f
4066 // t0 = Op * LOG2OF10;
4067 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4068 getF32Constant(DAG, 0x40549a78, dl));
4069 return getLimitedPrecisionExp2(t0, dl, DAG);
4072 // No special expansion.
4073 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4077 /// ExpandPowI - Expand a llvm.powi intrinsic.
4078 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4079 SelectionDAG &DAG) {
4080 // If RHS is a constant, we can expand this out to a multiplication tree,
4081 // otherwise we end up lowering to a call to __powidf2 (for example). When
4082 // optimizing for size, we only want to do this if the expansion would produce
4083 // a small number of multiplies, otherwise we do the full expansion.
4084 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4085 // Get the exponent as a positive value.
4086 unsigned Val = RHSC->getSExtValue();
4087 if ((int)Val < 0) Val = -Val;
4089 // powi(x, 0) -> 1.0
4091 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4093 const Function *F = DAG.getMachineFunction().getFunction();
4094 if (!F->optForSize() ||
4095 // If optimizing for size, don't insert too many multiplies.
4096 // This inserts up to 5 multiplies.
4097 countPopulation(Val) + Log2_32(Val) < 7) {
4098 // We use the simple binary decomposition method to generate the multiply
4099 // sequence. There are more optimal ways to do this (for example,
4100 // powi(x,15) generates one more multiply than it should), but this has
4101 // the benefit of being both really simple and much better than a libcall.
4102 SDValue Res; // Logically starts equal to 1.0
4103 SDValue CurSquare = LHS;
4104 // TODO: Intrinsics should have fast-math-flags that propagate to these
4109 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4111 Res = CurSquare; // 1.0*CurSquare.
4114 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4115 CurSquare, CurSquare);
4119 // If the original was negative, invert the result, producing 1/(x*x*x).
4120 if (RHSC->getSExtValue() < 0)
4121 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4122 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4127 // Otherwise, expand to a libcall.
4128 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4131 // getTruncatedArgReg - Find underlying register used for an truncated
4133 static unsigned getTruncatedArgReg(const SDValue &N) {
4134 if (N.getOpcode() != ISD::TRUNCATE)
4137 const SDValue &Ext = N.getOperand(0);
4138 if (Ext.getOpcode() == ISD::AssertZext ||
4139 Ext.getOpcode() == ISD::AssertSext) {
4140 const SDValue &CFR = Ext.getOperand(0);
4141 if (CFR.getOpcode() == ISD::CopyFromReg)
4142 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4143 if (CFR.getOpcode() == ISD::TRUNCATE)
4144 return getTruncatedArgReg(CFR);
4149 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4150 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4151 /// At the end of instruction selection, they will be inserted to the entry BB.
4152 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4153 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4154 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4155 const Argument *Arg = dyn_cast<Argument>(V);
4159 MachineFunction &MF = DAG.getMachineFunction();
4160 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4162 // Ignore inlined function arguments here.
4164 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4165 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4168 Optional<MachineOperand> Op;
4169 // Some arguments' frame index is recorded during argument lowering.
4170 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4171 Op = MachineOperand::CreateFI(FI);
4173 if (!Op && N.getNode()) {
4175 if (N.getOpcode() == ISD::CopyFromReg)
4176 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4178 Reg = getTruncatedArgReg(N);
4179 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4180 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4181 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4186 Op = MachineOperand::CreateReg(Reg, false);
4190 // Check if ValueMap has reg number.
4191 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4192 if (VMI != FuncInfo.ValueMap.end())
4193 Op = MachineOperand::CreateReg(VMI->second, false);
4196 if (!Op && N.getNode())
4197 // Check if frame index is available.
4198 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4199 if (FrameIndexSDNode *FINode =
4200 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4201 Op = MachineOperand::CreateFI(FINode->getIndex());
4206 assert(Variable->isValidLocationForIntrinsic(DL) &&
4207 "Expected inlined-at fields to agree");
4209 FuncInfo.ArgDbgValues.push_back(
4210 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4211 Op->getReg(), Offset, Variable, Expr));
4213 FuncInfo.ArgDbgValues.push_back(
4214 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4217 .addMetadata(Variable)
4218 .addMetadata(Expr));
4223 // VisualStudio defines setjmp as _setjmp
4224 #if defined(_MSC_VER) && defined(setjmp) && \
4225 !defined(setjmp_undefined_for_msvc)
4226 # pragma push_macro("setjmp")
4228 # define setjmp_undefined_for_msvc
4231 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4232 /// we want to emit this as a call to a named external function, return the name
4233 /// otherwise lower it and return null.
4235 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4236 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4237 SDLoc sdl = getCurSDLoc();
4238 DebugLoc dl = getCurDebugLoc();
4241 switch (Intrinsic) {
4243 // By default, turn this into a target intrinsic node.
4244 visitTargetIntrinsic(I, Intrinsic);
4246 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4247 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4248 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4249 case Intrinsic::returnaddress:
4250 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4251 TLI.getPointerTy(DAG.getDataLayout()),
4252 getValue(I.getArgOperand(0))));
4254 case Intrinsic::frameaddress:
4255 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4256 TLI.getPointerTy(DAG.getDataLayout()),
4257 getValue(I.getArgOperand(0))));
4259 case Intrinsic::read_register: {
4260 Value *Reg = I.getArgOperand(0);
4261 SDValue Chain = getRoot();
4263 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4264 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4265 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4266 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4268 DAG.setRoot(Res.getValue(1));
4271 case Intrinsic::write_register: {
4272 Value *Reg = I.getArgOperand(0);
4273 Value *RegValue = I.getArgOperand(1);
4274 SDValue Chain = getRoot();
4276 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4277 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4278 RegName, getValue(RegValue)));
4281 case Intrinsic::setjmp:
4282 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4283 case Intrinsic::longjmp:
4284 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4285 case Intrinsic::memcpy: {
4286 // FIXME: this definition of "user defined address space" is x86-specific
4287 // Assert for address < 256 since we support only user defined address
4289 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4291 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4293 "Unknown address space");
4294 SDValue Op1 = getValue(I.getArgOperand(0));
4295 SDValue Op2 = getValue(I.getArgOperand(1));
4296 SDValue Op3 = getValue(I.getArgOperand(2));
4297 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4299 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4300 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4301 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4302 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4304 MachinePointerInfo(I.getArgOperand(0)),
4305 MachinePointerInfo(I.getArgOperand(1)));
4306 updateDAGForMaybeTailCall(MC);
4309 case Intrinsic::memset: {
4310 // FIXME: this definition of "user defined address space" is x86-specific
4311 // Assert for address < 256 since we support only user defined address
4313 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4315 "Unknown address space");
4316 SDValue Op1 = getValue(I.getArgOperand(0));
4317 SDValue Op2 = getValue(I.getArgOperand(1));
4318 SDValue Op3 = getValue(I.getArgOperand(2));
4319 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4321 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4322 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4323 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4324 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4325 isTC, MachinePointerInfo(I.getArgOperand(0)));
4326 updateDAGForMaybeTailCall(MS);
4329 case Intrinsic::memmove: {
4330 // FIXME: this definition of "user defined address space" is x86-specific
4331 // Assert for address < 256 since we support only user defined address
4333 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4335 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4337 "Unknown address space");
4338 SDValue Op1 = getValue(I.getArgOperand(0));
4339 SDValue Op2 = getValue(I.getArgOperand(1));
4340 SDValue Op3 = getValue(I.getArgOperand(2));
4341 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4343 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4344 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4345 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4346 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4347 isTC, MachinePointerInfo(I.getArgOperand(0)),
4348 MachinePointerInfo(I.getArgOperand(1)));
4349 updateDAGForMaybeTailCall(MM);
4352 case Intrinsic::dbg_declare: {
4353 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4354 DILocalVariable *Variable = DI.getVariable();
4355 DIExpression *Expression = DI.getExpression();
4356 const Value *Address = DI.getAddress();
4357 assert(Variable && "Missing variable");
4359 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4363 // Check if address has undef value.
4364 if (isa<UndefValue>(Address) ||
4365 (Address->use_empty() && !isa<Argument>(Address))) {
4366 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4370 SDValue &N = NodeMap[Address];
4371 if (!N.getNode() && isa<Argument>(Address))
4372 // Check unused arguments map.
4373 N = UnusedArgNodeMap[Address];
4376 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4377 Address = BCI->getOperand(0);
4378 // Parameters are handled specially.
4379 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4381 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4383 if (isParameter && !AI) {
4384 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4386 // Byval parameter. We have a frame index at this point.
4387 SDV = DAG.getFrameIndexDbgValue(
4388 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4390 // Address is an argument, so try to emit its dbg value using
4391 // virtual register info from the FuncInfo.ValueMap.
4392 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4397 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4398 true, 0, dl, SDNodeOrder);
4400 // Can't do anything with other non-AI cases yet.
4401 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4402 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4403 DEBUG(Address->dump());
4406 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4408 // If Address is an argument then try to emit its dbg value using
4409 // virtual register info from the FuncInfo.ValueMap.
4410 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4412 // If variable is pinned by a alloca in dominating bb then
4413 // use StaticAllocaMap.
4414 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4415 if (AI->getParent() != DI.getParent()) {
4416 DenseMap<const AllocaInst*, int>::iterator SI =
4417 FuncInfo.StaticAllocaMap.find(AI);
4418 if (SI != FuncInfo.StaticAllocaMap.end()) {
4419 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4420 0, dl, SDNodeOrder);
4421 DAG.AddDbgValue(SDV, nullptr, false);
4426 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4431 case Intrinsic::dbg_value: {
4432 const DbgValueInst &DI = cast<DbgValueInst>(I);
4433 assert(DI.getVariable() && "Missing variable");
4435 DILocalVariable *Variable = DI.getVariable();
4436 DIExpression *Expression = DI.getExpression();
4437 uint64_t Offset = DI.getOffset();
4438 const Value *V = DI.getValue();
4443 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4444 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4446 DAG.AddDbgValue(SDV, nullptr, false);
4448 // Do not use getValue() in here; we don't want to generate code at
4449 // this point if it hasn't been done yet.
4450 SDValue N = NodeMap[V];
4451 if (!N.getNode() && isa<Argument>(V))
4452 // Check unused arguments map.
4453 N = UnusedArgNodeMap[V];
4455 // A dbg.value for an alloca is always indirect.
4456 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4457 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4459 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4460 IsIndirect, Offset, dl, SDNodeOrder);
4461 DAG.AddDbgValue(SDV, N.getNode(), false);
4463 } else if (!V->use_empty() ) {
4464 // Do not call getValue(V) yet, as we don't want to generate code.
4465 // Remember it for later.
4466 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4467 DanglingDebugInfoMap[V] = DDI;
4469 // We may expand this to cover more cases. One case where we have no
4470 // data available is an unreferenced parameter.
4471 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4475 // Build a debug info table entry.
4476 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4477 V = BCI->getOperand(0);
4478 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4479 // Don't handle byval struct arguments or VLAs, for example.
4481 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4482 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4485 DenseMap<const AllocaInst*, int>::iterator SI =
4486 FuncInfo.StaticAllocaMap.find(AI);
4487 if (SI == FuncInfo.StaticAllocaMap.end())
4488 return nullptr; // VLAs.
4492 case Intrinsic::eh_typeid_for: {
4493 // Find the type id for the given typeinfo.
4494 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4495 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4496 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4501 case Intrinsic::eh_return_i32:
4502 case Intrinsic::eh_return_i64:
4503 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4504 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4507 getValue(I.getArgOperand(0)),
4508 getValue(I.getArgOperand(1))));
4510 case Intrinsic::eh_unwind_init:
4511 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4513 case Intrinsic::eh_dwarf_cfa: {
4514 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4515 TLI.getPointerTy(DAG.getDataLayout()));
4516 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4517 CfaArg.getValueType(),
4518 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4519 CfaArg.getValueType()),
4521 SDValue FA = DAG.getNode(
4522 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4523 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4524 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4528 case Intrinsic::eh_sjlj_callsite: {
4529 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4530 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4531 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4532 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4534 MMI.setCurrentCallSite(CI->getZExtValue());
4537 case Intrinsic::eh_sjlj_functioncontext: {
4538 // Get and store the index of the function context.
4539 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4541 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4542 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4543 MFI->setFunctionContextIndex(FI);
4546 case Intrinsic::eh_sjlj_setjmp: {
4549 Ops[1] = getValue(I.getArgOperand(0));
4550 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4551 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4552 setValue(&I, Op.getValue(0));
4553 DAG.setRoot(Op.getValue(1));
4556 case Intrinsic::eh_sjlj_longjmp: {
4557 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4558 getRoot(), getValue(I.getArgOperand(0))));
4561 case Intrinsic::eh_sjlj_setup_dispatch: {
4562 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4567 case Intrinsic::masked_gather:
4568 visitMaskedGather(I);
4570 case Intrinsic::masked_load:
4573 case Intrinsic::masked_scatter:
4574 visitMaskedScatter(I);
4576 case Intrinsic::masked_store:
4577 visitMaskedStore(I);
4579 case Intrinsic::x86_mmx_pslli_w:
4580 case Intrinsic::x86_mmx_pslli_d:
4581 case Intrinsic::x86_mmx_pslli_q:
4582 case Intrinsic::x86_mmx_psrli_w:
4583 case Intrinsic::x86_mmx_psrli_d:
4584 case Intrinsic::x86_mmx_psrli_q:
4585 case Intrinsic::x86_mmx_psrai_w:
4586 case Intrinsic::x86_mmx_psrai_d: {
4587 SDValue ShAmt = getValue(I.getArgOperand(1));
4588 if (isa<ConstantSDNode>(ShAmt)) {
4589 visitTargetIntrinsic(I, Intrinsic);
4592 unsigned NewIntrinsic = 0;
4593 EVT ShAmtVT = MVT::v2i32;
4594 switch (Intrinsic) {
4595 case Intrinsic::x86_mmx_pslli_w:
4596 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4598 case Intrinsic::x86_mmx_pslli_d:
4599 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4601 case Intrinsic::x86_mmx_pslli_q:
4602 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4604 case Intrinsic::x86_mmx_psrli_w:
4605 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4607 case Intrinsic::x86_mmx_psrli_d:
4608 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4610 case Intrinsic::x86_mmx_psrli_q:
4611 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4613 case Intrinsic::x86_mmx_psrai_w:
4614 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4616 case Intrinsic::x86_mmx_psrai_d:
4617 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4619 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4622 // The vector shift intrinsics with scalars uses 32b shift amounts but
4623 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4625 // We must do this early because v2i32 is not a legal type.
4628 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4629 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4630 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4631 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4632 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4633 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4634 getValue(I.getArgOperand(0)), ShAmt);
4638 case Intrinsic::convertff:
4639 case Intrinsic::convertfsi:
4640 case Intrinsic::convertfui:
4641 case Intrinsic::convertsif:
4642 case Intrinsic::convertuif:
4643 case Intrinsic::convertss:
4644 case Intrinsic::convertsu:
4645 case Intrinsic::convertus:
4646 case Intrinsic::convertuu: {
4647 ISD::CvtCode Code = ISD::CVT_INVALID;
4648 switch (Intrinsic) {
4649 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4650 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4651 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4652 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4653 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4654 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4655 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4656 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4657 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4658 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4660 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4661 const Value *Op1 = I.getArgOperand(0);
4662 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4663 DAG.getValueType(DestVT),
4664 DAG.getValueType(getValue(Op1).getValueType()),
4665 getValue(I.getArgOperand(1)),
4666 getValue(I.getArgOperand(2)),
4671 case Intrinsic::powi:
4672 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4673 getValue(I.getArgOperand(1)), DAG));
4675 case Intrinsic::log:
4676 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4678 case Intrinsic::log2:
4679 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4681 case Intrinsic::log10:
4682 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4684 case Intrinsic::exp:
4685 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4687 case Intrinsic::exp2:
4688 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4690 case Intrinsic::pow:
4691 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4692 getValue(I.getArgOperand(1)), DAG, TLI));
4694 case Intrinsic::sqrt:
4695 case Intrinsic::fabs:
4696 case Intrinsic::sin:
4697 case Intrinsic::cos:
4698 case Intrinsic::floor:
4699 case Intrinsic::ceil:
4700 case Intrinsic::trunc:
4701 case Intrinsic::rint:
4702 case Intrinsic::nearbyint:
4703 case Intrinsic::round: {
4705 switch (Intrinsic) {
4706 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4707 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4708 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4709 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4710 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4711 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4712 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4713 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4714 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4715 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4716 case Intrinsic::round: Opcode = ISD::FROUND; break;
4719 setValue(&I, DAG.getNode(Opcode, sdl,
4720 getValue(I.getArgOperand(0)).getValueType(),
4721 getValue(I.getArgOperand(0))));
4724 case Intrinsic::minnum:
4725 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4726 getValue(I.getArgOperand(0)).getValueType(),
4727 getValue(I.getArgOperand(0)),
4728 getValue(I.getArgOperand(1))));
4730 case Intrinsic::maxnum:
4731 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4732 getValue(I.getArgOperand(0)).getValueType(),
4733 getValue(I.getArgOperand(0)),
4734 getValue(I.getArgOperand(1))));
4736 case Intrinsic::copysign:
4737 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4738 getValue(I.getArgOperand(0)).getValueType(),
4739 getValue(I.getArgOperand(0)),
4740 getValue(I.getArgOperand(1))));
4742 case Intrinsic::fma:
4743 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4744 getValue(I.getArgOperand(0)).getValueType(),
4745 getValue(I.getArgOperand(0)),
4746 getValue(I.getArgOperand(1)),
4747 getValue(I.getArgOperand(2))));
4749 case Intrinsic::fmuladd: {
4750 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4751 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4752 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4753 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4754 getValue(I.getArgOperand(0)).getValueType(),
4755 getValue(I.getArgOperand(0)),
4756 getValue(I.getArgOperand(1)),
4757 getValue(I.getArgOperand(2))));
4759 // TODO: Intrinsic calls should have fast-math-flags.
4760 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4761 getValue(I.getArgOperand(0)).getValueType(),
4762 getValue(I.getArgOperand(0)),
4763 getValue(I.getArgOperand(1)));
4764 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4765 getValue(I.getArgOperand(0)).getValueType(),
4767 getValue(I.getArgOperand(2)));
4772 case Intrinsic::convert_to_fp16:
4773 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4774 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4775 getValue(I.getArgOperand(0)),
4776 DAG.getTargetConstant(0, sdl,
4779 case Intrinsic::convert_from_fp16:
4780 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4781 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4782 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4783 getValue(I.getArgOperand(0)))));
4785 case Intrinsic::pcmarker: {
4786 SDValue Tmp = getValue(I.getArgOperand(0));
4787 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4790 case Intrinsic::readcyclecounter: {
4791 SDValue Op = getRoot();
4792 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4793 DAG.getVTList(MVT::i64, MVT::Other), Op);
4795 DAG.setRoot(Res.getValue(1));
4798 case Intrinsic::bswap:
4799 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4800 getValue(I.getArgOperand(0)).getValueType(),
4801 getValue(I.getArgOperand(0))));
4803 case Intrinsic::uabsdiff:
4804 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4805 getValue(I.getArgOperand(0)).getValueType(),
4806 getValue(I.getArgOperand(0)),
4807 getValue(I.getArgOperand(1))));
4809 case Intrinsic::sabsdiff:
4810 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4811 getValue(I.getArgOperand(0)).getValueType(),
4812 getValue(I.getArgOperand(0)),
4813 getValue(I.getArgOperand(1))));
4815 case Intrinsic::cttz: {
4816 SDValue Arg = getValue(I.getArgOperand(0));
4817 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4818 EVT Ty = Arg.getValueType();
4819 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4823 case Intrinsic::ctlz: {
4824 SDValue Arg = getValue(I.getArgOperand(0));
4825 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4826 EVT Ty = Arg.getValueType();
4827 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4831 case Intrinsic::ctpop: {
4832 SDValue Arg = getValue(I.getArgOperand(0));
4833 EVT Ty = Arg.getValueType();
4834 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4837 case Intrinsic::stacksave: {
4838 SDValue Op = getRoot();
4840 ISD::STACKSAVE, sdl,
4841 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4843 DAG.setRoot(Res.getValue(1));
4846 case Intrinsic::stackrestore: {
4847 Res = getValue(I.getArgOperand(0));
4848 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4851 case Intrinsic::stackprotector: {
4852 // Emit code into the DAG to store the stack guard onto the stack.
4853 MachineFunction &MF = DAG.getMachineFunction();
4854 MachineFrameInfo *MFI = MF.getFrameInfo();
4855 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4856 SDValue Src, Chain = getRoot();
4857 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4858 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4860 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4861 // global variable __stack_chk_guard.
4863 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4864 if (BC->getOpcode() == Instruction::BitCast)
4865 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4867 if (GV && TLI.useLoadStackGuardNode()) {
4868 // Emit a LOAD_STACK_GUARD node.
4869 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4871 MachinePointerInfo MPInfo(GV);
4872 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4873 unsigned Flags = MachineMemOperand::MOLoad |
4874 MachineMemOperand::MOInvariant;
4875 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4876 PtrTy.getSizeInBits() / 8,
4877 DAG.getEVTAlignment(PtrTy));
4878 Node->setMemRefs(MemRefs, MemRefs + 1);
4880 // Copy the guard value to a virtual register so that it can be
4881 // retrieved in the epilogue.
4882 Src = SDValue(Node, 0);
4883 const TargetRegisterClass *RC =
4884 TLI.getRegClassFor(Src.getSimpleValueType());
4885 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4887 SPDescriptor.setGuardReg(Reg);
4888 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4890 Src = getValue(I.getArgOperand(0)); // The guard's value.
4893 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4895 int FI = FuncInfo.StaticAllocaMap[Slot];
4896 MFI->setStackProtectorIndex(FI);
4898 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4900 // Store the stack protector onto the stack.
4901 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4902 DAG.getMachineFunction(), FI),
4908 case Intrinsic::objectsize: {
4909 // If we don't know by now, we're never going to know.
4910 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4912 assert(CI && "Non-constant type in __builtin_object_size?");
4914 SDValue Arg = getValue(I.getCalledValue());
4915 EVT Ty = Arg.getValueType();
4918 Res = DAG.getConstant(-1ULL, sdl, Ty);
4920 Res = DAG.getConstant(0, sdl, Ty);
4925 case Intrinsic::annotation:
4926 case Intrinsic::ptr_annotation:
4927 // Drop the intrinsic, but forward the value
4928 setValue(&I, getValue(I.getOperand(0)));
4930 case Intrinsic::assume:
4931 case Intrinsic::var_annotation:
4932 // Discard annotate attributes and assumptions
4935 case Intrinsic::init_trampoline: {
4936 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4940 Ops[1] = getValue(I.getArgOperand(0));
4941 Ops[2] = getValue(I.getArgOperand(1));
4942 Ops[3] = getValue(I.getArgOperand(2));
4943 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4944 Ops[5] = DAG.getSrcValue(F);
4946 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4951 case Intrinsic::adjust_trampoline: {
4952 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4953 TLI.getPointerTy(DAG.getDataLayout()),
4954 getValue(I.getArgOperand(0))));
4957 case Intrinsic::gcroot:
4959 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4960 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4962 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4963 GFI->addStackRoot(FI->getIndex(), TypeMap);
4966 case Intrinsic::gcread:
4967 case Intrinsic::gcwrite:
4968 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4969 case Intrinsic::flt_rounds:
4970 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4973 case Intrinsic::expect: {
4974 // Just replace __builtin_expect(exp, c) with EXP.
4975 setValue(&I, getValue(I.getArgOperand(0)));
4979 case Intrinsic::debugtrap:
4980 case Intrinsic::trap: {
4981 StringRef TrapFuncName =
4983 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4984 .getValueAsString();
4985 if (TrapFuncName.empty()) {
4986 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4987 ISD::TRAP : ISD::DEBUGTRAP;
4988 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4991 TargetLowering::ArgListTy Args;
4993 TargetLowering::CallLoweringInfo CLI(DAG);
4994 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4995 CallingConv::C, I.getType(),
4996 DAG.getExternalSymbol(TrapFuncName.data(),
4997 TLI.getPointerTy(DAG.getDataLayout())),
4998 std::move(Args), 0);
5000 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5001 DAG.setRoot(Result.second);
5005 case Intrinsic::uadd_with_overflow:
5006 case Intrinsic::sadd_with_overflow:
5007 case Intrinsic::usub_with_overflow:
5008 case Intrinsic::ssub_with_overflow:
5009 case Intrinsic::umul_with_overflow:
5010 case Intrinsic::smul_with_overflow: {
5012 switch (Intrinsic) {
5013 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5014 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5015 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5016 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5017 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5018 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5019 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5021 SDValue Op1 = getValue(I.getArgOperand(0));
5022 SDValue Op2 = getValue(I.getArgOperand(1));
5024 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5025 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5028 case Intrinsic::prefetch: {
5030 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5032 Ops[1] = getValue(I.getArgOperand(0));
5033 Ops[2] = getValue(I.getArgOperand(1));
5034 Ops[3] = getValue(I.getArgOperand(2));
5035 Ops[4] = getValue(I.getArgOperand(3));
5036 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5037 DAG.getVTList(MVT::Other), Ops,
5038 EVT::getIntegerVT(*Context, 8),
5039 MachinePointerInfo(I.getArgOperand(0)),
5041 false, /* volatile */
5043 rw==1)); /* write */
5046 case Intrinsic::lifetime_start:
5047 case Intrinsic::lifetime_end: {
5048 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5049 // Stack coloring is not enabled in O0, discard region information.
5050 if (TM.getOptLevel() == CodeGenOpt::None)
5053 SmallVector<Value *, 4> Allocas;
5054 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5056 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5057 E = Allocas.end(); Object != E; ++Object) {
5058 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5060 // Could not find an Alloca.
5061 if (!LifetimeObject)
5064 // First check that the Alloca is static, otherwise it won't have a
5065 // valid frame index.
5066 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5067 if (SI == FuncInfo.StaticAllocaMap.end())
5070 int FI = SI->second;
5075 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5076 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5078 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5083 case Intrinsic::invariant_start:
5084 // Discard region information.
5085 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5087 case Intrinsic::invariant_end:
5088 // Discard region information.
5090 case Intrinsic::stackprotectorcheck: {
5091 // Do not actually emit anything for this basic block. Instead we initialize
5092 // the stack protector descriptor and export the guard variable so we can
5093 // access it in FinishBasicBlock.
5094 const BasicBlock *BB = I.getParent();
5095 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5096 ExportFromCurrentBlock(SPDescriptor.getGuard());
5098 // Flush our exports since we are going to process a terminator.
5099 (void)getControlRoot();
5102 case Intrinsic::clear_cache:
5103 return TLI.getClearCacheBuiltinName();
5104 case Intrinsic::eh_actions:
5105 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5107 case Intrinsic::donothing:
5110 case Intrinsic::experimental_stackmap: {
5114 case Intrinsic::experimental_patchpoint_void:
5115 case Intrinsic::experimental_patchpoint_i64: {
5116 visitPatchpoint(&I);
5119 case Intrinsic::experimental_gc_statepoint: {
5123 case Intrinsic::experimental_gc_result_int:
5124 case Intrinsic::experimental_gc_result_float:
5125 case Intrinsic::experimental_gc_result_ptr:
5126 case Intrinsic::experimental_gc_result: {
5130 case Intrinsic::experimental_gc_relocate: {
5134 case Intrinsic::instrprof_increment:
5135 llvm_unreachable("instrprof failed to lower an increment");
5137 case Intrinsic::localescape: {
5138 MachineFunction &MF = DAG.getMachineFunction();
5139 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5141 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5142 // is the same on all targets.
5143 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5144 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5145 if (isa<ConstantPointerNull>(Arg))
5146 continue; // Skip null pointers. They represent a hole in index space.
5147 AllocaInst *Slot = cast<AllocaInst>(Arg);
5148 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5149 "can only escape static allocas");
5150 int FI = FuncInfo.StaticAllocaMap[Slot];
5151 MCSymbol *FrameAllocSym =
5152 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5153 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5154 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5155 TII->get(TargetOpcode::LOCAL_ESCAPE))
5156 .addSym(FrameAllocSym)
5163 case Intrinsic::localrecover: {
5164 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5165 MachineFunction &MF = DAG.getMachineFunction();
5166 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5168 // Get the symbol that defines the frame offset.
5169 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5170 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5171 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5172 MCSymbol *FrameAllocSym =
5173 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5174 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5176 // Create a MCSymbol for the label to avoid any target lowering
5177 // that would make this PC relative.
5178 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5180 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5182 // Add the offset to the FP.
5183 Value *FP = I.getArgOperand(1);
5184 SDValue FPVal = getValue(FP);
5185 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5190 case Intrinsic::eh_begincatch:
5191 case Intrinsic::eh_endcatch:
5192 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5193 case Intrinsic::eh_exceptioncode: {
5194 unsigned Reg = TLI.getExceptionPointerRegister();
5195 assert(Reg && "cannot get exception code on this platform");
5196 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5197 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5198 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5199 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5201 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5202 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5209 std::pair<SDValue, SDValue>
5210 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5211 const BasicBlock *EHPadBB) {
5212 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5213 MCSymbol *BeginLabel = nullptr;
5216 // Insert a label before the invoke call to mark the try range. This can be
5217 // used to detect deletion of the invoke via the MachineModuleInfo.
5218 BeginLabel = MMI.getContext().createTempSymbol();
5220 // For SjLj, keep track of which landing pads go with which invokes
5221 // so as to maintain the ordering of pads in the LSDA.
5222 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5223 if (CallSiteIndex) {
5224 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5225 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5227 // Now that the call site is handled, stop tracking it.
5228 MMI.setCurrentCallSite(0);
5231 // Both PendingLoads and PendingExports must be flushed here;
5232 // this call might not return.
5234 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5236 CLI.setChain(getRoot());
5238 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5239 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5241 assert((CLI.IsTailCall || Result.second.getNode()) &&
5242 "Non-null chain expected with non-tail call!");
5243 assert((Result.second.getNode() || !Result.first.getNode()) &&
5244 "Null value expected with tail call!");
5246 if (!Result.second.getNode()) {
5247 // As a special case, a null chain means that a tail call has been emitted
5248 // and the DAG root is already updated.
5251 // Since there's no actual continuation from this block, nothing can be
5252 // relying on us setting vregs for them.
5253 PendingExports.clear();
5255 DAG.setRoot(Result.second);
5259 // Insert a label at the end of the invoke call to mark the try range. This
5260 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5261 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5262 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5264 // Inform MachineModuleInfo of range.
5265 if (MMI.hasEHFunclets()) {
5266 WinEHFuncInfo &EHInfo =
5267 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5268 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5270 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5277 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5279 const BasicBlock *EHPadBB) {
5280 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5281 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5282 Type *RetTy = FTy->getReturnType();
5284 TargetLowering::ArgListTy Args;
5285 TargetLowering::ArgListEntry Entry;
5286 Args.reserve(CS.arg_size());
5288 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5290 const Value *V = *i;
5293 if (V->getType()->isEmptyTy())
5296 SDValue ArgNode = getValue(V);
5297 Entry.Node = ArgNode; Entry.Ty = V->getType();
5299 // Skip the first return-type Attribute to get to params.
5300 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5301 Args.push_back(Entry);
5303 // If we have an explicit sret argument that is an Instruction, (i.e., it
5304 // might point to function-local memory), we can't meaningfully tail-call.
5305 if (Entry.isSRet && isa<Instruction>(V))
5309 // Check if target-independent constraints permit a tail call here.
5310 // Target-dependent constraints are checked within TLI->LowerCallTo.
5311 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5314 TargetLowering::CallLoweringInfo CLI(DAG);
5315 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5316 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5317 .setTailCall(isTailCall);
5318 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5320 if (Result.first.getNode())
5321 setValue(CS.getInstruction(), Result.first);
5324 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5325 /// value is equal or not-equal to zero.
5326 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5327 for (const User *U : V->users()) {
5328 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5329 if (IC->isEquality())
5330 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5331 if (C->isNullValue())
5333 // Unknown instruction.
5339 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5341 SelectionDAGBuilder &Builder) {
5343 // Check to see if this load can be trivially constant folded, e.g. if the
5344 // input is from a string literal.
5345 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5346 // Cast pointer to the type we really want to load.
5347 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5348 PointerType::getUnqual(LoadTy));
5350 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5351 const_cast<Constant *>(LoadInput), *Builder.DL))
5352 return Builder.getValue(LoadCst);
5355 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5356 // still constant memory, the input chain can be the entry node.
5358 bool ConstantMemory = false;
5360 // Do not serialize (non-volatile) loads of constant memory with anything.
5361 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5362 Root = Builder.DAG.getEntryNode();
5363 ConstantMemory = true;
5365 // Do not serialize non-volatile loads against each other.
5366 Root = Builder.DAG.getRoot();
5369 SDValue Ptr = Builder.getValue(PtrVal);
5370 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5371 Ptr, MachinePointerInfo(PtrVal),
5373 false /*nontemporal*/,
5374 false /*isinvariant*/, 1 /* align=1 */);
5376 if (!ConstantMemory)
5377 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5381 /// processIntegerCallValue - Record the value for an instruction that
5382 /// produces an integer result, converting the type where necessary.
5383 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5386 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5389 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5391 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5392 setValue(&I, Value);
5395 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5396 /// If so, return true and lower it, otherwise return false and it will be
5397 /// lowered like a normal call.
5398 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5399 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5400 if (I.getNumArgOperands() != 3)
5403 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5404 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5405 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5406 !I.getType()->isIntegerTy())
5409 const Value *Size = I.getArgOperand(2);
5410 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5411 if (CSize && CSize->getZExtValue() == 0) {
5412 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5414 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5418 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5419 std::pair<SDValue, SDValue> Res =
5420 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5421 getValue(LHS), getValue(RHS), getValue(Size),
5422 MachinePointerInfo(LHS),
5423 MachinePointerInfo(RHS));
5424 if (Res.first.getNode()) {
5425 processIntegerCallValue(I, Res.first, true);
5426 PendingLoads.push_back(Res.second);
5430 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5431 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5432 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5433 bool ActuallyDoIt = true;
5436 switch (CSize->getZExtValue()) {
5438 LoadVT = MVT::Other;
5440 ActuallyDoIt = false;
5444 LoadTy = Type::getInt16Ty(CSize->getContext());
5448 LoadTy = Type::getInt32Ty(CSize->getContext());
5452 LoadTy = Type::getInt64Ty(CSize->getContext());
5456 LoadVT = MVT::v4i32;
5457 LoadTy = Type::getInt32Ty(CSize->getContext());
5458 LoadTy = VectorType::get(LoadTy, 4);
5463 // This turns into unaligned loads. We only do this if the target natively
5464 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5465 // we'll only produce a small number of byte loads.
5467 // Require that we can find a legal MVT, and only do this if the target
5468 // supports unaligned loads of that type. Expanding into byte loads would
5470 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5471 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5472 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5473 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5474 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5475 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5476 // TODO: Check alignment of src and dest ptrs.
5477 if (!TLI.isTypeLegal(LoadVT) ||
5478 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5479 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5480 ActuallyDoIt = false;
5484 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5485 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5487 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5489 processIntegerCallValue(I, Res, false);
5498 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5499 /// form. If so, return true and lower it, otherwise return false and it
5500 /// will be lowered like a normal call.
5501 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5502 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5503 if (I.getNumArgOperands() != 3)
5506 const Value *Src = I.getArgOperand(0);
5507 const Value *Char = I.getArgOperand(1);
5508 const Value *Length = I.getArgOperand(2);
5509 if (!Src->getType()->isPointerTy() ||
5510 !Char->getType()->isIntegerTy() ||
5511 !Length->getType()->isIntegerTy() ||
5512 !I.getType()->isPointerTy())
5515 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5516 std::pair<SDValue, SDValue> Res =
5517 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5518 getValue(Src), getValue(Char), getValue(Length),
5519 MachinePointerInfo(Src));
5520 if (Res.first.getNode()) {
5521 setValue(&I, Res.first);
5522 PendingLoads.push_back(Res.second);
5529 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5530 /// optimized form. If so, return true and lower it, otherwise return false
5531 /// and it will be lowered like a normal call.
5532 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5533 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5534 if (I.getNumArgOperands() != 2)
5537 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5538 if (!Arg0->getType()->isPointerTy() ||
5539 !Arg1->getType()->isPointerTy() ||
5540 !I.getType()->isPointerTy())
5543 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5544 std::pair<SDValue, SDValue> Res =
5545 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5546 getValue(Arg0), getValue(Arg1),
5547 MachinePointerInfo(Arg0),
5548 MachinePointerInfo(Arg1), isStpcpy);
5549 if (Res.first.getNode()) {
5550 setValue(&I, Res.first);
5551 DAG.setRoot(Res.second);
5558 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5559 /// If so, return true and lower it, otherwise return false and it will be
5560 /// lowered like a normal call.
5561 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5562 // Verify that the prototype makes sense. int strcmp(void*,void*)
5563 if (I.getNumArgOperands() != 2)
5566 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5567 if (!Arg0->getType()->isPointerTy() ||
5568 !Arg1->getType()->isPointerTy() ||
5569 !I.getType()->isIntegerTy())
5572 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5573 std::pair<SDValue, SDValue> Res =
5574 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5575 getValue(Arg0), getValue(Arg1),
5576 MachinePointerInfo(Arg0),
5577 MachinePointerInfo(Arg1));
5578 if (Res.first.getNode()) {
5579 processIntegerCallValue(I, Res.first, true);
5580 PendingLoads.push_back(Res.second);
5587 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5588 /// form. If so, return true and lower it, otherwise return false and it
5589 /// will be lowered like a normal call.
5590 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5591 // Verify that the prototype makes sense. size_t strlen(char *)
5592 if (I.getNumArgOperands() != 1)
5595 const Value *Arg0 = I.getArgOperand(0);
5596 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5599 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5600 std::pair<SDValue, SDValue> Res =
5601 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5602 getValue(Arg0), MachinePointerInfo(Arg0));
5603 if (Res.first.getNode()) {
5604 processIntegerCallValue(I, Res.first, false);
5605 PendingLoads.push_back(Res.second);
5612 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5613 /// form. If so, return true and lower it, otherwise return false and it
5614 /// will be lowered like a normal call.
5615 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5616 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5617 if (I.getNumArgOperands() != 2)
5620 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5621 if (!Arg0->getType()->isPointerTy() ||
5622 !Arg1->getType()->isIntegerTy() ||
5623 !I.getType()->isIntegerTy())
5626 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5627 std::pair<SDValue, SDValue> Res =
5628 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5629 getValue(Arg0), getValue(Arg1),
5630 MachinePointerInfo(Arg0));
5631 if (Res.first.getNode()) {
5632 processIntegerCallValue(I, Res.first, false);
5633 PendingLoads.push_back(Res.second);
5640 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5641 /// operation (as expected), translate it to an SDNode with the specified opcode
5642 /// and return true.
5643 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5645 // Sanity check that it really is a unary floating-point call.
5646 if (I.getNumArgOperands() != 1 ||
5647 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5648 I.getType() != I.getArgOperand(0)->getType() ||
5649 !I.onlyReadsMemory())
5652 SDValue Tmp = getValue(I.getArgOperand(0));
5653 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5657 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5658 /// operation (as expected), translate it to an SDNode with the specified opcode
5659 /// and return true.
5660 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5662 // Sanity check that it really is a binary floating-point call.
5663 if (I.getNumArgOperands() != 2 ||
5664 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5665 I.getType() != I.getArgOperand(0)->getType() ||
5666 I.getType() != I.getArgOperand(1)->getType() ||
5667 !I.onlyReadsMemory())
5670 SDValue Tmp0 = getValue(I.getArgOperand(0));
5671 SDValue Tmp1 = getValue(I.getArgOperand(1));
5672 EVT VT = Tmp0.getValueType();
5673 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5677 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5678 // Handle inline assembly differently.
5679 if (isa<InlineAsm>(I.getCalledValue())) {
5684 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5685 ComputeUsesVAFloatArgument(I, &MMI);
5687 const char *RenameFn = nullptr;
5688 if (Function *F = I.getCalledFunction()) {
5689 if (F->isDeclaration()) {
5690 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5691 if (unsigned IID = II->getIntrinsicID(F)) {
5692 RenameFn = visitIntrinsicCall(I, IID);
5697 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5698 RenameFn = visitIntrinsicCall(I, IID);
5704 // Check for well-known libc/libm calls. If the function is internal, it
5705 // can't be a library call.
5707 if (!F->hasLocalLinkage() && F->hasName() &&
5708 LibInfo->getLibFunc(F->getName(), Func) &&
5709 LibInfo->hasOptimizedCodeGen(Func)) {
5712 case LibFunc::copysign:
5713 case LibFunc::copysignf:
5714 case LibFunc::copysignl:
5715 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5716 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5717 I.getType() == I.getArgOperand(0)->getType() &&
5718 I.getType() == I.getArgOperand(1)->getType() &&
5719 I.onlyReadsMemory()) {
5720 SDValue LHS = getValue(I.getArgOperand(0));
5721 SDValue RHS = getValue(I.getArgOperand(1));
5722 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5723 LHS.getValueType(), LHS, RHS));
5728 case LibFunc::fabsf:
5729 case LibFunc::fabsl:
5730 if (visitUnaryFloatCall(I, ISD::FABS))
5734 case LibFunc::fminf:
5735 case LibFunc::fminl:
5736 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5740 case LibFunc::fmaxf:
5741 case LibFunc::fmaxl:
5742 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5748 if (visitUnaryFloatCall(I, ISD::FSIN))
5754 if (visitUnaryFloatCall(I, ISD::FCOS))
5758 case LibFunc::sqrtf:
5759 case LibFunc::sqrtl:
5760 case LibFunc::sqrt_finite:
5761 case LibFunc::sqrtf_finite:
5762 case LibFunc::sqrtl_finite:
5763 if (visitUnaryFloatCall(I, ISD::FSQRT))
5766 case LibFunc::floor:
5767 case LibFunc::floorf:
5768 case LibFunc::floorl:
5769 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5772 case LibFunc::nearbyint:
5773 case LibFunc::nearbyintf:
5774 case LibFunc::nearbyintl:
5775 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5779 case LibFunc::ceilf:
5780 case LibFunc::ceill:
5781 if (visitUnaryFloatCall(I, ISD::FCEIL))
5785 case LibFunc::rintf:
5786 case LibFunc::rintl:
5787 if (visitUnaryFloatCall(I, ISD::FRINT))
5790 case LibFunc::round:
5791 case LibFunc::roundf:
5792 case LibFunc::roundl:
5793 if (visitUnaryFloatCall(I, ISD::FROUND))
5796 case LibFunc::trunc:
5797 case LibFunc::truncf:
5798 case LibFunc::truncl:
5799 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5803 case LibFunc::log2f:
5804 case LibFunc::log2l:
5805 if (visitUnaryFloatCall(I, ISD::FLOG2))
5809 case LibFunc::exp2f:
5810 case LibFunc::exp2l:
5811 if (visitUnaryFloatCall(I, ISD::FEXP2))
5814 case LibFunc::memcmp:
5815 if (visitMemCmpCall(I))
5818 case LibFunc::memchr:
5819 if (visitMemChrCall(I))
5822 case LibFunc::strcpy:
5823 if (visitStrCpyCall(I, false))
5826 case LibFunc::stpcpy:
5827 if (visitStrCpyCall(I, true))
5830 case LibFunc::strcmp:
5831 if (visitStrCmpCall(I))
5834 case LibFunc::strlen:
5835 if (visitStrLenCall(I))
5838 case LibFunc::strnlen:
5839 if (visitStrNLenCall(I))
5848 Callee = getValue(I.getCalledValue());
5850 Callee = DAG.getExternalSymbol(
5852 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5854 // Check if we can potentially perform a tail call. More detailed checking is
5855 // be done within LowerCallTo, after more information about the call is known.
5856 LowerCallTo(&I, Callee, I.isTailCall());
5861 /// AsmOperandInfo - This contains information for each constraint that we are
5863 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5865 /// CallOperand - If this is the result output operand or a clobber
5866 /// this is null, otherwise it is the incoming operand to the CallInst.
5867 /// This gets modified as the asm is processed.
5868 SDValue CallOperand;
5870 /// AssignedRegs - If this is a register or register class operand, this
5871 /// contains the set of register corresponding to the operand.
5872 RegsForValue AssignedRegs;
5874 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5875 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5878 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5879 /// corresponds to. If there is no Value* for this operand, it returns
5881 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5882 const DataLayout &DL) const {
5883 if (!CallOperandVal) return MVT::Other;
5885 if (isa<BasicBlock>(CallOperandVal))
5886 return TLI.getPointerTy(DL);
5888 llvm::Type *OpTy = CallOperandVal->getType();
5890 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5891 // If this is an indirect operand, the operand is a pointer to the
5894 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5896 report_fatal_error("Indirect operand for inline asm not a pointer!");
5897 OpTy = PtrTy->getElementType();
5900 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5901 if (StructType *STy = dyn_cast<StructType>(OpTy))
5902 if (STy->getNumElements() == 1)
5903 OpTy = STy->getElementType(0);
5905 // If OpTy is not a single value, it may be a struct/union that we
5906 // can tile with integers.
5907 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5908 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5917 OpTy = IntegerType::get(Context, BitSize);
5922 return TLI.getValueType(DL, OpTy, true);
5926 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5928 } // end anonymous namespace
5930 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5931 /// specified operand. We prefer to assign virtual registers, to allow the
5932 /// register allocator to handle the assignment process. However, if the asm
5933 /// uses features that we can't model on machineinstrs, we have SDISel do the
5934 /// allocation. This produces generally horrible, but correct, code.
5936 /// OpInfo describes the operand.
5938 static void GetRegistersForValue(SelectionDAG &DAG,
5939 const TargetLowering &TLI,
5941 SDISelAsmOperandInfo &OpInfo) {
5942 LLVMContext &Context = *DAG.getContext();
5944 MachineFunction &MF = DAG.getMachineFunction();
5945 SmallVector<unsigned, 4> Regs;
5947 // If this is a constraint for a single physreg, or a constraint for a
5948 // register class, find it.
5949 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5950 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5951 OpInfo.ConstraintCode,
5952 OpInfo.ConstraintVT);
5954 unsigned NumRegs = 1;
5955 if (OpInfo.ConstraintVT != MVT::Other) {
5956 // If this is a FP input in an integer register (or visa versa) insert a bit
5957 // cast of the input value. More generally, handle any case where the input
5958 // value disagrees with the register class we plan to stick this in.
5959 if (OpInfo.Type == InlineAsm::isInput &&
5960 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5961 // Try to convert to the first EVT that the reg class contains. If the
5962 // types are identical size, use a bitcast to convert (e.g. two differing
5964 MVT RegVT = *PhysReg.second->vt_begin();
5965 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5966 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5967 RegVT, OpInfo.CallOperand);
5968 OpInfo.ConstraintVT = RegVT;
5969 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5970 // If the input is a FP value and we want it in FP registers, do a
5971 // bitcast to the corresponding integer type. This turns an f64 value
5972 // into i64, which can be passed with two i32 values on a 32-bit
5974 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5975 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5976 RegVT, OpInfo.CallOperand);
5977 OpInfo.ConstraintVT = RegVT;
5981 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5985 EVT ValueVT = OpInfo.ConstraintVT;
5987 // If this is a constraint for a specific physical register, like {r17},
5989 if (unsigned AssignedReg = PhysReg.first) {
5990 const TargetRegisterClass *RC = PhysReg.second;
5991 if (OpInfo.ConstraintVT == MVT::Other)
5992 ValueVT = *RC->vt_begin();
5994 // Get the actual register value type. This is important, because the user
5995 // may have asked for (e.g.) the AX register in i32 type. We need to
5996 // remember that AX is actually i16 to get the right extension.
5997 RegVT = *RC->vt_begin();
5999 // This is a explicit reference to a physical register.
6000 Regs.push_back(AssignedReg);
6002 // If this is an expanded reference, add the rest of the regs to Regs.
6004 TargetRegisterClass::iterator I = RC->begin();
6005 for (; *I != AssignedReg; ++I)
6006 assert(I != RC->end() && "Didn't find reg!");
6008 // Already added the first reg.
6010 for (; NumRegs; --NumRegs, ++I) {
6011 assert(I != RC->end() && "Ran out of registers to allocate!");
6016 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6020 // Otherwise, if this was a reference to an LLVM register class, create vregs
6021 // for this reference.
6022 if (const TargetRegisterClass *RC = PhysReg.second) {
6023 RegVT = *RC->vt_begin();
6024 if (OpInfo.ConstraintVT == MVT::Other)
6027 // Create the appropriate number of virtual registers.
6028 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6029 for (; NumRegs; --NumRegs)
6030 Regs.push_back(RegInfo.createVirtualRegister(RC));
6032 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6036 // Otherwise, we couldn't allocate enough registers for this.
6039 /// visitInlineAsm - Handle a call to an InlineAsm object.
6041 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6042 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6044 /// ConstraintOperands - Information about all of the constraints.
6045 SDISelAsmOperandInfoVector ConstraintOperands;
6047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6048 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6049 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6051 bool hasMemory = false;
6053 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6054 unsigned ResNo = 0; // ResNo - The result number of the next output.
6055 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6056 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6057 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6059 MVT OpVT = MVT::Other;
6061 // Compute the value type for each operand.
6062 switch (OpInfo.Type) {
6063 case InlineAsm::isOutput:
6064 // Indirect outputs just consume an argument.
6065 if (OpInfo.isIndirect) {
6066 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6070 // The return value of the call is this value. As such, there is no
6071 // corresponding argument.
6072 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6073 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6074 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6075 STy->getElementType(ResNo));
6077 assert(ResNo == 0 && "Asm only has one result!");
6078 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6082 case InlineAsm::isInput:
6083 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6085 case InlineAsm::isClobber:
6090 // If this is an input or an indirect output, process the call argument.
6091 // BasicBlocks are labels, currently appearing only in asm's.
6092 if (OpInfo.CallOperandVal) {
6093 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6094 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6096 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6099 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6100 DAG.getDataLayout()).getSimpleVT();
6103 OpInfo.ConstraintVT = OpVT;
6105 // Indirect operand accesses access memory.
6106 if (OpInfo.isIndirect)
6109 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6110 TargetLowering::ConstraintType
6111 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6112 if (CType == TargetLowering::C_Memory) {
6120 SDValue Chain, Flag;
6122 // We won't need to flush pending loads if this asm doesn't touch
6123 // memory and is nonvolatile.
6124 if (hasMemory || IA->hasSideEffects())
6127 Chain = DAG.getRoot();
6129 // Second pass over the constraints: compute which constraint option to use
6130 // and assign registers to constraints that want a specific physreg.
6131 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6132 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6134 // If this is an output operand with a matching input operand, look up the
6135 // matching input. If their types mismatch, e.g. one is an integer, the
6136 // other is floating point, or their sizes are different, flag it as an
6138 if (OpInfo.hasMatchingInput()) {
6139 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6141 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6142 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6143 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6144 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6145 OpInfo.ConstraintVT);
6146 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6147 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6148 Input.ConstraintVT);
6149 if ((OpInfo.ConstraintVT.isInteger() !=
6150 Input.ConstraintVT.isInteger()) ||
6151 (MatchRC.second != InputRC.second)) {
6152 report_fatal_error("Unsupported asm: input constraint"
6153 " with a matching output constraint of"
6154 " incompatible type!");
6156 Input.ConstraintVT = OpInfo.ConstraintVT;
6160 // Compute the constraint code and ConstraintType to use.
6161 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6163 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6164 OpInfo.Type == InlineAsm::isClobber)
6167 // If this is a memory input, and if the operand is not indirect, do what we
6168 // need to to provide an address for the memory input.
6169 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6170 !OpInfo.isIndirect) {
6171 assert((OpInfo.isMultipleAlternative ||
6172 (OpInfo.Type == InlineAsm::isInput)) &&
6173 "Can only indirectify direct input operands!");
6175 // Memory operands really want the address of the value. If we don't have
6176 // an indirect input, put it in the constpool if we can, otherwise spill
6177 // it to a stack slot.
6178 // TODO: This isn't quite right. We need to handle these according to
6179 // the addressing mode that the constraint wants. Also, this may take
6180 // an additional register for the computation and we don't want that
6183 // If the operand is a float, integer, or vector constant, spill to a
6184 // constant pool entry to get its address.
6185 const Value *OpVal = OpInfo.CallOperandVal;
6186 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6187 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6188 OpInfo.CallOperand = DAG.getConstantPool(
6189 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6191 // Otherwise, create a stack slot and emit a store to it before the
6193 Type *Ty = OpVal->getType();
6194 auto &DL = DAG.getDataLayout();
6195 uint64_t TySize = DL.getTypeAllocSize(Ty);
6196 unsigned Align = DL.getPrefTypeAlignment(Ty);
6197 MachineFunction &MF = DAG.getMachineFunction();
6198 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6200 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6201 Chain = DAG.getStore(
6202 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6203 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6205 OpInfo.CallOperand = StackSlot;
6208 // There is no longer a Value* corresponding to this operand.
6209 OpInfo.CallOperandVal = nullptr;
6211 // It is now an indirect operand.
6212 OpInfo.isIndirect = true;
6215 // If this constraint is for a specific register, allocate it before
6217 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6218 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6221 // Second pass - Loop over all of the operands, assigning virtual or physregs
6222 // to register class operands.
6223 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6224 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6226 // C_Register operands have already been allocated, Other/Memory don't need
6228 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6229 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6232 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6233 std::vector<SDValue> AsmNodeOperands;
6234 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6235 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6236 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6238 // If we have a !srcloc metadata node associated with it, we want to attach
6239 // this to the ultimately generated inline asm machineinstr. To do this, we
6240 // pass in the third operand as this (potentially null) inline asm MDNode.
6241 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6242 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6244 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6245 // bits as operand 3.
6246 unsigned ExtraInfo = 0;
6247 if (IA->hasSideEffects())
6248 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6249 if (IA->isAlignStack())
6250 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6251 // Set the asm dialect.
6252 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6254 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6255 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6256 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6258 // Compute the constraint code and ConstraintType to use.
6259 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6261 // Ideally, we would only check against memory constraints. However, the
6262 // meaning of an other constraint can be target-specific and we can't easily
6263 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6264 // for other constriants as well.
6265 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6266 OpInfo.ConstraintType == TargetLowering::C_Other) {
6267 if (OpInfo.Type == InlineAsm::isInput)
6268 ExtraInfo |= InlineAsm::Extra_MayLoad;
6269 else if (OpInfo.Type == InlineAsm::isOutput)
6270 ExtraInfo |= InlineAsm::Extra_MayStore;
6271 else if (OpInfo.Type == InlineAsm::isClobber)
6272 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6276 AsmNodeOperands.push_back(DAG.getTargetConstant(
6277 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6279 // Loop over all of the inputs, copying the operand values into the
6280 // appropriate registers and processing the output regs.
6281 RegsForValue RetValRegs;
6283 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6284 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6286 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6287 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6289 switch (OpInfo.Type) {
6290 case InlineAsm::isOutput: {
6291 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6292 OpInfo.ConstraintType != TargetLowering::C_Register) {
6293 // Memory output, or 'other' output (e.g. 'X' constraint).
6294 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6296 unsigned ConstraintID =
6297 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6298 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6299 "Failed to convert memory constraint code to constraint id.");
6301 // Add information to the INLINEASM node to know about this output.
6302 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6303 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6304 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6306 AsmNodeOperands.push_back(OpInfo.CallOperand);
6310 // Otherwise, this is a register or register class output.
6312 // Copy the output from the appropriate register. Find a register that
6314 if (OpInfo.AssignedRegs.Regs.empty()) {
6315 LLVMContext &Ctx = *DAG.getContext();
6316 Ctx.emitError(CS.getInstruction(),
6317 "couldn't allocate output register for constraint '" +
6318 Twine(OpInfo.ConstraintCode) + "'");
6322 // If this is an indirect operand, store through the pointer after the
6324 if (OpInfo.isIndirect) {
6325 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6326 OpInfo.CallOperandVal));
6328 // This is the result value of the call.
6329 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6330 // Concatenate this output onto the outputs list.
6331 RetValRegs.append(OpInfo.AssignedRegs);
6334 // Add information to the INLINEASM node to know that this register is
6337 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6338 ? InlineAsm::Kind_RegDefEarlyClobber
6339 : InlineAsm::Kind_RegDef,
6340 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6343 case InlineAsm::isInput: {
6344 SDValue InOperandVal = OpInfo.CallOperand;
6346 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6347 // If this is required to match an output register we have already set,
6348 // just use its register.
6349 unsigned OperandNo = OpInfo.getMatchedOperand();
6351 // Scan until we find the definition we already emitted of this operand.
6352 // When we find it, create a RegsForValue operand.
6353 unsigned CurOp = InlineAsm::Op_FirstOperand;
6354 for (; OperandNo; --OperandNo) {
6355 // Advance to the next operand.
6357 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6358 assert((InlineAsm::isRegDefKind(OpFlag) ||
6359 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6360 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6361 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6365 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6366 if (InlineAsm::isRegDefKind(OpFlag) ||
6367 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6368 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6369 if (OpInfo.isIndirect) {
6370 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6371 LLVMContext &Ctx = *DAG.getContext();
6372 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6373 " don't know how to handle tied "
6374 "indirect register inputs");
6378 RegsForValue MatchedRegs;
6379 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6380 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6381 MatchedRegs.RegVTs.push_back(RegVT);
6382 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6383 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6385 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6386 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6388 LLVMContext &Ctx = *DAG.getContext();
6389 Ctx.emitError(CS.getInstruction(),
6390 "inline asm error: This value"
6391 " type register class is not natively supported!");
6395 SDLoc dl = getCurSDLoc();
6396 // Use the produced MatchedRegs object to
6397 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6398 Chain, &Flag, CS.getInstruction());
6399 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6400 true, OpInfo.getMatchedOperand(), dl,
6401 DAG, AsmNodeOperands);
6405 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6406 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6407 "Unexpected number of operands");
6408 // Add information to the INLINEASM node to know about this input.
6409 // See InlineAsm.h isUseOperandTiedToDef.
6410 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6411 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6412 OpInfo.getMatchedOperand());
6413 AsmNodeOperands.push_back(DAG.getTargetConstant(
6414 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6415 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6419 // Treat indirect 'X' constraint as memory.
6420 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6422 OpInfo.ConstraintType = TargetLowering::C_Memory;
6424 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6425 std::vector<SDValue> Ops;
6426 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6429 LLVMContext &Ctx = *DAG.getContext();
6430 Ctx.emitError(CS.getInstruction(),
6431 "invalid operand for inline asm constraint '" +
6432 Twine(OpInfo.ConstraintCode) + "'");
6436 // Add information to the INLINEASM node to know about this input.
6437 unsigned ResOpType =
6438 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6439 AsmNodeOperands.push_back(DAG.getTargetConstant(
6440 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6441 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6445 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6446 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6447 assert(InOperandVal.getValueType() ==
6448 TLI.getPointerTy(DAG.getDataLayout()) &&
6449 "Memory operands expect pointer values");
6451 unsigned ConstraintID =
6452 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6453 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6454 "Failed to convert memory constraint code to constraint id.");
6456 // Add information to the INLINEASM node to know about this input.
6457 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6458 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6459 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6462 AsmNodeOperands.push_back(InOperandVal);
6466 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6467 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6468 "Unknown constraint type!");
6470 // TODO: Support this.
6471 if (OpInfo.isIndirect) {
6472 LLVMContext &Ctx = *DAG.getContext();
6473 Ctx.emitError(CS.getInstruction(),
6474 "Don't know how to handle indirect register inputs yet "
6475 "for constraint '" +
6476 Twine(OpInfo.ConstraintCode) + "'");
6480 // Copy the input into the appropriate registers.
6481 if (OpInfo.AssignedRegs.Regs.empty()) {
6482 LLVMContext &Ctx = *DAG.getContext();
6483 Ctx.emitError(CS.getInstruction(),
6484 "couldn't allocate input reg for constraint '" +
6485 Twine(OpInfo.ConstraintCode) + "'");
6489 SDLoc dl = getCurSDLoc();
6491 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6492 Chain, &Flag, CS.getInstruction());
6494 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6495 dl, DAG, AsmNodeOperands);
6498 case InlineAsm::isClobber: {
6499 // Add the clobbered value to the operand list, so that the register
6500 // allocator is aware that the physreg got clobbered.
6501 if (!OpInfo.AssignedRegs.Regs.empty())
6502 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6503 false, 0, getCurSDLoc(), DAG,
6510 // Finish up input operands. Set the input chain and add the flag last.
6511 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6512 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6514 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6515 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6516 Flag = Chain.getValue(1);
6518 // If this asm returns a register value, copy the result from that register
6519 // and set it as the value of the call.
6520 if (!RetValRegs.Regs.empty()) {
6521 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6522 Chain, &Flag, CS.getInstruction());
6524 // FIXME: Why don't we do this for inline asms with MRVs?
6525 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6526 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6528 // If any of the results of the inline asm is a vector, it may have the
6529 // wrong width/num elts. This can happen for register classes that can
6530 // contain multiple different value types. The preg or vreg allocated may
6531 // not have the same VT as was expected. Convert it to the right type
6532 // with bit_convert.
6533 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6534 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6537 } else if (ResultType != Val.getValueType() &&
6538 ResultType.isInteger() && Val.getValueType().isInteger()) {
6539 // If a result value was tied to an input value, the computed result may
6540 // have a wider width than the expected result. Extract the relevant
6542 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6545 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6548 setValue(CS.getInstruction(), Val);
6549 // Don't need to use this as a chain in this case.
6550 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6554 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6556 // Process indirect outputs, first output all of the flagged copies out of
6558 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6559 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6560 const Value *Ptr = IndirectStoresToEmit[i].second;
6561 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6563 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6566 // Emit the non-flagged stores from the physregs.
6567 SmallVector<SDValue, 8> OutChains;
6568 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6569 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6570 StoresToEmit[i].first,
6571 getValue(StoresToEmit[i].second),
6572 MachinePointerInfo(StoresToEmit[i].second),
6574 OutChains.push_back(Val);
6577 if (!OutChains.empty())
6578 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6583 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6584 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6585 MVT::Other, getRoot(),
6586 getValue(I.getArgOperand(0)),
6587 DAG.getSrcValue(I.getArgOperand(0))));
6590 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6591 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6592 const DataLayout &DL = DAG.getDataLayout();
6593 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6594 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6595 DAG.getSrcValue(I.getOperand(0)),
6596 DL.getABITypeAlignment(I.getType()));
6598 DAG.setRoot(V.getValue(1));
6601 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6602 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6603 MVT::Other, getRoot(),
6604 getValue(I.getArgOperand(0)),
6605 DAG.getSrcValue(I.getArgOperand(0))));
6608 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6609 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6610 MVT::Other, getRoot(),
6611 getValue(I.getArgOperand(0)),
6612 getValue(I.getArgOperand(1)),
6613 DAG.getSrcValue(I.getArgOperand(0)),
6614 DAG.getSrcValue(I.getArgOperand(1))));
6617 /// \brief Lower an argument list according to the target calling convention.
6619 /// \return A tuple of <return-value, token-chain>
6621 /// This is a helper for lowering intrinsics that follow a target calling
6622 /// convention or require stack pointer adjustment. Only a subset of the
6623 /// intrinsic's operands need to participate in the calling convention.
6624 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6625 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6626 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6627 TargetLowering::ArgListTy Args;
6628 Args.reserve(NumArgs);
6630 // Populate the argument list.
6631 // Attributes for args start at offset 1, after the return attribute.
6632 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6633 ArgI != ArgE; ++ArgI) {
6634 const Value *V = CS->getOperand(ArgI);
6636 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6638 TargetLowering::ArgListEntry Entry;
6639 Entry.Node = getValue(V);
6640 Entry.Ty = V->getType();
6641 Entry.setAttributes(&CS, AttrI);
6642 Args.push_back(Entry);
6645 TargetLowering::CallLoweringInfo CLI(DAG);
6646 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6647 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6648 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6650 return lowerInvokable(CLI, EHPadBB);
6653 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6654 /// or patchpoint target node's operand list.
6656 /// Constants are converted to TargetConstants purely as an optimization to
6657 /// avoid constant materialization and register allocation.
6659 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6660 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6661 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6662 /// address materialization and register allocation, but may also be required
6663 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6664 /// alloca in the entry block, then the runtime may assume that the alloca's
6665 /// StackMap location can be read immediately after compilation and that the
6666 /// location is valid at any point during execution (this is similar to the
6667 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6668 /// only available in a register, then the runtime would need to trap when
6669 /// execution reaches the StackMap in order to read the alloca's location.
6670 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6671 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6672 SelectionDAGBuilder &Builder) {
6673 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6674 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6675 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6677 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6679 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6680 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6681 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6682 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6683 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6685 Ops.push_back(OpVal);
6689 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6690 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6691 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6692 // [live variables...])
6694 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6696 SDValue Chain, InFlag, Callee, NullPtr;
6697 SmallVector<SDValue, 32> Ops;
6699 SDLoc DL = getCurSDLoc();
6700 Callee = getValue(CI.getCalledValue());
6701 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6703 // The stackmap intrinsic only records the live variables (the arguemnts
6704 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6705 // intrinsic, this won't be lowered to a function call. This means we don't
6706 // have to worry about calling conventions and target specific lowering code.
6707 // Instead we perform the call lowering right here.
6709 // chain, flag = CALLSEQ_START(chain, 0)
6710 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6711 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6713 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6714 InFlag = Chain.getValue(1);
6716 // Add the <id> and <numBytes> constants.
6717 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6718 Ops.push_back(DAG.getTargetConstant(
6719 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6720 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6721 Ops.push_back(DAG.getTargetConstant(
6722 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6725 // Push live variables for the stack map.
6726 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6728 // We are not pushing any register mask info here on the operands list,
6729 // because the stackmap doesn't clobber anything.
6731 // Push the chain and the glue flag.
6732 Ops.push_back(Chain);
6733 Ops.push_back(InFlag);
6735 // Create the STACKMAP node.
6736 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6737 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6738 Chain = SDValue(SM, 0);
6739 InFlag = Chain.getValue(1);
6741 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6743 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6745 // Set the root to the target-lowered call chain.
6748 // Inform the Frame Information that we have a stackmap in this function.
6749 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6752 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6753 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6754 const BasicBlock *EHPadBB) {
6755 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6760 // [live variables...])
6762 CallingConv::ID CC = CS.getCallingConv();
6763 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6764 bool HasDef = !CS->getType()->isVoidTy();
6765 SDLoc dl = getCurSDLoc();
6766 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6768 // Handle immediate and symbolic callees.
6769 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6770 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6772 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6773 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6774 SDLoc(SymbolicCallee),
6775 SymbolicCallee->getValueType(0));
6777 // Get the real number of arguments participating in the call <numArgs>
6778 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6779 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6781 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6782 // Intrinsics include all meta-operands up to but not including CC.
6783 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6784 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6785 "Not enough arguments provided to the patchpoint intrinsic");
6787 // For AnyRegCC the arguments are lowered later on manually.
6788 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6790 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6791 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6792 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6794 SDNode *CallEnd = Result.second.getNode();
6795 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6796 CallEnd = CallEnd->getOperand(0).getNode();
6798 /// Get a call instruction from the call sequence chain.
6799 /// Tail calls are not allowed.
6800 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6801 "Expected a callseq node.");
6802 SDNode *Call = CallEnd->getOperand(0).getNode();
6803 bool HasGlue = Call->getGluedNode();
6805 // Replace the target specific call node with the patchable intrinsic.
6806 SmallVector<SDValue, 8> Ops;
6808 // Add the <id> and <numBytes> constants.
6809 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6810 Ops.push_back(DAG.getTargetConstant(
6811 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6812 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6813 Ops.push_back(DAG.getTargetConstant(
6814 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6818 Ops.push_back(Callee);
6820 // Adjust <numArgs> to account for any arguments that have been passed on the
6822 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6823 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6824 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6825 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6827 // Add the calling convention
6828 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6830 // Add the arguments we omitted previously. The register allocator should
6831 // place these in any free register.
6833 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6834 Ops.push_back(getValue(CS.getArgument(i)));
6836 // Push the arguments from the call instruction up to the register mask.
6837 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6838 Ops.append(Call->op_begin() + 2, e);
6840 // Push live variables for the stack map.
6841 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6843 // Push the register mask info.
6845 Ops.push_back(*(Call->op_end()-2));
6847 Ops.push_back(*(Call->op_end()-1));
6849 // Push the chain (this is originally the first operand of the call, but
6850 // becomes now the last or second to last operand).
6851 Ops.push_back(*(Call->op_begin()));
6853 // Push the glue flag (last operand).
6855 Ops.push_back(*(Call->op_end()-1));
6858 if (IsAnyRegCC && HasDef) {
6859 // Create the return types based on the intrinsic definition
6860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6861 SmallVector<EVT, 3> ValueVTs;
6862 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6863 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6865 // There is always a chain and a glue type at the end
6866 ValueVTs.push_back(MVT::Other);
6867 ValueVTs.push_back(MVT::Glue);
6868 NodeTys = DAG.getVTList(ValueVTs);
6870 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6872 // Replace the target specific call node with a PATCHPOINT node.
6873 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6876 // Update the NodeMap.
6879 setValue(CS.getInstruction(), SDValue(MN, 0));
6881 setValue(CS.getInstruction(), Result.first);
6884 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6885 // call sequence. Furthermore the location of the chain and glue can change
6886 // when the AnyReg calling convention is used and the intrinsic returns a
6888 if (IsAnyRegCC && HasDef) {
6889 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6890 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6891 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6893 DAG.ReplaceAllUsesWith(Call, MN);
6894 DAG.DeleteNode(Call);
6896 // Inform the Frame Information that we have a patchpoint in this function.
6897 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6900 /// Returns an AttributeSet representing the attributes applied to the return
6901 /// value of the given call.
6902 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6903 SmallVector<Attribute::AttrKind, 2> Attrs;
6905 Attrs.push_back(Attribute::SExt);
6907 Attrs.push_back(Attribute::ZExt);
6909 Attrs.push_back(Attribute::InReg);
6911 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6915 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6916 /// implementation, which just calls LowerCall.
6917 /// FIXME: When all targets are
6918 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6919 std::pair<SDValue, SDValue>
6920 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6921 // Handle the incoming return values from the call.
6923 Type *OrigRetTy = CLI.RetTy;
6924 SmallVector<EVT, 4> RetTys;
6925 SmallVector<uint64_t, 4> Offsets;
6926 auto &DL = CLI.DAG.getDataLayout();
6927 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6929 SmallVector<ISD::OutputArg, 4> Outs;
6930 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6932 bool CanLowerReturn =
6933 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6934 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6936 SDValue DemoteStackSlot;
6937 int DemoteStackIdx = -100;
6938 if (!CanLowerReturn) {
6939 // FIXME: equivalent assert?
6940 // assert(!CS.hasInAllocaArgument() &&
6941 // "sret demotion is incompatible with inalloca");
6942 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6943 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6944 MachineFunction &MF = CLI.DAG.getMachineFunction();
6945 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6946 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6948 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6950 Entry.Node = DemoteStackSlot;
6951 Entry.Ty = StackSlotPtrType;
6952 Entry.isSExt = false;
6953 Entry.isZExt = false;
6954 Entry.isInReg = false;
6955 Entry.isSRet = true;
6956 Entry.isNest = false;
6957 Entry.isByVal = false;
6958 Entry.isReturned = false;
6959 Entry.Alignment = Align;
6960 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6961 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6963 // sret demotion isn't compatible with tail-calls, since the sret argument
6964 // points into the callers stack frame.
6965 CLI.IsTailCall = false;
6967 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6969 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6970 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6971 for (unsigned i = 0; i != NumRegs; ++i) {
6972 ISD::InputArg MyFlags;
6973 MyFlags.VT = RegisterVT;
6975 MyFlags.Used = CLI.IsReturnValueUsed;
6977 MyFlags.Flags.setSExt();
6979 MyFlags.Flags.setZExt();
6981 MyFlags.Flags.setInReg();
6982 CLI.Ins.push_back(MyFlags);
6987 // Handle all of the outgoing arguments.
6989 CLI.OutVals.clear();
6990 ArgListTy &Args = CLI.getArgs();
6991 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6992 SmallVector<EVT, 4> ValueVTs;
6993 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6994 Type *FinalType = Args[i].Ty;
6995 if (Args[i].isByVal)
6996 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6997 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6998 FinalType, CLI.CallConv, CLI.IsVarArg);
6999 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7001 EVT VT = ValueVTs[Value];
7002 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7003 SDValue Op = SDValue(Args[i].Node.getNode(),
7004 Args[i].Node.getResNo() + Value);
7005 ISD::ArgFlagsTy Flags;
7006 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7012 if (Args[i].isInReg)
7016 if (Args[i].isByVal)
7018 if (Args[i].isInAlloca) {
7019 Flags.setInAlloca();
7020 // Set the byval flag for CCAssignFn callbacks that don't know about
7021 // inalloca. This way we can know how many bytes we should've allocated
7022 // and how many bytes a callee cleanup function will pop. If we port
7023 // inalloca to more targets, we'll have to add custom inalloca handling
7024 // in the various CC lowering callbacks.
7027 if (Args[i].isByVal || Args[i].isInAlloca) {
7028 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7029 Type *ElementTy = Ty->getElementType();
7030 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7031 // For ByVal, alignment should come from FE. BE will guess if this
7032 // info is not there but there are cases it cannot get right.
7033 unsigned FrameAlign;
7034 if (Args[i].Alignment)
7035 FrameAlign = Args[i].Alignment;
7037 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7038 Flags.setByValAlign(FrameAlign);
7043 Flags.setInConsecutiveRegs();
7044 Flags.setOrigAlign(OriginalAlignment);
7046 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7047 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7048 SmallVector<SDValue, 4> Parts(NumParts);
7049 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7052 ExtendKind = ISD::SIGN_EXTEND;
7053 else if (Args[i].isZExt)
7054 ExtendKind = ISD::ZERO_EXTEND;
7056 // Conservatively only handle 'returned' on non-vectors for now
7057 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7058 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7059 "unexpected use of 'returned'");
7060 // Before passing 'returned' to the target lowering code, ensure that
7061 // either the register MVT and the actual EVT are the same size or that
7062 // the return value and argument are extended in the same way; in these
7063 // cases it's safe to pass the argument register value unchanged as the
7064 // return register value (although it's at the target's option whether
7066 // TODO: allow code generation to take advantage of partially preserved
7067 // registers rather than clobbering the entire register when the
7068 // parameter extension method is not compatible with the return
7070 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7071 (ExtendKind != ISD::ANY_EXTEND &&
7072 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7073 Flags.setReturned();
7076 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7077 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7079 for (unsigned j = 0; j != NumParts; ++j) {
7080 // if it isn't first piece, alignment must be 1
7081 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7082 i < CLI.NumFixedArgs,
7083 i, j*Parts[j].getValueType().getStoreSize());
7084 if (NumParts > 1 && j == 0)
7085 MyFlags.Flags.setSplit();
7087 MyFlags.Flags.setOrigAlign(1);
7089 CLI.Outs.push_back(MyFlags);
7090 CLI.OutVals.push_back(Parts[j]);
7093 if (NeedsRegBlock && Value == NumValues - 1)
7094 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7098 SmallVector<SDValue, 4> InVals;
7099 CLI.Chain = LowerCall(CLI, InVals);
7101 // Verify that the target's LowerCall behaved as expected.
7102 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7103 "LowerCall didn't return a valid chain!");
7104 assert((!CLI.IsTailCall || InVals.empty()) &&
7105 "LowerCall emitted a return value for a tail call!");
7106 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7107 "LowerCall didn't emit the correct number of values!");
7109 // For a tail call, the return value is merely live-out and there aren't
7110 // any nodes in the DAG representing it. Return a special value to
7111 // indicate that a tail call has been emitted and no more Instructions
7112 // should be processed in the current block.
7113 if (CLI.IsTailCall) {
7114 CLI.DAG.setRoot(CLI.Chain);
7115 return std::make_pair(SDValue(), SDValue());
7118 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7119 assert(InVals[i].getNode() &&
7120 "LowerCall emitted a null value!");
7121 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7122 "LowerCall emitted a value with the wrong type!");
7125 SmallVector<SDValue, 4> ReturnValues;
7126 if (!CanLowerReturn) {
7127 // The instruction result is the result of loading from the
7128 // hidden sret parameter.
7129 SmallVector<EVT, 1> PVTs;
7130 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7132 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7133 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7134 EVT PtrVT = PVTs[0];
7136 unsigned NumValues = RetTys.size();
7137 ReturnValues.resize(NumValues);
7138 SmallVector<SDValue, 4> Chains(NumValues);
7140 for (unsigned i = 0; i < NumValues; ++i) {
7141 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7142 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7144 SDValue L = CLI.DAG.getLoad(
7145 RetTys[i], CLI.DL, CLI.Chain, Add,
7146 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7147 DemoteStackIdx, Offsets[i]),
7148 false, false, false, 1);
7149 ReturnValues[i] = L;
7150 Chains[i] = L.getValue(1);
7153 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7155 // Collect the legal value parts into potentially illegal values
7156 // that correspond to the original function's return values.
7157 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7159 AssertOp = ISD::AssertSext;
7160 else if (CLI.RetZExt)
7161 AssertOp = ISD::AssertZext;
7162 unsigned CurReg = 0;
7163 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7165 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7166 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7168 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7169 NumRegs, RegisterVT, VT, nullptr,
7174 // For a function returning void, there is no return value. We can't create
7175 // such a node, so we just return a null return value in that case. In
7176 // that case, nothing will actually look at the value.
7177 if (ReturnValues.empty())
7178 return std::make_pair(SDValue(), CLI.Chain);
7181 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7182 CLI.DAG.getVTList(RetTys), ReturnValues);
7183 return std::make_pair(Res, CLI.Chain);
7186 void TargetLowering::LowerOperationWrapper(SDNode *N,
7187 SmallVectorImpl<SDValue> &Results,
7188 SelectionDAG &DAG) const {
7189 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7191 Results.push_back(Res);
7194 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7195 llvm_unreachable("LowerOperation not implemented for this target!");
7199 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7200 SDValue Op = getNonRegisterValue(V);
7201 assert((Op.getOpcode() != ISD::CopyFromReg ||
7202 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7203 "Copy from a reg to the same reg!");
7204 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7206 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7207 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7209 SDValue Chain = DAG.getEntryNode();
7211 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7212 FuncInfo.PreferredExtendType.end())
7214 : FuncInfo.PreferredExtendType[V];
7215 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7216 PendingExports.push_back(Chain);
7219 #include "llvm/CodeGen/SelectionDAGISel.h"
7221 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7222 /// entry block, return true. This includes arguments used by switches, since
7223 /// the switch may expand into multiple basic blocks.
7224 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7225 // With FastISel active, we may be splitting blocks, so force creation
7226 // of virtual registers for all non-dead arguments.
7228 return A->use_empty();
7230 const BasicBlock *Entry = A->getParent()->begin();
7231 for (const User *U : A->users())
7232 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7233 return false; // Use not in entry block.
7238 void SelectionDAGISel::LowerArguments(const Function &F) {
7239 SelectionDAG &DAG = SDB->DAG;
7240 SDLoc dl = SDB->getCurSDLoc();
7241 const DataLayout &DL = DAG.getDataLayout();
7242 SmallVector<ISD::InputArg, 16> Ins;
7244 if (!FuncInfo->CanLowerReturn) {
7245 // Put in an sret pointer parameter before all the other parameters.
7246 SmallVector<EVT, 1> ValueVTs;
7247 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7248 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7250 // NOTE: Assuming that a pointer will never break down to more than one VT
7252 ISD::ArgFlagsTy Flags;
7254 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7255 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7256 ISD::InputArg::NoArgIndex, 0);
7257 Ins.push_back(RetArg);
7260 // Set up the incoming argument description vector.
7262 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7263 I != E; ++I, ++Idx) {
7264 SmallVector<EVT, 4> ValueVTs;
7265 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7266 bool isArgValueUsed = !I->use_empty();
7267 unsigned PartBase = 0;
7268 Type *FinalType = I->getType();
7269 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7270 FinalType = cast<PointerType>(FinalType)->getElementType();
7271 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7272 FinalType, F.getCallingConv(), F.isVarArg());
7273 for (unsigned Value = 0, NumValues = ValueVTs.size();
7274 Value != NumValues; ++Value) {
7275 EVT VT = ValueVTs[Value];
7276 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7277 ISD::ArgFlagsTy Flags;
7278 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7280 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7282 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7284 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7286 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7288 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7290 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7291 Flags.setInAlloca();
7292 // Set the byval flag for CCAssignFn callbacks that don't know about
7293 // inalloca. This way we can know how many bytes we should've allocated
7294 // and how many bytes a callee cleanup function will pop. If we port
7295 // inalloca to more targets, we'll have to add custom inalloca handling
7296 // in the various CC lowering callbacks.
7299 if (Flags.isByVal() || Flags.isInAlloca()) {
7300 PointerType *Ty = cast<PointerType>(I->getType());
7301 Type *ElementTy = Ty->getElementType();
7302 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7303 // For ByVal, alignment should be passed from FE. BE will guess if
7304 // this info is not there but there are cases it cannot get right.
7305 unsigned FrameAlign;
7306 if (F.getParamAlignment(Idx))
7307 FrameAlign = F.getParamAlignment(Idx);
7309 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7310 Flags.setByValAlign(FrameAlign);
7312 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7315 Flags.setInConsecutiveRegs();
7316 Flags.setOrigAlign(OriginalAlignment);
7318 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7319 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7320 for (unsigned i = 0; i != NumRegs; ++i) {
7321 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7322 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7323 if (NumRegs > 1 && i == 0)
7324 MyFlags.Flags.setSplit();
7325 // if it isn't first piece, alignment must be 1
7327 MyFlags.Flags.setOrigAlign(1);
7328 Ins.push_back(MyFlags);
7330 if (NeedsRegBlock && Value == NumValues - 1)
7331 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7332 PartBase += VT.getStoreSize();
7336 // Call the target to set up the argument values.
7337 SmallVector<SDValue, 8> InVals;
7338 SDValue NewRoot = TLI->LowerFormalArguments(
7339 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7341 // Verify that the target's LowerFormalArguments behaved as expected.
7342 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7343 "LowerFormalArguments didn't return a valid chain!");
7344 assert(InVals.size() == Ins.size() &&
7345 "LowerFormalArguments didn't emit the correct number of values!");
7347 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7348 assert(InVals[i].getNode() &&
7349 "LowerFormalArguments emitted a null value!");
7350 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7351 "LowerFormalArguments emitted a value with the wrong type!");
7355 // Update the DAG with the new chain value resulting from argument lowering.
7356 DAG.setRoot(NewRoot);
7358 // Set up the argument values.
7361 if (!FuncInfo->CanLowerReturn) {
7362 // Create a virtual register for the sret pointer, and put in a copy
7363 // from the sret argument into it.
7364 SmallVector<EVT, 1> ValueVTs;
7365 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7366 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7367 MVT VT = ValueVTs[0].getSimpleVT();
7368 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7369 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7370 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7371 RegVT, VT, nullptr, AssertOp);
7373 MachineFunction& MF = SDB->DAG.getMachineFunction();
7374 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7375 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7376 FuncInfo->DemoteRegister = SRetReg;
7378 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7379 DAG.setRoot(NewRoot);
7381 // i indexes lowered arguments. Bump it past the hidden sret argument.
7382 // Idx indexes LLVM arguments. Don't touch it.
7386 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7388 SmallVector<SDValue, 4> ArgValues;
7389 SmallVector<EVT, 4> ValueVTs;
7390 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7391 unsigned NumValues = ValueVTs.size();
7393 // If this argument is unused then remember its value. It is used to generate
7394 // debugging information.
7395 if (I->use_empty() && NumValues) {
7396 SDB->setUnusedArgValue(I, InVals[i]);
7398 // Also remember any frame index for use in FastISel.
7399 if (FrameIndexSDNode *FI =
7400 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7401 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7404 for (unsigned Val = 0; Val != NumValues; ++Val) {
7405 EVT VT = ValueVTs[Val];
7406 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7407 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7409 if (!I->use_empty()) {
7410 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7411 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7412 AssertOp = ISD::AssertSext;
7413 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7414 AssertOp = ISD::AssertZext;
7416 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7417 NumParts, PartVT, VT,
7418 nullptr, AssertOp));
7424 // We don't need to do anything else for unused arguments.
7425 if (ArgValues.empty())
7428 // Note down frame index.
7429 if (FrameIndexSDNode *FI =
7430 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7431 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7433 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7434 SDB->getCurSDLoc());
7436 SDB->setValue(I, Res);
7437 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7438 if (LoadSDNode *LNode =
7439 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7440 if (FrameIndexSDNode *FI =
7441 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7442 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7445 // If this argument is live outside of the entry block, insert a copy from
7446 // wherever we got it to the vreg that other BB's will reference it as.
7447 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7448 // If we can, though, try to skip creating an unnecessary vreg.
7449 // FIXME: This isn't very clean... it would be nice to make this more
7450 // general. It's also subtly incompatible with the hacks FastISel
7452 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7453 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7454 FuncInfo->ValueMap[I] = Reg;
7458 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7459 FuncInfo->InitializeRegForValue(I);
7460 SDB->CopyToExportRegsIfNeeded(I);
7464 assert(i == InVals.size() && "Argument register count mismatch!");
7466 // Finally, if the target has anything special to do, allow it to do so.
7467 EmitFunctionEntryCode();
7470 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7471 /// ensure constants are generated when needed. Remember the virtual registers
7472 /// that need to be added to the Machine PHI nodes as input. We cannot just
7473 /// directly add them, because expansion might result in multiple MBB's for one
7474 /// BB. As such, the start of the BB might correspond to a different MBB than
7478 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7479 const TerminatorInst *TI = LLVMBB->getTerminator();
7481 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7483 // Check PHI nodes in successors that expect a value to be available from this
7485 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7486 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7487 if (!isa<PHINode>(SuccBB->begin())) continue;
7488 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7490 // If this terminator has multiple identical successors (common for
7491 // switches), only handle each succ once.
7492 if (!SuccsHandled.insert(SuccMBB).second)
7495 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7497 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7498 // nodes and Machine PHI nodes, but the incoming operands have not been
7500 for (BasicBlock::const_iterator I = SuccBB->begin();
7501 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7502 // Ignore dead phi's.
7503 if (PN->use_empty()) continue;
7506 if (PN->getType()->isEmptyTy())
7510 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7512 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7513 unsigned &RegOut = ConstantsOut[C];
7515 RegOut = FuncInfo.CreateRegs(C->getType());
7516 CopyValueToVirtualRegister(C, RegOut);
7520 DenseMap<const Value *, unsigned>::iterator I =
7521 FuncInfo.ValueMap.find(PHIOp);
7522 if (I != FuncInfo.ValueMap.end())
7525 assert(isa<AllocaInst>(PHIOp) &&
7526 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7527 "Didn't codegen value into a register!??");
7528 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7529 CopyValueToVirtualRegister(PHIOp, Reg);
7533 // Remember that this register needs to added to the machine PHI node as
7534 // the input for this MBB.
7535 SmallVector<EVT, 4> ValueVTs;
7536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7537 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7538 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7539 EVT VT = ValueVTs[vti];
7540 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7541 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7542 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7543 Reg += NumRegisters;
7548 ConstantsOut.clear();
7551 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7554 SelectionDAGBuilder::StackProtectorDescriptor::
7555 AddSuccessorMBB(const BasicBlock *BB,
7556 MachineBasicBlock *ParentMBB,
7558 MachineBasicBlock *SuccMBB) {
7559 // If SuccBB has not been created yet, create it.
7561 MachineFunction *MF = ParentMBB->getParent();
7562 MachineFunction::iterator BBI = ParentMBB;
7563 SuccMBB = MF->CreateMachineBasicBlock(BB);
7564 MF->insert(++BBI, SuccMBB);
7566 // Add it as a successor of ParentMBB.
7567 ParentMBB->addSuccessor(
7568 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7572 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7573 MachineFunction::iterator I = MBB;
7574 if (++I == FuncInfo.MF->end())
7579 /// During lowering new call nodes can be created (such as memset, etc.).
7580 /// Those will become new roots of the current DAG, but complications arise
7581 /// when they are tail calls. In such cases, the call lowering will update
7582 /// the root, but the builder still needs to know that a tail call has been
7583 /// lowered in order to avoid generating an additional return.
7584 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7585 // If the node is null, we do have a tail call.
7586 if (MaybeTC.getNode() != nullptr)
7587 DAG.setRoot(MaybeTC);
7592 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7593 unsigned *TotalCases, unsigned First,
7595 assert(Last >= First);
7596 assert(TotalCases[Last] >= TotalCases[First]);
7598 APInt LowCase = Clusters[First].Low->getValue();
7599 APInt HighCase = Clusters[Last].High->getValue();
7600 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7602 // FIXME: A range of consecutive cases has 100% density, but only requires one
7603 // comparison to lower. We should discriminate against such consecutive ranges
7606 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7607 uint64_t Range = Diff + 1;
7610 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7612 assert(NumCases < UINT64_MAX / 100);
7613 assert(Range >= NumCases);
7615 return NumCases * 100 >= Range * MinJumpTableDensity;
7618 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7619 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7620 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7623 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7624 unsigned First, unsigned Last,
7625 const SwitchInst *SI,
7626 MachineBasicBlock *DefaultMBB,
7627 CaseCluster &JTCluster) {
7628 assert(First <= Last);
7630 uint32_t Weight = 0;
7631 unsigned NumCmps = 0;
7632 std::vector<MachineBasicBlock*> Table;
7633 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7634 for (unsigned I = First; I <= Last; ++I) {
7635 assert(Clusters[I].Kind == CC_Range);
7636 Weight += Clusters[I].Weight;
7637 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7638 APInt Low = Clusters[I].Low->getValue();
7639 APInt High = Clusters[I].High->getValue();
7640 NumCmps += (Low == High) ? 1 : 2;
7642 // Fill the gap between this and the previous cluster.
7643 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7644 assert(PreviousHigh.slt(Low));
7645 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7646 for (uint64_t J = 0; J < Gap; J++)
7647 Table.push_back(DefaultMBB);
7649 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7650 for (uint64_t J = 0; J < ClusterSize; ++J)
7651 Table.push_back(Clusters[I].MBB);
7652 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7655 unsigned NumDests = JTWeights.size();
7656 if (isSuitableForBitTests(NumDests, NumCmps,
7657 Clusters[First].Low->getValue(),
7658 Clusters[Last].High->getValue())) {
7659 // Clusters[First..Last] should be lowered as bit tests instead.
7663 // Create the MBB that will load from and jump through the table.
7664 // Note: We create it here, but it's not inserted into the function yet.
7665 MachineFunction *CurMF = FuncInfo.MF;
7666 MachineBasicBlock *JumpTableMBB =
7667 CurMF->CreateMachineBasicBlock(SI->getParent());
7669 // Add successors. Note: use table order for determinism.
7670 SmallPtrSet<MachineBasicBlock *, 8> Done;
7671 for (MachineBasicBlock *Succ : Table) {
7672 if (Done.count(Succ))
7674 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7678 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7679 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7680 ->createJumpTableIndex(Table);
7682 // Set up the jump table info.
7683 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7684 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7685 Clusters[Last].High->getValue(), SI->getCondition(),
7687 JTCases.emplace_back(std::move(JTH), std::move(JT));
7689 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7690 JTCases.size() - 1, Weight);
7694 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7695 const SwitchInst *SI,
7696 MachineBasicBlock *DefaultMBB) {
7698 // Clusters must be non-empty, sorted, and only contain Range clusters.
7699 assert(!Clusters.empty());
7700 for (CaseCluster &C : Clusters)
7701 assert(C.Kind == CC_Range);
7702 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7703 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7707 if (!areJTsAllowed(TLI))
7710 const int64_t N = Clusters.size();
7711 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7713 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7714 SmallVector<unsigned, 8> TotalCases(N);
7716 for (unsigned i = 0; i < N; ++i) {
7717 APInt Hi = Clusters[i].High->getValue();
7718 APInt Lo = Clusters[i].Low->getValue();
7719 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7721 TotalCases[i] += TotalCases[i - 1];
7724 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7725 // Cheap case: the whole range might be suitable for jump table.
7726 CaseCluster JTCluster;
7727 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7728 Clusters[0] = JTCluster;
7734 // The algorithm below is not suitable for -O0.
7735 if (TM.getOptLevel() == CodeGenOpt::None)
7738 // Split Clusters into minimum number of dense partitions. The algorithm uses
7739 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7740 // for the Case Statement'" (1994), but builds the MinPartitions array in
7741 // reverse order to make it easier to reconstruct the partitions in ascending
7742 // order. In the choice between two optimal partitionings, it picks the one
7743 // which yields more jump tables.
7745 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7746 SmallVector<unsigned, 8> MinPartitions(N);
7747 // LastElement[i] is the last element of the partition starting at i.
7748 SmallVector<unsigned, 8> LastElement(N);
7749 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7750 SmallVector<unsigned, 8> NumTables(N);
7752 // Base case: There is only one way to partition Clusters[N-1].
7753 MinPartitions[N - 1] = 1;
7754 LastElement[N - 1] = N - 1;
7755 assert(MinJumpTableSize > 1);
7756 NumTables[N - 1] = 0;
7758 // Note: loop indexes are signed to avoid underflow.
7759 for (int64_t i = N - 2; i >= 0; i--) {
7760 // Find optimal partitioning of Clusters[i..N-1].
7761 // Baseline: Put Clusters[i] into a partition on its own.
7762 MinPartitions[i] = MinPartitions[i + 1] + 1;
7764 NumTables[i] = NumTables[i + 1];
7766 // Search for a solution that results in fewer partitions.
7767 for (int64_t j = N - 1; j > i; j--) {
7768 // Try building a partition from Clusters[i..j].
7769 if (isDense(Clusters, &TotalCases[0], i, j)) {
7770 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7771 bool IsTable = j - i + 1 >= MinJumpTableSize;
7772 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7774 // If this j leads to fewer partitions, or same number of partitions
7775 // with more lookup tables, it is a better partitioning.
7776 if (NumPartitions < MinPartitions[i] ||
7777 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7778 MinPartitions[i] = NumPartitions;
7780 NumTables[i] = Tables;
7786 // Iterate over the partitions, replacing some with jump tables in-place.
7787 unsigned DstIndex = 0;
7788 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7789 Last = LastElement[First];
7790 assert(Last >= First);
7791 assert(DstIndex <= First);
7792 unsigned NumClusters = Last - First + 1;
7794 CaseCluster JTCluster;
7795 if (NumClusters >= MinJumpTableSize &&
7796 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7797 Clusters[DstIndex++] = JTCluster;
7799 for (unsigned I = First; I <= Last; ++I)
7800 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7803 Clusters.resize(DstIndex);
7806 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7807 // FIXME: Using the pointer type doesn't seem ideal.
7808 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7809 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7813 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7816 const APInt &High) {
7817 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7818 // range of cases both require only one branch to lower. Just looking at the
7819 // number of clusters and destinations should be enough to decide whether to
7822 // To lower a range with bit tests, the range must fit the bitwidth of a
7824 if (!rangeFitsInWord(Low, High))
7827 // Decide whether it's profitable to lower this range with bit tests. Each
7828 // destination requires a bit test and branch, and there is an overall range
7829 // check branch. For a small number of clusters, separate comparisons might be
7830 // cheaper, and for many destinations, splitting the range might be better.
7831 return (NumDests == 1 && NumCmps >= 3) ||
7832 (NumDests == 2 && NumCmps >= 5) ||
7833 (NumDests == 3 && NumCmps >= 6);
7836 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7837 unsigned First, unsigned Last,
7838 const SwitchInst *SI,
7839 CaseCluster &BTCluster) {
7840 assert(First <= Last);
7844 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7845 unsigned NumCmps = 0;
7846 for (int64_t I = First; I <= Last; ++I) {
7847 assert(Clusters[I].Kind == CC_Range);
7848 Dests.set(Clusters[I].MBB->getNumber());
7849 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7851 unsigned NumDests = Dests.count();
7853 APInt Low = Clusters[First].Low->getValue();
7854 APInt High = Clusters[Last].High->getValue();
7855 assert(Low.slt(High));
7857 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7863 const int BitWidth = DAG.getTargetLoweringInfo()
7864 .getPointerTy(DAG.getDataLayout())
7866 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7868 // Check if the clusters cover a contiguous range such that no value in the
7869 // range will jump to the default statement.
7870 bool ContiguousRange = true;
7871 for (int64_t I = First + 1; I <= Last; ++I) {
7872 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7873 ContiguousRange = false;
7878 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7879 // Optimize the case where all the case values fit in a word without having
7880 // to subtract minValue. In this case, we can optimize away the subtraction.
7881 LowBound = APInt::getNullValue(Low.getBitWidth());
7883 ContiguousRange = false;
7886 CmpRange = High - Low;
7890 uint32_t TotalWeight = 0;
7891 for (unsigned i = First; i <= Last; ++i) {
7892 // Find the CaseBits for this destination.
7894 for (j = 0; j < CBV.size(); ++j)
7895 if (CBV[j].BB == Clusters[i].MBB)
7897 if (j == CBV.size())
7898 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7899 CaseBits *CB = &CBV[j];
7901 // Update Mask, Bits and ExtraWeight.
7902 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7903 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7904 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7905 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7906 CB->Bits += Hi - Lo + 1;
7907 CB->ExtraWeight += Clusters[i].Weight;
7908 TotalWeight += Clusters[i].Weight;
7909 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7913 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7914 // Sort by weight first, number of bits second.
7915 if (a.ExtraWeight != b.ExtraWeight)
7916 return a.ExtraWeight > b.ExtraWeight;
7917 return a.Bits > b.Bits;
7920 for (auto &CB : CBV) {
7921 MachineBasicBlock *BitTestBB =
7922 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7923 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7925 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7926 SI->getCondition(), -1U, MVT::Other, false,
7927 ContiguousRange, nullptr, nullptr, std::move(BTI),
7930 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7931 BitTestCases.size() - 1, TotalWeight);
7935 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7936 const SwitchInst *SI) {
7937 // Partition Clusters into as few subsets as possible, where each subset has a
7938 // range that fits in a machine word and has <= 3 unique destinations.
7941 // Clusters must be sorted and contain Range or JumpTable clusters.
7942 assert(!Clusters.empty());
7943 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7944 for (const CaseCluster &C : Clusters)
7945 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7946 for (unsigned i = 1; i < Clusters.size(); ++i)
7947 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7950 // The algorithm below is not suitable for -O0.
7951 if (TM.getOptLevel() == CodeGenOpt::None)
7954 // If target does not have legal shift left, do not emit bit tests at all.
7955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7956 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7957 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7960 int BitWidth = PTy.getSizeInBits();
7961 const int64_t N = Clusters.size();
7963 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7964 SmallVector<unsigned, 8> MinPartitions(N);
7965 // LastElement[i] is the last element of the partition starting at i.
7966 SmallVector<unsigned, 8> LastElement(N);
7968 // FIXME: This might not be the best algorithm for finding bit test clusters.
7970 // Base case: There is only one way to partition Clusters[N-1].
7971 MinPartitions[N - 1] = 1;
7972 LastElement[N - 1] = N - 1;
7974 // Note: loop indexes are signed to avoid underflow.
7975 for (int64_t i = N - 2; i >= 0; --i) {
7976 // Find optimal partitioning of Clusters[i..N-1].
7977 // Baseline: Put Clusters[i] into a partition on its own.
7978 MinPartitions[i] = MinPartitions[i + 1] + 1;
7981 // Search for a solution that results in fewer partitions.
7982 // Note: the search is limited by BitWidth, reducing time complexity.
7983 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7984 // Try building a partition from Clusters[i..j].
7987 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7988 Clusters[j].High->getValue()))
7991 // Check nbr of destinations and cluster types.
7992 // FIXME: This works, but doesn't seem very efficient.
7993 bool RangesOnly = true;
7994 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7995 for (int64_t k = i; k <= j; k++) {
7996 if (Clusters[k].Kind != CC_Range) {
8000 Dests.set(Clusters[k].MBB->getNumber());
8002 if (!RangesOnly || Dests.count() > 3)
8005 // Check if it's a better partition.
8006 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8007 if (NumPartitions < MinPartitions[i]) {
8008 // Found a better partition.
8009 MinPartitions[i] = NumPartitions;
8015 // Iterate over the partitions, replacing with bit-test clusters in-place.
8016 unsigned DstIndex = 0;
8017 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8018 Last = LastElement[First];
8019 assert(First <= Last);
8020 assert(DstIndex <= First);
8022 CaseCluster BitTestCluster;
8023 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8024 Clusters[DstIndex++] = BitTestCluster;
8026 size_t NumClusters = Last - First + 1;
8027 std::memmove(&Clusters[DstIndex], &Clusters[First],
8028 sizeof(Clusters[0]) * NumClusters);
8029 DstIndex += NumClusters;
8032 Clusters.resize(DstIndex);
8035 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8036 MachineBasicBlock *SwitchMBB,
8037 MachineBasicBlock *DefaultMBB) {
8038 MachineFunction *CurMF = FuncInfo.MF;
8039 MachineBasicBlock *NextMBB = nullptr;
8040 MachineFunction::iterator BBI = W.MBB;
8041 if (++BBI != FuncInfo.MF->end())
8044 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8046 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8048 if (Size == 2 && W.MBB == SwitchMBB) {
8049 // If any two of the cases has the same destination, and if one value
8050 // is the same as the other, but has one bit unset that the other has set,
8051 // use bit manipulation to do two compares at once. For example:
8052 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8053 // TODO: This could be extended to merge any 2 cases in switches with 3
8055 // TODO: Handle cases where W.CaseBB != SwitchBB.
8056 CaseCluster &Small = *W.FirstCluster;
8057 CaseCluster &Big = *W.LastCluster;
8059 if (Small.Low == Small.High && Big.Low == Big.High &&
8060 Small.MBB == Big.MBB) {
8061 const APInt &SmallValue = Small.Low->getValue();
8062 const APInt &BigValue = Big.Low->getValue();
8064 // Check that there is only one bit different.
8065 APInt CommonBit = BigValue ^ SmallValue;
8066 if (CommonBit.isPowerOf2()) {
8067 SDValue CondLHS = getValue(Cond);
8068 EVT VT = CondLHS.getValueType();
8069 SDLoc DL = getCurSDLoc();
8071 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8072 DAG.getConstant(CommonBit, DL, VT));
8073 SDValue Cond = DAG.getSetCC(
8074 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8077 // Update successor info.
8078 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8079 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8080 addSuccessorWithWeight(
8081 SwitchMBB, DefaultMBB,
8082 // The default destination is the first successor in IR.
8083 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8086 // Insert the true branch.
8088 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8089 DAG.getBasicBlock(Small.MBB));
8090 // Insert the false branch.
8091 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8092 DAG.getBasicBlock(DefaultMBB));
8094 DAG.setRoot(BrCond);
8100 if (TM.getOptLevel() != CodeGenOpt::None) {
8101 // Order cases by weight so the most likely case will be checked first.
8102 std::sort(W.FirstCluster, W.LastCluster + 1,
8103 [](const CaseCluster &a, const CaseCluster &b) {
8104 return a.Weight > b.Weight;
8107 // Rearrange the case blocks so that the last one falls through if possible
8108 // without without changing the order of weights.
8109 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8111 if (I->Weight > W.LastCluster->Weight)
8113 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8114 std::swap(*I, *W.LastCluster);
8120 // Compute total weight.
8121 uint32_t DefaultWeight = W.DefaultWeight;
8122 uint32_t UnhandledWeights = DefaultWeight;
8123 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8124 UnhandledWeights += I->Weight;
8125 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8128 MachineBasicBlock *CurMBB = W.MBB;
8129 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8130 MachineBasicBlock *Fallthrough;
8131 if (I == W.LastCluster) {
8132 // For the last cluster, fall through to the default destination.
8133 Fallthrough = DefaultMBB;
8135 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8136 CurMF->insert(BBI, Fallthrough);
8137 // Put Cond in a virtual register to make it available from the new blocks.
8138 ExportFromCurrentBlock(Cond);
8140 UnhandledWeights -= I->Weight;
8143 case CC_JumpTable: {
8144 // FIXME: Optimize away range check based on pivot comparisons.
8145 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8146 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8148 // The jump block hasn't been inserted yet; insert it here.
8149 MachineBasicBlock *JumpMBB = JT->MBB;
8150 CurMF->insert(BBI, JumpMBB);
8152 uint32_t JumpWeight = I->Weight;
8153 uint32_t FallthroughWeight = UnhandledWeights;
8155 // If the default statement is a target of the jump table, we evenly
8156 // distribute the default weight to successors of CurMBB. Also update
8157 // the weight on the edge from JumpMBB to Fallthrough.
8158 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8159 SE = JumpMBB->succ_end();
8161 if (*SI == DefaultMBB) {
8162 JumpWeight += DefaultWeight / 2;
8163 FallthroughWeight -= DefaultWeight / 2;
8164 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8169 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8170 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8172 // The jump table header will be inserted in our current block, do the
8173 // range check, and fall through to our fallthrough block.
8174 JTH->HeaderBB = CurMBB;
8175 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8177 // If we're in the right place, emit the jump table header right now.
8178 if (CurMBB == SwitchMBB) {
8179 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8180 JTH->Emitted = true;
8185 // FIXME: Optimize away range check based on pivot comparisons.
8186 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8188 // The bit test blocks haven't been inserted yet; insert them here.
8189 for (BitTestCase &BTC : BTB->Cases)
8190 CurMF->insert(BBI, BTC.ThisBB);
8192 // Fill in fields of the BitTestBlock.
8193 BTB->Parent = CurMBB;
8194 BTB->Default = Fallthrough;
8196 BTB->DefaultWeight = UnhandledWeights;
8197 // If the cases in bit test don't form a contiguous range, we evenly
8198 // distribute the weight on the edge to Fallthrough to two successors
8200 if (!BTB->ContiguousRange) {
8201 BTB->Weight += DefaultWeight / 2;
8202 BTB->DefaultWeight -= DefaultWeight / 2;
8205 // If we're in the right place, emit the bit test header right now.
8206 if (CurMBB == SwitchMBB) {
8207 visitBitTestHeader(*BTB, SwitchMBB);
8208 BTB->Emitted = true;
8213 const Value *RHS, *LHS, *MHS;
8215 if (I->Low == I->High) {
8216 // Check Cond == I->Low.
8222 // Check I->Low <= Cond <= I->High.
8229 // The false weight is the sum of all unhandled cases.
8230 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8233 if (CurMBB == SwitchMBB)
8234 visitSwitchCase(CB, SwitchMBB);
8236 SwitchCases.push_back(CB);
8241 CurMBB = Fallthrough;
8245 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8246 CaseClusterIt First,
8247 CaseClusterIt Last) {
8248 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8249 if (X.Weight != CC.Weight)
8250 return X.Weight > CC.Weight;
8252 // Ties are broken by comparing the case value.
8253 return X.Low->getValue().slt(CC.Low->getValue());
8257 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8258 const SwitchWorkListItem &W,
8260 MachineBasicBlock *SwitchMBB) {
8261 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8262 "Clusters not sorted?");
8264 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8266 // Balance the tree based on branch weights to create a near-optimal (in terms
8267 // of search time given key frequency) binary search tree. See e.g. Kurt
8268 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8269 CaseClusterIt LastLeft = W.FirstCluster;
8270 CaseClusterIt FirstRight = W.LastCluster;
8271 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8272 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8274 // Move LastLeft and FirstRight towards each other from opposite directions to
8275 // find a partitioning of the clusters which balances the weight on both
8276 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8277 // taken to ensure 0-weight nodes are distributed evenly.
8279 while (LastLeft + 1 < FirstRight) {
8280 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8281 LeftWeight += (++LastLeft)->Weight;
8283 RightWeight += (--FirstRight)->Weight;
8288 // Our binary search tree differs from a typical BST in that ours can have up
8289 // to three values in each leaf. The pivot selection above doesn't take that
8290 // into account, which means the tree might require more nodes and be less
8291 // efficient. We compensate for this here.
8293 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8294 unsigned NumRight = W.LastCluster - FirstRight + 1;
8296 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8297 // If one side has less than 3 clusters, and the other has more than 3,
8298 // consider taking a cluster from the other side.
8300 if (NumLeft < NumRight) {
8301 // Consider moving the first cluster on the right to the left side.
8302 CaseCluster &CC = *FirstRight;
8303 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8304 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8305 if (LeftSideRank <= RightSideRank) {
8306 // Moving the cluster to the left does not demote it.
8312 assert(NumRight < NumLeft);
8313 // Consider moving the last element on the left to the right side.
8314 CaseCluster &CC = *LastLeft;
8315 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8316 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8317 if (RightSideRank <= LeftSideRank) {
8318 // Moving the cluster to the right does not demot it.
8328 assert(LastLeft + 1 == FirstRight);
8329 assert(LastLeft >= W.FirstCluster);
8330 assert(FirstRight <= W.LastCluster);
8332 // Use the first element on the right as pivot since we will make less-than
8333 // comparisons against it.
8334 CaseClusterIt PivotCluster = FirstRight;
8335 assert(PivotCluster > W.FirstCluster);
8336 assert(PivotCluster <= W.LastCluster);
8338 CaseClusterIt FirstLeft = W.FirstCluster;
8339 CaseClusterIt LastRight = W.LastCluster;
8341 const ConstantInt *Pivot = PivotCluster->Low;
8343 // New blocks will be inserted immediately after the current one.
8344 MachineFunction::iterator BBI = W.MBB;
8347 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8348 // we can branch to its destination directly if it's squeezed exactly in
8349 // between the known lower bound and Pivot - 1.
8350 MachineBasicBlock *LeftMBB;
8351 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8352 FirstLeft->Low == W.GE &&
8353 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8354 LeftMBB = FirstLeft->MBB;
8356 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8357 FuncInfo.MF->insert(BBI, LeftMBB);
8359 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8360 // Put Cond in a virtual register to make it available from the new blocks.
8361 ExportFromCurrentBlock(Cond);
8364 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8365 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8366 // directly if RHS.High equals the current upper bound.
8367 MachineBasicBlock *RightMBB;
8368 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8369 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8370 RightMBB = FirstRight->MBB;
8372 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8373 FuncInfo.MF->insert(BBI, RightMBB);
8375 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8376 // Put Cond in a virtual register to make it available from the new blocks.
8377 ExportFromCurrentBlock(Cond);
8380 // Create the CaseBlock record that will be used to lower the branch.
8381 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8382 LeftWeight, RightWeight);
8384 if (W.MBB == SwitchMBB)
8385 visitSwitchCase(CB, SwitchMBB);
8387 SwitchCases.push_back(CB);
8390 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8391 // Extract cases from the switch.
8392 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8393 CaseClusterVector Clusters;
8394 Clusters.reserve(SI.getNumCases());
8395 for (auto I : SI.cases()) {
8396 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8397 const ConstantInt *CaseVal = I.getCaseValue();
8399 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8400 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8403 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8405 // Cluster adjacent cases with the same destination. We do this at all
8406 // optimization levels because it's cheap to do and will make codegen faster
8407 // if there are many clusters.
8408 sortAndRangeify(Clusters);
8410 if (TM.getOptLevel() != CodeGenOpt::None) {
8411 // Replace an unreachable default with the most popular destination.
8412 // FIXME: Exploit unreachable default more aggressively.
8413 bool UnreachableDefault =
8414 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8415 if (UnreachableDefault && !Clusters.empty()) {
8416 DenseMap<const BasicBlock *, unsigned> Popularity;
8417 unsigned MaxPop = 0;
8418 const BasicBlock *MaxBB = nullptr;
8419 for (auto I : SI.cases()) {
8420 const BasicBlock *BB = I.getCaseSuccessor();
8421 if (++Popularity[BB] > MaxPop) {
8422 MaxPop = Popularity[BB];
8427 assert(MaxPop > 0 && MaxBB);
8428 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8430 // Remove cases that were pointing to the destination that is now the
8432 CaseClusterVector New;
8433 New.reserve(Clusters.size());
8434 for (CaseCluster &CC : Clusters) {
8435 if (CC.MBB != DefaultMBB)
8438 Clusters = std::move(New);
8442 // If there is only the default destination, jump there directly.
8443 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8444 if (Clusters.empty()) {
8445 SwitchMBB->addSuccessor(DefaultMBB);
8446 if (DefaultMBB != NextBlock(SwitchMBB)) {
8447 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8448 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8453 findJumpTables(Clusters, &SI, DefaultMBB);
8454 findBitTestClusters(Clusters, &SI);
8457 dbgs() << "Case clusters: ";
8458 for (const CaseCluster &C : Clusters) {
8459 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8460 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8462 C.Low->getValue().print(dbgs(), true);
8463 if (C.Low != C.High) {
8465 C.High->getValue().print(dbgs(), true);
8472 assert(!Clusters.empty());
8473 SwitchWorkList WorkList;
8474 CaseClusterIt First = Clusters.begin();
8475 CaseClusterIt Last = Clusters.end() - 1;
8476 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8477 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8479 while (!WorkList.empty()) {
8480 SwitchWorkListItem W = WorkList.back();
8481 WorkList.pop_back();
8482 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8484 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8485 // For optimized builds, lower large range as a balanced binary tree.
8486 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8490 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);