1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
82 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
83 cl::desc("Enable fast-math-flags for DAG nodes"));
85 // Limit the width of DAG chains. This is important in general to prevent
86 // DAG-based analysis from blowing up. For example, alias analysis and
87 // load clustering may not complete in reasonable time. It is difficult to
88 // recognize and avoid this situation within each individual analysis, and
89 // future analyses are likely to have the same behavior. Limiting DAG width is
90 // the safe approach and will be especially important with global DAGs.
92 // MaxParallelChains default is arbitrarily high to avoid affecting
93 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
94 // sequence over this should have been converted to llvm.memcpy by the
95 // frontend. It easy to induce this behavior with .ll code such as:
96 // %buffer = alloca [4096 x i8]
97 // %data = load [4096 x i8]* %argPtr
98 // store [4096 x i8] %data, [4096 x i8]* %buffer
99 static const unsigned MaxParallelChains = 64;
101 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts, unsigned NumParts,
103 MVT PartVT, EVT ValueVT, const Value *V);
105 /// getCopyFromParts - Create a value that contains the specified legal parts
106 /// combined into the value they represent. If the parts combine to a type
107 /// larger then ValueVT then AssertOp can be used to specify whether the extra
108 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
109 /// (ISD::AssertSext).
110 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
111 const SDValue *Parts,
112 unsigned NumParts, MVT PartVT, EVT ValueVT,
114 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
115 if (ValueVT.isVector())
116 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
119 assert(NumParts > 0 && "No parts to assemble!");
120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
121 SDValue Val = Parts[0];
124 // Assemble the value from multiple parts.
125 if (ValueVT.isInteger()) {
126 unsigned PartBits = PartVT.getSizeInBits();
127 unsigned ValueBits = ValueVT.getSizeInBits();
129 // Assemble the power of 2 part.
130 unsigned RoundParts = NumParts & (NumParts - 1) ?
131 1 << Log2_32(NumParts) : NumParts;
132 unsigned RoundBits = PartBits * RoundParts;
133 EVT RoundVT = RoundBits == ValueBits ?
134 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
137 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
139 if (RoundParts > 2) {
140 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
142 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
143 RoundParts / 2, PartVT, HalfVT, V);
145 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
146 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
149 if (TLI.isBigEndian())
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
154 if (RoundParts < NumParts) {
155 // Assemble the trailing non-power-of-2 part.
156 unsigned OddParts = NumParts - RoundParts;
157 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
158 Hi = getCopyFromParts(DAG, DL,
159 Parts + RoundParts, OddParts, PartVT, OddVT, V);
161 // Combine the round and odd parts.
163 if (TLI.isBigEndian())
165 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
166 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
167 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
168 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
169 TLI.getPointerTy()));
170 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
171 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
173 } else if (PartVT.isFloatingPoint()) {
174 // FP split into multiple FP parts (for ppcf128)
175 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
178 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
179 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
180 if (TLI.hasBigEndianPartOrdering(ValueVT))
182 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
184 // FP split into integer parts (soft fp)
185 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
186 !PartVT.isVector() && "Unexpected split");
187 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
188 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
192 // There is now one part, held in Val. Correct it to match ValueVT.
193 EVT PartEVT = Val.getValueType();
195 if (PartEVT == ValueVT)
198 if (PartEVT.isInteger() && ValueVT.isInteger()) {
199 if (ValueVT.bitsLT(PartEVT)) {
200 // For a truncate, see if we have any information to
201 // indicate whether the truncated bits will always be
202 // zero or sign-extension.
203 if (AssertOp != ISD::DELETED_NODE)
204 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
205 DAG.getValueType(ValueVT));
206 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
208 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
211 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
212 // FP_ROUND's are always exact here.
213 if (ValueVT.bitsLT(Val.getValueType()))
214 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
215 DAG.getTargetConstant(1, DL, TLI.getPointerTy()));
217 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
220 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
221 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
223 llvm_unreachable("Unknown mismatch!");
226 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
227 const Twine &ErrMsg) {
228 const Instruction *I = dyn_cast_or_null<Instruction>(V);
230 return Ctx.emitError(ErrMsg);
232 const char *AsmError = ", possible invalid constraint for vector type";
233 if (const CallInst *CI = dyn_cast<CallInst>(I))
234 if (isa<InlineAsm>(CI->getCalledValue()))
235 return Ctx.emitError(I, ErrMsg + AsmError);
237 return Ctx.emitError(I, ErrMsg);
240 /// getCopyFromPartsVector - Create a value that contains the specified legal
241 /// parts combined into the value they represent. If the parts combine to a
242 /// type larger then ValueVT then AssertOp can be used to specify whether the
243 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
244 /// ValueVT (ISD::AssertSext).
245 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
246 const SDValue *Parts, unsigned NumParts,
247 MVT PartVT, EVT ValueVT, const Value *V) {
248 assert(ValueVT.isVector() && "Not a vector value");
249 assert(NumParts > 0 && "No parts to assemble!");
250 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
251 SDValue Val = Parts[0];
253 // Handle a multi-element vector.
257 unsigned NumIntermediates;
259 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
260 NumIntermediates, RegisterVT);
261 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
262 NumParts = NumRegs; // Silence a compiler warning.
263 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
264 assert(RegisterVT == Parts[0].getSimpleValueType() &&
265 "Part type doesn't match part!");
267 // Assemble the parts into intermediate operands.
268 SmallVector<SDValue, 8> Ops(NumIntermediates);
269 if (NumIntermediates == NumParts) {
270 // If the register was not expanded, truncate or copy the value,
272 for (unsigned i = 0; i != NumParts; ++i)
273 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
274 PartVT, IntermediateVT, V);
275 } else if (NumParts > 0) {
276 // If the intermediate type was expanded, build the intermediate
277 // operands from the parts.
278 assert(NumParts % NumIntermediates == 0 &&
279 "Must expand into a divisible number of parts!");
280 unsigned Factor = NumParts / NumIntermediates;
281 for (unsigned i = 0; i != NumIntermediates; ++i)
282 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
283 PartVT, IntermediateVT, V);
286 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
287 // intermediate operands.
288 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
293 // There is now one part, held in Val. Correct it to match ValueVT.
294 EVT PartEVT = Val.getValueType();
296 if (PartEVT == ValueVT)
299 if (PartEVT.isVector()) {
300 // If the element type of the source/dest vectors are the same, but the
301 // parts vector has more elements than the value vector, then we have a
302 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
304 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
305 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
306 "Cannot narrow, it would be a lossy transformation");
307 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
308 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
311 // Vector/Vector bitcast.
312 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
313 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
315 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
316 "Cannot handle this kind of promotion");
317 // Promoted vector extract
318 bool Smaller = ValueVT.bitsLE(PartEVT);
319 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
324 // Trivial bitcast if the types are the same size and the destination
325 // vector type is legal.
326 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
327 TLI.isTypeLegal(ValueVT))
328 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
330 // Handle cases such as i8 -> <1 x i1>
331 if (ValueVT.getVectorNumElements() != 1) {
332 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
333 "non-trivial scalar-to-vector conversion");
334 return DAG.getUNDEF(ValueVT);
337 if (ValueVT.getVectorNumElements() == 1 &&
338 ValueVT.getVectorElementType() != PartEVT) {
339 bool Smaller = ValueVT.bitsLE(PartEVT);
340 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
341 DL, ValueVT.getScalarType(), Val);
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
365 unsigned PartBits = PartVT.getSizeInBits();
366 unsigned OrigNumParts = NumParts;
367 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (TLI.isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (TLI.isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
500 ElementVT, Val, DAG.getConstant(i, DL,
501 TLI.getVectorIdxTy())));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 bool Smaller = PartEVT.bitsLE(ValueVT);
520 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
523 // Vector -> scalar conversion.
524 assert(ValueVT.getVectorNumElements() == 1 &&
525 "Only trivial vector-to-scalar conversions should get here!");
526 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
528 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
530 bool Smaller = ValueVT.bitsLE(PartVT);
531 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
539 // Handle a multi-element vector.
542 unsigned NumIntermediates;
543 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
545 NumIntermediates, RegisterVT);
546 unsigned NumElements = ValueVT.getVectorNumElements();
548 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
549 NumParts = NumRegs; // Silence a compiler warning.
550 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
552 // Split the vector into intermediate operands.
553 SmallVector<SDValue, 8> Ops(NumIntermediates);
554 for (unsigned i = 0; i != NumIntermediates; ++i) {
555 if (IntermediateVT.isVector())
556 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
558 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
559 TLI.getVectorIdxTy()));
561 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
563 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
566 // Split the intermediate operands into legal parts.
567 if (NumParts == NumIntermediates) {
568 // If the register was not expanded, promote or copy the value,
570 for (unsigned i = 0; i != NumParts; ++i)
571 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
572 } else if (NumParts > 0) {
573 // If the intermediate type was expanded, split each the value into
575 assert(NumIntermediates != 0 && "division by zero");
576 assert(NumParts % NumIntermediates == 0 &&
577 "Must expand into a divisible number of parts!");
578 unsigned Factor = NumParts / NumIntermediates;
579 for (unsigned i = 0; i != NumIntermediates; ++i)
580 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
584 RegsForValue::RegsForValue() {}
586 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
588 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
590 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &tli,
591 unsigned Reg, Type *Ty) {
592 ComputeValueVTs(tli, Ty, ValueVTs);
594 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
595 EVT ValueVT = ValueVTs[Value];
596 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
597 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
598 for (unsigned i = 0; i != NumRegs; ++i)
599 Regs.push_back(Reg + i);
600 RegVTs.push_back(RegisterVT);
605 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
606 /// this value and returns the result as a ValueVT value. This uses
607 /// Chain/Flag as the input and updates them for the output Chain/Flag.
608 /// If the Flag pointer is NULL, no flag is used.
609 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
610 FunctionLoweringInfo &FuncInfo,
612 SDValue &Chain, SDValue *Flag,
613 const Value *V) const {
614 // A Value with type {} or [0 x %t] needs no registers.
615 if (ValueVTs.empty())
618 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
620 // Assemble the legal parts into the final values.
621 SmallVector<SDValue, 4> Values(ValueVTs.size());
622 SmallVector<SDValue, 8> Parts;
623 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
624 // Copy the legal parts from the registers.
625 EVT ValueVT = ValueVTs[Value];
626 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
627 MVT RegisterVT = RegVTs[Value];
629 Parts.resize(NumRegs);
630 for (unsigned i = 0; i != NumRegs; ++i) {
633 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
635 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
636 *Flag = P.getValue(2);
639 Chain = P.getValue(1);
642 // If the source register was virtual and if we know something about it,
643 // add an assert node.
644 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
645 !RegisterVT.isInteger() || RegisterVT.isVector())
648 const FunctionLoweringInfo::LiveOutInfo *LOI =
649 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
653 unsigned RegSize = RegisterVT.getSizeInBits();
654 unsigned NumSignBits = LOI->NumSignBits;
655 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
657 if (NumZeroBits == RegSize) {
658 // The current value is a zero.
659 // Explicitly express that as it would be easier for
660 // optimizations to kick in.
661 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
665 // FIXME: We capture more information than the dag can represent. For
666 // now, just use the tightest assertzext/assertsext possible.
668 EVT FromVT(MVT::Other);
669 if (NumSignBits == RegSize)
670 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
671 else if (NumZeroBits >= RegSize-1)
672 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
673 else if (NumSignBits > RegSize-8)
674 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
675 else if (NumZeroBits >= RegSize-8)
676 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
677 else if (NumSignBits > RegSize-16)
678 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
679 else if (NumZeroBits >= RegSize-16)
680 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
681 else if (NumSignBits > RegSize-32)
682 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
683 else if (NumZeroBits >= RegSize-32)
684 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
688 // Add an assertion node.
689 assert(FromVT != MVT::Other);
690 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
691 RegisterVT, P, DAG.getValueType(FromVT));
694 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
695 NumRegs, RegisterVT, ValueVT, V);
700 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
703 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
704 /// specified value into the registers specified by this object. This uses
705 /// Chain/Flag as the input and updates them for the output Chain/Flag.
706 /// If the Flag pointer is NULL, no flag is used.
707 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
708 SDValue &Chain, SDValue *Flag, const Value *V,
709 ISD::NodeType PreferredExtendType) const {
710 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
711 ISD::NodeType ExtendKind = PreferredExtendType;
713 // Get the list of the values's legal parts.
714 unsigned NumRegs = Regs.size();
715 SmallVector<SDValue, 8> Parts(NumRegs);
716 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
717 EVT ValueVT = ValueVTs[Value];
718 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
719 MVT RegisterVT = RegVTs[Value];
721 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
722 ExtendKind = ISD::ZERO_EXTEND;
724 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
725 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
729 // Copy the parts into the registers.
730 SmallVector<SDValue, 8> Chains(NumRegs);
731 for (unsigned i = 0; i != NumRegs; ++i) {
734 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
736 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
737 *Flag = Part.getValue(1);
740 Chains[i] = Part.getValue(0);
743 if (NumRegs == 1 || Flag)
744 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
745 // flagged to it. That is the CopyToReg nodes and the user are considered
746 // a single scheduling unit. If we create a TokenFactor and return it as
747 // chain, then the TokenFactor is both a predecessor (operand) of the
748 // user as well as a successor (the TF operands are flagged to the user).
749 // c1, f1 = CopyToReg
750 // c2, f2 = CopyToReg
751 // c3 = TokenFactor c1, c2
754 Chain = Chains[NumRegs-1];
756 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
759 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
760 /// operand list. This adds the code marker and includes the number of
761 /// values added into it.
762 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
763 unsigned MatchingIdx, SDLoc dl,
765 std::vector<SDValue> &Ops) const {
766 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
768 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
770 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
771 else if (!Regs.empty() &&
772 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
773 // Put the register class of the virtual registers in the flag word. That
774 // way, later passes can recompute register class constraints for inline
775 // assembly as well as normal instructions.
776 // Don't do this for tied operands that can use the regclass information
778 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
779 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
780 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
783 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
786 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
787 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
788 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
789 MVT RegisterVT = RegVTs[Value];
790 for (unsigned i = 0; i != NumRegs; ++i) {
791 assert(Reg < Regs.size() && "Mismatch in # registers expected");
792 unsigned TheReg = Regs[Reg++];
793 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
795 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
796 // If we clobbered the stack pointer, MFI should know about it.
797 assert(DAG.getMachineFunction().getFrameInfo()->
798 hasInlineAsmWithSPAdjust());
804 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
805 const TargetLibraryInfo *li) {
809 DL = DAG.getTarget().getDataLayout();
810 Context = DAG.getContext();
811 LPadToCallSiteMap.clear();
814 /// clear - Clear out the current SelectionDAG and the associated
815 /// state and prepare this SelectionDAGBuilder object to be used
816 /// for a new block. This doesn't clear out information about
817 /// additional blocks that are needed to complete switch lowering
818 /// or PHI node updating; that information is cleared out as it is
820 void SelectionDAGBuilder::clear() {
822 UnusedArgNodeMap.clear();
823 PendingLoads.clear();
824 PendingExports.clear();
827 SDNodeOrder = LowestSDNodeOrder;
828 StatepointLowering.clear();
831 /// clearDanglingDebugInfo - Clear the dangling debug information
832 /// map. This function is separated from the clear so that debug
833 /// information that is dangling in a basic block can be properly
834 /// resolved in a different basic block. This allows the
835 /// SelectionDAG to resolve dangling debug information attached
837 void SelectionDAGBuilder::clearDanglingDebugInfo() {
838 DanglingDebugInfoMap.clear();
841 /// getRoot - Return the current virtual root of the Selection DAG,
842 /// flushing any PendingLoad items. This must be done before emitting
843 /// a store or any other node that may need to be ordered after any
844 /// prior load instructions.
846 SDValue SelectionDAGBuilder::getRoot() {
847 if (PendingLoads.empty())
848 return DAG.getRoot();
850 if (PendingLoads.size() == 1) {
851 SDValue Root = PendingLoads[0];
853 PendingLoads.clear();
857 // Otherwise, we have to make a token factor node.
858 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
860 PendingLoads.clear();
865 /// getControlRoot - Similar to getRoot, but instead of flushing all the
866 /// PendingLoad items, flush all the PendingExports items. It is necessary
867 /// to do this before emitting a terminator instruction.
869 SDValue SelectionDAGBuilder::getControlRoot() {
870 SDValue Root = DAG.getRoot();
872 if (PendingExports.empty())
875 // Turn all of the CopyToReg chains into one factored node.
876 if (Root.getOpcode() != ISD::EntryToken) {
877 unsigned i = 0, e = PendingExports.size();
878 for (; i != e; ++i) {
879 assert(PendingExports[i].getNode()->getNumOperands() > 1);
880 if (PendingExports[i].getNode()->getOperand(0) == Root)
881 break; // Don't add the root if we already indirectly depend on it.
885 PendingExports.push_back(Root);
888 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
890 PendingExports.clear();
895 void SelectionDAGBuilder::visit(const Instruction &I) {
896 // Set up outgoing PHI node register values before emitting the terminator.
897 if (isa<TerminatorInst>(&I))
898 HandlePHINodesInSuccessorBlocks(I.getParent());
904 visit(I.getOpcode(), I);
906 if (!isa<TerminatorInst>(&I) && !HasTailCall)
907 CopyToExportRegsIfNeeded(&I);
912 void SelectionDAGBuilder::visitPHI(const PHINode &) {
913 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
916 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
917 // Note: this doesn't use InstVisitor, because it has to work with
918 // ConstantExpr's in addition to instructions.
920 default: llvm_unreachable("Unknown instruction type encountered!");
921 // Build the switch statement using the Instruction.def file.
922 #define HANDLE_INST(NUM, OPCODE, CLASS) \
923 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
924 #include "llvm/IR/Instruction.def"
928 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
929 // generate the debug data structures now that we've seen its definition.
930 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
932 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
934 const DbgValueInst *DI = DDI.getDI();
935 DebugLoc dl = DDI.getdl();
936 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
937 DILocalVariable *Variable = DI->getVariable();
938 DIExpression *Expr = DI->getExpression();
939 assert(Variable->isValidLocationForIntrinsic(dl) &&
940 "Expected inlined-at fields to agree");
941 uint64_t Offset = DI->getOffset();
942 // A dbg.value for an alloca is always indirect.
943 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
946 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
948 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
949 IsIndirect, Offset, dl, DbgSDNodeOrder);
950 DAG.AddDbgValue(SDV, Val.getNode(), false);
953 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
954 DanglingDebugInfoMap[V] = DanglingDebugInfo();
958 /// getCopyFromRegs - If there was virtual register allocated for the value V
959 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
960 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
961 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
964 if (It != FuncInfo.ValueMap.end()) {
965 unsigned InReg = It->second;
966 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
968 SDValue Chain = DAG.getEntryNode();
969 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
970 resolveDanglingDebugInfo(V, Result);
976 /// getValue - Return an SDValue for the given Value.
977 SDValue SelectionDAGBuilder::getValue(const Value *V) {
978 // If we already have an SDValue for this value, use it. It's important
979 // to do this first, so that we don't create a CopyFromReg if we already
980 // have a regular SDValue.
981 SDValue &N = NodeMap[V];
982 if (N.getNode()) return N;
984 // If there's a virtual register allocated and initialized for this
986 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
987 if (copyFromReg.getNode()) {
991 // Otherwise create a new SDValue and remember it.
992 SDValue Val = getValueImpl(V);
994 resolveDanglingDebugInfo(V, Val);
998 // Return true if SDValue exists for the given Value
999 bool SelectionDAGBuilder::findValue(const Value *V) const {
1000 return (NodeMap.find(V) != NodeMap.end()) ||
1001 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1004 /// getNonRegisterValue - Return an SDValue for the given Value, but
1005 /// don't look in FuncInfo.ValueMap for a virtual register.
1006 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1007 // If we already have an SDValue for this value, use it.
1008 SDValue &N = NodeMap[V];
1010 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1011 // Remove the debug location from the node as the node is about to be used
1012 // in a location which may differ from the original debug location. This
1013 // is relevant to Constant and ConstantFP nodes because they can appear
1014 // as constant expressions inside PHI nodes.
1015 N->setDebugLoc(DebugLoc());
1020 // Otherwise create a new SDValue and remember it.
1021 SDValue Val = getValueImpl(V);
1023 resolveDanglingDebugInfo(V, Val);
1027 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1028 /// Create an SDValue for the given value.
1029 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1030 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1032 if (const Constant *C = dyn_cast<Constant>(V)) {
1033 EVT VT = TLI.getValueType(V->getType(), true);
1035 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1036 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1038 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1039 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1041 if (isa<ConstantPointerNull>(C)) {
1042 unsigned AS = V->getType()->getPointerAddressSpace();
1043 return DAG.getConstant(0, getCurSDLoc(), TLI.getPointerTy(AS));
1046 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1047 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1049 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1050 return DAG.getUNDEF(VT);
1052 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1053 visit(CE->getOpcode(), *CE);
1054 SDValue N1 = NodeMap[V];
1055 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1059 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1060 SmallVector<SDValue, 4> Constants;
1061 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1063 SDNode *Val = getValue(*OI).getNode();
1064 // If the operand is an empty aggregate, there are no values.
1066 // Add each leaf value from the operand to the Constants list
1067 // to form a flattened list of all the values.
1068 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1069 Constants.push_back(SDValue(Val, i));
1072 return DAG.getMergeValues(Constants, getCurSDLoc());
1075 if (const ConstantDataSequential *CDS =
1076 dyn_cast<ConstantDataSequential>(C)) {
1077 SmallVector<SDValue, 4> Ops;
1078 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1079 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1080 // Add each leaf value from the operand to the Constants list
1081 // to form a flattened list of all the values.
1082 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1083 Ops.push_back(SDValue(Val, i));
1086 if (isa<ArrayType>(CDS->getType()))
1087 return DAG.getMergeValues(Ops, getCurSDLoc());
1088 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1092 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1093 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1094 "Unknown struct or array constant!");
1096 SmallVector<EVT, 4> ValueVTs;
1097 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1098 unsigned NumElts = ValueVTs.size();
1100 return SDValue(); // empty struct
1101 SmallVector<SDValue, 4> Constants(NumElts);
1102 for (unsigned i = 0; i != NumElts; ++i) {
1103 EVT EltVT = ValueVTs[i];
1104 if (isa<UndefValue>(C))
1105 Constants[i] = DAG.getUNDEF(EltVT);
1106 else if (EltVT.isFloatingPoint())
1107 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1109 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1112 return DAG.getMergeValues(Constants, getCurSDLoc());
1115 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1116 return DAG.getBlockAddress(BA, VT);
1118 VectorType *VecTy = cast<VectorType>(V->getType());
1119 unsigned NumElements = VecTy->getNumElements();
1121 // Now that we know the number and type of the elements, get that number of
1122 // elements into the Ops array based on what kind of constant it is.
1123 SmallVector<SDValue, 16> Ops;
1124 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1125 for (unsigned i = 0; i != NumElements; ++i)
1126 Ops.push_back(getValue(CV->getOperand(i)));
1128 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1129 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1132 if (EltVT.isFloatingPoint())
1133 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1135 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1136 Ops.assign(NumElements, Op);
1139 // Create a BUILD_VECTOR node.
1140 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1143 // If this is a static alloca, generate it as the frameindex instead of
1145 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1146 DenseMap<const AllocaInst*, int>::iterator SI =
1147 FuncInfo.StaticAllocaMap.find(AI);
1148 if (SI != FuncInfo.StaticAllocaMap.end())
1149 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1152 // If this is an instruction which fast-isel has deferred, select it now.
1153 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1154 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1155 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1156 SDValue Chain = DAG.getEntryNode();
1157 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1160 llvm_unreachable("Can't get register for value!");
1163 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1164 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1165 SDValue Chain = getControlRoot();
1166 SmallVector<ISD::OutputArg, 8> Outs;
1167 SmallVector<SDValue, 8> OutVals;
1169 if (!FuncInfo.CanLowerReturn) {
1170 unsigned DemoteReg = FuncInfo.DemoteRegister;
1171 const Function *F = I.getParent()->getParent();
1173 // Emit a store of the return value through the virtual register.
1174 // Leave Outs empty so that LowerReturn won't try to load return
1175 // registers the usual way.
1176 SmallVector<EVT, 1> PtrValueVTs;
1177 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1180 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1181 SDValue RetOp = getValue(I.getOperand(0));
1183 SmallVector<EVT, 4> ValueVTs;
1184 SmallVector<uint64_t, 4> Offsets;
1185 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1186 unsigned NumValues = ValueVTs.size();
1188 SmallVector<SDValue, 4> Chains(NumValues);
1189 for (unsigned i = 0; i != NumValues; ++i) {
1190 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1191 RetPtr.getValueType(), RetPtr,
1192 DAG.getIntPtrConstant(Offsets[i],
1195 DAG.getStore(Chain, getCurSDLoc(),
1196 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1197 // FIXME: better loc info would be nice.
1198 Add, MachinePointerInfo(), false, false, 0);
1201 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1202 MVT::Other, Chains);
1203 } else if (I.getNumOperands() != 0) {
1204 SmallVector<EVT, 4> ValueVTs;
1205 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1206 unsigned NumValues = ValueVTs.size();
1208 SDValue RetOp = getValue(I.getOperand(0));
1210 const Function *F = I.getParent()->getParent();
1212 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1213 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1215 ExtendKind = ISD::SIGN_EXTEND;
1216 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1218 ExtendKind = ISD::ZERO_EXTEND;
1220 LLVMContext &Context = F->getContext();
1221 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1224 for (unsigned j = 0; j != NumValues; ++j) {
1225 EVT VT = ValueVTs[j];
1227 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1228 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1230 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1231 MVT PartVT = TLI.getRegisterType(Context, VT);
1232 SmallVector<SDValue, 4> Parts(NumParts);
1233 getCopyToParts(DAG, getCurSDLoc(),
1234 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1235 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1237 // 'inreg' on function refers to return value
1238 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1242 // Propagate extension type if any
1243 if (ExtendKind == ISD::SIGN_EXTEND)
1245 else if (ExtendKind == ISD::ZERO_EXTEND)
1248 for (unsigned i = 0; i < NumParts; ++i) {
1249 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1250 VT, /*isfixed=*/true, 0, 0));
1251 OutVals.push_back(Parts[i]);
1257 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1258 CallingConv::ID CallConv =
1259 DAG.getMachineFunction().getFunction()->getCallingConv();
1260 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1261 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1263 // Verify that the target's LowerReturn behaved as expected.
1264 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1265 "LowerReturn didn't return a valid chain!");
1267 // Update the DAG with the new chain value resulting from return lowering.
1271 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1272 /// created for it, emit nodes to copy the value into the virtual
1274 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1276 if (V->getType()->isEmptyTy())
1279 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1280 if (VMI != FuncInfo.ValueMap.end()) {
1281 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1282 CopyValueToVirtualRegister(V, VMI->second);
1286 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1287 /// the current basic block, add it to ValueMap now so that we'll get a
1289 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1290 // No need to export constants.
1291 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1293 // Already exported?
1294 if (FuncInfo.isExportedInst(V)) return;
1296 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1297 CopyValueToVirtualRegister(V, Reg);
1300 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1301 const BasicBlock *FromBB) {
1302 // The operands of the setcc have to be in this block. We don't know
1303 // how to export them from some other block.
1304 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1305 // Can export from current BB.
1306 if (VI->getParent() == FromBB)
1309 // Is already exported, noop.
1310 return FuncInfo.isExportedInst(V);
1313 // If this is an argument, we can export it if the BB is the entry block or
1314 // if it is already exported.
1315 if (isa<Argument>(V)) {
1316 if (FromBB == &FromBB->getParent()->getEntryBlock())
1319 // Otherwise, can only export this if it is already exported.
1320 return FuncInfo.isExportedInst(V);
1323 // Otherwise, constants can always be exported.
1327 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1328 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1329 const MachineBasicBlock *Dst) const {
1330 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1333 const BasicBlock *SrcBB = Src->getBasicBlock();
1334 const BasicBlock *DstBB = Dst->getBasicBlock();
1335 return BPI->getEdgeWeight(SrcBB, DstBB);
1338 void SelectionDAGBuilder::
1339 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1340 uint32_t Weight /* = 0 */) {
1342 Weight = getEdgeWeight(Src, Dst);
1343 Src->addSuccessor(Dst, Weight);
1347 static bool InBlock(const Value *V, const BasicBlock *BB) {
1348 if (const Instruction *I = dyn_cast<Instruction>(V))
1349 return I->getParent() == BB;
1353 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1354 /// This function emits a branch and is used at the leaves of an OR or an
1355 /// AND operator tree.
1358 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1359 MachineBasicBlock *TBB,
1360 MachineBasicBlock *FBB,
1361 MachineBasicBlock *CurBB,
1362 MachineBasicBlock *SwitchBB,
1365 const BasicBlock *BB = CurBB->getBasicBlock();
1367 // If the leaf of the tree is a comparison, merge the condition into
1369 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1370 // The operands of the cmp have to be in this block. We don't know
1371 // how to export them from some other block. If this is the first block
1372 // of the sequence, no exporting is needed.
1373 if (CurBB == SwitchBB ||
1374 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1375 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1376 ISD::CondCode Condition;
1377 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1378 Condition = getICmpCondCode(IC->getPredicate());
1379 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1380 Condition = getFCmpCondCode(FC->getPredicate());
1381 if (TM.Options.NoNaNsFPMath)
1382 Condition = getFCmpCodeWithoutNaN(Condition);
1384 (void)Condition; // silence warning.
1385 llvm_unreachable("Unknown compare instruction");
1388 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1389 TBB, FBB, CurBB, TWeight, FWeight);
1390 SwitchCases.push_back(CB);
1395 // Create a CaseBlock record representing this branch.
1396 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1397 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1398 SwitchCases.push_back(CB);
1401 /// Scale down both weights to fit into uint32_t.
1402 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1403 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1404 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1405 NewTrue = NewTrue / Scale;
1406 NewFalse = NewFalse / Scale;
1409 /// FindMergedConditions - If Cond is an expression like
1410 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1411 MachineBasicBlock *TBB,
1412 MachineBasicBlock *FBB,
1413 MachineBasicBlock *CurBB,
1414 MachineBasicBlock *SwitchBB,
1415 unsigned Opc, uint32_t TWeight,
1417 // If this node is not part of the or/and tree, emit it as a branch.
1418 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1419 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1420 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1421 BOp->getParent() != CurBB->getBasicBlock() ||
1422 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1423 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1424 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1429 // Create TmpBB after CurBB.
1430 MachineFunction::iterator BBI = CurBB;
1431 MachineFunction &MF = DAG.getMachineFunction();
1432 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1433 CurBB->getParent()->insert(++BBI, TmpBB);
1435 if (Opc == Instruction::Or) {
1436 // Codegen X | Y as:
1445 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1446 // The requirement is that
1447 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1448 // = TrueProb for orignal BB.
1449 // Assuming the orignal weights are A and B, one choice is to set BB1's
1450 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1452 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1453 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1454 // TmpBB, but the math is more complicated.
1456 uint64_t NewTrueWeight = TWeight;
1457 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1458 ScaleWeights(NewTrueWeight, NewFalseWeight);
1459 // Emit the LHS condition.
1460 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1461 NewTrueWeight, NewFalseWeight);
1463 NewTrueWeight = TWeight;
1464 NewFalseWeight = 2 * (uint64_t)FWeight;
1465 ScaleWeights(NewTrueWeight, NewFalseWeight);
1466 // Emit the RHS condition into TmpBB.
1467 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1468 NewTrueWeight, NewFalseWeight);
1470 assert(Opc == Instruction::And && "Unknown merge op!");
1471 // Codegen X & Y as:
1479 // This requires creation of TmpBB after CurBB.
1481 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1482 // The requirement is that
1483 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1484 // = FalseProb for orignal BB.
1485 // Assuming the orignal weights are A and B, one choice is to set BB1's
1486 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1488 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1490 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1491 uint64_t NewFalseWeight = FWeight;
1492 ScaleWeights(NewTrueWeight, NewFalseWeight);
1493 // Emit the LHS condition.
1494 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1495 NewTrueWeight, NewFalseWeight);
1497 NewTrueWeight = 2 * (uint64_t)TWeight;
1498 NewFalseWeight = FWeight;
1499 ScaleWeights(NewTrueWeight, NewFalseWeight);
1500 // Emit the RHS condition into TmpBB.
1501 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1502 NewTrueWeight, NewFalseWeight);
1506 /// If the set of cases should be emitted as a series of branches, return true.
1507 /// If we should emit this as a bunch of and/or'd together conditions, return
1510 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1511 if (Cases.size() != 2) return true;
1513 // If this is two comparisons of the same values or'd or and'd together, they
1514 // will get folded into a single comparison, so don't emit two blocks.
1515 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1516 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1517 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1518 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1522 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1523 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1524 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1525 Cases[0].CC == Cases[1].CC &&
1526 isa<Constant>(Cases[0].CmpRHS) &&
1527 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1528 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1530 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1537 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1538 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1540 // Update machine-CFG edges.
1541 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1543 if (I.isUnconditional()) {
1544 // Update machine-CFG edges.
1545 BrMBB->addSuccessor(Succ0MBB);
1547 // If this is not a fall-through branch or optimizations are switched off,
1549 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1550 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1551 MVT::Other, getControlRoot(),
1552 DAG.getBasicBlock(Succ0MBB)));
1557 // If this condition is one of the special cases we handle, do special stuff
1559 const Value *CondVal = I.getCondition();
1560 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1562 // If this is a series of conditions that are or'd or and'd together, emit
1563 // this as a sequence of branches instead of setcc's with and/or operations.
1564 // As long as jumps are not expensive, this should improve performance.
1565 // For example, instead of something like:
1578 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1579 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1580 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1581 BOp->getOpcode() == Instruction::Or)) {
1582 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1583 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1584 getEdgeWeight(BrMBB, Succ1MBB));
1585 // If the compares in later blocks need to use values not currently
1586 // exported from this block, export them now. This block should always
1587 // be the first entry.
1588 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1590 // Allow some cases to be rejected.
1591 if (ShouldEmitAsBranches(SwitchCases)) {
1592 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1593 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1594 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1597 // Emit the branch for this block.
1598 visitSwitchCase(SwitchCases[0], BrMBB);
1599 SwitchCases.erase(SwitchCases.begin());
1603 // Okay, we decided not to do this, remove any inserted MBB's and clear
1605 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1606 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1608 SwitchCases.clear();
1612 // Create a CaseBlock record representing this branch.
1613 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1614 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1616 // Use visitSwitchCase to actually insert the fast branch sequence for this
1618 visitSwitchCase(CB, BrMBB);
1621 /// visitSwitchCase - Emits the necessary code to represent a single node in
1622 /// the binary search tree resulting from lowering a switch instruction.
1623 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1624 MachineBasicBlock *SwitchBB) {
1626 SDValue CondLHS = getValue(CB.CmpLHS);
1627 SDLoc dl = getCurSDLoc();
1629 // Build the setcc now.
1631 // Fold "(X == true)" to X and "(X == false)" to !X to
1632 // handle common cases produced by branch lowering.
1633 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1634 CB.CC == ISD::SETEQ)
1636 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1637 CB.CC == ISD::SETEQ) {
1638 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1639 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1641 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1643 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1645 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1646 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1648 SDValue CmpOp = getValue(CB.CmpMHS);
1649 EVT VT = CmpOp.getValueType();
1651 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1652 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1655 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1656 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1657 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1658 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1662 // Update successor info
1663 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1664 // TrueBB and FalseBB are always different unless the incoming IR is
1665 // degenerate. This only happens when running llc on weird IR.
1666 if (CB.TrueBB != CB.FalseBB)
1667 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1669 // If the lhs block is the next block, invert the condition so that we can
1670 // fall through to the lhs instead of the rhs block.
1671 if (CB.TrueBB == NextBlock(SwitchBB)) {
1672 std::swap(CB.TrueBB, CB.FalseBB);
1673 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1674 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1677 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1678 MVT::Other, getControlRoot(), Cond,
1679 DAG.getBasicBlock(CB.TrueBB));
1681 // Insert the false branch. Do this even if it's a fall through branch,
1682 // this makes it easier to do DAG optimizations which require inverting
1683 // the branch condition.
1684 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1685 DAG.getBasicBlock(CB.FalseBB));
1687 DAG.setRoot(BrCond);
1690 /// visitJumpTable - Emit JumpTable node in the current MBB
1691 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1692 // Emit the code for the jump table
1693 assert(JT.Reg != -1U && "Should lower JT Header first!");
1694 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1695 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1697 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1698 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1699 MVT::Other, Index.getValue(1),
1701 DAG.setRoot(BrJumpTable);
1704 /// visitJumpTableHeader - This function emits necessary code to produce index
1705 /// in the JumpTable from switch case.
1706 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1707 JumpTableHeader &JTH,
1708 MachineBasicBlock *SwitchBB) {
1709 SDLoc dl = getCurSDLoc();
1711 // Subtract the lowest switch case value from the value being switched on and
1712 // conditional branch to default mbb if the result is greater than the
1713 // difference between smallest and largest cases.
1714 SDValue SwitchOp = getValue(JTH.SValue);
1715 EVT VT = SwitchOp.getValueType();
1716 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1717 DAG.getConstant(JTH.First, dl, VT));
1719 // The SDNode we just created, which holds the value being switched on minus
1720 // the smallest case value, needs to be copied to a virtual register so it
1721 // can be used as an index into the jump table in a subsequent basic block.
1722 // This value may be smaller or larger than the target's pointer type, and
1723 // therefore require extension or truncating.
1724 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1725 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy());
1727 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1728 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1729 JumpTableReg, SwitchOp);
1730 JT.Reg = JumpTableReg;
1732 // Emit the range check for the jump table, and branch to the default block
1733 // for the switch statement if the value being switched on exceeds the largest
1734 // case in the switch.
1736 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1737 Sub.getValueType()),
1738 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT),
1741 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1742 MVT::Other, CopyTo, CMP,
1743 DAG.getBasicBlock(JT.Default));
1745 // Avoid emitting unnecessary branches to the next block.
1746 if (JT.MBB != NextBlock(SwitchBB))
1747 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1748 DAG.getBasicBlock(JT.MBB));
1750 DAG.setRoot(BrCond);
1753 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1754 /// tail spliced into a stack protector check success bb.
1756 /// For a high level explanation of how this fits into the stack protector
1757 /// generation see the comment on the declaration of class
1758 /// StackProtectorDescriptor.
1759 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1760 MachineBasicBlock *ParentBB) {
1762 // First create the loads to the guard/stack slot for the comparison.
1763 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1764 EVT PtrTy = TLI.getPointerTy();
1766 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1767 int FI = MFI->getStackProtectorIndex();
1769 const Value *IRGuard = SPD.getGuard();
1770 SDValue GuardPtr = getValue(IRGuard);
1771 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1774 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1777 SDLoc dl = getCurSDLoc();
1779 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1780 // guard value from the virtual register holding the value. Otherwise, emit a
1781 // volatile load to retrieve the stack guard value.
1782 unsigned GuardReg = SPD.getGuardReg();
1784 if (GuardReg && TLI.useLoadStackGuardNode())
1785 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1788 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1789 GuardPtr, MachinePointerInfo(IRGuard, 0),
1790 true, false, false, Align);
1792 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1794 MachinePointerInfo::getFixedStack(FI),
1795 true, false, false, Align);
1797 // Perform the comparison via a subtract/getsetcc.
1798 EVT VT = Guard.getValueType();
1799 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1802 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1803 Sub.getValueType()),
1804 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1806 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1807 // branch to failure MBB.
1808 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1809 MVT::Other, StackSlot.getOperand(0),
1810 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1811 // Otherwise branch to success MBB.
1812 SDValue Br = DAG.getNode(ISD::BR, dl,
1814 DAG.getBasicBlock(SPD.getSuccessMBB()));
1819 /// Codegen the failure basic block for a stack protector check.
1821 /// A failure stack protector machine basic block consists simply of a call to
1822 /// __stack_chk_fail().
1824 /// For a high level explanation of how this fits into the stack protector
1825 /// generation see the comment on the declaration of class
1826 /// StackProtectorDescriptor.
1828 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1831 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1832 nullptr, 0, false, getCurSDLoc(), false, false).second;
1836 /// visitBitTestHeader - This function emits necessary code to produce value
1837 /// suitable for "bit tests"
1838 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1839 MachineBasicBlock *SwitchBB) {
1840 SDLoc dl = getCurSDLoc();
1842 // Subtract the minimum value
1843 SDValue SwitchOp = getValue(B.SValue);
1844 EVT VT = SwitchOp.getValueType();
1845 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1846 DAG.getConstant(B.First, dl, VT));
1849 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1851 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1852 Sub.getValueType()),
1853 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1855 // Determine the type of the test operands.
1856 bool UsePtrType = false;
1857 if (!TLI.isTypeLegal(VT))
1860 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1861 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1862 // Switch table case range are encoded into series of masks.
1863 // Just use pointer type, it's guaranteed to fit.
1869 VT = TLI.getPointerTy();
1870 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1873 B.RegVT = VT.getSimpleVT();
1874 B.Reg = FuncInfo.CreateReg(B.RegVT);
1875 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1877 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1879 addSuccessorWithWeight(SwitchBB, B.Default);
1880 addSuccessorWithWeight(SwitchBB, MBB);
1882 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1883 MVT::Other, CopyTo, RangeCmp,
1884 DAG.getBasicBlock(B.Default));
1886 // Avoid emitting unnecessary branches to the next block.
1887 if (MBB != NextBlock(SwitchBB))
1888 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1889 DAG.getBasicBlock(MBB));
1891 DAG.setRoot(BrRange);
1894 /// visitBitTestCase - this function produces one "bit test"
1895 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1896 MachineBasicBlock* NextMBB,
1897 uint32_t BranchWeightToNext,
1900 MachineBasicBlock *SwitchBB) {
1901 SDLoc dl = getCurSDLoc();
1903 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1905 unsigned PopCount = countPopulation(B.Mask);
1906 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1907 if (PopCount == 1) {
1908 // Testing for a single bit; just compare the shift count with what it
1909 // would need to be to shift a 1 bit in that position.
1911 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1912 DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), ISD::SETEQ);
1913 } else if (PopCount == BB.Range) {
1914 // There is only one zero bit in the range, test for it directly.
1916 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1917 DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), ISD::SETNE);
1919 // Make desired shift
1920 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1921 DAG.getConstant(1, dl, VT), ShiftOp);
1923 // Emit bit tests and jumps
1924 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1925 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1926 Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1927 DAG.getConstant(0, dl, VT), ISD::SETNE);
1930 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1931 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1932 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1933 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1935 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1936 MVT::Other, getControlRoot(),
1937 Cmp, DAG.getBasicBlock(B.TargetBB));
1939 // Avoid emitting unnecessary branches to the next block.
1940 if (NextMBB != NextBlock(SwitchBB))
1941 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1942 DAG.getBasicBlock(NextMBB));
1947 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1948 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1950 // Retrieve successors.
1951 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1952 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1954 const Value *Callee(I.getCalledValue());
1955 const Function *Fn = dyn_cast<Function>(Callee);
1956 if (isa<InlineAsm>(Callee))
1958 else if (Fn && Fn->isIntrinsic()) {
1959 switch (Fn->getIntrinsicID()) {
1961 llvm_unreachable("Cannot invoke this intrinsic");
1962 case Intrinsic::donothing:
1963 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1965 case Intrinsic::experimental_patchpoint_void:
1966 case Intrinsic::experimental_patchpoint_i64:
1967 visitPatchpoint(&I, LandingPad);
1969 case Intrinsic::experimental_gc_statepoint:
1970 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1974 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1976 // If the value of the invoke is used outside of its defining block, make it
1977 // available as a virtual register.
1978 // We already took care of the exported value for the statepoint instruction
1979 // during call to the LowerStatepoint.
1980 if (!isStatepoint(I)) {
1981 CopyToExportRegsIfNeeded(&I);
1984 // Update successor info
1985 addSuccessorWithWeight(InvokeMBB, Return);
1986 addSuccessorWithWeight(InvokeMBB, LandingPad);
1988 // Drop into normal successor.
1989 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1990 MVT::Other, getControlRoot(),
1991 DAG.getBasicBlock(Return)));
1994 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1995 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1998 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1999 assert(FuncInfo.MBB->isLandingPad() &&
2000 "Call to landingpad not in landing pad!");
2002 MachineBasicBlock *MBB = FuncInfo.MBB;
2003 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2004 AddLandingPadInfo(LP, MMI, MBB);
2006 // If there aren't registers to copy the values into (e.g., during SjLj
2007 // exceptions), then don't bother to create these DAG nodes.
2008 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2009 if (TLI.getExceptionPointerRegister() == 0 &&
2010 TLI.getExceptionSelectorRegister() == 0)
2013 SmallVector<EVT, 2> ValueVTs;
2014 SDLoc dl = getCurSDLoc();
2015 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2016 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2018 // Get the two live-in registers as SDValues. The physregs have already been
2019 // copied into virtual registers.
2021 if (FuncInfo.ExceptionPointerVirtReg) {
2022 Ops[0] = DAG.getZExtOrTrunc(
2023 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2024 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2027 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy());
2029 Ops[1] = DAG.getZExtOrTrunc(
2030 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2031 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2035 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2036 DAG.getVTList(ValueVTs), Ops);
2041 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2042 MachineBasicBlock *LPadBB) {
2043 SDValue Chain = getControlRoot();
2044 SDLoc dl = getCurSDLoc();
2046 // Get the typeid that we will dispatch on later.
2047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2048 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2049 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2050 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2051 SDValue Sel = DAG.getConstant(TypeID, dl, TLI.getPointerTy());
2052 Chain = DAG.getCopyToReg(Chain, dl, VReg, Sel);
2054 // Branch to the main landing pad block.
2055 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2056 ClauseMBB->addSuccessor(LPadBB);
2057 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, Chain,
2058 DAG.getBasicBlock(LPadBB)));
2062 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2064 for (const CaseCluster &CC : Clusters)
2065 assert(CC.Low == CC.High && "Input clusters must be single-case");
2068 std::sort(Clusters.begin(), Clusters.end(),
2069 [](const CaseCluster &a, const CaseCluster &b) {
2070 return a.Low->getValue().slt(b.Low->getValue());
2073 // Merge adjacent clusters with the same destination.
2074 const unsigned N = Clusters.size();
2075 unsigned DstIndex = 0;
2076 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2077 CaseCluster &CC = Clusters[SrcIndex];
2078 const ConstantInt *CaseVal = CC.Low;
2079 MachineBasicBlock *Succ = CC.MBB;
2081 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2082 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2083 // If this case has the same successor and is a neighbour, merge it into
2084 // the previous cluster.
2085 Clusters[DstIndex - 1].High = CaseVal;
2086 Clusters[DstIndex - 1].Weight += CC.Weight;
2087 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2089 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2090 sizeof(Clusters[SrcIndex]));
2093 Clusters.resize(DstIndex);
2096 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2097 MachineBasicBlock *Last) {
2099 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2100 if (JTCases[i].first.HeaderBB == First)
2101 JTCases[i].first.HeaderBB = Last;
2103 // Update BitTestCases.
2104 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2105 if (BitTestCases[i].Parent == First)
2106 BitTestCases[i].Parent = Last;
2109 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2110 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2112 // Update machine-CFG edges with unique successors.
2113 SmallSet<BasicBlock*, 32> Done;
2114 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2115 BasicBlock *BB = I.getSuccessor(i);
2116 bool Inserted = Done.insert(BB).second;
2120 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2121 addSuccessorWithWeight(IndirectBrMBB, Succ);
2124 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2125 MVT::Other, getControlRoot(),
2126 getValue(I.getAddress())));
2129 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2130 if (DAG.getTarget().Options.TrapUnreachable)
2131 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2134 void SelectionDAGBuilder::visitFSub(const User &I) {
2135 // -0.0 - X --> fneg
2136 Type *Ty = I.getType();
2137 if (isa<Constant>(I.getOperand(0)) &&
2138 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2139 SDValue Op2 = getValue(I.getOperand(1));
2140 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2141 Op2.getValueType(), Op2));
2145 visitBinary(I, ISD::FSUB);
2148 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2149 SDValue Op1 = getValue(I.getOperand(0));
2150 SDValue Op2 = getValue(I.getOperand(1));
2157 if (const OverflowingBinaryOperator *OFBinOp =
2158 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2159 nuw = OFBinOp->hasNoUnsignedWrap();
2160 nsw = OFBinOp->hasNoSignedWrap();
2162 if (const PossiblyExactOperator *ExactOp =
2163 dyn_cast<const PossiblyExactOperator>(&I))
2164 exact = ExactOp->isExact();
2165 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2166 FMF = FPOp->getFastMathFlags();
2169 Flags.setExact(exact);
2170 Flags.setNoSignedWrap(nsw);
2171 Flags.setNoUnsignedWrap(nuw);
2172 if (EnableFMFInDAG) {
2173 Flags.setAllowReciprocal(FMF.allowReciprocal());
2174 Flags.setNoInfs(FMF.noInfs());
2175 Flags.setNoNaNs(FMF.noNaNs());
2176 Flags.setNoSignedZeros(FMF.noSignedZeros());
2177 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2179 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2181 setValue(&I, BinNodeValue);
2184 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2185 SDValue Op1 = getValue(I.getOperand(0));
2186 SDValue Op2 = getValue(I.getOperand(1));
2189 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2191 // Coerce the shift amount to the right type if we can.
2192 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2193 unsigned ShiftSize = ShiftTy.getSizeInBits();
2194 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2195 SDLoc DL = getCurSDLoc();
2197 // If the operand is smaller than the shift count type, promote it.
2198 if (ShiftSize > Op2Size)
2199 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2201 // If the operand is larger than the shift count type but the shift
2202 // count type has enough bits to represent any shift value, truncate
2203 // it now. This is a common case and it exposes the truncate to
2204 // optimization early.
2205 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2206 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2207 // Otherwise we'll need to temporarily settle for some other convenient
2208 // type. Type legalization will make adjustments once the shiftee is split.
2210 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2217 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2219 if (const OverflowingBinaryOperator *OFBinOp =
2220 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2221 nuw = OFBinOp->hasNoUnsignedWrap();
2222 nsw = OFBinOp->hasNoSignedWrap();
2224 if (const PossiblyExactOperator *ExactOp =
2225 dyn_cast<const PossiblyExactOperator>(&I))
2226 exact = ExactOp->isExact();
2229 Flags.setExact(exact);
2230 Flags.setNoSignedWrap(nsw);
2231 Flags.setNoUnsignedWrap(nuw);
2232 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2237 void SelectionDAGBuilder::visitSDiv(const User &I) {
2238 SDValue Op1 = getValue(I.getOperand(0));
2239 SDValue Op2 = getValue(I.getOperand(1));
2241 // Turn exact SDivs into multiplications.
2242 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2244 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2245 !isa<ConstantSDNode>(Op1) &&
2246 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2247 setValue(&I, DAG.getTargetLoweringInfo()
2248 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2250 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2254 void SelectionDAGBuilder::visitICmp(const User &I) {
2255 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2256 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2257 predicate = IC->getPredicate();
2258 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2259 predicate = ICmpInst::Predicate(IC->getPredicate());
2260 SDValue Op1 = getValue(I.getOperand(0));
2261 SDValue Op2 = getValue(I.getOperand(1));
2262 ISD::CondCode Opcode = getICmpCondCode(predicate);
2264 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2265 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2268 void SelectionDAGBuilder::visitFCmp(const User &I) {
2269 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2270 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2271 predicate = FC->getPredicate();
2272 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2273 predicate = FCmpInst::Predicate(FC->getPredicate());
2274 SDValue Op1 = getValue(I.getOperand(0));
2275 SDValue Op2 = getValue(I.getOperand(1));
2276 ISD::CondCode Condition = getFCmpCondCode(predicate);
2277 if (TM.Options.NoNaNsFPMath)
2278 Condition = getFCmpCodeWithoutNaN(Condition);
2279 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2280 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2283 void SelectionDAGBuilder::visitSelect(const User &I) {
2284 SmallVector<EVT, 4> ValueVTs;
2285 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2286 unsigned NumValues = ValueVTs.size();
2287 if (NumValues == 0) return;
2289 SmallVector<SDValue, 4> Values(NumValues);
2290 SDValue Cond = getValue(I.getOperand(0));
2291 SDValue LHSVal = getValue(I.getOperand(1));
2292 SDValue RHSVal = getValue(I.getOperand(2));
2293 auto BaseOps = {Cond};
2294 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2295 ISD::VSELECT : ISD::SELECT;
2297 // Min/max matching is only viable if all output VTs are the same.
2298 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2300 SelectPatternFlavor SPF = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2301 ISD::NodeType Opc = ISD::DELETED_NODE;
2303 case SPF_UMAX: Opc = ISD::UMAX; break;
2304 case SPF_UMIN: Opc = ISD::UMIN; break;
2305 case SPF_SMAX: Opc = ISD::SMAX; break;
2306 case SPF_SMIN: Opc = ISD::SMIN; break;
2310 EVT VT = ValueVTs[0];
2311 LLVMContext &Ctx = *DAG.getContext();
2312 auto &TLI = DAG.getTargetLoweringInfo();
2313 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2314 VT = TLI.getTypeToTransformTo(Ctx, VT);
2316 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2317 // If the underlying comparison instruction is used by any other instruction,
2318 // the consumed instructions won't be destroyed, so it is not profitable
2319 // to convert to a min/max.
2320 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2322 LHSVal = getValue(LHS);
2323 RHSVal = getValue(RHS);
2328 for (unsigned i = 0; i != NumValues; ++i) {
2329 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2330 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2331 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2332 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2333 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2337 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2338 DAG.getVTList(ValueVTs), Values));
2341 void SelectionDAGBuilder::visitTrunc(const User &I) {
2342 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2343 SDValue N = getValue(I.getOperand(0));
2344 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2345 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2348 void SelectionDAGBuilder::visitZExt(const User &I) {
2349 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2350 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2351 SDValue N = getValue(I.getOperand(0));
2352 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2353 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2356 void SelectionDAGBuilder::visitSExt(const User &I) {
2357 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2358 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2359 SDValue N = getValue(I.getOperand(0));
2360 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2361 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2364 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2365 // FPTrunc is never a no-op cast, no need to check
2366 SDValue N = getValue(I.getOperand(0));
2367 SDLoc dl = getCurSDLoc();
2368 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2369 EVT DestVT = TLI.getValueType(I.getType());
2370 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2371 DAG.getTargetConstant(0, dl, TLI.getPointerTy())));
2374 void SelectionDAGBuilder::visitFPExt(const User &I) {
2375 // FPExt is never a no-op cast, no need to check
2376 SDValue N = getValue(I.getOperand(0));
2377 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2378 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2381 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2382 // FPToUI is never a no-op cast, no need to check
2383 SDValue N = getValue(I.getOperand(0));
2384 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2385 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2388 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2389 // FPToSI is never a no-op cast, no need to check
2390 SDValue N = getValue(I.getOperand(0));
2391 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2392 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2395 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2396 // UIToFP is never a no-op cast, no need to check
2397 SDValue N = getValue(I.getOperand(0));
2398 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2399 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2402 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2403 // SIToFP is never a no-op cast, no need to check
2404 SDValue N = getValue(I.getOperand(0));
2405 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2406 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2409 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2410 // What to do depends on the size of the integer and the size of the pointer.
2411 // We can either truncate, zero extend, or no-op, accordingly.
2412 SDValue N = getValue(I.getOperand(0));
2413 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2414 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2417 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2418 // What to do depends on the size of the integer and the size of the pointer.
2419 // We can either truncate, zero extend, or no-op, accordingly.
2420 SDValue N = getValue(I.getOperand(0));
2421 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2422 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2425 void SelectionDAGBuilder::visitBitCast(const User &I) {
2426 SDValue N = getValue(I.getOperand(0));
2427 SDLoc dl = getCurSDLoc();
2428 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2430 // BitCast assures us that source and destination are the same size so this is
2431 // either a BITCAST or a no-op.
2432 if (DestVT != N.getValueType())
2433 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2434 DestVT, N)); // convert types.
2435 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2436 // might fold any kind of constant expression to an integer constant and that
2437 // is not what we are looking for. Only regcognize a bitcast of a genuine
2438 // constant integer as an opaque constant.
2439 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2440 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2443 setValue(&I, N); // noop cast.
2446 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2448 const Value *SV = I.getOperand(0);
2449 SDValue N = getValue(SV);
2450 EVT DestVT = TLI.getValueType(I.getType());
2452 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2453 unsigned DestAS = I.getType()->getPointerAddressSpace();
2455 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2456 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2461 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2462 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2463 SDValue InVec = getValue(I.getOperand(0));
2464 SDValue InVal = getValue(I.getOperand(1));
2465 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2466 getCurSDLoc(), TLI.getVectorIdxTy());
2467 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2468 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
2471 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2472 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2473 SDValue InVec = getValue(I.getOperand(0));
2474 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2475 getCurSDLoc(), TLI.getVectorIdxTy());
2476 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2477 TLI.getValueType(I.getType()), InVec, InIdx));
2480 // Utility for visitShuffleVector - Return true if every element in Mask,
2481 // beginning from position Pos and ending in Pos+Size, falls within the
2482 // specified sequential range [L, L+Pos). or is undef.
2483 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2484 unsigned Pos, unsigned Size, int Low) {
2485 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2486 if (Mask[i] >= 0 && Mask[i] != Low)
2491 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2492 SDValue Src1 = getValue(I.getOperand(0));
2493 SDValue Src2 = getValue(I.getOperand(1));
2495 SmallVector<int, 8> Mask;
2496 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2497 unsigned MaskNumElts = Mask.size();
2499 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2500 EVT VT = TLI.getValueType(I.getType());
2501 EVT SrcVT = Src1.getValueType();
2502 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2504 if (SrcNumElts == MaskNumElts) {
2505 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2510 // Normalize the shuffle vector since mask and vector length don't match.
2511 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2512 // Mask is longer than the source vectors and is a multiple of the source
2513 // vectors. We can use concatenate vector to make the mask and vectors
2515 if (SrcNumElts*2 == MaskNumElts) {
2516 // First check for Src1 in low and Src2 in high
2517 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2518 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2519 // The shuffle is concatenating two vectors together.
2520 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2524 // Then check for Src2 in low and Src1 in high
2525 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2526 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2527 // The shuffle is concatenating two vectors together.
2528 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2534 // Pad both vectors with undefs to make them the same length as the mask.
2535 unsigned NumConcat = MaskNumElts / SrcNumElts;
2536 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2537 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2538 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2540 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2541 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2545 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2546 getCurSDLoc(), VT, MOps1);
2547 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2548 getCurSDLoc(), VT, MOps2);
2550 // Readjust mask for new input vector length.
2551 SmallVector<int, 8> MappedOps;
2552 for (unsigned i = 0; i != MaskNumElts; ++i) {
2554 if (Idx >= (int)SrcNumElts)
2555 Idx -= SrcNumElts - MaskNumElts;
2556 MappedOps.push_back(Idx);
2559 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2564 if (SrcNumElts > MaskNumElts) {
2565 // Analyze the access pattern of the vector to see if we can extract
2566 // two subvectors and do the shuffle. The analysis is done by calculating
2567 // the range of elements the mask access on both vectors.
2568 int MinRange[2] = { static_cast<int>(SrcNumElts),
2569 static_cast<int>(SrcNumElts)};
2570 int MaxRange[2] = {-1, -1};
2572 for (unsigned i = 0; i != MaskNumElts; ++i) {
2578 if (Idx >= (int)SrcNumElts) {
2582 if (Idx > MaxRange[Input])
2583 MaxRange[Input] = Idx;
2584 if (Idx < MinRange[Input])
2585 MinRange[Input] = Idx;
2588 // Check if the access is smaller than the vector size and can we find
2589 // a reasonable extract index.
2590 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2592 int StartIdx[2]; // StartIdx to extract from
2593 for (unsigned Input = 0; Input < 2; ++Input) {
2594 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2595 RangeUse[Input] = 0; // Unused
2596 StartIdx[Input] = 0;
2600 // Find a good start index that is a multiple of the mask length. Then
2601 // see if the rest of the elements are in range.
2602 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2603 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2604 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2605 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2608 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2609 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2612 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2613 // Extract appropriate subvector and generate a vector shuffle
2614 for (unsigned Input = 0; Input < 2; ++Input) {
2615 SDValue &Src = Input == 0 ? Src1 : Src2;
2616 if (RangeUse[Input] == 0)
2617 Src = DAG.getUNDEF(VT);
2619 SDLoc dl = getCurSDLoc();
2621 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2622 DAG.getConstant(StartIdx[Input], dl, TLI.getVectorIdxTy()));
2626 // Calculate new mask.
2627 SmallVector<int, 8> MappedOps;
2628 for (unsigned i = 0; i != MaskNumElts; ++i) {
2631 if (Idx < (int)SrcNumElts)
2634 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2636 MappedOps.push_back(Idx);
2639 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2645 // We can't use either concat vectors or extract subvectors so fall back to
2646 // replacing the shuffle with extract and build vector.
2647 // to insert and build vector.
2648 EVT EltVT = VT.getVectorElementType();
2649 EVT IdxVT = TLI.getVectorIdxTy();
2650 SDLoc dl = getCurSDLoc();
2651 SmallVector<SDValue,8> Ops;
2652 for (unsigned i = 0; i != MaskNumElts; ++i) {
2657 Res = DAG.getUNDEF(EltVT);
2659 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2660 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2662 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2663 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2669 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2672 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2673 const Value *Op0 = I.getOperand(0);
2674 const Value *Op1 = I.getOperand(1);
2675 Type *AggTy = I.getType();
2676 Type *ValTy = Op1->getType();
2677 bool IntoUndef = isa<UndefValue>(Op0);
2678 bool FromUndef = isa<UndefValue>(Op1);
2680 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2683 SmallVector<EVT, 4> AggValueVTs;
2684 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2685 SmallVector<EVT, 4> ValValueVTs;
2686 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2688 unsigned NumAggValues = AggValueVTs.size();
2689 unsigned NumValValues = ValValueVTs.size();
2690 SmallVector<SDValue, 4> Values(NumAggValues);
2692 // Ignore an insertvalue that produces an empty object
2693 if (!NumAggValues) {
2694 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2698 SDValue Agg = getValue(Op0);
2700 // Copy the beginning value(s) from the original aggregate.
2701 for (; i != LinearIndex; ++i)
2702 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2703 SDValue(Agg.getNode(), Agg.getResNo() + i);
2704 // Copy values from the inserted value(s).
2706 SDValue Val = getValue(Op1);
2707 for (; i != LinearIndex + NumValValues; ++i)
2708 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2709 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2711 // Copy remaining value(s) from the original aggregate.
2712 for (; i != NumAggValues; ++i)
2713 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2714 SDValue(Agg.getNode(), Agg.getResNo() + i);
2716 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2717 DAG.getVTList(AggValueVTs), Values));
2720 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2721 const Value *Op0 = I.getOperand(0);
2722 Type *AggTy = Op0->getType();
2723 Type *ValTy = I.getType();
2724 bool OutOfUndef = isa<UndefValue>(Op0);
2726 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2729 SmallVector<EVT, 4> ValValueVTs;
2730 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2732 unsigned NumValValues = ValValueVTs.size();
2734 // Ignore a extractvalue that produces an empty object
2735 if (!NumValValues) {
2736 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2740 SmallVector<SDValue, 4> Values(NumValValues);
2742 SDValue Agg = getValue(Op0);
2743 // Copy out the selected value(s).
2744 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2745 Values[i - LinearIndex] =
2747 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2748 SDValue(Agg.getNode(), Agg.getResNo() + i);
2750 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2751 DAG.getVTList(ValValueVTs), Values));
2754 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2755 Value *Op0 = I.getOperand(0);
2756 // Note that the pointer operand may be a vector of pointers. Take the scalar
2757 // element which holds a pointer.
2758 Type *Ty = Op0->getType()->getScalarType();
2759 unsigned AS = Ty->getPointerAddressSpace();
2760 SDValue N = getValue(Op0);
2761 SDLoc dl = getCurSDLoc();
2763 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2765 const Value *Idx = *OI;
2766 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2767 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2770 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2771 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2772 DAG.getConstant(Offset, dl, N.getValueType()));
2775 Ty = StTy->getElementType(Field);
2777 Ty = cast<SequentialType>(Ty)->getElementType();
2778 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
2779 unsigned PtrSize = PtrTy.getSizeInBits();
2780 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2782 // If this is a constant subscript, handle it quickly.
2783 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
2786 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2787 SDValue OffsVal = DAG.getConstant(Offs, dl, PtrTy);
2788 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2792 // N = N + Idx * ElementSize;
2793 SDValue IdxN = getValue(Idx);
2795 // If the index is smaller or larger than intptr_t, truncate or extend
2797 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2799 // If this is a multiply by a power of two, turn it into a shl
2800 // immediately. This is a very common case.
2801 if (ElementSize != 1) {
2802 if (ElementSize.isPowerOf2()) {
2803 unsigned Amt = ElementSize.logBase2();
2804 IdxN = DAG.getNode(ISD::SHL, dl,
2805 N.getValueType(), IdxN,
2806 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2808 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2809 IdxN = DAG.getNode(ISD::MUL, dl,
2810 N.getValueType(), IdxN, Scale);
2814 N = DAG.getNode(ISD::ADD, dl,
2815 N.getValueType(), N, IdxN);
2822 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2823 // If this is a fixed sized alloca in the entry block of the function,
2824 // allocate it statically on the stack.
2825 if (FuncInfo.StaticAllocaMap.count(&I))
2826 return; // getValue will auto-populate this.
2828 SDLoc dl = getCurSDLoc();
2829 Type *Ty = I.getAllocatedType();
2830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2831 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
2833 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
2836 SDValue AllocSize = getValue(I.getArraySize());
2838 EVT IntPtr = TLI.getPointerTy();
2839 if (AllocSize.getValueType() != IntPtr)
2840 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2842 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2844 DAG.getConstant(TySize, dl, IntPtr));
2846 // Handle alignment. If the requested alignment is less than or equal to
2847 // the stack alignment, ignore it. If the size is greater than or equal to
2848 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2849 unsigned StackAlign =
2850 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2851 if (Align <= StackAlign)
2854 // Round the size of the allocation up to the stack alignment size
2855 // by add SA-1 to the size.
2856 AllocSize = DAG.getNode(ISD::ADD, dl,
2857 AllocSize.getValueType(), AllocSize,
2858 DAG.getIntPtrConstant(StackAlign - 1, dl));
2860 // Mask out the low bits for alignment purposes.
2861 AllocSize = DAG.getNode(ISD::AND, dl,
2862 AllocSize.getValueType(), AllocSize,
2863 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2866 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2867 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2868 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2870 DAG.setRoot(DSA.getValue(1));
2872 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2875 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2877 return visitAtomicLoad(I);
2879 const Value *SV = I.getOperand(0);
2880 SDValue Ptr = getValue(SV);
2882 Type *Ty = I.getType();
2884 bool isVolatile = I.isVolatile();
2885 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2887 // The IR notion of invariant_load only guarantees that all *non-faulting*
2888 // invariant loads result in the same value. The MI notion of invariant load
2889 // guarantees that the load can be legally moved to any location within its
2890 // containing function. The MI notion of invariant_load is stronger than the
2891 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2892 // with a guarantee that the location being loaded from is dereferenceable
2893 // throughout the function's lifetime.
2895 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2896 isDereferenceablePointer(SV, *DAG.getTarget().getDataLayout());
2897 unsigned Alignment = I.getAlignment();
2900 I.getAAMetadata(AAInfo);
2901 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2904 SmallVector<EVT, 4> ValueVTs;
2905 SmallVector<uint64_t, 4> Offsets;
2906 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2907 unsigned NumValues = ValueVTs.size();
2912 bool ConstantMemory = false;
2913 if (isVolatile || NumValues > MaxParallelChains)
2914 // Serialize volatile loads with other side effects.
2916 else if (AA->pointsToConstantMemory(
2917 MemoryLocation(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2918 // Do not serialize (non-volatile) loads of constant memory with anything.
2919 Root = DAG.getEntryNode();
2920 ConstantMemory = true;
2922 // Do not serialize non-volatile loads against each other.
2923 Root = DAG.getRoot();
2926 SDLoc dl = getCurSDLoc();
2929 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2931 SmallVector<SDValue, 4> Values(NumValues);
2932 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
2933 EVT PtrVT = Ptr.getValueType();
2934 unsigned ChainI = 0;
2935 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2936 // Serializing loads here may result in excessive register pressure, and
2937 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2938 // could recover a bit by hoisting nodes upward in the chain by recognizing
2939 // they are side-effect free or do not alias. The optimizer should really
2940 // avoid this case by converting large object/array copies to llvm.memcpy
2941 // (MaxParallelChains should always remain as failsafe).
2942 if (ChainI == MaxParallelChains) {
2943 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2944 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2945 makeArrayRef(Chains.data(), ChainI));
2949 SDValue A = DAG.getNode(ISD::ADD, dl,
2951 DAG.getConstant(Offsets[i], dl, PtrVT));
2952 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2953 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2954 isNonTemporal, isInvariant, Alignment, AAInfo,
2958 Chains[ChainI] = L.getValue(1);
2961 if (!ConstantMemory) {
2962 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2963 makeArrayRef(Chains.data(), ChainI));
2967 PendingLoads.push_back(Chain);
2970 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
2971 DAG.getVTList(ValueVTs), Values));
2974 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2976 return visitAtomicStore(I);
2978 const Value *SrcV = I.getOperand(0);
2979 const Value *PtrV = I.getOperand(1);
2981 SmallVector<EVT, 4> ValueVTs;
2982 SmallVector<uint64_t, 4> Offsets;
2983 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
2984 ValueVTs, &Offsets);
2985 unsigned NumValues = ValueVTs.size();
2989 // Get the lowered operands. Note that we do this after
2990 // checking if NumResults is zero, because with zero results
2991 // the operands won't have values in the map.
2992 SDValue Src = getValue(SrcV);
2993 SDValue Ptr = getValue(PtrV);
2995 SDValue Root = getRoot();
2996 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
2997 EVT PtrVT = Ptr.getValueType();
2998 bool isVolatile = I.isVolatile();
2999 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3000 unsigned Alignment = I.getAlignment();
3001 SDLoc dl = getCurSDLoc();
3004 I.getAAMetadata(AAInfo);
3006 unsigned ChainI = 0;
3007 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3008 // See visitLoad comments.
3009 if (ChainI == MaxParallelChains) {
3010 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3011 makeArrayRef(Chains.data(), ChainI));
3015 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3016 DAG.getConstant(Offsets[i], dl, PtrVT));
3017 SDValue St = DAG.getStore(Root, dl,
3018 SDValue(Src.getNode(), Src.getResNo() + i),
3019 Add, MachinePointerInfo(PtrV, Offsets[i]),
3020 isVolatile, isNonTemporal, Alignment, AAInfo);
3021 Chains[ChainI] = St;
3024 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3025 makeArrayRef(Chains.data(), ChainI));
3026 DAG.setRoot(StoreNode);
3029 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3030 SDLoc sdl = getCurSDLoc();
3032 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3033 Value *PtrOperand = I.getArgOperand(1);
3034 SDValue Ptr = getValue(PtrOperand);
3035 SDValue Src0 = getValue(I.getArgOperand(0));
3036 SDValue Mask = getValue(I.getArgOperand(3));
3037 EVT VT = Src0.getValueType();
3038 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3040 Alignment = DAG.getEVTAlignment(VT);
3043 I.getAAMetadata(AAInfo);
3045 MachineMemOperand *MMO =
3046 DAG.getMachineFunction().
3047 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3048 MachineMemOperand::MOStore, VT.getStoreSize(),
3050 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3052 DAG.setRoot(StoreNode);
3053 setValue(&I, StoreNode);
3056 // Gather/scatter receive a vector of pointers.
3057 // This vector of pointers may be represented as a base pointer + vector of
3058 // indices, it depends on GEP and instruction preceeding GEP
3059 // that calculates indices
3060 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3061 SelectionDAGBuilder* SDB) {
3063 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3064 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3065 if (!Gep || Gep->getNumOperands() > 2)
3067 ShuffleVectorInst *ShuffleInst =
3068 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3069 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3070 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3071 Instruction::InsertElement)
3074 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3076 SelectionDAG& DAG = SDB->DAG;
3077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3078 // Check is the Ptr is inside current basic block
3079 // If not, look for the shuffle instruction
3080 if (SDB->findValue(Ptr))
3081 Base = SDB->getValue(Ptr);
3082 else if (SDB->findValue(ShuffleInst)) {
3083 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3084 SDLoc sdl = ShuffleNode;
3085 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
3086 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3087 DAG.getConstant(0, sdl, TLI.getVectorIdxTy()));
3088 SDB->setValue(Ptr, Base);
3093 Value *IndexVal = Gep->getOperand(1);
3094 if (SDB->findValue(IndexVal)) {
3095 Index = SDB->getValue(IndexVal);
3097 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3098 IndexVal = Sext->getOperand(0);
3099 if (SDB->findValue(IndexVal))
3100 Index = SDB->getValue(IndexVal);
3107 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3108 SDLoc sdl = getCurSDLoc();
3110 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3111 Value *Ptr = I.getArgOperand(1);
3112 SDValue Src0 = getValue(I.getArgOperand(0));
3113 SDValue Mask = getValue(I.getArgOperand(3));
3114 EVT VT = Src0.getValueType();
3115 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3117 Alignment = DAG.getEVTAlignment(VT);
3118 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3121 I.getAAMetadata(AAInfo);
3125 Value *BasePtr = Ptr;
3126 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3128 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3129 MachineMemOperand *MMO = DAG.getMachineFunction().
3130 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3131 MachineMemOperand::MOStore, VT.getStoreSize(),
3134 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3135 Index = getValue(Ptr);
3137 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3138 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3140 DAG.setRoot(Scatter);
3141 setValue(&I, Scatter);
3144 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3145 SDLoc sdl = getCurSDLoc();
3147 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3148 Value *PtrOperand = I.getArgOperand(0);
3149 SDValue Ptr = getValue(PtrOperand);
3150 SDValue Src0 = getValue(I.getArgOperand(3));
3151 SDValue Mask = getValue(I.getArgOperand(2));
3153 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3154 EVT VT = TLI.getValueType(I.getType());
3155 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3157 Alignment = DAG.getEVTAlignment(VT);
3160 I.getAAMetadata(AAInfo);
3161 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3163 SDValue InChain = DAG.getRoot();
3164 if (AA->pointsToConstantMemory(MemoryLocation(
3165 PtrOperand, AA->getTypeStoreSize(I.getType()), AAInfo))) {
3166 // Do not serialize (non-volatile) loads of constant memory with anything.
3167 InChain = DAG.getEntryNode();
3170 MachineMemOperand *MMO =
3171 DAG.getMachineFunction().
3172 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3173 MachineMemOperand::MOLoad, VT.getStoreSize(),
3174 Alignment, AAInfo, Ranges);
3176 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3178 SDValue OutChain = Load.getValue(1);
3179 DAG.setRoot(OutChain);
3183 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3184 SDLoc sdl = getCurSDLoc();
3186 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3187 Value *Ptr = I.getArgOperand(0);
3188 SDValue Src0 = getValue(I.getArgOperand(3));
3189 SDValue Mask = getValue(I.getArgOperand(2));
3191 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3192 EVT VT = TLI.getValueType(I.getType());
3193 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3195 Alignment = DAG.getEVTAlignment(VT);
3198 I.getAAMetadata(AAInfo);
3199 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3201 SDValue Root = DAG.getRoot();
3204 Value *BasePtr = Ptr;
3205 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3206 bool ConstantMemory = false;
3208 AA->pointsToConstantMemory(
3209 MemoryLocation(BasePtr, AA->getTypeStoreSize(I.getType()), AAInfo))) {
3210 // Do not serialize (non-volatile) loads of constant memory with anything.
3211 Root = DAG.getEntryNode();
3212 ConstantMemory = true;
3215 MachineMemOperand *MMO =
3216 DAG.getMachineFunction().
3217 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3218 MachineMemOperand::MOLoad, VT.getStoreSize(),
3219 Alignment, AAInfo, Ranges);
3222 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3223 Index = getValue(Ptr);
3225 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3226 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3229 SDValue OutChain = Gather.getValue(1);
3230 if (!ConstantMemory)
3231 PendingLoads.push_back(OutChain);
3232 setValue(&I, Gather);
3235 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3236 SDLoc dl = getCurSDLoc();
3237 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3238 AtomicOrdering FailureOrder = I.getFailureOrdering();
3239 SynchronizationScope Scope = I.getSynchScope();
3241 SDValue InChain = getRoot();
3243 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3244 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3245 SDValue L = DAG.getAtomicCmpSwap(
3246 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3247 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3248 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3249 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3251 SDValue OutChain = L.getValue(2);
3254 DAG.setRoot(OutChain);
3257 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3258 SDLoc dl = getCurSDLoc();
3260 switch (I.getOperation()) {
3261 default: llvm_unreachable("Unknown atomicrmw operation");
3262 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3263 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3264 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3265 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3266 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3267 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3268 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3269 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3270 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3271 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3272 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3274 AtomicOrdering Order = I.getOrdering();
3275 SynchronizationScope Scope = I.getSynchScope();
3277 SDValue InChain = getRoot();
3280 DAG.getAtomic(NT, dl,
3281 getValue(I.getValOperand()).getSimpleValueType(),
3283 getValue(I.getPointerOperand()),
3284 getValue(I.getValOperand()),
3285 I.getPointerOperand(),
3286 /* Alignment=*/ 0, Order, Scope);
3288 SDValue OutChain = L.getValue(1);
3291 DAG.setRoot(OutChain);
3294 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3295 SDLoc dl = getCurSDLoc();
3296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3299 Ops[1] = DAG.getConstant(I.getOrdering(), dl, TLI.getPointerTy());
3300 Ops[2] = DAG.getConstant(I.getSynchScope(), dl, TLI.getPointerTy());
3301 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3304 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3305 SDLoc dl = getCurSDLoc();
3306 AtomicOrdering Order = I.getOrdering();
3307 SynchronizationScope Scope = I.getSynchScope();
3309 SDValue InChain = getRoot();
3311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3312 EVT VT = TLI.getValueType(I.getType());
3314 if (I.getAlignment() < VT.getSizeInBits() / 8)
3315 report_fatal_error("Cannot generate unaligned atomic load");
3317 MachineMemOperand *MMO =
3318 DAG.getMachineFunction().
3319 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3320 MachineMemOperand::MOVolatile |
3321 MachineMemOperand::MOLoad,
3323 I.getAlignment() ? I.getAlignment() :
3324 DAG.getEVTAlignment(VT));
3326 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3328 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3329 getValue(I.getPointerOperand()), MMO,
3332 SDValue OutChain = L.getValue(1);
3335 DAG.setRoot(OutChain);
3338 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3339 SDLoc dl = getCurSDLoc();
3341 AtomicOrdering Order = I.getOrdering();
3342 SynchronizationScope Scope = I.getSynchScope();
3344 SDValue InChain = getRoot();
3346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3347 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3349 if (I.getAlignment() < VT.getSizeInBits() / 8)
3350 report_fatal_error("Cannot generate unaligned atomic store");
3353 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3355 getValue(I.getPointerOperand()),
3356 getValue(I.getValueOperand()),
3357 I.getPointerOperand(), I.getAlignment(),
3360 DAG.setRoot(OutChain);
3363 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3365 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3366 unsigned Intrinsic) {
3367 bool HasChain = !I.doesNotAccessMemory();
3368 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3370 // Build the operand list.
3371 SmallVector<SDValue, 8> Ops;
3372 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3374 // We don't need to serialize loads against other loads.
3375 Ops.push_back(DAG.getRoot());
3377 Ops.push_back(getRoot());
3381 // Info is set by getTgtMemInstrinsic
3382 TargetLowering::IntrinsicInfo Info;
3383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3384 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3386 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3387 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3388 Info.opc == ISD::INTRINSIC_W_CHAIN)
3389 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3390 TLI.getPointerTy()));
3392 // Add all operands of the call to the operand list.
3393 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3394 SDValue Op = getValue(I.getArgOperand(i));
3398 SmallVector<EVT, 4> ValueVTs;
3399 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3402 ValueVTs.push_back(MVT::Other);
3404 SDVTList VTs = DAG.getVTList(ValueVTs);
3408 if (IsTgtIntrinsic) {
3409 // This is target intrinsic that touches memory
3410 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3411 VTs, Ops, Info.memVT,
3412 MachinePointerInfo(Info.ptrVal, Info.offset),
3413 Info.align, Info.vol,
3414 Info.readMem, Info.writeMem, Info.size);
3415 } else if (!HasChain) {
3416 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3417 } else if (!I.getType()->isVoidTy()) {
3418 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3420 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3424 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3426 PendingLoads.push_back(Chain);
3431 if (!I.getType()->isVoidTy()) {
3432 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3433 EVT VT = TLI.getValueType(PTy);
3434 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3437 setValue(&I, Result);
3441 /// GetSignificand - Get the significand and build it into a floating-point
3442 /// number with exponent of 1:
3444 /// Op = (Op & 0x007fffff) | 0x3f800000;
3446 /// where Op is the hexadecimal representation of floating point value.
3448 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3449 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3450 DAG.getConstant(0x007fffff, dl, MVT::i32));
3451 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3452 DAG.getConstant(0x3f800000, dl, MVT::i32));
3453 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3456 /// GetExponent - Get the exponent:
3458 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3460 /// where Op is the hexadecimal representation of floating point value.
3462 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3464 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3465 DAG.getConstant(0x7f800000, dl, MVT::i32));
3466 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3467 DAG.getConstant(23, dl, TLI.getPointerTy()));
3468 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3469 DAG.getConstant(127, dl, MVT::i32));
3470 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3473 /// getF32Constant - Get 32-bit floating point constant.
3475 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3476 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3480 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3481 SelectionDAG &DAG) {
3482 // IntegerPartOfX = ((int32_t)(t0);
3483 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3485 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3486 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3487 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3489 // IntegerPartOfX <<= 23;
3490 IntegerPartOfX = DAG.getNode(
3491 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3492 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy()));
3494 SDValue TwoToFractionalPartOfX;
3495 if (LimitFloatPrecision <= 6) {
3496 // For floating-point precision of 6:
3498 // TwoToFractionalPartOfX =
3500 // (0.735607626f + 0.252464424f * x) * x;
3502 // error 0.0144103317, which is 6 bits
3503 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3504 getF32Constant(DAG, 0x3e814304, dl));
3505 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3506 getF32Constant(DAG, 0x3f3c50c8, dl));
3507 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3508 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3509 getF32Constant(DAG, 0x3f7f5e7e, dl));
3510 } else if (LimitFloatPrecision <= 12) {
3511 // For floating-point precision of 12:
3513 // TwoToFractionalPartOfX =
3516 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3518 // error 0.000107046256, which is 13 to 14 bits
3519 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3520 getF32Constant(DAG, 0x3da235e3, dl));
3521 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3522 getF32Constant(DAG, 0x3e65b8f3, dl));
3523 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3524 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3525 getF32Constant(DAG, 0x3f324b07, dl));
3526 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3527 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3528 getF32Constant(DAG, 0x3f7ff8fd, dl));
3529 } else { // LimitFloatPrecision <= 18
3530 // For floating-point precision of 18:
3532 // TwoToFractionalPartOfX =
3536 // (0.554906021e-1f +
3537 // (0.961591928e-2f +
3538 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3539 // error 2.47208000*10^(-7), which is better than 18 bits
3540 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3541 getF32Constant(DAG, 0x3924b03e, dl));
3542 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3543 getF32Constant(DAG, 0x3ab24b87, dl));
3544 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3545 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3546 getF32Constant(DAG, 0x3c1d8c17, dl));
3547 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3548 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3549 getF32Constant(DAG, 0x3d634a1d, dl));
3550 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3551 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3552 getF32Constant(DAG, 0x3e75fe14, dl));
3553 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3554 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3555 getF32Constant(DAG, 0x3f317234, dl));
3556 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3557 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3558 getF32Constant(DAG, 0x3f800000, dl));
3561 // Add the exponent into the result in integer domain.
3562 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3563 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3564 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3567 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3568 /// limited-precision mode.
3569 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3570 const TargetLowering &TLI) {
3571 if (Op.getValueType() == MVT::f32 &&
3572 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3574 // Put the exponent in the right bit position for later addition to the
3577 // #define LOG2OFe 1.4426950f
3578 // t0 = Op * LOG2OFe
3579 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3580 getF32Constant(DAG, 0x3fb8aa3b, dl));
3581 return getLimitedPrecisionExp2(t0, dl, DAG);
3584 // No special expansion.
3585 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3588 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3589 /// limited-precision mode.
3590 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3591 const TargetLowering &TLI) {
3592 if (Op.getValueType() == MVT::f32 &&
3593 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3594 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3596 // Scale the exponent by log(2) [0.69314718f].
3597 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3598 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3599 getF32Constant(DAG, 0x3f317218, dl));
3601 // Get the significand and build it into a floating-point number with
3603 SDValue X = GetSignificand(DAG, Op1, dl);
3605 SDValue LogOfMantissa;
3606 if (LimitFloatPrecision <= 6) {
3607 // For floating-point precision of 6:
3611 // (1.4034025f - 0.23903021f * x) * x;
3613 // error 0.0034276066, which is better than 8 bits
3614 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3615 getF32Constant(DAG, 0xbe74c456, dl));
3616 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3617 getF32Constant(DAG, 0x3fb3a2b1, dl));
3618 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3619 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3620 getF32Constant(DAG, 0x3f949a29, dl));
3621 } else if (LimitFloatPrecision <= 12) {
3622 // For floating-point precision of 12:
3628 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3630 // error 0.000061011436, which is 14 bits
3631 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3632 getF32Constant(DAG, 0xbd67b6d6, dl));
3633 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3634 getF32Constant(DAG, 0x3ee4f4b8, dl));
3635 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3636 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3637 getF32Constant(DAG, 0x3fbc278b, dl));
3638 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3639 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3640 getF32Constant(DAG, 0x40348e95, dl));
3641 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3642 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3643 getF32Constant(DAG, 0x3fdef31a, dl));
3644 } else { // LimitFloatPrecision <= 18
3645 // For floating-point precision of 18:
3653 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3655 // error 0.0000023660568, which is better than 18 bits
3656 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3657 getF32Constant(DAG, 0xbc91e5ac, dl));
3658 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3659 getF32Constant(DAG, 0x3e4350aa, dl));
3660 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3661 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3662 getF32Constant(DAG, 0x3f60d3e3, dl));
3663 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3664 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3665 getF32Constant(DAG, 0x4011cdf0, dl));
3666 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3667 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3668 getF32Constant(DAG, 0x406cfd1c, dl));
3669 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3670 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3671 getF32Constant(DAG, 0x408797cb, dl));
3672 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3673 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3674 getF32Constant(DAG, 0x4006dcab, dl));
3677 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3680 // No special expansion.
3681 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3684 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3685 /// limited-precision mode.
3686 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3687 const TargetLowering &TLI) {
3688 if (Op.getValueType() == MVT::f32 &&
3689 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3690 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3692 // Get the exponent.
3693 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3695 // Get the significand and build it into a floating-point number with
3697 SDValue X = GetSignificand(DAG, Op1, dl);
3699 // Different possible minimax approximations of significand in
3700 // floating-point for various degrees of accuracy over [1,2].
3701 SDValue Log2ofMantissa;
3702 if (LimitFloatPrecision <= 6) {
3703 // For floating-point precision of 6:
3705 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3707 // error 0.0049451742, which is more than 7 bits
3708 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3709 getF32Constant(DAG, 0xbeb08fe0, dl));
3710 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3711 getF32Constant(DAG, 0x40019463, dl));
3712 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3713 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3714 getF32Constant(DAG, 0x3fd6633d, dl));
3715 } else if (LimitFloatPrecision <= 12) {
3716 // For floating-point precision of 12:
3722 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3724 // error 0.0000876136000, which is better than 13 bits
3725 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3726 getF32Constant(DAG, 0xbda7262e, dl));
3727 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3728 getF32Constant(DAG, 0x3f25280b, dl));
3729 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3730 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3731 getF32Constant(DAG, 0x4007b923, dl));
3732 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3733 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3734 getF32Constant(DAG, 0x40823e2f, dl));
3735 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3736 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3737 getF32Constant(DAG, 0x4020d29c, dl));
3738 } else { // LimitFloatPrecision <= 18
3739 // For floating-point precision of 18:
3748 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3750 // error 0.0000018516, which is better than 18 bits
3751 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3752 getF32Constant(DAG, 0xbcd2769e, dl));
3753 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3754 getF32Constant(DAG, 0x3e8ce0b9, dl));
3755 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3756 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3757 getF32Constant(DAG, 0x3fa22ae7, dl));
3758 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3759 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3760 getF32Constant(DAG, 0x40525723, dl));
3761 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3762 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3763 getF32Constant(DAG, 0x40aaf200, dl));
3764 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3765 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3766 getF32Constant(DAG, 0x40c39dad, dl));
3767 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3768 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3769 getF32Constant(DAG, 0x4042902c, dl));
3772 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3775 // No special expansion.
3776 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3779 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3780 /// limited-precision mode.
3781 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3782 const TargetLowering &TLI) {
3783 if (Op.getValueType() == MVT::f32 &&
3784 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3785 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3787 // Scale the exponent by log10(2) [0.30102999f].
3788 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3789 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3790 getF32Constant(DAG, 0x3e9a209a, dl));
3792 // Get the significand and build it into a floating-point number with
3794 SDValue X = GetSignificand(DAG, Op1, dl);
3796 SDValue Log10ofMantissa;
3797 if (LimitFloatPrecision <= 6) {
3798 // For floating-point precision of 6:
3800 // Log10ofMantissa =
3802 // (0.60948995f - 0.10380950f * x) * x;
3804 // error 0.0014886165, which is 6 bits
3805 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3806 getF32Constant(DAG, 0xbdd49a13, dl));
3807 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3808 getF32Constant(DAG, 0x3f1c0789, dl));
3809 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3810 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3811 getF32Constant(DAG, 0x3f011300, dl));
3812 } else if (LimitFloatPrecision <= 12) {
3813 // For floating-point precision of 12:
3815 // Log10ofMantissa =
3818 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3820 // error 0.00019228036, which is better than 12 bits
3821 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3822 getF32Constant(DAG, 0x3d431f31, dl));
3823 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3824 getF32Constant(DAG, 0x3ea21fb2, dl));
3825 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3826 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3827 getF32Constant(DAG, 0x3f6ae232, dl));
3828 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3829 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3830 getF32Constant(DAG, 0x3f25f7c3, dl));
3831 } else { // LimitFloatPrecision <= 18
3832 // For floating-point precision of 18:
3834 // Log10ofMantissa =
3839 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3841 // error 0.0000037995730, which is better than 18 bits
3842 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3843 getF32Constant(DAG, 0x3c5d51ce, dl));
3844 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3845 getF32Constant(DAG, 0x3e00685a, dl));
3846 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3847 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3848 getF32Constant(DAG, 0x3efb6798, dl));
3849 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3850 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3851 getF32Constant(DAG, 0x3f88d192, dl));
3852 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3853 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3854 getF32Constant(DAG, 0x3fc4316c, dl));
3855 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3856 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3857 getF32Constant(DAG, 0x3f57ce70, dl));
3860 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3863 // No special expansion.
3864 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3867 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3868 /// limited-precision mode.
3869 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3870 const TargetLowering &TLI) {
3871 if (Op.getValueType() == MVT::f32 &&
3872 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3873 return getLimitedPrecisionExp2(Op, dl, DAG);
3875 // No special expansion.
3876 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3879 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3880 /// limited-precision mode with x == 10.0f.
3881 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3882 SelectionDAG &DAG, const TargetLowering &TLI) {
3883 bool IsExp10 = false;
3884 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3885 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3886 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3888 IsExp10 = LHSC->isExactlyValue(Ten);
3893 // Put the exponent in the right bit position for later addition to the
3896 // #define LOG2OF10 3.3219281f
3897 // t0 = Op * LOG2OF10;
3898 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3899 getF32Constant(DAG, 0x40549a78, dl));
3900 return getLimitedPrecisionExp2(t0, dl, DAG);
3903 // No special expansion.
3904 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3908 /// ExpandPowI - Expand a llvm.powi intrinsic.
3909 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3910 SelectionDAG &DAG) {
3911 // If RHS is a constant, we can expand this out to a multiplication tree,
3912 // otherwise we end up lowering to a call to __powidf2 (for example). When
3913 // optimizing for size, we only want to do this if the expansion would produce
3914 // a small number of multiplies, otherwise we do the full expansion.
3915 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3916 // Get the exponent as a positive value.
3917 unsigned Val = RHSC->getSExtValue();
3918 if ((int)Val < 0) Val = -Val;
3920 // powi(x, 0) -> 1.0
3922 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3924 const Function *F = DAG.getMachineFunction().getFunction();
3925 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3926 // If optimizing for size, don't insert too many multiplies. This
3927 // inserts up to 5 multiplies.
3928 countPopulation(Val) + Log2_32(Val) < 7) {
3929 // We use the simple binary decomposition method to generate the multiply
3930 // sequence. There are more optimal ways to do this (for example,
3931 // powi(x,15) generates one more multiply than it should), but this has
3932 // the benefit of being both really simple and much better than a libcall.
3933 SDValue Res; // Logically starts equal to 1.0
3934 SDValue CurSquare = LHS;
3938 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3940 Res = CurSquare; // 1.0*CurSquare.
3943 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3944 CurSquare, CurSquare);
3948 // If the original was negative, invert the result, producing 1/(x*x*x).
3949 if (RHSC->getSExtValue() < 0)
3950 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3951 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
3956 // Otherwise, expand to a libcall.
3957 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3960 // getTruncatedArgReg - Find underlying register used for an truncated
3962 static unsigned getTruncatedArgReg(const SDValue &N) {
3963 if (N.getOpcode() != ISD::TRUNCATE)
3966 const SDValue &Ext = N.getOperand(0);
3967 if (Ext.getOpcode() == ISD::AssertZext ||
3968 Ext.getOpcode() == ISD::AssertSext) {
3969 const SDValue &CFR = Ext.getOperand(0);
3970 if (CFR.getOpcode() == ISD::CopyFromReg)
3971 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3972 if (CFR.getOpcode() == ISD::TRUNCATE)
3973 return getTruncatedArgReg(CFR);
3978 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3979 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3980 /// At the end of instruction selection, they will be inserted to the entry BB.
3981 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
3982 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
3983 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
3984 const Argument *Arg = dyn_cast<Argument>(V);
3988 MachineFunction &MF = DAG.getMachineFunction();
3989 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
3991 // Ignore inlined function arguments here.
3993 // FIXME: Should we be checking DL->inlinedAt() to determine this?
3994 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
3997 Optional<MachineOperand> Op;
3998 // Some arguments' frame index is recorded during argument lowering.
3999 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4000 Op = MachineOperand::CreateFI(FI);
4002 if (!Op && N.getNode()) {
4004 if (N.getOpcode() == ISD::CopyFromReg)
4005 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4007 Reg = getTruncatedArgReg(N);
4008 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4009 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4010 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4015 Op = MachineOperand::CreateReg(Reg, false);
4019 // Check if ValueMap has reg number.
4020 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4021 if (VMI != FuncInfo.ValueMap.end())
4022 Op = MachineOperand::CreateReg(VMI->second, false);
4025 if (!Op && N.getNode())
4026 // Check if frame index is available.
4027 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4028 if (FrameIndexSDNode *FINode =
4029 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4030 Op = MachineOperand::CreateFI(FINode->getIndex());
4035 assert(Variable->isValidLocationForIntrinsic(DL) &&
4036 "Expected inlined-at fields to agree");
4038 FuncInfo.ArgDbgValues.push_back(
4039 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4040 Op->getReg(), Offset, Variable, Expr));
4042 FuncInfo.ArgDbgValues.push_back(
4043 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4046 .addMetadata(Variable)
4047 .addMetadata(Expr));
4052 // VisualStudio defines setjmp as _setjmp
4053 #if defined(_MSC_VER) && defined(setjmp) && \
4054 !defined(setjmp_undefined_for_msvc)
4055 # pragma push_macro("setjmp")
4057 # define setjmp_undefined_for_msvc
4060 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4061 /// we want to emit this as a call to a named external function, return the name
4062 /// otherwise lower it and return null.
4064 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4065 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4066 SDLoc sdl = getCurSDLoc();
4067 DebugLoc dl = getCurDebugLoc();
4070 switch (Intrinsic) {
4072 // By default, turn this into a target intrinsic node.
4073 visitTargetIntrinsic(I, Intrinsic);
4075 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4076 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4077 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4078 case Intrinsic::returnaddress:
4079 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4080 getValue(I.getArgOperand(0))));
4082 case Intrinsic::frameaddress:
4083 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4084 getValue(I.getArgOperand(0))));
4086 case Intrinsic::read_register: {
4087 Value *Reg = I.getArgOperand(0);
4088 SDValue Chain = getRoot();
4090 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4091 EVT VT = TLI.getValueType(I.getType());
4092 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4093 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4095 DAG.setRoot(Res.getValue(1));
4098 case Intrinsic::write_register: {
4099 Value *Reg = I.getArgOperand(0);
4100 Value *RegValue = I.getArgOperand(1);
4101 SDValue Chain = getRoot();
4103 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4104 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4105 RegName, getValue(RegValue)));
4108 case Intrinsic::setjmp:
4109 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4110 case Intrinsic::longjmp:
4111 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4112 case Intrinsic::memcpy: {
4113 // FIXME: this definition of "user defined address space" is x86-specific
4114 // Assert for address < 256 since we support only user defined address
4116 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4118 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4120 "Unknown address space");
4121 SDValue Op1 = getValue(I.getArgOperand(0));
4122 SDValue Op2 = getValue(I.getArgOperand(1));
4123 SDValue Op3 = getValue(I.getArgOperand(2));
4124 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4126 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4127 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4128 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4129 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4131 MachinePointerInfo(I.getArgOperand(0)),
4132 MachinePointerInfo(I.getArgOperand(1)));
4133 updateDAGForMaybeTailCall(MC);
4136 case Intrinsic::memset: {
4137 // FIXME: this definition of "user defined address space" is x86-specific
4138 // Assert for address < 256 since we support only user defined address
4140 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4142 "Unknown address space");
4143 SDValue Op1 = getValue(I.getArgOperand(0));
4144 SDValue Op2 = getValue(I.getArgOperand(1));
4145 SDValue Op3 = getValue(I.getArgOperand(2));
4146 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4148 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4149 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4150 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4151 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4152 isTC, MachinePointerInfo(I.getArgOperand(0)));
4153 updateDAGForMaybeTailCall(MS);
4156 case Intrinsic::memmove: {
4157 // FIXME: this definition of "user defined address space" is x86-specific
4158 // Assert for address < 256 since we support only user defined address
4160 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4162 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4164 "Unknown address space");
4165 SDValue Op1 = getValue(I.getArgOperand(0));
4166 SDValue Op2 = getValue(I.getArgOperand(1));
4167 SDValue Op3 = getValue(I.getArgOperand(2));
4168 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4170 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4171 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4172 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4173 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4174 isTC, MachinePointerInfo(I.getArgOperand(0)),
4175 MachinePointerInfo(I.getArgOperand(1)));
4176 updateDAGForMaybeTailCall(MM);
4179 case Intrinsic::dbg_declare: {
4180 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4181 DILocalVariable *Variable = DI.getVariable();
4182 DIExpression *Expression = DI.getExpression();
4183 const Value *Address = DI.getAddress();
4184 assert(Variable && "Missing variable");
4186 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4190 // Check if address has undef value.
4191 if (isa<UndefValue>(Address) ||
4192 (Address->use_empty() && !isa<Argument>(Address))) {
4193 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4197 SDValue &N = NodeMap[Address];
4198 if (!N.getNode() && isa<Argument>(Address))
4199 // Check unused arguments map.
4200 N = UnusedArgNodeMap[Address];
4203 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4204 Address = BCI->getOperand(0);
4205 // Parameters are handled specially.
4206 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4207 isa<Argument>(Address);
4209 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4211 if (isParameter && !AI) {
4212 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4214 // Byval parameter. We have a frame index at this point.
4215 SDV = DAG.getFrameIndexDbgValue(
4216 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4218 // Address is an argument, so try to emit its dbg value using
4219 // virtual register info from the FuncInfo.ValueMap.
4220 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4225 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4226 true, 0, dl, SDNodeOrder);
4228 // Can't do anything with other non-AI cases yet.
4229 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4230 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4231 DEBUG(Address->dump());
4234 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4236 // If Address is an argument then try to emit its dbg value using
4237 // virtual register info from the FuncInfo.ValueMap.
4238 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4240 // If variable is pinned by a alloca in dominating bb then
4241 // use StaticAllocaMap.
4242 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4243 if (AI->getParent() != DI.getParent()) {
4244 DenseMap<const AllocaInst*, int>::iterator SI =
4245 FuncInfo.StaticAllocaMap.find(AI);
4246 if (SI != FuncInfo.StaticAllocaMap.end()) {
4247 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4248 0, dl, SDNodeOrder);
4249 DAG.AddDbgValue(SDV, nullptr, false);
4254 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4259 case Intrinsic::dbg_value: {
4260 const DbgValueInst &DI = cast<DbgValueInst>(I);
4261 assert(DI.getVariable() && "Missing variable");
4263 DILocalVariable *Variable = DI.getVariable();
4264 DIExpression *Expression = DI.getExpression();
4265 uint64_t Offset = DI.getOffset();
4266 const Value *V = DI.getValue();
4271 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4272 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4274 DAG.AddDbgValue(SDV, nullptr, false);
4276 // Do not use getValue() in here; we don't want to generate code at
4277 // this point if it hasn't been done yet.
4278 SDValue N = NodeMap[V];
4279 if (!N.getNode() && isa<Argument>(V))
4280 // Check unused arguments map.
4281 N = UnusedArgNodeMap[V];
4283 // A dbg.value for an alloca is always indirect.
4284 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4285 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4287 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4288 IsIndirect, Offset, dl, SDNodeOrder);
4289 DAG.AddDbgValue(SDV, N.getNode(), false);
4291 } else if (!V->use_empty() ) {
4292 // Do not call getValue(V) yet, as we don't want to generate code.
4293 // Remember it for later.
4294 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4295 DanglingDebugInfoMap[V] = DDI;
4297 // We may expand this to cover more cases. One case where we have no
4298 // data available is an unreferenced parameter.
4299 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4303 // Build a debug info table entry.
4304 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4305 V = BCI->getOperand(0);
4306 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4307 // Don't handle byval struct arguments or VLAs, for example.
4309 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4310 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4313 DenseMap<const AllocaInst*, int>::iterator SI =
4314 FuncInfo.StaticAllocaMap.find(AI);
4315 if (SI == FuncInfo.StaticAllocaMap.end())
4316 return nullptr; // VLAs.
4320 case Intrinsic::eh_typeid_for: {
4321 // Find the type id for the given typeinfo.
4322 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4323 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4324 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4329 case Intrinsic::eh_return_i32:
4330 case Intrinsic::eh_return_i64:
4331 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4332 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4335 getValue(I.getArgOperand(0)),
4336 getValue(I.getArgOperand(1))));
4338 case Intrinsic::eh_unwind_init:
4339 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4341 case Intrinsic::eh_dwarf_cfa: {
4342 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4343 TLI.getPointerTy());
4344 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4345 CfaArg.getValueType(),
4346 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4347 CfaArg.getValueType()),
4349 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4350 DAG.getConstant(0, sdl, TLI.getPointerTy()));
4351 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4355 case Intrinsic::eh_sjlj_callsite: {
4356 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4357 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4358 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4359 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4361 MMI.setCurrentCallSite(CI->getZExtValue());
4364 case Intrinsic::eh_sjlj_functioncontext: {
4365 // Get and store the index of the function context.
4366 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4368 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4369 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4370 MFI->setFunctionContextIndex(FI);
4373 case Intrinsic::eh_sjlj_setjmp: {
4376 Ops[1] = getValue(I.getArgOperand(0));
4377 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4378 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4379 setValue(&I, Op.getValue(0));
4380 DAG.setRoot(Op.getValue(1));
4383 case Intrinsic::eh_sjlj_longjmp: {
4384 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4385 getRoot(), getValue(I.getArgOperand(0))));
4389 case Intrinsic::masked_gather:
4390 visitMaskedGather(I);
4392 case Intrinsic::masked_load:
4395 case Intrinsic::masked_scatter:
4396 visitMaskedScatter(I);
4398 case Intrinsic::masked_store:
4399 visitMaskedStore(I);
4401 case Intrinsic::x86_mmx_pslli_w:
4402 case Intrinsic::x86_mmx_pslli_d:
4403 case Intrinsic::x86_mmx_pslli_q:
4404 case Intrinsic::x86_mmx_psrli_w:
4405 case Intrinsic::x86_mmx_psrli_d:
4406 case Intrinsic::x86_mmx_psrli_q:
4407 case Intrinsic::x86_mmx_psrai_w:
4408 case Intrinsic::x86_mmx_psrai_d: {
4409 SDValue ShAmt = getValue(I.getArgOperand(1));
4410 if (isa<ConstantSDNode>(ShAmt)) {
4411 visitTargetIntrinsic(I, Intrinsic);
4414 unsigned NewIntrinsic = 0;
4415 EVT ShAmtVT = MVT::v2i32;
4416 switch (Intrinsic) {
4417 case Intrinsic::x86_mmx_pslli_w:
4418 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4420 case Intrinsic::x86_mmx_pslli_d:
4421 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4423 case Intrinsic::x86_mmx_pslli_q:
4424 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4426 case Intrinsic::x86_mmx_psrli_w:
4427 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4429 case Intrinsic::x86_mmx_psrli_d:
4430 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4432 case Intrinsic::x86_mmx_psrli_q:
4433 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4435 case Intrinsic::x86_mmx_psrai_w:
4436 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4438 case Intrinsic::x86_mmx_psrai_d:
4439 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4441 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4444 // The vector shift intrinsics with scalars uses 32b shift amounts but
4445 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4447 // We must do this early because v2i32 is not a legal type.
4450 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4451 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4452 EVT DestVT = TLI.getValueType(I.getType());
4453 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4454 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4455 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4456 getValue(I.getArgOperand(0)), ShAmt);
4460 case Intrinsic::convertff:
4461 case Intrinsic::convertfsi:
4462 case Intrinsic::convertfui:
4463 case Intrinsic::convertsif:
4464 case Intrinsic::convertuif:
4465 case Intrinsic::convertss:
4466 case Intrinsic::convertsu:
4467 case Intrinsic::convertus:
4468 case Intrinsic::convertuu: {
4469 ISD::CvtCode Code = ISD::CVT_INVALID;
4470 switch (Intrinsic) {
4471 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4472 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4473 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4474 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4475 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4476 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4477 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4478 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4479 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4480 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4482 EVT DestVT = TLI.getValueType(I.getType());
4483 const Value *Op1 = I.getArgOperand(0);
4484 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4485 DAG.getValueType(DestVT),
4486 DAG.getValueType(getValue(Op1).getValueType()),
4487 getValue(I.getArgOperand(1)),
4488 getValue(I.getArgOperand(2)),
4493 case Intrinsic::powi:
4494 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4495 getValue(I.getArgOperand(1)), DAG));
4497 case Intrinsic::log:
4498 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4500 case Intrinsic::log2:
4501 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4503 case Intrinsic::log10:
4504 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4506 case Intrinsic::exp:
4507 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4509 case Intrinsic::exp2:
4510 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4512 case Intrinsic::pow:
4513 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4514 getValue(I.getArgOperand(1)), DAG, TLI));
4516 case Intrinsic::sqrt:
4517 case Intrinsic::fabs:
4518 case Intrinsic::sin:
4519 case Intrinsic::cos:
4520 case Intrinsic::floor:
4521 case Intrinsic::ceil:
4522 case Intrinsic::trunc:
4523 case Intrinsic::rint:
4524 case Intrinsic::nearbyint:
4525 case Intrinsic::round: {
4527 switch (Intrinsic) {
4528 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4529 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4530 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4531 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4532 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4533 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4534 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4535 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4536 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4537 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4538 case Intrinsic::round: Opcode = ISD::FROUND; break;
4541 setValue(&I, DAG.getNode(Opcode, sdl,
4542 getValue(I.getArgOperand(0)).getValueType(),
4543 getValue(I.getArgOperand(0))));
4546 case Intrinsic::minnum:
4547 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4548 getValue(I.getArgOperand(0)).getValueType(),
4549 getValue(I.getArgOperand(0)),
4550 getValue(I.getArgOperand(1))));
4552 case Intrinsic::maxnum:
4553 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4554 getValue(I.getArgOperand(0)).getValueType(),
4555 getValue(I.getArgOperand(0)),
4556 getValue(I.getArgOperand(1))));
4558 case Intrinsic::copysign:
4559 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4560 getValue(I.getArgOperand(0)).getValueType(),
4561 getValue(I.getArgOperand(0)),
4562 getValue(I.getArgOperand(1))));
4564 case Intrinsic::fma:
4565 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4566 getValue(I.getArgOperand(0)).getValueType(),
4567 getValue(I.getArgOperand(0)),
4568 getValue(I.getArgOperand(1)),
4569 getValue(I.getArgOperand(2))));
4571 case Intrinsic::fmuladd: {
4572 EVT VT = TLI.getValueType(I.getType());
4573 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4574 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4575 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4576 getValue(I.getArgOperand(0)).getValueType(),
4577 getValue(I.getArgOperand(0)),
4578 getValue(I.getArgOperand(1)),
4579 getValue(I.getArgOperand(2))));
4581 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4582 getValue(I.getArgOperand(0)).getValueType(),
4583 getValue(I.getArgOperand(0)),
4584 getValue(I.getArgOperand(1)));
4585 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4586 getValue(I.getArgOperand(0)).getValueType(),
4588 getValue(I.getArgOperand(2)));
4593 case Intrinsic::convert_to_fp16:
4594 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4595 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4596 getValue(I.getArgOperand(0)),
4597 DAG.getTargetConstant(0, sdl,
4600 case Intrinsic::convert_from_fp16:
4602 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
4603 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4604 getValue(I.getArgOperand(0)))));
4606 case Intrinsic::pcmarker: {
4607 SDValue Tmp = getValue(I.getArgOperand(0));
4608 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4611 case Intrinsic::readcyclecounter: {
4612 SDValue Op = getRoot();
4613 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4614 DAG.getVTList(MVT::i64, MVT::Other), Op);
4616 DAG.setRoot(Res.getValue(1));
4619 case Intrinsic::bswap:
4620 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4621 getValue(I.getArgOperand(0)).getValueType(),
4622 getValue(I.getArgOperand(0))));
4624 case Intrinsic::cttz: {
4625 SDValue Arg = getValue(I.getArgOperand(0));
4626 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4627 EVT Ty = Arg.getValueType();
4628 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4632 case Intrinsic::ctlz: {
4633 SDValue Arg = getValue(I.getArgOperand(0));
4634 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4635 EVT Ty = Arg.getValueType();
4636 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4640 case Intrinsic::ctpop: {
4641 SDValue Arg = getValue(I.getArgOperand(0));
4642 EVT Ty = Arg.getValueType();
4643 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4646 case Intrinsic::stacksave: {
4647 SDValue Op = getRoot();
4648 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4649 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
4651 DAG.setRoot(Res.getValue(1));
4654 case Intrinsic::stackrestore: {
4655 Res = getValue(I.getArgOperand(0));
4656 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4659 case Intrinsic::stackprotector: {
4660 // Emit code into the DAG to store the stack guard onto the stack.
4661 MachineFunction &MF = DAG.getMachineFunction();
4662 MachineFrameInfo *MFI = MF.getFrameInfo();
4663 EVT PtrTy = TLI.getPointerTy();
4664 SDValue Src, Chain = getRoot();
4665 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4666 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4668 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4669 // global variable __stack_chk_guard.
4671 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4672 if (BC->getOpcode() == Instruction::BitCast)
4673 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4675 if (GV && TLI.useLoadStackGuardNode()) {
4676 // Emit a LOAD_STACK_GUARD node.
4677 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4679 MachinePointerInfo MPInfo(GV);
4680 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4681 unsigned Flags = MachineMemOperand::MOLoad |
4682 MachineMemOperand::MOInvariant;
4683 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4684 PtrTy.getSizeInBits() / 8,
4685 DAG.getEVTAlignment(PtrTy));
4686 Node->setMemRefs(MemRefs, MemRefs + 1);
4688 // Copy the guard value to a virtual register so that it can be
4689 // retrieved in the epilogue.
4690 Src = SDValue(Node, 0);
4691 const TargetRegisterClass *RC =
4692 TLI.getRegClassFor(Src.getSimpleValueType());
4693 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4695 SPDescriptor.setGuardReg(Reg);
4696 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4698 Src = getValue(I.getArgOperand(0)); // The guard's value.
4701 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4703 int FI = FuncInfo.StaticAllocaMap[Slot];
4704 MFI->setStackProtectorIndex(FI);
4706 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4708 // Store the stack protector onto the stack.
4709 Res = DAG.getStore(Chain, sdl, Src, FIN,
4710 MachinePointerInfo::getFixedStack(FI),
4716 case Intrinsic::objectsize: {
4717 // If we don't know by now, we're never going to know.
4718 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4720 assert(CI && "Non-constant type in __builtin_object_size?");
4722 SDValue Arg = getValue(I.getCalledValue());
4723 EVT Ty = Arg.getValueType();
4726 Res = DAG.getConstant(-1ULL, sdl, Ty);
4728 Res = DAG.getConstant(0, sdl, Ty);
4733 case Intrinsic::annotation:
4734 case Intrinsic::ptr_annotation:
4735 // Drop the intrinsic, but forward the value
4736 setValue(&I, getValue(I.getOperand(0)));
4738 case Intrinsic::assume:
4739 case Intrinsic::var_annotation:
4740 // Discard annotate attributes and assumptions
4743 case Intrinsic::init_trampoline: {
4744 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4748 Ops[1] = getValue(I.getArgOperand(0));
4749 Ops[2] = getValue(I.getArgOperand(1));
4750 Ops[3] = getValue(I.getArgOperand(2));
4751 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4752 Ops[5] = DAG.getSrcValue(F);
4754 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4759 case Intrinsic::adjust_trampoline: {
4760 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4762 getValue(I.getArgOperand(0))));
4765 case Intrinsic::gcroot:
4767 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4768 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4770 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4771 GFI->addStackRoot(FI->getIndex(), TypeMap);
4774 case Intrinsic::gcread:
4775 case Intrinsic::gcwrite:
4776 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4777 case Intrinsic::flt_rounds:
4778 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4781 case Intrinsic::expect: {
4782 // Just replace __builtin_expect(exp, c) with EXP.
4783 setValue(&I, getValue(I.getArgOperand(0)));
4787 case Intrinsic::debugtrap:
4788 case Intrinsic::trap: {
4789 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
4790 if (TrapFuncName.empty()) {
4791 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4792 ISD::TRAP : ISD::DEBUGTRAP;
4793 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4796 TargetLowering::ArgListTy Args;
4798 TargetLowering::CallLoweringInfo CLI(DAG);
4799 CLI.setDebugLoc(sdl).setChain(getRoot())
4800 .setCallee(CallingConv::C, I.getType(),
4801 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4802 std::move(Args), 0);
4804 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4805 DAG.setRoot(Result.second);
4809 case Intrinsic::uadd_with_overflow:
4810 case Intrinsic::sadd_with_overflow:
4811 case Intrinsic::usub_with_overflow:
4812 case Intrinsic::ssub_with_overflow:
4813 case Intrinsic::umul_with_overflow:
4814 case Intrinsic::smul_with_overflow: {
4816 switch (Intrinsic) {
4817 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4818 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4819 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4820 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4821 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4822 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4823 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4825 SDValue Op1 = getValue(I.getArgOperand(0));
4826 SDValue Op2 = getValue(I.getArgOperand(1));
4828 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4829 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4832 case Intrinsic::prefetch: {
4834 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4836 Ops[1] = getValue(I.getArgOperand(0));
4837 Ops[2] = getValue(I.getArgOperand(1));
4838 Ops[3] = getValue(I.getArgOperand(2));
4839 Ops[4] = getValue(I.getArgOperand(3));
4840 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4841 DAG.getVTList(MVT::Other), Ops,
4842 EVT::getIntegerVT(*Context, 8),
4843 MachinePointerInfo(I.getArgOperand(0)),
4845 false, /* volatile */
4847 rw==1)); /* write */
4850 case Intrinsic::lifetime_start:
4851 case Intrinsic::lifetime_end: {
4852 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4853 // Stack coloring is not enabled in O0, discard region information.
4854 if (TM.getOptLevel() == CodeGenOpt::None)
4857 SmallVector<Value *, 4> Allocas;
4858 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4860 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4861 E = Allocas.end(); Object != E; ++Object) {
4862 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4864 // Could not find an Alloca.
4865 if (!LifetimeObject)
4868 // First check that the Alloca is static, otherwise it won't have a
4869 // valid frame index.
4870 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4871 if (SI == FuncInfo.StaticAllocaMap.end())
4874 int FI = SI->second;
4878 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
4879 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4881 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4886 case Intrinsic::invariant_start:
4887 // Discard region information.
4888 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4890 case Intrinsic::invariant_end:
4891 // Discard region information.
4893 case Intrinsic::stackprotectorcheck: {
4894 // Do not actually emit anything for this basic block. Instead we initialize
4895 // the stack protector descriptor and export the guard variable so we can
4896 // access it in FinishBasicBlock.
4897 const BasicBlock *BB = I.getParent();
4898 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4899 ExportFromCurrentBlock(SPDescriptor.getGuard());
4901 // Flush our exports since we are going to process a terminator.
4902 (void)getControlRoot();
4905 case Intrinsic::clear_cache:
4906 return TLI.getClearCacheBuiltinName();
4907 case Intrinsic::eh_actions:
4908 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4910 case Intrinsic::donothing:
4913 case Intrinsic::experimental_stackmap: {
4917 case Intrinsic::experimental_patchpoint_void:
4918 case Intrinsic::experimental_patchpoint_i64: {
4919 visitPatchpoint(&I);
4922 case Intrinsic::experimental_gc_statepoint: {
4926 case Intrinsic::experimental_gc_result_int:
4927 case Intrinsic::experimental_gc_result_float:
4928 case Intrinsic::experimental_gc_result_ptr:
4929 case Intrinsic::experimental_gc_result: {
4933 case Intrinsic::experimental_gc_relocate: {
4937 case Intrinsic::instrprof_increment:
4938 llvm_unreachable("instrprof failed to lower an increment");
4940 case Intrinsic::frameescape: {
4941 MachineFunction &MF = DAG.getMachineFunction();
4942 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4944 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
4945 // is the same on all targets.
4946 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4947 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4948 if (isa<ConstantPointerNull>(Arg))
4949 continue; // Skip null pointers. They represent a hole in index space.
4950 AllocaInst *Slot = cast<AllocaInst>(Arg);
4951 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4952 "can only escape static allocas");
4953 int FI = FuncInfo.StaticAllocaMap[Slot];
4954 MCSymbol *FrameAllocSym =
4955 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4956 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4958 TII->get(TargetOpcode::FRAME_ALLOC))
4959 .addSym(FrameAllocSym)
4966 case Intrinsic::framerecover: {
4967 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
4968 MachineFunction &MF = DAG.getMachineFunction();
4969 MVT PtrVT = TLI.getPointerTy(0);
4971 // Get the symbol that defines the frame offset.
4972 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
4973 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
4974 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
4975 MCSymbol *FrameAllocSym =
4976 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4977 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
4979 // Create a TargetExternalSymbol for the label to avoid any target lowering
4980 // that would make this PC relative.
4981 StringRef Name = FrameAllocSym->getName();
4982 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
4983 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
4985 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
4987 // Add the offset to the FP.
4988 Value *FP = I.getArgOperand(1);
4989 SDValue FPVal = getValue(FP);
4990 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
4995 case Intrinsic::eh_begincatch:
4996 case Intrinsic::eh_endcatch:
4997 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
4998 case Intrinsic::eh_exceptioncode: {
4999 unsigned Reg = TLI.getExceptionPointerRegister();
5000 assert(Reg && "cannot get exception code on this platform");
5001 MVT PtrVT = TLI.getPointerTy();
5002 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5003 assert(FuncInfo.MBB->isLandingPad() && "eh.exceptioncode in non-lpad");
5004 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5006 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5007 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5014 std::pair<SDValue, SDValue>
5015 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5016 MachineBasicBlock *LandingPad) {
5017 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5018 MCSymbol *BeginLabel = nullptr;
5021 // Insert a label before the invoke call to mark the try range. This can be
5022 // used to detect deletion of the invoke via the MachineModuleInfo.
5023 BeginLabel = MMI.getContext().createTempSymbol();
5025 // For SjLj, keep track of which landing pads go with which invokes
5026 // so as to maintain the ordering of pads in the LSDA.
5027 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5028 if (CallSiteIndex) {
5029 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5030 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5032 // Now that the call site is handled, stop tracking it.
5033 MMI.setCurrentCallSite(0);
5036 // Both PendingLoads and PendingExports must be flushed here;
5037 // this call might not return.
5039 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5041 CLI.setChain(getRoot());
5043 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5044 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5046 assert((CLI.IsTailCall || Result.second.getNode()) &&
5047 "Non-null chain expected with non-tail call!");
5048 assert((Result.second.getNode() || !Result.first.getNode()) &&
5049 "Null value expected with tail call!");
5051 if (!Result.second.getNode()) {
5052 // As a special case, a null chain means that a tail call has been emitted
5053 // and the DAG root is already updated.
5056 // Since there's no actual continuation from this block, nothing can be
5057 // relying on us setting vregs for them.
5058 PendingExports.clear();
5060 DAG.setRoot(Result.second);
5064 // Insert a label at the end of the invoke call to mark the try range. This
5065 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5066 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5067 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5069 // Inform MachineModuleInfo of range.
5070 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5076 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5078 MachineBasicBlock *LandingPad) {
5079 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5080 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5081 Type *RetTy = FTy->getReturnType();
5083 TargetLowering::ArgListTy Args;
5084 TargetLowering::ArgListEntry Entry;
5085 Args.reserve(CS.arg_size());
5087 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5089 const Value *V = *i;
5092 if (V->getType()->isEmptyTy())
5095 SDValue ArgNode = getValue(V);
5096 Entry.Node = ArgNode; Entry.Ty = V->getType();
5098 // Skip the first return-type Attribute to get to params.
5099 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5100 Args.push_back(Entry);
5102 // If we have an explicit sret argument that is an Instruction, (i.e., it
5103 // might point to function-local memory), we can't meaningfully tail-call.
5104 if (Entry.isSRet && isa<Instruction>(V))
5108 // Check if target-independent constraints permit a tail call here.
5109 // Target-dependent constraints are checked within TLI->LowerCallTo.
5110 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5113 TargetLowering::CallLoweringInfo CLI(DAG);
5114 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5115 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5116 .setTailCall(isTailCall);
5117 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5119 if (Result.first.getNode())
5120 setValue(CS.getInstruction(), Result.first);
5123 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5124 /// value is equal or not-equal to zero.
5125 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5126 for (const User *U : V->users()) {
5127 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5128 if (IC->isEquality())
5129 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5130 if (C->isNullValue())
5132 // Unknown instruction.
5138 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5140 SelectionDAGBuilder &Builder) {
5142 // Check to see if this load can be trivially constant folded, e.g. if the
5143 // input is from a string literal.
5144 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5145 // Cast pointer to the type we really want to load.
5146 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5147 PointerType::getUnqual(LoadTy));
5149 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5150 const_cast<Constant *>(LoadInput), *Builder.DL))
5151 return Builder.getValue(LoadCst);
5154 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5155 // still constant memory, the input chain can be the entry node.
5157 bool ConstantMemory = false;
5159 // Do not serialize (non-volatile) loads of constant memory with anything.
5160 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5161 Root = Builder.DAG.getEntryNode();
5162 ConstantMemory = true;
5164 // Do not serialize non-volatile loads against each other.
5165 Root = Builder.DAG.getRoot();
5168 SDValue Ptr = Builder.getValue(PtrVal);
5169 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5170 Ptr, MachinePointerInfo(PtrVal),
5172 false /*nontemporal*/,
5173 false /*isinvariant*/, 1 /* align=1 */);
5175 if (!ConstantMemory)
5176 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5180 /// processIntegerCallValue - Record the value for an instruction that
5181 /// produces an integer result, converting the type where necessary.
5182 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5185 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5187 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5189 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5190 setValue(&I, Value);
5193 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5194 /// If so, return true and lower it, otherwise return false and it will be
5195 /// lowered like a normal call.
5196 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5197 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5198 if (I.getNumArgOperands() != 3)
5201 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5202 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5203 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5204 !I.getType()->isIntegerTy())
5207 const Value *Size = I.getArgOperand(2);
5208 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5209 if (CSize && CSize->getZExtValue() == 0) {
5210 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5211 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5215 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5216 std::pair<SDValue, SDValue> Res =
5217 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5218 getValue(LHS), getValue(RHS), getValue(Size),
5219 MachinePointerInfo(LHS),
5220 MachinePointerInfo(RHS));
5221 if (Res.first.getNode()) {
5222 processIntegerCallValue(I, Res.first, true);
5223 PendingLoads.push_back(Res.second);
5227 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5228 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5229 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5230 bool ActuallyDoIt = true;
5233 switch (CSize->getZExtValue()) {
5235 LoadVT = MVT::Other;
5237 ActuallyDoIt = false;
5241 LoadTy = Type::getInt16Ty(CSize->getContext());
5245 LoadTy = Type::getInt32Ty(CSize->getContext());
5249 LoadTy = Type::getInt64Ty(CSize->getContext());
5253 LoadVT = MVT::v4i32;
5254 LoadTy = Type::getInt32Ty(CSize->getContext());
5255 LoadTy = VectorType::get(LoadTy, 4);
5260 // This turns into unaligned loads. We only do this if the target natively
5261 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5262 // we'll only produce a small number of byte loads.
5264 // Require that we can find a legal MVT, and only do this if the target
5265 // supports unaligned loads of that type. Expanding into byte loads would
5267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5268 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5269 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5270 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5271 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5272 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5273 // TODO: Check alignment of src and dest ptrs.
5274 if (!TLI.isTypeLegal(LoadVT) ||
5275 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5276 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5277 ActuallyDoIt = false;
5281 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5282 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5284 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5286 processIntegerCallValue(I, Res, false);
5295 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5296 /// form. If so, return true and lower it, otherwise return false and it
5297 /// will be lowered like a normal call.
5298 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5299 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5300 if (I.getNumArgOperands() != 3)
5303 const Value *Src = I.getArgOperand(0);
5304 const Value *Char = I.getArgOperand(1);
5305 const Value *Length = I.getArgOperand(2);
5306 if (!Src->getType()->isPointerTy() ||
5307 !Char->getType()->isIntegerTy() ||
5308 !Length->getType()->isIntegerTy() ||
5309 !I.getType()->isPointerTy())
5312 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5313 std::pair<SDValue, SDValue> Res =
5314 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5315 getValue(Src), getValue(Char), getValue(Length),
5316 MachinePointerInfo(Src));
5317 if (Res.first.getNode()) {
5318 setValue(&I, Res.first);
5319 PendingLoads.push_back(Res.second);
5326 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5327 /// optimized form. If so, return true and lower it, otherwise return false
5328 /// and it will be lowered like a normal call.
5329 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5330 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5331 if (I.getNumArgOperands() != 2)
5334 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5335 if (!Arg0->getType()->isPointerTy() ||
5336 !Arg1->getType()->isPointerTy() ||
5337 !I.getType()->isPointerTy())
5340 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5341 std::pair<SDValue, SDValue> Res =
5342 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5343 getValue(Arg0), getValue(Arg1),
5344 MachinePointerInfo(Arg0),
5345 MachinePointerInfo(Arg1), isStpcpy);
5346 if (Res.first.getNode()) {
5347 setValue(&I, Res.first);
5348 DAG.setRoot(Res.second);
5355 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5356 /// If so, return true and lower it, otherwise return false and it will be
5357 /// lowered like a normal call.
5358 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5359 // Verify that the prototype makes sense. int strcmp(void*,void*)
5360 if (I.getNumArgOperands() != 2)
5363 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5364 if (!Arg0->getType()->isPointerTy() ||
5365 !Arg1->getType()->isPointerTy() ||
5366 !I.getType()->isIntegerTy())
5369 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5370 std::pair<SDValue, SDValue> Res =
5371 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5372 getValue(Arg0), getValue(Arg1),
5373 MachinePointerInfo(Arg0),
5374 MachinePointerInfo(Arg1));
5375 if (Res.first.getNode()) {
5376 processIntegerCallValue(I, Res.first, true);
5377 PendingLoads.push_back(Res.second);
5384 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5385 /// form. If so, return true and lower it, otherwise return false and it
5386 /// will be lowered like a normal call.
5387 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5388 // Verify that the prototype makes sense. size_t strlen(char *)
5389 if (I.getNumArgOperands() != 1)
5392 const Value *Arg0 = I.getArgOperand(0);
5393 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5396 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5397 std::pair<SDValue, SDValue> Res =
5398 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5399 getValue(Arg0), MachinePointerInfo(Arg0));
5400 if (Res.first.getNode()) {
5401 processIntegerCallValue(I, Res.first, false);
5402 PendingLoads.push_back(Res.second);
5409 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5410 /// form. If so, return true and lower it, otherwise return false and it
5411 /// will be lowered like a normal call.
5412 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5413 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5414 if (I.getNumArgOperands() != 2)
5417 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5418 if (!Arg0->getType()->isPointerTy() ||
5419 !Arg1->getType()->isIntegerTy() ||
5420 !I.getType()->isIntegerTy())
5423 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5424 std::pair<SDValue, SDValue> Res =
5425 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5426 getValue(Arg0), getValue(Arg1),
5427 MachinePointerInfo(Arg0));
5428 if (Res.first.getNode()) {
5429 processIntegerCallValue(I, Res.first, false);
5430 PendingLoads.push_back(Res.second);
5437 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5438 /// operation (as expected), translate it to an SDNode with the specified opcode
5439 /// and return true.
5440 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5442 // Sanity check that it really is a unary floating-point call.
5443 if (I.getNumArgOperands() != 1 ||
5444 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5445 I.getType() != I.getArgOperand(0)->getType() ||
5446 !I.onlyReadsMemory())
5449 SDValue Tmp = getValue(I.getArgOperand(0));
5450 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5454 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5455 /// operation (as expected), translate it to an SDNode with the specified opcode
5456 /// and return true.
5457 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5459 // Sanity check that it really is a binary floating-point call.
5460 if (I.getNumArgOperands() != 2 ||
5461 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5462 I.getType() != I.getArgOperand(0)->getType() ||
5463 I.getType() != I.getArgOperand(1)->getType() ||
5464 !I.onlyReadsMemory())
5467 SDValue Tmp0 = getValue(I.getArgOperand(0));
5468 SDValue Tmp1 = getValue(I.getArgOperand(1));
5469 EVT VT = Tmp0.getValueType();
5470 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5474 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5475 // Handle inline assembly differently.
5476 if (isa<InlineAsm>(I.getCalledValue())) {
5481 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5482 ComputeUsesVAFloatArgument(I, &MMI);
5484 const char *RenameFn = nullptr;
5485 if (Function *F = I.getCalledFunction()) {
5486 if (F->isDeclaration()) {
5487 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5488 if (unsigned IID = II->getIntrinsicID(F)) {
5489 RenameFn = visitIntrinsicCall(I, IID);
5494 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5495 RenameFn = visitIntrinsicCall(I, IID);
5501 // Check for well-known libc/libm calls. If the function is internal, it
5502 // can't be a library call.
5504 if (!F->hasLocalLinkage() && F->hasName() &&
5505 LibInfo->getLibFunc(F->getName(), Func) &&
5506 LibInfo->hasOptimizedCodeGen(Func)) {
5509 case LibFunc::copysign:
5510 case LibFunc::copysignf:
5511 case LibFunc::copysignl:
5512 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5513 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5514 I.getType() == I.getArgOperand(0)->getType() &&
5515 I.getType() == I.getArgOperand(1)->getType() &&
5516 I.onlyReadsMemory()) {
5517 SDValue LHS = getValue(I.getArgOperand(0));
5518 SDValue RHS = getValue(I.getArgOperand(1));
5519 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5520 LHS.getValueType(), LHS, RHS));
5525 case LibFunc::fabsf:
5526 case LibFunc::fabsl:
5527 if (visitUnaryFloatCall(I, ISD::FABS))
5531 case LibFunc::fminf:
5532 case LibFunc::fminl:
5533 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5537 case LibFunc::fmaxf:
5538 case LibFunc::fmaxl:
5539 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5545 if (visitUnaryFloatCall(I, ISD::FSIN))
5551 if (visitUnaryFloatCall(I, ISD::FCOS))
5555 case LibFunc::sqrtf:
5556 case LibFunc::sqrtl:
5557 case LibFunc::sqrt_finite:
5558 case LibFunc::sqrtf_finite:
5559 case LibFunc::sqrtl_finite:
5560 if (visitUnaryFloatCall(I, ISD::FSQRT))
5563 case LibFunc::floor:
5564 case LibFunc::floorf:
5565 case LibFunc::floorl:
5566 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5569 case LibFunc::nearbyint:
5570 case LibFunc::nearbyintf:
5571 case LibFunc::nearbyintl:
5572 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5576 case LibFunc::ceilf:
5577 case LibFunc::ceill:
5578 if (visitUnaryFloatCall(I, ISD::FCEIL))
5582 case LibFunc::rintf:
5583 case LibFunc::rintl:
5584 if (visitUnaryFloatCall(I, ISD::FRINT))
5587 case LibFunc::round:
5588 case LibFunc::roundf:
5589 case LibFunc::roundl:
5590 if (visitUnaryFloatCall(I, ISD::FROUND))
5593 case LibFunc::trunc:
5594 case LibFunc::truncf:
5595 case LibFunc::truncl:
5596 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5600 case LibFunc::log2f:
5601 case LibFunc::log2l:
5602 if (visitUnaryFloatCall(I, ISD::FLOG2))
5606 case LibFunc::exp2f:
5607 case LibFunc::exp2l:
5608 if (visitUnaryFloatCall(I, ISD::FEXP2))
5611 case LibFunc::memcmp:
5612 if (visitMemCmpCall(I))
5615 case LibFunc::memchr:
5616 if (visitMemChrCall(I))
5619 case LibFunc::strcpy:
5620 if (visitStrCpyCall(I, false))
5623 case LibFunc::stpcpy:
5624 if (visitStrCpyCall(I, true))
5627 case LibFunc::strcmp:
5628 if (visitStrCmpCall(I))
5631 case LibFunc::strlen:
5632 if (visitStrLenCall(I))
5635 case LibFunc::strnlen:
5636 if (visitStrNLenCall(I))
5645 Callee = getValue(I.getCalledValue());
5647 Callee = DAG.getExternalSymbol(RenameFn,
5648 DAG.getTargetLoweringInfo().getPointerTy());
5650 // Check if we can potentially perform a tail call. More detailed checking is
5651 // be done within LowerCallTo, after more information about the call is known.
5652 LowerCallTo(&I, Callee, I.isTailCall());
5657 /// AsmOperandInfo - This contains information for each constraint that we are
5659 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5661 /// CallOperand - If this is the result output operand or a clobber
5662 /// this is null, otherwise it is the incoming operand to the CallInst.
5663 /// This gets modified as the asm is processed.
5664 SDValue CallOperand;
5666 /// AssignedRegs - If this is a register or register class operand, this
5667 /// contains the set of register corresponding to the operand.
5668 RegsForValue AssignedRegs;
5670 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5671 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5674 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5675 /// corresponds to. If there is no Value* for this operand, it returns
5677 EVT getCallOperandValEVT(LLVMContext &Context,
5678 const TargetLowering &TLI,
5679 const DataLayout *DL) const {
5680 if (!CallOperandVal) return MVT::Other;
5682 if (isa<BasicBlock>(CallOperandVal))
5683 return TLI.getPointerTy();
5685 llvm::Type *OpTy = CallOperandVal->getType();
5687 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5688 // If this is an indirect operand, the operand is a pointer to the
5691 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5693 report_fatal_error("Indirect operand for inline asm not a pointer!");
5694 OpTy = PtrTy->getElementType();
5697 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5698 if (StructType *STy = dyn_cast<StructType>(OpTy))
5699 if (STy->getNumElements() == 1)
5700 OpTy = STy->getElementType(0);
5702 // If OpTy is not a single value, it may be a struct/union that we
5703 // can tile with integers.
5704 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5705 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
5714 OpTy = IntegerType::get(Context, BitSize);
5719 return TLI.getValueType(OpTy, true);
5723 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5725 } // end anonymous namespace
5727 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5728 /// specified operand. We prefer to assign virtual registers, to allow the
5729 /// register allocator to handle the assignment process. However, if the asm
5730 /// uses features that we can't model on machineinstrs, we have SDISel do the
5731 /// allocation. This produces generally horrible, but correct, code.
5733 /// OpInfo describes the operand.
5735 static void GetRegistersForValue(SelectionDAG &DAG,
5736 const TargetLowering &TLI,
5738 SDISelAsmOperandInfo &OpInfo) {
5739 LLVMContext &Context = *DAG.getContext();
5741 MachineFunction &MF = DAG.getMachineFunction();
5742 SmallVector<unsigned, 4> Regs;
5744 // If this is a constraint for a single physreg, or a constraint for a
5745 // register class, find it.
5746 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5747 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5748 OpInfo.ConstraintCode,
5749 OpInfo.ConstraintVT);
5751 unsigned NumRegs = 1;
5752 if (OpInfo.ConstraintVT != MVT::Other) {
5753 // If this is a FP input in an integer register (or visa versa) insert a bit
5754 // cast of the input value. More generally, handle any case where the input
5755 // value disagrees with the register class we plan to stick this in.
5756 if (OpInfo.Type == InlineAsm::isInput &&
5757 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5758 // Try to convert to the first EVT that the reg class contains. If the
5759 // types are identical size, use a bitcast to convert (e.g. two differing
5761 MVT RegVT = *PhysReg.second->vt_begin();
5762 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5763 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5764 RegVT, OpInfo.CallOperand);
5765 OpInfo.ConstraintVT = RegVT;
5766 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5767 // If the input is a FP value and we want it in FP registers, do a
5768 // bitcast to the corresponding integer type. This turns an f64 value
5769 // into i64, which can be passed with two i32 values on a 32-bit
5771 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5772 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5773 RegVT, OpInfo.CallOperand);
5774 OpInfo.ConstraintVT = RegVT;
5778 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5782 EVT ValueVT = OpInfo.ConstraintVT;
5784 // If this is a constraint for a specific physical register, like {r17},
5786 if (unsigned AssignedReg = PhysReg.first) {
5787 const TargetRegisterClass *RC = PhysReg.second;
5788 if (OpInfo.ConstraintVT == MVT::Other)
5789 ValueVT = *RC->vt_begin();
5791 // Get the actual register value type. This is important, because the user
5792 // may have asked for (e.g.) the AX register in i32 type. We need to
5793 // remember that AX is actually i16 to get the right extension.
5794 RegVT = *RC->vt_begin();
5796 // This is a explicit reference to a physical register.
5797 Regs.push_back(AssignedReg);
5799 // If this is an expanded reference, add the rest of the regs to Regs.
5801 TargetRegisterClass::iterator I = RC->begin();
5802 for (; *I != AssignedReg; ++I)
5803 assert(I != RC->end() && "Didn't find reg!");
5805 // Already added the first reg.
5807 for (; NumRegs; --NumRegs, ++I) {
5808 assert(I != RC->end() && "Ran out of registers to allocate!");
5813 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5817 // Otherwise, if this was a reference to an LLVM register class, create vregs
5818 // for this reference.
5819 if (const TargetRegisterClass *RC = PhysReg.second) {
5820 RegVT = *RC->vt_begin();
5821 if (OpInfo.ConstraintVT == MVT::Other)
5824 // Create the appropriate number of virtual registers.
5825 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5826 for (; NumRegs; --NumRegs)
5827 Regs.push_back(RegInfo.createVirtualRegister(RC));
5829 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5833 // Otherwise, we couldn't allocate enough registers for this.
5836 /// visitInlineAsm - Handle a call to an InlineAsm object.
5838 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5839 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5841 /// ConstraintOperands - Information about all of the constraints.
5842 SDISelAsmOperandInfoVector ConstraintOperands;
5844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5845 TargetLowering::AsmOperandInfoVector TargetConstraints =
5846 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
5848 bool hasMemory = false;
5850 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5851 unsigned ResNo = 0; // ResNo - The result number of the next output.
5852 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5853 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5854 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5856 MVT OpVT = MVT::Other;
5858 // Compute the value type for each operand.
5859 switch (OpInfo.Type) {
5860 case InlineAsm::isOutput:
5861 // Indirect outputs just consume an argument.
5862 if (OpInfo.isIndirect) {
5863 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5867 // The return value of the call is this value. As such, there is no
5868 // corresponding argument.
5869 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5870 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5871 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5873 assert(ResNo == 0 && "Asm only has one result!");
5874 OpVT = TLI.getSimpleValueType(CS.getType());
5878 case InlineAsm::isInput:
5879 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5881 case InlineAsm::isClobber:
5886 // If this is an input or an indirect output, process the call argument.
5887 // BasicBlocks are labels, currently appearing only in asm's.
5888 if (OpInfo.CallOperandVal) {
5889 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5890 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5892 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5896 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
5899 OpInfo.ConstraintVT = OpVT;
5901 // Indirect operand accesses access memory.
5902 if (OpInfo.isIndirect)
5905 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5906 TargetLowering::ConstraintType
5907 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5908 if (CType == TargetLowering::C_Memory) {
5916 SDValue Chain, Flag;
5918 // We won't need to flush pending loads if this asm doesn't touch
5919 // memory and is nonvolatile.
5920 if (hasMemory || IA->hasSideEffects())
5923 Chain = DAG.getRoot();
5925 // Second pass over the constraints: compute which constraint option to use
5926 // and assign registers to constraints that want a specific physreg.
5927 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5928 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5930 // If this is an output operand with a matching input operand, look up the
5931 // matching input. If their types mismatch, e.g. one is an integer, the
5932 // other is floating point, or their sizes are different, flag it as an
5934 if (OpInfo.hasMatchingInput()) {
5935 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5937 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5938 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5939 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5940 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5941 OpInfo.ConstraintVT);
5942 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5943 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5944 Input.ConstraintVT);
5945 if ((OpInfo.ConstraintVT.isInteger() !=
5946 Input.ConstraintVT.isInteger()) ||
5947 (MatchRC.second != InputRC.second)) {
5948 report_fatal_error("Unsupported asm: input constraint"
5949 " with a matching output constraint of"
5950 " incompatible type!");
5952 Input.ConstraintVT = OpInfo.ConstraintVT;
5956 // Compute the constraint code and ConstraintType to use.
5957 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5959 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5960 OpInfo.Type == InlineAsm::isClobber)
5963 // If this is a memory input, and if the operand is not indirect, do what we
5964 // need to to provide an address for the memory input.
5965 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5966 !OpInfo.isIndirect) {
5967 assert((OpInfo.isMultipleAlternative ||
5968 (OpInfo.Type == InlineAsm::isInput)) &&
5969 "Can only indirectify direct input operands!");
5971 // Memory operands really want the address of the value. If we don't have
5972 // an indirect input, put it in the constpool if we can, otherwise spill
5973 // it to a stack slot.
5974 // TODO: This isn't quite right. We need to handle these according to
5975 // the addressing mode that the constraint wants. Also, this may take
5976 // an additional register for the computation and we don't want that
5979 // If the operand is a float, integer, or vector constant, spill to a
5980 // constant pool entry to get its address.
5981 const Value *OpVal = OpInfo.CallOperandVal;
5982 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5983 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5984 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5985 TLI.getPointerTy());
5987 // Otherwise, create a stack slot and emit a store to it before the
5989 Type *Ty = OpVal->getType();
5990 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5991 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5992 MachineFunction &MF = DAG.getMachineFunction();
5993 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5994 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5995 Chain = DAG.getStore(Chain, getCurSDLoc(),
5996 OpInfo.CallOperand, StackSlot,
5997 MachinePointerInfo::getFixedStack(SSFI),
5999 OpInfo.CallOperand = StackSlot;
6002 // There is no longer a Value* corresponding to this operand.
6003 OpInfo.CallOperandVal = nullptr;
6005 // It is now an indirect operand.
6006 OpInfo.isIndirect = true;
6009 // If this constraint is for a specific register, allocate it before
6011 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6012 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6015 // Second pass - Loop over all of the operands, assigning virtual or physregs
6016 // to register class operands.
6017 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6018 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6020 // C_Register operands have already been allocated, Other/Memory don't need
6022 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6023 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6026 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6027 std::vector<SDValue> AsmNodeOperands;
6028 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6029 AsmNodeOperands.push_back(
6030 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6031 TLI.getPointerTy()));
6033 // If we have a !srcloc metadata node associated with it, we want to attach
6034 // this to the ultimately generated inline asm machineinstr. To do this, we
6035 // pass in the third operand as this (potentially null) inline asm MDNode.
6036 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6037 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6039 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6040 // bits as operand 3.
6041 unsigned ExtraInfo = 0;
6042 if (IA->hasSideEffects())
6043 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6044 if (IA->isAlignStack())
6045 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6046 // Set the asm dialect.
6047 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6049 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6050 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6051 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6053 // Compute the constraint code and ConstraintType to use.
6054 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6056 // Ideally, we would only check against memory constraints. However, the
6057 // meaning of an other constraint can be target-specific and we can't easily
6058 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6059 // for other constriants as well.
6060 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6061 OpInfo.ConstraintType == TargetLowering::C_Other) {
6062 if (OpInfo.Type == InlineAsm::isInput)
6063 ExtraInfo |= InlineAsm::Extra_MayLoad;
6064 else if (OpInfo.Type == InlineAsm::isOutput)
6065 ExtraInfo |= InlineAsm::Extra_MayStore;
6066 else if (OpInfo.Type == InlineAsm::isClobber)
6067 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6071 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, getCurSDLoc(),
6072 TLI.getPointerTy()));
6074 // Loop over all of the inputs, copying the operand values into the
6075 // appropriate registers and processing the output regs.
6076 RegsForValue RetValRegs;
6078 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6079 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6081 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6082 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6084 switch (OpInfo.Type) {
6085 case InlineAsm::isOutput: {
6086 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6087 OpInfo.ConstraintType != TargetLowering::C_Register) {
6088 // Memory output, or 'other' output (e.g. 'X' constraint).
6089 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6091 unsigned ConstraintID =
6092 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6093 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6094 "Failed to convert memory constraint code to constraint id.");
6096 // Add information to the INLINEASM node to know about this output.
6097 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6098 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6099 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6101 AsmNodeOperands.push_back(OpInfo.CallOperand);
6105 // Otherwise, this is a register or register class output.
6107 // Copy the output from the appropriate register. Find a register that
6109 if (OpInfo.AssignedRegs.Regs.empty()) {
6110 LLVMContext &Ctx = *DAG.getContext();
6111 Ctx.emitError(CS.getInstruction(),
6112 "couldn't allocate output register for constraint '" +
6113 Twine(OpInfo.ConstraintCode) + "'");
6117 // If this is an indirect operand, store through the pointer after the
6119 if (OpInfo.isIndirect) {
6120 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6121 OpInfo.CallOperandVal));
6123 // This is the result value of the call.
6124 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6125 // Concatenate this output onto the outputs list.
6126 RetValRegs.append(OpInfo.AssignedRegs);
6129 // Add information to the INLINEASM node to know that this register is
6132 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6133 ? InlineAsm::Kind_RegDefEarlyClobber
6134 : InlineAsm::Kind_RegDef,
6135 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6138 case InlineAsm::isInput: {
6139 SDValue InOperandVal = OpInfo.CallOperand;
6141 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6142 // If this is required to match an output register we have already set,
6143 // just use its register.
6144 unsigned OperandNo = OpInfo.getMatchedOperand();
6146 // Scan until we find the definition we already emitted of this operand.
6147 // When we find it, create a RegsForValue operand.
6148 unsigned CurOp = InlineAsm::Op_FirstOperand;
6149 for (; OperandNo; --OperandNo) {
6150 // Advance to the next operand.
6152 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6153 assert((InlineAsm::isRegDefKind(OpFlag) ||
6154 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6155 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6156 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6160 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6161 if (InlineAsm::isRegDefKind(OpFlag) ||
6162 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6163 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6164 if (OpInfo.isIndirect) {
6165 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6166 LLVMContext &Ctx = *DAG.getContext();
6167 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6168 " don't know how to handle tied "
6169 "indirect register inputs");
6173 RegsForValue MatchedRegs;
6174 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6175 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6176 MatchedRegs.RegVTs.push_back(RegVT);
6177 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6178 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6180 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6181 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6183 LLVMContext &Ctx = *DAG.getContext();
6184 Ctx.emitError(CS.getInstruction(),
6185 "inline asm error: This value"
6186 " type register class is not natively supported!");
6190 SDLoc dl = getCurSDLoc();
6191 // Use the produced MatchedRegs object to
6192 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6193 Chain, &Flag, CS.getInstruction());
6194 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6195 true, OpInfo.getMatchedOperand(), dl,
6196 DAG, AsmNodeOperands);
6200 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6201 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6202 "Unexpected number of operands");
6203 // Add information to the INLINEASM node to know about this input.
6204 // See InlineAsm.h isUseOperandTiedToDef.
6205 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6206 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6207 OpInfo.getMatchedOperand());
6208 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, getCurSDLoc(),
6209 TLI.getPointerTy()));
6210 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6214 // Treat indirect 'X' constraint as memory.
6215 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6217 OpInfo.ConstraintType = TargetLowering::C_Memory;
6219 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6220 std::vector<SDValue> Ops;
6221 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6224 LLVMContext &Ctx = *DAG.getContext();
6225 Ctx.emitError(CS.getInstruction(),
6226 "invalid operand for inline asm constraint '" +
6227 Twine(OpInfo.ConstraintCode) + "'");
6231 // Add information to the INLINEASM node to know about this input.
6232 unsigned ResOpType =
6233 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6234 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6236 TLI.getPointerTy()));
6237 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6241 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6242 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6243 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6244 "Memory operands expect pointer values");
6246 unsigned ConstraintID =
6247 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6248 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6249 "Failed to convert memory constraint code to constraint id.");
6251 // Add information to the INLINEASM node to know about this input.
6252 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6253 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6254 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6257 AsmNodeOperands.push_back(InOperandVal);
6261 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6262 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6263 "Unknown constraint type!");
6265 // TODO: Support this.
6266 if (OpInfo.isIndirect) {
6267 LLVMContext &Ctx = *DAG.getContext();
6268 Ctx.emitError(CS.getInstruction(),
6269 "Don't know how to handle indirect register inputs yet "
6270 "for constraint '" +
6271 Twine(OpInfo.ConstraintCode) + "'");
6275 // Copy the input into the appropriate registers.
6276 if (OpInfo.AssignedRegs.Regs.empty()) {
6277 LLVMContext &Ctx = *DAG.getContext();
6278 Ctx.emitError(CS.getInstruction(),
6279 "couldn't allocate input reg for constraint '" +
6280 Twine(OpInfo.ConstraintCode) + "'");
6284 SDLoc dl = getCurSDLoc();
6286 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6287 Chain, &Flag, CS.getInstruction());
6289 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6290 dl, DAG, AsmNodeOperands);
6293 case InlineAsm::isClobber: {
6294 // Add the clobbered value to the operand list, so that the register
6295 // allocator is aware that the physreg got clobbered.
6296 if (!OpInfo.AssignedRegs.Regs.empty())
6297 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6298 false, 0, getCurSDLoc(), DAG,
6305 // Finish up input operands. Set the input chain and add the flag last.
6306 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6307 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6309 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6310 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6311 Flag = Chain.getValue(1);
6313 // If this asm returns a register value, copy the result from that register
6314 // and set it as the value of the call.
6315 if (!RetValRegs.Regs.empty()) {
6316 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6317 Chain, &Flag, CS.getInstruction());
6319 // FIXME: Why don't we do this for inline asms with MRVs?
6320 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6321 EVT ResultType = TLI.getValueType(CS.getType());
6323 // If any of the results of the inline asm is a vector, it may have the
6324 // wrong width/num elts. This can happen for register classes that can
6325 // contain multiple different value types. The preg or vreg allocated may
6326 // not have the same VT as was expected. Convert it to the right type
6327 // with bit_convert.
6328 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6329 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6332 } else if (ResultType != Val.getValueType() &&
6333 ResultType.isInteger() && Val.getValueType().isInteger()) {
6334 // If a result value was tied to an input value, the computed result may
6335 // have a wider width than the expected result. Extract the relevant
6337 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6340 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6343 setValue(CS.getInstruction(), Val);
6344 // Don't need to use this as a chain in this case.
6345 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6349 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6351 // Process indirect outputs, first output all of the flagged copies out of
6353 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6354 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6355 const Value *Ptr = IndirectStoresToEmit[i].second;
6356 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6358 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6361 // Emit the non-flagged stores from the physregs.
6362 SmallVector<SDValue, 8> OutChains;
6363 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6364 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6365 StoresToEmit[i].first,
6366 getValue(StoresToEmit[i].second),
6367 MachinePointerInfo(StoresToEmit[i].second),
6369 OutChains.push_back(Val);
6372 if (!OutChains.empty())
6373 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6378 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6379 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6380 MVT::Other, getRoot(),
6381 getValue(I.getArgOperand(0)),
6382 DAG.getSrcValue(I.getArgOperand(0))));
6385 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6386 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6387 const DataLayout &DL = *TLI.getDataLayout();
6388 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6389 getRoot(), getValue(I.getOperand(0)),
6390 DAG.getSrcValue(I.getOperand(0)),
6391 DL.getABITypeAlignment(I.getType()));
6393 DAG.setRoot(V.getValue(1));
6396 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6397 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6398 MVT::Other, getRoot(),
6399 getValue(I.getArgOperand(0)),
6400 DAG.getSrcValue(I.getArgOperand(0))));
6403 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6404 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6405 MVT::Other, getRoot(),
6406 getValue(I.getArgOperand(0)),
6407 getValue(I.getArgOperand(1)),
6408 DAG.getSrcValue(I.getArgOperand(0)),
6409 DAG.getSrcValue(I.getArgOperand(1))));
6412 /// \brief Lower an argument list according to the target calling convention.
6414 /// \return A tuple of <return-value, token-chain>
6416 /// This is a helper for lowering intrinsics that follow a target calling
6417 /// convention or require stack pointer adjustment. Only a subset of the
6418 /// intrinsic's operands need to participate in the calling convention.
6419 std::pair<SDValue, SDValue>
6420 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6421 unsigned NumArgs, SDValue Callee,
6423 MachineBasicBlock *LandingPad,
6424 bool IsPatchPoint) {
6425 TargetLowering::ArgListTy Args;
6426 Args.reserve(NumArgs);
6428 // Populate the argument list.
6429 // Attributes for args start at offset 1, after the return attribute.
6430 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6431 ArgI != ArgE; ++ArgI) {
6432 const Value *V = CS->getOperand(ArgI);
6434 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6436 TargetLowering::ArgListEntry Entry;
6437 Entry.Node = getValue(V);
6438 Entry.Ty = V->getType();
6439 Entry.setAttributes(&CS, AttrI);
6440 Args.push_back(Entry);
6443 TargetLowering::CallLoweringInfo CLI(DAG);
6444 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6445 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6446 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6448 return lowerInvokable(CLI, LandingPad);
6451 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6452 /// or patchpoint target node's operand list.
6454 /// Constants are converted to TargetConstants purely as an optimization to
6455 /// avoid constant materialization and register allocation.
6457 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6458 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6459 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6460 /// address materialization and register allocation, but may also be required
6461 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6462 /// alloca in the entry block, then the runtime may assume that the alloca's
6463 /// StackMap location can be read immediately after compilation and that the
6464 /// location is valid at any point during execution (this is similar to the
6465 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6466 /// only available in a register, then the runtime would need to trap when
6467 /// execution reaches the StackMap in order to read the alloca's location.
6468 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6469 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6470 SelectionDAGBuilder &Builder) {
6471 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6472 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6473 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6475 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6477 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6478 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6479 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6481 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6483 Ops.push_back(OpVal);
6487 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6488 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6489 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6490 // [live variables...])
6492 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6494 SDValue Chain, InFlag, Callee, NullPtr;
6495 SmallVector<SDValue, 32> Ops;
6497 SDLoc DL = getCurSDLoc();
6498 Callee = getValue(CI.getCalledValue());
6499 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6501 // The stackmap intrinsic only records the live variables (the arguemnts
6502 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6503 // intrinsic, this won't be lowered to a function call. This means we don't
6504 // have to worry about calling conventions and target specific lowering code.
6505 // Instead we perform the call lowering right here.
6507 // chain, flag = CALLSEQ_START(chain, 0)
6508 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6509 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6511 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6512 InFlag = Chain.getValue(1);
6514 // Add the <id> and <numBytes> constants.
6515 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6516 Ops.push_back(DAG.getTargetConstant(
6517 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6518 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6519 Ops.push_back(DAG.getTargetConstant(
6520 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6523 // Push live variables for the stack map.
6524 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6526 // We are not pushing any register mask info here on the operands list,
6527 // because the stackmap doesn't clobber anything.
6529 // Push the chain and the glue flag.
6530 Ops.push_back(Chain);
6531 Ops.push_back(InFlag);
6533 // Create the STACKMAP node.
6534 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6535 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6536 Chain = SDValue(SM, 0);
6537 InFlag = Chain.getValue(1);
6539 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6541 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6543 // Set the root to the target-lowered call chain.
6546 // Inform the Frame Information that we have a stackmap in this function.
6547 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6550 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6551 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6552 MachineBasicBlock *LandingPad) {
6553 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6558 // [live variables...])
6560 CallingConv::ID CC = CS.getCallingConv();
6561 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6562 bool HasDef = !CS->getType()->isVoidTy();
6563 SDLoc dl = getCurSDLoc();
6564 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6566 // Handle immediate and symbolic callees.
6567 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6568 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6570 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6571 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6572 SDLoc(SymbolicCallee),
6573 SymbolicCallee->getValueType(0));
6575 // Get the real number of arguments participating in the call <numArgs>
6576 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6577 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6579 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6580 // Intrinsics include all meta-operands up to but not including CC.
6581 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6582 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6583 "Not enough arguments provided to the patchpoint intrinsic");
6585 // For AnyRegCC the arguments are lowered later on manually.
6586 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6588 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6589 std::pair<SDValue, SDValue> Result =
6590 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6593 SDNode *CallEnd = Result.second.getNode();
6594 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6595 CallEnd = CallEnd->getOperand(0).getNode();
6597 /// Get a call instruction from the call sequence chain.
6598 /// Tail calls are not allowed.
6599 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6600 "Expected a callseq node.");
6601 SDNode *Call = CallEnd->getOperand(0).getNode();
6602 bool HasGlue = Call->getGluedNode();
6604 // Replace the target specific call node with the patchable intrinsic.
6605 SmallVector<SDValue, 8> Ops;
6607 // Add the <id> and <numBytes> constants.
6608 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6609 Ops.push_back(DAG.getTargetConstant(
6610 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6611 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6612 Ops.push_back(DAG.getTargetConstant(
6613 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6617 Ops.push_back(Callee);
6619 // Adjust <numArgs> to account for any arguments that have been passed on the
6621 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6622 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6623 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6624 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6626 // Add the calling convention
6627 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6629 // Add the arguments we omitted previously. The register allocator should
6630 // place these in any free register.
6632 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6633 Ops.push_back(getValue(CS.getArgument(i)));
6635 // Push the arguments from the call instruction up to the register mask.
6636 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6637 Ops.append(Call->op_begin() + 2, e);
6639 // Push live variables for the stack map.
6640 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6642 // Push the register mask info.
6644 Ops.push_back(*(Call->op_end()-2));
6646 Ops.push_back(*(Call->op_end()-1));
6648 // Push the chain (this is originally the first operand of the call, but
6649 // becomes now the last or second to last operand).
6650 Ops.push_back(*(Call->op_begin()));
6652 // Push the glue flag (last operand).
6654 Ops.push_back(*(Call->op_end()-1));
6657 if (IsAnyRegCC && HasDef) {
6658 // Create the return types based on the intrinsic definition
6659 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6660 SmallVector<EVT, 3> ValueVTs;
6661 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
6662 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6664 // There is always a chain and a glue type at the end
6665 ValueVTs.push_back(MVT::Other);
6666 ValueVTs.push_back(MVT::Glue);
6667 NodeTys = DAG.getVTList(ValueVTs);
6669 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6671 // Replace the target specific call node with a PATCHPOINT node.
6672 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6675 // Update the NodeMap.
6678 setValue(CS.getInstruction(), SDValue(MN, 0));
6680 setValue(CS.getInstruction(), Result.first);
6683 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6684 // call sequence. Furthermore the location of the chain and glue can change
6685 // when the AnyReg calling convention is used and the intrinsic returns a
6687 if (IsAnyRegCC && HasDef) {
6688 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6689 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6690 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6692 DAG.ReplaceAllUsesWith(Call, MN);
6693 DAG.DeleteNode(Call);
6695 // Inform the Frame Information that we have a patchpoint in this function.
6696 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6699 /// Returns an AttributeSet representing the attributes applied to the return
6700 /// value of the given call.
6701 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6702 SmallVector<Attribute::AttrKind, 2> Attrs;
6704 Attrs.push_back(Attribute::SExt);
6706 Attrs.push_back(Attribute::ZExt);
6708 Attrs.push_back(Attribute::InReg);
6710 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6714 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6715 /// implementation, which just calls LowerCall.
6716 /// FIXME: When all targets are
6717 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6718 std::pair<SDValue, SDValue>
6719 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6720 // Handle the incoming return values from the call.
6722 Type *OrigRetTy = CLI.RetTy;
6723 SmallVector<EVT, 4> RetTys;
6724 SmallVector<uint64_t, 4> Offsets;
6725 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
6727 SmallVector<ISD::OutputArg, 4> Outs;
6728 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
6730 bool CanLowerReturn =
6731 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6732 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6734 SDValue DemoteStackSlot;
6735 int DemoteStackIdx = -100;
6736 if (!CanLowerReturn) {
6737 // FIXME: equivalent assert?
6738 // assert(!CS.hasInAllocaArgument() &&
6739 // "sret demotion is incompatible with inalloca");
6740 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
6741 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
6742 MachineFunction &MF = CLI.DAG.getMachineFunction();
6743 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6744 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6746 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
6748 Entry.Node = DemoteStackSlot;
6749 Entry.Ty = StackSlotPtrType;
6750 Entry.isSExt = false;
6751 Entry.isZExt = false;
6752 Entry.isInReg = false;
6753 Entry.isSRet = true;
6754 Entry.isNest = false;
6755 Entry.isByVal = false;
6756 Entry.isReturned = false;
6757 Entry.Alignment = Align;
6758 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6759 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6761 // sret demotion isn't compatible with tail-calls, since the sret argument
6762 // points into the callers stack frame.
6763 CLI.IsTailCall = false;
6765 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6767 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6768 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6769 for (unsigned i = 0; i != NumRegs; ++i) {
6770 ISD::InputArg MyFlags;
6771 MyFlags.VT = RegisterVT;
6773 MyFlags.Used = CLI.IsReturnValueUsed;
6775 MyFlags.Flags.setSExt();
6777 MyFlags.Flags.setZExt();
6779 MyFlags.Flags.setInReg();
6780 CLI.Ins.push_back(MyFlags);
6785 // Handle all of the outgoing arguments.
6787 CLI.OutVals.clear();
6788 ArgListTy &Args = CLI.getArgs();
6789 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6790 SmallVector<EVT, 4> ValueVTs;
6791 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6792 Type *FinalType = Args[i].Ty;
6793 if (Args[i].isByVal)
6794 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6795 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6796 FinalType, CLI.CallConv, CLI.IsVarArg);
6797 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6799 EVT VT = ValueVTs[Value];
6800 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6801 SDValue Op = SDValue(Args[i].Node.getNode(),
6802 Args[i].Node.getResNo() + Value);
6803 ISD::ArgFlagsTy Flags;
6804 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
6810 if (Args[i].isInReg)
6814 if (Args[i].isByVal)
6816 if (Args[i].isInAlloca) {
6817 Flags.setInAlloca();
6818 // Set the byval flag for CCAssignFn callbacks that don't know about
6819 // inalloca. This way we can know how many bytes we should've allocated
6820 // and how many bytes a callee cleanup function will pop. If we port
6821 // inalloca to more targets, we'll have to add custom inalloca handling
6822 // in the various CC lowering callbacks.
6825 if (Args[i].isByVal || Args[i].isInAlloca) {
6826 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6827 Type *ElementTy = Ty->getElementType();
6828 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6829 // For ByVal, alignment should come from FE. BE will guess if this
6830 // info is not there but there are cases it cannot get right.
6831 unsigned FrameAlign;
6832 if (Args[i].Alignment)
6833 FrameAlign = Args[i].Alignment;
6835 FrameAlign = getByValTypeAlignment(ElementTy);
6836 Flags.setByValAlign(FrameAlign);
6841 Flags.setInConsecutiveRegs();
6842 Flags.setOrigAlign(OriginalAlignment);
6844 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6845 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6846 SmallVector<SDValue, 4> Parts(NumParts);
6847 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6850 ExtendKind = ISD::SIGN_EXTEND;
6851 else if (Args[i].isZExt)
6852 ExtendKind = ISD::ZERO_EXTEND;
6854 // Conservatively only handle 'returned' on non-vectors for now
6855 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6856 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6857 "unexpected use of 'returned'");
6858 // Before passing 'returned' to the target lowering code, ensure that
6859 // either the register MVT and the actual EVT are the same size or that
6860 // the return value and argument are extended in the same way; in these
6861 // cases it's safe to pass the argument register value unchanged as the
6862 // return register value (although it's at the target's option whether
6864 // TODO: allow code generation to take advantage of partially preserved
6865 // registers rather than clobbering the entire register when the
6866 // parameter extension method is not compatible with the return
6868 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6869 (ExtendKind != ISD::ANY_EXTEND &&
6870 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6871 Flags.setReturned();
6874 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6875 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6877 for (unsigned j = 0; j != NumParts; ++j) {
6878 // if it isn't first piece, alignment must be 1
6879 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6880 i < CLI.NumFixedArgs,
6881 i, j*Parts[j].getValueType().getStoreSize());
6882 if (NumParts > 1 && j == 0)
6883 MyFlags.Flags.setSplit();
6885 MyFlags.Flags.setOrigAlign(1);
6887 CLI.Outs.push_back(MyFlags);
6888 CLI.OutVals.push_back(Parts[j]);
6891 if (NeedsRegBlock && Value == NumValues - 1)
6892 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6896 SmallVector<SDValue, 4> InVals;
6897 CLI.Chain = LowerCall(CLI, InVals);
6899 // Verify that the target's LowerCall behaved as expected.
6900 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6901 "LowerCall didn't return a valid chain!");
6902 assert((!CLI.IsTailCall || InVals.empty()) &&
6903 "LowerCall emitted a return value for a tail call!");
6904 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6905 "LowerCall didn't emit the correct number of values!");
6907 // For a tail call, the return value is merely live-out and there aren't
6908 // any nodes in the DAG representing it. Return a special value to
6909 // indicate that a tail call has been emitted and no more Instructions
6910 // should be processed in the current block.
6911 if (CLI.IsTailCall) {
6912 CLI.DAG.setRoot(CLI.Chain);
6913 return std::make_pair(SDValue(), SDValue());
6916 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6917 assert(InVals[i].getNode() &&
6918 "LowerCall emitted a null value!");
6919 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6920 "LowerCall emitted a value with the wrong type!");
6923 SmallVector<SDValue, 4> ReturnValues;
6924 if (!CanLowerReturn) {
6925 // The instruction result is the result of loading from the
6926 // hidden sret parameter.
6927 SmallVector<EVT, 1> PVTs;
6928 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6930 ComputeValueVTs(*this, PtrRetTy, PVTs);
6931 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6932 EVT PtrVT = PVTs[0];
6934 unsigned NumValues = RetTys.size();
6935 ReturnValues.resize(NumValues);
6936 SmallVector<SDValue, 4> Chains(NumValues);
6938 for (unsigned i = 0; i < NumValues; ++i) {
6939 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6940 CLI.DAG.getConstant(Offsets[i], CLI.DL,
6942 SDValue L = CLI.DAG.getLoad(
6943 RetTys[i], CLI.DL, CLI.Chain, Add,
6944 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6946 ReturnValues[i] = L;
6947 Chains[i] = L.getValue(1);
6950 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6952 // Collect the legal value parts into potentially illegal values
6953 // that correspond to the original function's return values.
6954 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6956 AssertOp = ISD::AssertSext;
6957 else if (CLI.RetZExt)
6958 AssertOp = ISD::AssertZext;
6959 unsigned CurReg = 0;
6960 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6962 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6963 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6965 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6966 NumRegs, RegisterVT, VT, nullptr,
6971 // For a function returning void, there is no return value. We can't create
6972 // such a node, so we just return a null return value in that case. In
6973 // that case, nothing will actually look at the value.
6974 if (ReturnValues.empty())
6975 return std::make_pair(SDValue(), CLI.Chain);
6978 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6979 CLI.DAG.getVTList(RetTys), ReturnValues);
6980 return std::make_pair(Res, CLI.Chain);
6983 void TargetLowering::LowerOperationWrapper(SDNode *N,
6984 SmallVectorImpl<SDValue> &Results,
6985 SelectionDAG &DAG) const {
6986 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6988 Results.push_back(Res);
6991 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6992 llvm_unreachable("LowerOperation not implemented for this target!");
6996 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6997 SDValue Op = getNonRegisterValue(V);
6998 assert((Op.getOpcode() != ISD::CopyFromReg ||
6999 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7000 "Copy from a reg to the same reg!");
7001 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7003 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7004 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7005 SDValue Chain = DAG.getEntryNode();
7007 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7008 FuncInfo.PreferredExtendType.end())
7010 : FuncInfo.PreferredExtendType[V];
7011 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7012 PendingExports.push_back(Chain);
7015 #include "llvm/CodeGen/SelectionDAGISel.h"
7017 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7018 /// entry block, return true. This includes arguments used by switches, since
7019 /// the switch may expand into multiple basic blocks.
7020 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7021 // With FastISel active, we may be splitting blocks, so force creation
7022 // of virtual registers for all non-dead arguments.
7024 return A->use_empty();
7026 const BasicBlock *Entry = A->getParent()->begin();
7027 for (const User *U : A->users())
7028 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7029 return false; // Use not in entry block.
7034 void SelectionDAGISel::LowerArguments(const Function &F) {
7035 SelectionDAG &DAG = SDB->DAG;
7036 SDLoc dl = SDB->getCurSDLoc();
7037 const DataLayout *DL = TLI->getDataLayout();
7038 SmallVector<ISD::InputArg, 16> Ins;
7040 if (!FuncInfo->CanLowerReturn) {
7041 // Put in an sret pointer parameter before all the other parameters.
7042 SmallVector<EVT, 1> ValueVTs;
7043 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7045 // NOTE: Assuming that a pointer will never break down to more than one VT
7047 ISD::ArgFlagsTy Flags;
7049 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7050 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7051 ISD::InputArg::NoArgIndex, 0);
7052 Ins.push_back(RetArg);
7055 // Set up the incoming argument description vector.
7057 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7058 I != E; ++I, ++Idx) {
7059 SmallVector<EVT, 4> ValueVTs;
7060 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7061 bool isArgValueUsed = !I->use_empty();
7062 unsigned PartBase = 0;
7063 Type *FinalType = I->getType();
7064 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7065 FinalType = cast<PointerType>(FinalType)->getElementType();
7066 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7067 FinalType, F.getCallingConv(), F.isVarArg());
7068 for (unsigned Value = 0, NumValues = ValueVTs.size();
7069 Value != NumValues; ++Value) {
7070 EVT VT = ValueVTs[Value];
7071 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7072 ISD::ArgFlagsTy Flags;
7073 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7075 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7077 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7079 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7081 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7083 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7085 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7086 Flags.setInAlloca();
7087 // Set the byval flag for CCAssignFn callbacks that don't know about
7088 // inalloca. This way we can know how many bytes we should've allocated
7089 // and how many bytes a callee cleanup function will pop. If we port
7090 // inalloca to more targets, we'll have to add custom inalloca handling
7091 // in the various CC lowering callbacks.
7094 if (Flags.isByVal() || Flags.isInAlloca()) {
7095 PointerType *Ty = cast<PointerType>(I->getType());
7096 Type *ElementTy = Ty->getElementType();
7097 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7098 // For ByVal, alignment should be passed from FE. BE will guess if
7099 // this info is not there but there are cases it cannot get right.
7100 unsigned FrameAlign;
7101 if (F.getParamAlignment(Idx))
7102 FrameAlign = F.getParamAlignment(Idx);
7104 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7105 Flags.setByValAlign(FrameAlign);
7107 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7110 Flags.setInConsecutiveRegs();
7111 Flags.setOrigAlign(OriginalAlignment);
7113 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7114 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7115 for (unsigned i = 0; i != NumRegs; ++i) {
7116 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7117 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7118 if (NumRegs > 1 && i == 0)
7119 MyFlags.Flags.setSplit();
7120 // if it isn't first piece, alignment must be 1
7122 MyFlags.Flags.setOrigAlign(1);
7123 Ins.push_back(MyFlags);
7125 if (NeedsRegBlock && Value == NumValues - 1)
7126 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7127 PartBase += VT.getStoreSize();
7131 // Call the target to set up the argument values.
7132 SmallVector<SDValue, 8> InVals;
7133 SDValue NewRoot = TLI->LowerFormalArguments(
7134 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7136 // Verify that the target's LowerFormalArguments behaved as expected.
7137 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7138 "LowerFormalArguments didn't return a valid chain!");
7139 assert(InVals.size() == Ins.size() &&
7140 "LowerFormalArguments didn't emit the correct number of values!");
7142 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7143 assert(InVals[i].getNode() &&
7144 "LowerFormalArguments emitted a null value!");
7145 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7146 "LowerFormalArguments emitted a value with the wrong type!");
7150 // Update the DAG with the new chain value resulting from argument lowering.
7151 DAG.setRoot(NewRoot);
7153 // Set up the argument values.
7156 if (!FuncInfo->CanLowerReturn) {
7157 // Create a virtual register for the sret pointer, and put in a copy
7158 // from the sret argument into it.
7159 SmallVector<EVT, 1> ValueVTs;
7160 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7161 MVT VT = ValueVTs[0].getSimpleVT();
7162 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7163 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7164 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7165 RegVT, VT, nullptr, AssertOp);
7167 MachineFunction& MF = SDB->DAG.getMachineFunction();
7168 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7169 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7170 FuncInfo->DemoteRegister = SRetReg;
7172 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7173 DAG.setRoot(NewRoot);
7175 // i indexes lowered arguments. Bump it past the hidden sret argument.
7176 // Idx indexes LLVM arguments. Don't touch it.
7180 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7182 SmallVector<SDValue, 4> ArgValues;
7183 SmallVector<EVT, 4> ValueVTs;
7184 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7185 unsigned NumValues = ValueVTs.size();
7187 // If this argument is unused then remember its value. It is used to generate
7188 // debugging information.
7189 if (I->use_empty() && NumValues) {
7190 SDB->setUnusedArgValue(I, InVals[i]);
7192 // Also remember any frame index for use in FastISel.
7193 if (FrameIndexSDNode *FI =
7194 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7195 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7198 for (unsigned Val = 0; Val != NumValues; ++Val) {
7199 EVT VT = ValueVTs[Val];
7200 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7201 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7203 if (!I->use_empty()) {
7204 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7205 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7206 AssertOp = ISD::AssertSext;
7207 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7208 AssertOp = ISD::AssertZext;
7210 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7211 NumParts, PartVT, VT,
7212 nullptr, AssertOp));
7218 // We don't need to do anything else for unused arguments.
7219 if (ArgValues.empty())
7222 // Note down frame index.
7223 if (FrameIndexSDNode *FI =
7224 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7225 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7227 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7228 SDB->getCurSDLoc());
7230 SDB->setValue(I, Res);
7231 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7232 if (LoadSDNode *LNode =
7233 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7234 if (FrameIndexSDNode *FI =
7235 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7236 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7239 // If this argument is live outside of the entry block, insert a copy from
7240 // wherever we got it to the vreg that other BB's will reference it as.
7241 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7242 // If we can, though, try to skip creating an unnecessary vreg.
7243 // FIXME: This isn't very clean... it would be nice to make this more
7244 // general. It's also subtly incompatible with the hacks FastISel
7246 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7247 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7248 FuncInfo->ValueMap[I] = Reg;
7252 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7253 FuncInfo->InitializeRegForValue(I);
7254 SDB->CopyToExportRegsIfNeeded(I);
7258 assert(i == InVals.size() && "Argument register count mismatch!");
7260 // Finally, if the target has anything special to do, allow it to do so.
7261 EmitFunctionEntryCode();
7264 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7265 /// ensure constants are generated when needed. Remember the virtual registers
7266 /// that need to be added to the Machine PHI nodes as input. We cannot just
7267 /// directly add them, because expansion might result in multiple MBB's for one
7268 /// BB. As such, the start of the BB might correspond to a different MBB than
7272 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7273 const TerminatorInst *TI = LLVMBB->getTerminator();
7275 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7277 // Check PHI nodes in successors that expect a value to be available from this
7279 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7280 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7281 if (!isa<PHINode>(SuccBB->begin())) continue;
7282 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7284 // If this terminator has multiple identical successors (common for
7285 // switches), only handle each succ once.
7286 if (!SuccsHandled.insert(SuccMBB).second)
7289 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7291 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7292 // nodes and Machine PHI nodes, but the incoming operands have not been
7294 for (BasicBlock::const_iterator I = SuccBB->begin();
7295 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7296 // Ignore dead phi's.
7297 if (PN->use_empty()) continue;
7300 if (PN->getType()->isEmptyTy())
7304 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7306 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7307 unsigned &RegOut = ConstantsOut[C];
7309 RegOut = FuncInfo.CreateRegs(C->getType());
7310 CopyValueToVirtualRegister(C, RegOut);
7314 DenseMap<const Value *, unsigned>::iterator I =
7315 FuncInfo.ValueMap.find(PHIOp);
7316 if (I != FuncInfo.ValueMap.end())
7319 assert(isa<AllocaInst>(PHIOp) &&
7320 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7321 "Didn't codegen value into a register!??");
7322 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7323 CopyValueToVirtualRegister(PHIOp, Reg);
7327 // Remember that this register needs to added to the machine PHI node as
7328 // the input for this MBB.
7329 SmallVector<EVT, 4> ValueVTs;
7330 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7331 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7332 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7333 EVT VT = ValueVTs[vti];
7334 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7335 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7336 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7337 Reg += NumRegisters;
7342 ConstantsOut.clear();
7345 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7348 SelectionDAGBuilder::StackProtectorDescriptor::
7349 AddSuccessorMBB(const BasicBlock *BB,
7350 MachineBasicBlock *ParentMBB,
7352 MachineBasicBlock *SuccMBB) {
7353 // If SuccBB has not been created yet, create it.
7355 MachineFunction *MF = ParentMBB->getParent();
7356 MachineFunction::iterator BBI = ParentMBB;
7357 SuccMBB = MF->CreateMachineBasicBlock(BB);
7358 MF->insert(++BBI, SuccMBB);
7360 // Add it as a successor of ParentMBB.
7361 ParentMBB->addSuccessor(
7362 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7366 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7367 MachineFunction::iterator I = MBB;
7368 if (++I == FuncInfo.MF->end())
7373 /// During lowering new call nodes can be created (such as memset, etc.).
7374 /// Those will become new roots of the current DAG, but complications arise
7375 /// when they are tail calls. In such cases, the call lowering will update
7376 /// the root, but the builder still needs to know that a tail call has been
7377 /// lowered in order to avoid generating an additional return.
7378 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7379 // If the node is null, we do have a tail call.
7380 if (MaybeTC.getNode() != nullptr)
7381 DAG.setRoot(MaybeTC);
7386 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7387 unsigned *TotalCases, unsigned First,
7389 assert(Last >= First);
7390 assert(TotalCases[Last] >= TotalCases[First]);
7392 APInt LowCase = Clusters[First].Low->getValue();
7393 APInt HighCase = Clusters[Last].High->getValue();
7394 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7396 // FIXME: A range of consecutive cases has 100% density, but only requires one
7397 // comparison to lower. We should discriminate against such consecutive ranges
7400 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7401 uint64_t Range = Diff + 1;
7404 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7406 assert(NumCases < UINT64_MAX / 100);
7407 assert(Range >= NumCases);
7409 return NumCases * 100 >= Range * MinJumpTableDensity;
7412 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7413 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7414 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7417 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7418 unsigned First, unsigned Last,
7419 const SwitchInst *SI,
7420 MachineBasicBlock *DefaultMBB,
7421 CaseCluster &JTCluster) {
7422 assert(First <= Last);
7424 uint32_t Weight = 0;
7425 unsigned NumCmps = 0;
7426 std::vector<MachineBasicBlock*> Table;
7427 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7428 for (unsigned I = First; I <= Last; ++I) {
7429 assert(Clusters[I].Kind == CC_Range);
7430 Weight += Clusters[I].Weight;
7431 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7432 APInt Low = Clusters[I].Low->getValue();
7433 APInt High = Clusters[I].High->getValue();
7434 NumCmps += (Low == High) ? 1 : 2;
7436 // Fill the gap between this and the previous cluster.
7437 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7438 assert(PreviousHigh.slt(Low));
7439 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7440 for (uint64_t J = 0; J < Gap; J++)
7441 Table.push_back(DefaultMBB);
7443 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7444 for (uint64_t J = 0; J < ClusterSize; ++J)
7445 Table.push_back(Clusters[I].MBB);
7446 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7449 unsigned NumDests = JTWeights.size();
7450 if (isSuitableForBitTests(NumDests, NumCmps,
7451 Clusters[First].Low->getValue(),
7452 Clusters[Last].High->getValue())) {
7453 // Clusters[First..Last] should be lowered as bit tests instead.
7457 // Create the MBB that will load from and jump through the table.
7458 // Note: We create it here, but it's not inserted into the function yet.
7459 MachineFunction *CurMF = FuncInfo.MF;
7460 MachineBasicBlock *JumpTableMBB =
7461 CurMF->CreateMachineBasicBlock(SI->getParent());
7463 // Add successors. Note: use table order for determinism.
7464 SmallPtrSet<MachineBasicBlock *, 8> Done;
7465 for (MachineBasicBlock *Succ : Table) {
7466 if (Done.count(Succ))
7468 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7472 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7473 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7474 ->createJumpTableIndex(Table);
7476 // Set up the jump table info.
7477 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7478 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7479 Clusters[Last].High->getValue(), SI->getCondition(),
7481 JTCases.emplace_back(std::move(JTH), std::move(JT));
7483 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7484 JTCases.size() - 1, Weight);
7488 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7489 const SwitchInst *SI,
7490 MachineBasicBlock *DefaultMBB) {
7492 // Clusters must be non-empty, sorted, and only contain Range clusters.
7493 assert(!Clusters.empty());
7494 for (CaseCluster &C : Clusters)
7495 assert(C.Kind == CC_Range);
7496 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7497 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7500 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7501 if (!areJTsAllowed(TLI))
7504 const int64_t N = Clusters.size();
7505 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7507 // Split Clusters into minimum number of dense partitions. The algorithm uses
7508 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7509 // for the Case Statement'" (1994), but builds the MinPartitions array in
7510 // reverse order to make it easier to reconstruct the partitions in ascending
7511 // order. In the choice between two optimal partitionings, it picks the one
7512 // which yields more jump tables.
7514 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7515 SmallVector<unsigned, 8> MinPartitions(N);
7516 // LastElement[i] is the last element of the partition starting at i.
7517 SmallVector<unsigned, 8> LastElement(N);
7518 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7519 SmallVector<unsigned, 8> NumTables(N);
7520 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7521 SmallVector<unsigned, 8> TotalCases(N);
7523 for (unsigned i = 0; i < N; ++i) {
7524 APInt Hi = Clusters[i].High->getValue();
7525 APInt Lo = Clusters[i].Low->getValue();
7526 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7528 TotalCases[i] += TotalCases[i - 1];
7531 // Base case: There is only one way to partition Clusters[N-1].
7532 MinPartitions[N - 1] = 1;
7533 LastElement[N - 1] = N - 1;
7534 assert(MinJumpTableSize > 1);
7535 NumTables[N - 1] = 0;
7537 // Note: loop indexes are signed to avoid underflow.
7538 for (int64_t i = N - 2; i >= 0; i--) {
7539 // Find optimal partitioning of Clusters[i..N-1].
7540 // Baseline: Put Clusters[i] into a partition on its own.
7541 MinPartitions[i] = MinPartitions[i + 1] + 1;
7543 NumTables[i] = NumTables[i + 1];
7545 // Search for a solution that results in fewer partitions.
7546 for (int64_t j = N - 1; j > i; j--) {
7547 // Try building a partition from Clusters[i..j].
7548 if (isDense(Clusters, &TotalCases[0], i, j)) {
7549 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7550 bool IsTable = j - i + 1 >= MinJumpTableSize;
7551 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7553 // If this j leads to fewer partitions, or same number of partitions
7554 // with more lookup tables, it is a better partitioning.
7555 if (NumPartitions < MinPartitions[i] ||
7556 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7557 MinPartitions[i] = NumPartitions;
7559 NumTables[i] = Tables;
7565 // Iterate over the partitions, replacing some with jump tables in-place.
7566 unsigned DstIndex = 0;
7567 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7568 Last = LastElement[First];
7569 assert(Last >= First);
7570 assert(DstIndex <= First);
7571 unsigned NumClusters = Last - First + 1;
7573 CaseCluster JTCluster;
7574 if (NumClusters >= MinJumpTableSize &&
7575 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7576 Clusters[DstIndex++] = JTCluster;
7578 for (unsigned I = First; I <= Last; ++I)
7579 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7582 Clusters.resize(DstIndex);
7585 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7586 // FIXME: Using the pointer type doesn't seem ideal.
7587 uint64_t BW = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7588 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7592 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7595 const APInt &High) {
7596 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7597 // range of cases both require only one branch to lower. Just looking at the
7598 // number of clusters and destinations should be enough to decide whether to
7601 // To lower a range with bit tests, the range must fit the bitwidth of a
7603 if (!rangeFitsInWord(Low, High))
7606 // Decide whether it's profitable to lower this range with bit tests. Each
7607 // destination requires a bit test and branch, and there is an overall range
7608 // check branch. For a small number of clusters, separate comparisons might be
7609 // cheaper, and for many destinations, splitting the range might be better.
7610 return (NumDests == 1 && NumCmps >= 3) ||
7611 (NumDests == 2 && NumCmps >= 5) ||
7612 (NumDests == 3 && NumCmps >= 6);
7615 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7616 unsigned First, unsigned Last,
7617 const SwitchInst *SI,
7618 CaseCluster &BTCluster) {
7619 assert(First <= Last);
7623 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7624 unsigned NumCmps = 0;
7625 for (int64_t I = First; I <= Last; ++I) {
7626 assert(Clusters[I].Kind == CC_Range);
7627 Dests.set(Clusters[I].MBB->getNumber());
7628 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7630 unsigned NumDests = Dests.count();
7632 APInt Low = Clusters[First].Low->getValue();
7633 APInt High = Clusters[Last].High->getValue();
7634 assert(Low.slt(High));
7636 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7642 const int BitWidth =
7643 DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7644 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7646 if (Low.isNonNegative() && High.slt(BitWidth)) {
7647 // Optimize the case where all the case values fit in a
7648 // word without having to subtract minValue. In this case,
7649 // we can optimize away the subtraction.
7650 LowBound = APInt::getNullValue(Low.getBitWidth());
7654 CmpRange = High - Low;
7658 uint32_t TotalWeight = 0;
7659 for (unsigned i = First; i <= Last; ++i) {
7660 // Find the CaseBits for this destination.
7662 for (j = 0; j < CBV.size(); ++j)
7663 if (CBV[j].BB == Clusters[i].MBB)
7665 if (j == CBV.size())
7666 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7667 CaseBits *CB = &CBV[j];
7669 // Update Mask, Bits and ExtraWeight.
7670 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7671 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7672 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7673 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7674 CB->Bits += Hi - Lo + 1;
7675 CB->ExtraWeight += Clusters[i].Weight;
7676 TotalWeight += Clusters[i].Weight;
7677 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7681 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7682 // Sort by weight first, number of bits second.
7683 if (a.ExtraWeight != b.ExtraWeight)
7684 return a.ExtraWeight > b.ExtraWeight;
7685 return a.Bits > b.Bits;
7688 for (auto &CB : CBV) {
7689 MachineBasicBlock *BitTestBB =
7690 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7691 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7693 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7694 SI->getCondition(), -1U, MVT::Other, false, nullptr,
7695 nullptr, std::move(BTI));
7697 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7698 BitTestCases.size() - 1, TotalWeight);
7702 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7703 const SwitchInst *SI) {
7704 // Partition Clusters into as few subsets as possible, where each subset has a
7705 // range that fits in a machine word and has <= 3 unique destinations.
7708 // Clusters must be sorted and contain Range or JumpTable clusters.
7709 assert(!Clusters.empty());
7710 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7711 for (const CaseCluster &C : Clusters)
7712 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7713 for (unsigned i = 1; i < Clusters.size(); ++i)
7714 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7717 // If target does not have legal shift left, do not emit bit tests at all.
7718 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7719 EVT PTy = TLI.getPointerTy();
7720 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7723 int BitWidth = PTy.getSizeInBits();
7724 const int64_t N = Clusters.size();
7726 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7727 SmallVector<unsigned, 8> MinPartitions(N);
7728 // LastElement[i] is the last element of the partition starting at i.
7729 SmallVector<unsigned, 8> LastElement(N);
7731 // FIXME: This might not be the best algorithm for finding bit test clusters.
7733 // Base case: There is only one way to partition Clusters[N-1].
7734 MinPartitions[N - 1] = 1;
7735 LastElement[N - 1] = N - 1;
7737 // Note: loop indexes are signed to avoid underflow.
7738 for (int64_t i = N - 2; i >= 0; --i) {
7739 // Find optimal partitioning of Clusters[i..N-1].
7740 // Baseline: Put Clusters[i] into a partition on its own.
7741 MinPartitions[i] = MinPartitions[i + 1] + 1;
7744 // Search for a solution that results in fewer partitions.
7745 // Note: the search is limited by BitWidth, reducing time complexity.
7746 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7747 // Try building a partition from Clusters[i..j].
7750 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7751 Clusters[j].High->getValue()))
7754 // Check nbr of destinations and cluster types.
7755 // FIXME: This works, but doesn't seem very efficient.
7756 bool RangesOnly = true;
7757 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7758 for (int64_t k = i; k <= j; k++) {
7759 if (Clusters[k].Kind != CC_Range) {
7763 Dests.set(Clusters[k].MBB->getNumber());
7765 if (!RangesOnly || Dests.count() > 3)
7768 // Check if it's a better partition.
7769 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7770 if (NumPartitions < MinPartitions[i]) {
7771 // Found a better partition.
7772 MinPartitions[i] = NumPartitions;
7778 // Iterate over the partitions, replacing with bit-test clusters in-place.
7779 unsigned DstIndex = 0;
7780 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7781 Last = LastElement[First];
7782 assert(First <= Last);
7783 assert(DstIndex <= First);
7785 CaseCluster BitTestCluster;
7786 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7787 Clusters[DstIndex++] = BitTestCluster;
7789 size_t NumClusters = Last - First + 1;
7790 std::memmove(&Clusters[DstIndex], &Clusters[First],
7791 sizeof(Clusters[0]) * NumClusters);
7792 DstIndex += NumClusters;
7795 Clusters.resize(DstIndex);
7798 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7799 MachineBasicBlock *SwitchMBB,
7800 MachineBasicBlock *DefaultMBB) {
7801 MachineFunction *CurMF = FuncInfo.MF;
7802 MachineBasicBlock *NextMBB = nullptr;
7803 MachineFunction::iterator BBI = W.MBB;
7804 if (++BBI != FuncInfo.MF->end())
7807 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7809 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7811 if (Size == 2 && W.MBB == SwitchMBB) {
7812 // If any two of the cases has the same destination, and if one value
7813 // is the same as the other, but has one bit unset that the other has set,
7814 // use bit manipulation to do two compares at once. For example:
7815 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7816 // TODO: This could be extended to merge any 2 cases in switches with 3
7818 // TODO: Handle cases where W.CaseBB != SwitchBB.
7819 CaseCluster &Small = *W.FirstCluster;
7820 CaseCluster &Big = *W.LastCluster;
7822 if (Small.Low == Small.High && Big.Low == Big.High &&
7823 Small.MBB == Big.MBB) {
7824 const APInt &SmallValue = Small.Low->getValue();
7825 const APInt &BigValue = Big.Low->getValue();
7827 // Check that there is only one bit different.
7828 APInt CommonBit = BigValue ^ SmallValue;
7829 if (CommonBit.isPowerOf2()) {
7830 SDValue CondLHS = getValue(Cond);
7831 EVT VT = CondLHS.getValueType();
7832 SDLoc DL = getCurSDLoc();
7834 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7835 DAG.getConstant(CommonBit, DL, VT));
7836 SDValue Cond = DAG.getSetCC(
7837 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7840 // Update successor info.
7841 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7842 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7843 addSuccessorWithWeight(
7844 SwitchMBB, DefaultMBB,
7845 // The default destination is the first successor in IR.
7846 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7849 // Insert the true branch.
7851 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7852 DAG.getBasicBlock(Small.MBB));
7853 // Insert the false branch.
7854 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7855 DAG.getBasicBlock(DefaultMBB));
7857 DAG.setRoot(BrCond);
7863 if (TM.getOptLevel() != CodeGenOpt::None) {
7864 // Order cases by weight so the most likely case will be checked first.
7865 std::sort(W.FirstCluster, W.LastCluster + 1,
7866 [](const CaseCluster &a, const CaseCluster &b) {
7867 return a.Weight > b.Weight;
7870 // Rearrange the case blocks so that the last one falls through if possible
7871 // without without changing the order of weights.
7872 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7874 if (I->Weight > W.LastCluster->Weight)
7876 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7877 std::swap(*I, *W.LastCluster);
7883 // Compute total weight.
7884 uint32_t UnhandledWeights = 0;
7885 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7886 UnhandledWeights += I->Weight;
7887 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7890 MachineBasicBlock *CurMBB = W.MBB;
7891 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7892 MachineBasicBlock *Fallthrough;
7893 if (I == W.LastCluster) {
7894 // For the last cluster, fall through to the default destination.
7895 Fallthrough = DefaultMBB;
7897 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7898 CurMF->insert(BBI, Fallthrough);
7899 // Put Cond in a virtual register to make it available from the new blocks.
7900 ExportFromCurrentBlock(Cond);
7904 case CC_JumpTable: {
7905 // FIXME: Optimize away range check based on pivot comparisons.
7906 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7907 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7909 // The jump block hasn't been inserted yet; insert it here.
7910 MachineBasicBlock *JumpMBB = JT->MBB;
7911 CurMF->insert(BBI, JumpMBB);
7912 addSuccessorWithWeight(CurMBB, Fallthrough);
7913 addSuccessorWithWeight(CurMBB, JumpMBB);
7915 // The jump table header will be inserted in our current block, do the
7916 // range check, and fall through to our fallthrough block.
7917 JTH->HeaderBB = CurMBB;
7918 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7920 // If we're in the right place, emit the jump table header right now.
7921 if (CurMBB == SwitchMBB) {
7922 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7923 JTH->Emitted = true;
7928 // FIXME: Optimize away range check based on pivot comparisons.
7929 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7931 // The bit test blocks haven't been inserted yet; insert them here.
7932 for (BitTestCase &BTC : BTB->Cases)
7933 CurMF->insert(BBI, BTC.ThisBB);
7935 // Fill in fields of the BitTestBlock.
7936 BTB->Parent = CurMBB;
7937 BTB->Default = Fallthrough;
7939 // If we're in the right place, emit the bit test header header right now.
7940 if (CurMBB ==SwitchMBB) {
7941 visitBitTestHeader(*BTB, SwitchMBB);
7942 BTB->Emitted = true;
7947 const Value *RHS, *LHS, *MHS;
7949 if (I->Low == I->High) {
7950 // Check Cond == I->Low.
7956 // Check I->Low <= Cond <= I->High.
7963 // The false weight is the sum of all unhandled cases.
7964 UnhandledWeights -= I->Weight;
7965 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
7968 if (CurMBB == SwitchMBB)
7969 visitSwitchCase(CB, SwitchMBB);
7971 SwitchCases.push_back(CB);
7976 CurMBB = Fallthrough;
7980 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
7981 const SwitchWorkListItem &W,
7983 MachineBasicBlock *SwitchMBB) {
7984 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
7985 "Clusters not sorted?");
7987 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
7989 // Balance the tree based on branch weights to create a near-optimal (in terms
7990 // of search time given key frequency) binary search tree. See e.g. Kurt
7991 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
7992 CaseClusterIt LastLeft = W.FirstCluster;
7993 CaseClusterIt FirstRight = W.LastCluster;
7994 uint32_t LeftWeight = LastLeft->Weight;
7995 uint32_t RightWeight = FirstRight->Weight;
7997 // Move LastLeft and FirstRight towards each other from opposite directions to
7998 // find a partitioning of the clusters which balances the weight on both
7999 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8000 // taken to ensure 0-weight nodes are distributed evenly.
8002 while (LastLeft + 1 < FirstRight) {
8003 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8004 LeftWeight += (++LastLeft)->Weight;
8006 RightWeight += (--FirstRight)->Weight;
8009 assert(LastLeft + 1 == FirstRight);
8010 assert(LastLeft >= W.FirstCluster);
8011 assert(FirstRight <= W.LastCluster);
8013 // Use the first element on the right as pivot since we will make less-than
8014 // comparisons against it.
8015 CaseClusterIt PivotCluster = FirstRight;
8016 assert(PivotCluster > W.FirstCluster);
8017 assert(PivotCluster <= W.LastCluster);
8019 CaseClusterIt FirstLeft = W.FirstCluster;
8020 CaseClusterIt LastRight = W.LastCluster;
8022 const ConstantInt *Pivot = PivotCluster->Low;
8024 // New blocks will be inserted immediately after the current one.
8025 MachineFunction::iterator BBI = W.MBB;
8028 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8029 // we can branch to its destination directly if it's squeezed exactly in
8030 // between the known lower bound and Pivot - 1.
8031 MachineBasicBlock *LeftMBB;
8032 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8033 FirstLeft->Low == W.GE &&
8034 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8035 LeftMBB = FirstLeft->MBB;
8037 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8038 FuncInfo.MF->insert(BBI, LeftMBB);
8039 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8040 // Put Cond in a virtual register to make it available from the new blocks.
8041 ExportFromCurrentBlock(Cond);
8044 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8045 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8046 // directly if RHS.High equals the current upper bound.
8047 MachineBasicBlock *RightMBB;
8048 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8049 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8050 RightMBB = FirstRight->MBB;
8052 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8053 FuncInfo.MF->insert(BBI, RightMBB);
8054 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8055 // Put Cond in a virtual register to make it available from the new blocks.
8056 ExportFromCurrentBlock(Cond);
8059 // Create the CaseBlock record that will be used to lower the branch.
8060 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8061 LeftWeight, RightWeight);
8063 if (W.MBB == SwitchMBB)
8064 visitSwitchCase(CB, SwitchMBB);
8066 SwitchCases.push_back(CB);
8069 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8070 // Extract cases from the switch.
8071 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8072 CaseClusterVector Clusters;
8073 Clusters.reserve(SI.getNumCases());
8074 for (auto I : SI.cases()) {
8075 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8076 const ConstantInt *CaseVal = I.getCaseValue();
8078 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8079 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8082 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8084 // Cluster adjacent cases with the same destination. We do this at all
8085 // optimization levels because it's cheap to do and will make codegen faster
8086 // if there are many clusters.
8087 sortAndRangeify(Clusters);
8089 if (TM.getOptLevel() != CodeGenOpt::None) {
8090 // Replace an unreachable default with the most popular destination.
8091 // FIXME: Exploit unreachable default more aggressively.
8092 bool UnreachableDefault =
8093 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8094 if (UnreachableDefault && !Clusters.empty()) {
8095 DenseMap<const BasicBlock *, unsigned> Popularity;
8096 unsigned MaxPop = 0;
8097 const BasicBlock *MaxBB = nullptr;
8098 for (auto I : SI.cases()) {
8099 const BasicBlock *BB = I.getCaseSuccessor();
8100 if (++Popularity[BB] > MaxPop) {
8101 MaxPop = Popularity[BB];
8106 assert(MaxPop > 0 && MaxBB);
8107 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8109 // Remove cases that were pointing to the destination that is now the
8111 CaseClusterVector New;
8112 New.reserve(Clusters.size());
8113 for (CaseCluster &CC : Clusters) {
8114 if (CC.MBB != DefaultMBB)
8117 Clusters = std::move(New);
8121 // If there is only the default destination, jump there directly.
8122 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8123 if (Clusters.empty()) {
8124 SwitchMBB->addSuccessor(DefaultMBB);
8125 if (DefaultMBB != NextBlock(SwitchMBB)) {
8126 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8127 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8132 if (TM.getOptLevel() != CodeGenOpt::None) {
8133 findJumpTables(Clusters, &SI, DefaultMBB);
8134 findBitTestClusters(Clusters, &SI);
8139 dbgs() << "Case clusters: ";
8140 for (const CaseCluster &C : Clusters) {
8141 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8142 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8144 C.Low->getValue().print(dbgs(), true);
8145 if (C.Low != C.High) {
8147 C.High->getValue().print(dbgs(), true);
8154 assert(!Clusters.empty());
8155 SwitchWorkList WorkList;
8156 CaseClusterIt First = Clusters.begin();
8157 CaseClusterIt Last = Clusters.end() - 1;
8158 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8160 while (!WorkList.empty()) {
8161 SwitchWorkListItem W = WorkList.back();
8162 WorkList.pop_back();
8163 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8165 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8166 // For optimized builds, lower large range as a balanced binary tree.
8167 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8171 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);