1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
82 // Limit the width of DAG chains. This is important in general to prevent
83 // prevent DAG-based analysis from blowing up. For example, alias analysis and
84 // load clustering may not complete in reasonable time. It is difficult to
85 // recognize and avoid this situation within each individual analysis, and
86 // future analyses are likely to have the same behavior. Limiting DAG width is
87 // the safe approach, and will be especially important with global DAGs.
89 // MaxParallelChains default is arbitrarily high to avoid affecting
90 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
91 // sequence over this should have been converted to llvm.memcpy by the
92 // frontend. It easy to induce this behavior with .ll code such as:
93 // %buffer = alloca [4096 x i8]
94 // %data = load [4096 x i8]* %argPtr
95 // store [4096 x i8] %data, [4096 x i8]* %buffer
96 static const unsigned MaxParallelChains = 64;
98 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
99 const SDValue *Parts, unsigned NumParts,
100 MVT PartVT, EVT ValueVT, const Value *V);
102 /// getCopyFromParts - Create a value that contains the specified legal parts
103 /// combined into the value they represent. If the parts combine to a type
104 /// larger then ValueVT then AssertOp can be used to specify whether the extra
105 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
106 /// (ISD::AssertSext).
107 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
108 const SDValue *Parts,
109 unsigned NumParts, MVT PartVT, EVT ValueVT,
111 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
112 if (ValueVT.isVector())
113 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
116 assert(NumParts > 0 && "No parts to assemble!");
117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
118 SDValue Val = Parts[0];
121 // Assemble the value from multiple parts.
122 if (ValueVT.isInteger()) {
123 unsigned PartBits = PartVT.getSizeInBits();
124 unsigned ValueBits = ValueVT.getSizeInBits();
126 // Assemble the power of 2 part.
127 unsigned RoundParts = NumParts & (NumParts - 1) ?
128 1 << Log2_32(NumParts) : NumParts;
129 unsigned RoundBits = PartBits * RoundParts;
130 EVT RoundVT = RoundBits == ValueBits ?
131 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
134 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
136 if (RoundParts > 2) {
137 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
139 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
140 RoundParts / 2, PartVT, HalfVT, V);
142 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
143 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
146 if (TLI.isBigEndian())
149 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
151 if (RoundParts < NumParts) {
152 // Assemble the trailing non-power-of-2 part.
153 unsigned OddParts = NumParts - RoundParts;
154 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
155 Hi = getCopyFromParts(DAG, DL,
156 Parts + RoundParts, OddParts, PartVT, OddVT, V);
158 // Combine the round and odd parts.
160 if (TLI.isBigEndian())
162 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
163 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
164 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
165 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
166 TLI.getPointerTy()));
167 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
168 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
170 } else if (PartVT.isFloatingPoint()) {
171 // FP split into multiple FP parts (for ppcf128)
172 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
175 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
176 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
177 if (TLI.hasBigEndianPartOrdering(ValueVT))
179 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
181 // FP split into integer parts (soft fp)
182 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
183 !PartVT.isVector() && "Unexpected split");
184 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
185 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
189 // There is now one part, held in Val. Correct it to match ValueVT.
190 EVT PartEVT = Val.getValueType();
192 if (PartEVT == ValueVT)
195 if (PartEVT.isInteger() && ValueVT.isInteger()) {
196 if (ValueVT.bitsLT(PartEVT)) {
197 // For a truncate, see if we have any information to
198 // indicate whether the truncated bits will always be
199 // zero or sign-extension.
200 if (AssertOp != ISD::DELETED_NODE)
201 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
202 DAG.getValueType(ValueVT));
203 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
205 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
208 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
209 // FP_ROUND's are always exact here.
210 if (ValueVT.bitsLT(Val.getValueType()))
211 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
212 DAG.getTargetConstant(1, DL, TLI.getPointerTy()));
214 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
217 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
218 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
220 llvm_unreachable("Unknown mismatch!");
223 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
224 const Twine &ErrMsg) {
225 const Instruction *I = dyn_cast_or_null<Instruction>(V);
227 return Ctx.emitError(ErrMsg);
229 const char *AsmError = ", possible invalid constraint for vector type";
230 if (const CallInst *CI = dyn_cast<CallInst>(I))
231 if (isa<InlineAsm>(CI->getCalledValue()))
232 return Ctx.emitError(I, ErrMsg + AsmError);
234 return Ctx.emitError(I, ErrMsg);
237 /// getCopyFromPartsVector - Create a value that contains the specified legal
238 /// parts combined into the value they represent. If the parts combine to a
239 /// type larger then ValueVT then AssertOp can be used to specify whether the
240 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
241 /// ValueVT (ISD::AssertSext).
242 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
243 const SDValue *Parts, unsigned NumParts,
244 MVT PartVT, EVT ValueVT, const Value *V) {
245 assert(ValueVT.isVector() && "Not a vector value");
246 assert(NumParts > 0 && "No parts to assemble!");
247 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
248 SDValue Val = Parts[0];
250 // Handle a multi-element vector.
254 unsigned NumIntermediates;
256 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
257 NumIntermediates, RegisterVT);
258 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
259 NumParts = NumRegs; // Silence a compiler warning.
260 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
261 assert(RegisterVT == Parts[0].getSimpleValueType() &&
262 "Part type doesn't match part!");
264 // Assemble the parts into intermediate operands.
265 SmallVector<SDValue, 8> Ops(NumIntermediates);
266 if (NumIntermediates == NumParts) {
267 // If the register was not expanded, truncate or copy the value,
269 for (unsigned i = 0; i != NumParts; ++i)
270 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
271 PartVT, IntermediateVT, V);
272 } else if (NumParts > 0) {
273 // If the intermediate type was expanded, build the intermediate
274 // operands from the parts.
275 assert(NumParts % NumIntermediates == 0 &&
276 "Must expand into a divisible number of parts!");
277 unsigned Factor = NumParts / NumIntermediates;
278 for (unsigned i = 0; i != NumIntermediates; ++i)
279 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
280 PartVT, IntermediateVT, V);
283 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
284 // intermediate operands.
285 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
290 // There is now one part, held in Val. Correct it to match ValueVT.
291 EVT PartEVT = Val.getValueType();
293 if (PartEVT == ValueVT)
296 if (PartEVT.isVector()) {
297 // If the element type of the source/dest vectors are the same, but the
298 // parts vector has more elements than the value vector, then we have a
299 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
301 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
302 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
303 "Cannot narrow, it would be a lossy transformation");
304 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
305 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
308 // Vector/Vector bitcast.
309 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
310 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
312 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
313 "Cannot handle this kind of promotion");
314 // Promoted vector extract
315 bool Smaller = ValueVT.bitsLE(PartEVT);
316 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
321 // Trivial bitcast if the types are the same size and the destination
322 // vector type is legal.
323 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
324 TLI.isTypeLegal(ValueVT))
325 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
327 // Handle cases such as i8 -> <1 x i1>
328 if (ValueVT.getVectorNumElements() != 1) {
329 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
330 "non-trivial scalar-to-vector conversion");
331 return DAG.getUNDEF(ValueVT);
334 if (ValueVT.getVectorNumElements() == 1 &&
335 ValueVT.getVectorElementType() != PartEVT) {
336 bool Smaller = ValueVT.bitsLE(PartEVT);
337 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
338 DL, ValueVT.getScalarType(), Val);
341 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
344 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
345 SDValue Val, SDValue *Parts, unsigned NumParts,
346 MVT PartVT, const Value *V);
348 /// getCopyToParts - Create a series of nodes that contain the specified value
349 /// split into legal parts. If the parts contain more bits than Val, then, for
350 /// integers, ExtendKind can be used to specify how to generate the extra bits.
351 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
352 SDValue Val, SDValue *Parts, unsigned NumParts,
353 MVT PartVT, const Value *V,
354 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
355 EVT ValueVT = Val.getValueType();
357 // Handle the vector case separately.
358 if (ValueVT.isVector())
359 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
362 unsigned PartBits = PartVT.getSizeInBits();
363 unsigned OrigNumParts = NumParts;
364 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
369 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
370 EVT PartEVT = PartVT;
371 if (PartEVT == ValueVT) {
372 assert(NumParts == 1 && "No-op copy with multiple parts!");
377 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
378 // If the parts cover more bits than the value has, promote the value.
379 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
380 assert(NumParts == 1 && "Do not know what to promote to!");
381 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
384 ValueVT.isInteger() &&
385 "Unknown mismatch!");
386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
387 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
388 if (PartVT == MVT::x86mmx)
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (PartBits == ValueVT.getSizeInBits()) {
392 // Different types of the same size.
393 assert(NumParts == 1 && PartEVT != ValueVT);
394 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
395 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
396 // If the parts cover less bits than value has, truncate the value.
397 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
398 ValueVT.isInteger() &&
399 "Unknown mismatch!");
400 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
401 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
402 if (PartVT == MVT::x86mmx)
403 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
406 // The value may have changed - recompute ValueVT.
407 ValueVT = Val.getValueType();
408 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
409 "Failed to tile the value with PartVT!");
412 if (PartEVT != ValueVT)
413 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
414 "scalar-to-vector conversion failed");
420 // Expand the value into multiple parts.
421 if (NumParts & (NumParts - 1)) {
422 // The number of parts is not a power of 2. Split off and copy the tail.
423 assert(PartVT.isInteger() && ValueVT.isInteger() &&
424 "Do not know what to expand to!");
425 unsigned RoundParts = 1 << Log2_32(NumParts);
426 unsigned RoundBits = RoundParts * PartBits;
427 unsigned OddParts = NumParts - RoundParts;
428 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
429 DAG.getIntPtrConstant(RoundBits, DL));
430 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
432 if (TLI.isBigEndian())
433 // The odd parts were reversed by getCopyToParts - unreverse them.
434 std::reverse(Parts + RoundParts, Parts + NumParts);
436 NumParts = RoundParts;
437 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
438 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
441 // The number of parts is a power of 2. Repeatedly bisect the value using
443 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
444 EVT::getIntegerVT(*DAG.getContext(),
445 ValueVT.getSizeInBits()),
448 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
449 for (unsigned i = 0; i < NumParts; i += StepSize) {
450 unsigned ThisBits = StepSize * PartBits / 2;
451 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
452 SDValue &Part0 = Parts[i];
453 SDValue &Part1 = Parts[i+StepSize/2];
455 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
456 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
457 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
458 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
460 if (ThisBits == PartBits && ThisVT != PartVT) {
461 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
462 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
467 if (TLI.isBigEndian())
468 std::reverse(Parts, Parts + OrigNumParts);
472 /// getCopyToPartsVector - Create a series of nodes that contain the specified
473 /// value split into legal parts.
474 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
475 SDValue Val, SDValue *Parts, unsigned NumParts,
476 MVT PartVT, const Value *V) {
477 EVT ValueVT = Val.getValueType();
478 assert(ValueVT.isVector() && "Not a vector");
479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
482 EVT PartEVT = PartVT;
483 if (PartEVT == ValueVT) {
485 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
486 // Bitconvert vector->vector case.
487 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
488 } else if (PartVT.isVector() &&
489 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
490 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
491 EVT ElementVT = PartVT.getVectorElementType();
492 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
494 SmallVector<SDValue, 16> Ops;
495 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
497 ElementVT, Val, DAG.getConstant(i, DL,
498 TLI.getVectorIdxTy())));
500 for (unsigned i = ValueVT.getVectorNumElements(),
501 e = PartVT.getVectorNumElements(); i != e; ++i)
502 Ops.push_back(DAG.getUNDEF(ElementVT));
504 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
506 // FIXME: Use CONCAT for 2x -> 4x.
508 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
509 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
510 } else if (PartVT.isVector() &&
511 PartEVT.getVectorElementType().bitsGE(
512 ValueVT.getVectorElementType()) &&
513 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
515 // Promoted vector extract
516 bool Smaller = PartEVT.bitsLE(ValueVT);
517 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
520 // Vector -> scalar conversion.
521 assert(ValueVT.getVectorNumElements() == 1 &&
522 "Only trivial vector-to-scalar conversions should get here!");
523 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
525 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
527 bool Smaller = ValueVT.bitsLE(PartVT);
528 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
536 // Handle a multi-element vector.
539 unsigned NumIntermediates;
540 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
542 NumIntermediates, RegisterVT);
543 unsigned NumElements = ValueVT.getVectorNumElements();
545 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
546 NumParts = NumRegs; // Silence a compiler warning.
547 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
549 // Split the vector into intermediate operands.
550 SmallVector<SDValue, 8> Ops(NumIntermediates);
551 for (unsigned i = 0; i != NumIntermediates; ++i) {
552 if (IntermediateVT.isVector())
553 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
555 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
556 TLI.getVectorIdxTy()));
558 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
560 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
563 // Split the intermediate operands into legal parts.
564 if (NumParts == NumIntermediates) {
565 // If the register was not expanded, promote or copy the value,
567 for (unsigned i = 0; i != NumParts; ++i)
568 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
569 } else if (NumParts > 0) {
570 // If the intermediate type was expanded, split each the value into
572 assert(NumIntermediates != 0 && "division by zero");
573 assert(NumParts % NumIntermediates == 0 &&
574 "Must expand into a divisible number of parts!");
575 unsigned Factor = NumParts / NumIntermediates;
576 for (unsigned i = 0; i != NumIntermediates; ++i)
577 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
582 /// RegsForValue - This struct represents the registers (physical or virtual)
583 /// that a particular set of values is assigned, and the type information
584 /// about the value. The most common situation is to represent one value at a
585 /// time, but struct or array values are handled element-wise as multiple
586 /// values. The splitting of aggregates is performed recursively, so that we
587 /// never have aggregate-typed registers. The values at this point do not
588 /// necessarily have legal types, so each value may require one or more
589 /// registers of some legal type.
591 struct RegsForValue {
592 /// ValueVTs - The value types of the values, which may not be legal, and
593 /// may need be promoted or synthesized from one or more registers.
595 SmallVector<EVT, 4> ValueVTs;
597 /// RegVTs - The value types of the registers. This is the same size as
598 /// ValueVTs and it records, for each value, what the type of the assigned
599 /// register or registers are. (Individual values are never synthesized
600 /// from more than one type of register.)
602 /// With virtual registers, the contents of RegVTs is redundant with TLI's
603 /// getRegisterType member function, however when with physical registers
604 /// it is necessary to have a separate record of the types.
606 SmallVector<MVT, 4> RegVTs;
608 /// Regs - This list holds the registers assigned to the values.
609 /// Each legal or promoted value requires one register, and each
610 /// expanded value requires multiple registers.
612 SmallVector<unsigned, 4> Regs;
616 RegsForValue(const SmallVector<unsigned, 4> ®s,
617 MVT regvt, EVT valuevt)
618 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
620 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
621 unsigned Reg, Type *Ty) {
622 ComputeValueVTs(tli, Ty, ValueVTs);
624 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
625 EVT ValueVT = ValueVTs[Value];
626 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
627 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
628 for (unsigned i = 0; i != NumRegs; ++i)
629 Regs.push_back(Reg + i);
630 RegVTs.push_back(RegisterVT);
635 /// append - Add the specified values to this one.
636 void append(const RegsForValue &RHS) {
637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
639 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
643 /// this value and returns the result as a ValueVTs value. This uses
644 /// Chain/Flag as the input and updates them for the output Chain/Flag.
645 /// If the Flag pointer is NULL, no flag is used.
646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
648 SDValue &Chain, SDValue *Flag,
649 const Value *V = nullptr) const;
651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
652 /// specified value into the registers specified by this object. This uses
653 /// Chain/Flag as the input and updates them for the output Chain/Flag.
654 /// If the Flag pointer is NULL, no flag is used.
656 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
657 SDValue *Flag, const Value *V,
658 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
660 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
661 /// operand list. This adds the code marker, matching input operand index
662 /// (if applicable), and includes the number of values added into it.
663 void AddInlineAsmOperands(unsigned Kind,
664 bool HasMatching, unsigned MatchingIdx, SDLoc dl,
666 std::vector<SDValue> &Ops) const;
670 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
671 /// this value and returns the result as a ValueVT value. This uses
672 /// Chain/Flag as the input and updates them for the output Chain/Flag.
673 /// If the Flag pointer is NULL, no flag is used.
674 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
675 FunctionLoweringInfo &FuncInfo,
677 SDValue &Chain, SDValue *Flag,
678 const Value *V) const {
679 // A Value with type {} or [0 x %t] needs no registers.
680 if (ValueVTs.empty())
683 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
685 // Assemble the legal parts into the final values.
686 SmallVector<SDValue, 4> Values(ValueVTs.size());
687 SmallVector<SDValue, 8> Parts;
688 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
689 // Copy the legal parts from the registers.
690 EVT ValueVT = ValueVTs[Value];
691 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
692 MVT RegisterVT = RegVTs[Value];
694 Parts.resize(NumRegs);
695 for (unsigned i = 0; i != NumRegs; ++i) {
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
700 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
701 *Flag = P.getValue(2);
704 Chain = P.getValue(1);
707 // If the source register was virtual and if we know something about it,
708 // add an assert node.
709 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
710 !RegisterVT.isInteger() || RegisterVT.isVector())
713 const FunctionLoweringInfo::LiveOutInfo *LOI =
714 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
718 unsigned RegSize = RegisterVT.getSizeInBits();
719 unsigned NumSignBits = LOI->NumSignBits;
720 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
722 if (NumZeroBits == RegSize) {
723 // The current value is a zero.
724 // Explicitly express that as it would be easier for
725 // optimizations to kick in.
726 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
730 // FIXME: We capture more information than the dag can represent. For
731 // now, just use the tightest assertzext/assertsext possible.
733 EVT FromVT(MVT::Other);
734 if (NumSignBits == RegSize)
735 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
736 else if (NumZeroBits >= RegSize-1)
737 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
738 else if (NumSignBits > RegSize-8)
739 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
740 else if (NumZeroBits >= RegSize-8)
741 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
742 else if (NumSignBits > RegSize-16)
743 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
744 else if (NumZeroBits >= RegSize-16)
745 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
746 else if (NumSignBits > RegSize-32)
747 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
748 else if (NumZeroBits >= RegSize-32)
749 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
753 // Add an assertion node.
754 assert(FromVT != MVT::Other);
755 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
756 RegisterVT, P, DAG.getValueType(FromVT));
759 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
760 NumRegs, RegisterVT, ValueVT, V);
765 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
768 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
769 /// specified value into the registers specified by this object. This uses
770 /// Chain/Flag as the input and updates them for the output Chain/Flag.
771 /// If the Flag pointer is NULL, no flag is used.
772 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
773 SDValue &Chain, SDValue *Flag, const Value *V,
774 ISD::NodeType PreferredExtendType) const {
775 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
776 ISD::NodeType ExtendKind = PreferredExtendType;
778 // Get the list of the values's legal parts.
779 unsigned NumRegs = Regs.size();
780 SmallVector<SDValue, 8> Parts(NumRegs);
781 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
782 EVT ValueVT = ValueVTs[Value];
783 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
784 MVT RegisterVT = RegVTs[Value];
786 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
787 ExtendKind = ISD::ZERO_EXTEND;
789 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
790 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
794 // Copy the parts into the registers.
795 SmallVector<SDValue, 8> Chains(NumRegs);
796 for (unsigned i = 0; i != NumRegs; ++i) {
799 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
801 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
802 *Flag = Part.getValue(1);
805 Chains[i] = Part.getValue(0);
808 if (NumRegs == 1 || Flag)
809 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
810 // flagged to it. That is the CopyToReg nodes and the user are considered
811 // a single scheduling unit. If we create a TokenFactor and return it as
812 // chain, then the TokenFactor is both a predecessor (operand) of the
813 // user as well as a successor (the TF operands are flagged to the user).
814 // c1, f1 = CopyToReg
815 // c2, f2 = CopyToReg
816 // c3 = TokenFactor c1, c2
819 Chain = Chains[NumRegs-1];
821 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
824 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
825 /// operand list. This adds the code marker and includes the number of
826 /// values added into it.
827 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
828 unsigned MatchingIdx, SDLoc dl,
830 std::vector<SDValue> &Ops) const {
831 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
833 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
835 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
836 else if (!Regs.empty() &&
837 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
838 // Put the register class of the virtual registers in the flag word. That
839 // way, later passes can recompute register class constraints for inline
840 // assembly as well as normal instructions.
841 // Don't do this for tied operands that can use the regclass information
843 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
844 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
845 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
848 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
851 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
852 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
853 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
854 MVT RegisterVT = RegVTs[Value];
855 for (unsigned i = 0; i != NumRegs; ++i) {
856 assert(Reg < Regs.size() && "Mismatch in # registers expected");
857 unsigned TheReg = Regs[Reg++];
858 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
860 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
861 // If we clobbered the stack pointer, MFI should know about it.
862 assert(DAG.getMachineFunction().getFrameInfo()->
863 hasInlineAsmWithSPAdjust());
869 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
870 const TargetLibraryInfo *li) {
874 DL = DAG.getTarget().getDataLayout();
875 Context = DAG.getContext();
876 LPadToCallSiteMap.clear();
879 /// clear - Clear out the current SelectionDAG and the associated
880 /// state and prepare this SelectionDAGBuilder object to be used
881 /// for a new block. This doesn't clear out information about
882 /// additional blocks that are needed to complete switch lowering
883 /// or PHI node updating; that information is cleared out as it is
885 void SelectionDAGBuilder::clear() {
887 UnusedArgNodeMap.clear();
888 PendingLoads.clear();
889 PendingExports.clear();
892 SDNodeOrder = LowestSDNodeOrder;
893 StatepointLowering.clear();
896 /// clearDanglingDebugInfo - Clear the dangling debug information
897 /// map. This function is separated from the clear so that debug
898 /// information that is dangling in a basic block can be properly
899 /// resolved in a different basic block. This allows the
900 /// SelectionDAG to resolve dangling debug information attached
902 void SelectionDAGBuilder::clearDanglingDebugInfo() {
903 DanglingDebugInfoMap.clear();
906 /// getRoot - Return the current virtual root of the Selection DAG,
907 /// flushing any PendingLoad items. This must be done before emitting
908 /// a store or any other node that may need to be ordered after any
909 /// prior load instructions.
911 SDValue SelectionDAGBuilder::getRoot() {
912 if (PendingLoads.empty())
913 return DAG.getRoot();
915 if (PendingLoads.size() == 1) {
916 SDValue Root = PendingLoads[0];
918 PendingLoads.clear();
922 // Otherwise, we have to make a token factor node.
923 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
925 PendingLoads.clear();
930 /// getControlRoot - Similar to getRoot, but instead of flushing all the
931 /// PendingLoad items, flush all the PendingExports items. It is necessary
932 /// to do this before emitting a terminator instruction.
934 SDValue SelectionDAGBuilder::getControlRoot() {
935 SDValue Root = DAG.getRoot();
937 if (PendingExports.empty())
940 // Turn all of the CopyToReg chains into one factored node.
941 if (Root.getOpcode() != ISD::EntryToken) {
942 unsigned i = 0, e = PendingExports.size();
943 for (; i != e; ++i) {
944 assert(PendingExports[i].getNode()->getNumOperands() > 1);
945 if (PendingExports[i].getNode()->getOperand(0) == Root)
946 break; // Don't add the root if we already indirectly depend on it.
950 PendingExports.push_back(Root);
953 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
955 PendingExports.clear();
960 void SelectionDAGBuilder::visit(const Instruction &I) {
961 // Set up outgoing PHI node register values before emitting the terminator.
962 if (isa<TerminatorInst>(&I))
963 HandlePHINodesInSuccessorBlocks(I.getParent());
969 visit(I.getOpcode(), I);
971 if (!isa<TerminatorInst>(&I) && !HasTailCall)
972 CopyToExportRegsIfNeeded(&I);
977 void SelectionDAGBuilder::visitPHI(const PHINode &) {
978 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
981 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
982 // Note: this doesn't use InstVisitor, because it has to work with
983 // ConstantExpr's in addition to instructions.
985 default: llvm_unreachable("Unknown instruction type encountered!");
986 // Build the switch statement using the Instruction.def file.
987 #define HANDLE_INST(NUM, OPCODE, CLASS) \
988 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
989 #include "llvm/IR/Instruction.def"
993 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
994 // generate the debug data structures now that we've seen its definition.
995 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
997 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
999 const DbgValueInst *DI = DDI.getDI();
1000 DebugLoc dl = DDI.getdl();
1001 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1002 MDLocalVariable *Variable = DI->getVariable();
1003 MDExpression *Expr = DI->getExpression();
1004 assert(Variable->isValidLocationForIntrinsic(dl) &&
1005 "Expected inlined-at fields to agree");
1006 uint64_t Offset = DI->getOffset();
1007 // A dbg.value for an alloca is always indirect.
1008 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1010 if (Val.getNode()) {
1011 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
1013 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1014 IsIndirect, Offset, dl, DbgSDNodeOrder);
1015 DAG.AddDbgValue(SDV, Val.getNode(), false);
1018 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1019 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1023 /// getCopyFromRegs - If there was virtual register allocated for the value V
1024 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1025 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1026 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1029 if (It != FuncInfo.ValueMap.end()) {
1030 unsigned InReg = It->second;
1031 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1033 SDValue Chain = DAG.getEntryNode();
1034 res = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1035 resolveDanglingDebugInfo(V, res);
1041 /// getValue - Return an SDValue for the given Value.
1042 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1043 // If we already have an SDValue for this value, use it. It's important
1044 // to do this first, so that we don't create a CopyFromReg if we already
1045 // have a regular SDValue.
1046 SDValue &N = NodeMap[V];
1047 if (N.getNode()) return N;
1049 // If there's a virtual register allocated and initialized for this
1051 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
1052 if (copyFromReg.getNode()) {
1056 // Otherwise create a new SDValue and remember it.
1057 SDValue Val = getValueImpl(V);
1059 resolveDanglingDebugInfo(V, Val);
1063 // Return true if SDValue exists for the given Value
1064 bool SelectionDAGBuilder::findValue(const Value *V) const {
1065 return (NodeMap.find(V) != NodeMap.end()) ||
1066 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1069 /// getNonRegisterValue - Return an SDValue for the given Value, but
1070 /// don't look in FuncInfo.ValueMap for a virtual register.
1071 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1072 // If we already have an SDValue for this value, use it.
1073 SDValue &N = NodeMap[V];
1074 if (N.getNode()) return N;
1076 // Otherwise create a new SDValue and remember it.
1077 SDValue Val = getValueImpl(V);
1079 resolveDanglingDebugInfo(V, Val);
1083 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1084 /// Create an SDValue for the given value.
1085 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1086 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1088 if (const Constant *C = dyn_cast<Constant>(V)) {
1089 EVT VT = TLI.getValueType(V->getType(), true);
1091 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1092 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1094 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1095 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1097 if (isa<ConstantPointerNull>(C)) {
1098 unsigned AS = V->getType()->getPointerAddressSpace();
1099 return DAG.getConstant(0, getCurSDLoc(), TLI.getPointerTy(AS));
1102 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1103 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1105 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1106 return DAG.getUNDEF(VT);
1108 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1109 visit(CE->getOpcode(), *CE);
1110 SDValue N1 = NodeMap[V];
1111 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1115 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1116 SmallVector<SDValue, 4> Constants;
1117 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1119 SDNode *Val = getValue(*OI).getNode();
1120 // If the operand is an empty aggregate, there are no values.
1122 // Add each leaf value from the operand to the Constants list
1123 // to form a flattened list of all the values.
1124 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1125 Constants.push_back(SDValue(Val, i));
1128 return DAG.getMergeValues(Constants, getCurSDLoc());
1131 if (const ConstantDataSequential *CDS =
1132 dyn_cast<ConstantDataSequential>(C)) {
1133 SmallVector<SDValue, 4> Ops;
1134 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1135 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1136 // Add each leaf value from the operand to the Constants list
1137 // to form a flattened list of all the values.
1138 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1139 Ops.push_back(SDValue(Val, i));
1142 if (isa<ArrayType>(CDS->getType()))
1143 return DAG.getMergeValues(Ops, getCurSDLoc());
1144 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1148 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1149 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1150 "Unknown struct or array constant!");
1152 SmallVector<EVT, 4> ValueVTs;
1153 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1154 unsigned NumElts = ValueVTs.size();
1156 return SDValue(); // empty struct
1157 SmallVector<SDValue, 4> Constants(NumElts);
1158 for (unsigned i = 0; i != NumElts; ++i) {
1159 EVT EltVT = ValueVTs[i];
1160 if (isa<UndefValue>(C))
1161 Constants[i] = DAG.getUNDEF(EltVT);
1162 else if (EltVT.isFloatingPoint())
1163 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1165 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1168 return DAG.getMergeValues(Constants, getCurSDLoc());
1171 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1172 return DAG.getBlockAddress(BA, VT);
1174 VectorType *VecTy = cast<VectorType>(V->getType());
1175 unsigned NumElements = VecTy->getNumElements();
1177 // Now that we know the number and type of the elements, get that number of
1178 // elements into the Ops array based on what kind of constant it is.
1179 SmallVector<SDValue, 16> Ops;
1180 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1181 for (unsigned i = 0; i != NumElements; ++i)
1182 Ops.push_back(getValue(CV->getOperand(i)));
1184 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1185 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1188 if (EltVT.isFloatingPoint())
1189 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1191 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1192 Ops.assign(NumElements, Op);
1195 // Create a BUILD_VECTOR node.
1196 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1199 // If this is a static alloca, generate it as the frameindex instead of
1201 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1202 DenseMap<const AllocaInst*, int>::iterator SI =
1203 FuncInfo.StaticAllocaMap.find(AI);
1204 if (SI != FuncInfo.StaticAllocaMap.end())
1205 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1208 // If this is an instruction which fast-isel has deferred, select it now.
1209 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1210 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1211 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1212 SDValue Chain = DAG.getEntryNode();
1213 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1216 llvm_unreachable("Can't get register for value!");
1219 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1220 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1221 SDValue Chain = getControlRoot();
1222 SmallVector<ISD::OutputArg, 8> Outs;
1223 SmallVector<SDValue, 8> OutVals;
1225 if (!FuncInfo.CanLowerReturn) {
1226 unsigned DemoteReg = FuncInfo.DemoteRegister;
1227 const Function *F = I.getParent()->getParent();
1229 // Emit a store of the return value through the virtual register.
1230 // Leave Outs empty so that LowerReturn won't try to load return
1231 // registers the usual way.
1232 SmallVector<EVT, 1> PtrValueVTs;
1233 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1236 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1237 SDValue RetOp = getValue(I.getOperand(0));
1239 SmallVector<EVT, 4> ValueVTs;
1240 SmallVector<uint64_t, 4> Offsets;
1241 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1242 unsigned NumValues = ValueVTs.size();
1244 SmallVector<SDValue, 4> Chains(NumValues);
1245 for (unsigned i = 0; i != NumValues; ++i) {
1246 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1247 RetPtr.getValueType(), RetPtr,
1248 DAG.getIntPtrConstant(Offsets[i],
1251 DAG.getStore(Chain, getCurSDLoc(),
1252 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1253 // FIXME: better loc info would be nice.
1254 Add, MachinePointerInfo(), false, false, 0);
1257 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1258 MVT::Other, Chains);
1259 } else if (I.getNumOperands() != 0) {
1260 SmallVector<EVT, 4> ValueVTs;
1261 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1262 unsigned NumValues = ValueVTs.size();
1264 SDValue RetOp = getValue(I.getOperand(0));
1266 const Function *F = I.getParent()->getParent();
1268 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1269 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1271 ExtendKind = ISD::SIGN_EXTEND;
1272 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1274 ExtendKind = ISD::ZERO_EXTEND;
1276 LLVMContext &Context = F->getContext();
1277 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1280 for (unsigned j = 0; j != NumValues; ++j) {
1281 EVT VT = ValueVTs[j];
1283 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1284 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1286 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1287 MVT PartVT = TLI.getRegisterType(Context, VT);
1288 SmallVector<SDValue, 4> Parts(NumParts);
1289 getCopyToParts(DAG, getCurSDLoc(),
1290 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1291 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1293 // 'inreg' on function refers to return value
1294 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1298 // Propagate extension type if any
1299 if (ExtendKind == ISD::SIGN_EXTEND)
1301 else if (ExtendKind == ISD::ZERO_EXTEND)
1304 for (unsigned i = 0; i < NumParts; ++i) {
1305 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1306 VT, /*isfixed=*/true, 0, 0));
1307 OutVals.push_back(Parts[i]);
1313 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1314 CallingConv::ID CallConv =
1315 DAG.getMachineFunction().getFunction()->getCallingConv();
1316 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1317 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1319 // Verify that the target's LowerReturn behaved as expected.
1320 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1321 "LowerReturn didn't return a valid chain!");
1323 // Update the DAG with the new chain value resulting from return lowering.
1327 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1328 /// created for it, emit nodes to copy the value into the virtual
1330 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1332 if (V->getType()->isEmptyTy())
1335 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1336 if (VMI != FuncInfo.ValueMap.end()) {
1337 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1338 CopyValueToVirtualRegister(V, VMI->second);
1342 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1343 /// the current basic block, add it to ValueMap now so that we'll get a
1345 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1346 // No need to export constants.
1347 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1349 // Already exported?
1350 if (FuncInfo.isExportedInst(V)) return;
1352 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1353 CopyValueToVirtualRegister(V, Reg);
1356 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1357 const BasicBlock *FromBB) {
1358 // The operands of the setcc have to be in this block. We don't know
1359 // how to export them from some other block.
1360 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1361 // Can export from current BB.
1362 if (VI->getParent() == FromBB)
1365 // Is already exported, noop.
1366 return FuncInfo.isExportedInst(V);
1369 // If this is an argument, we can export it if the BB is the entry block or
1370 // if it is already exported.
1371 if (isa<Argument>(V)) {
1372 if (FromBB == &FromBB->getParent()->getEntryBlock())
1375 // Otherwise, can only export this if it is already exported.
1376 return FuncInfo.isExportedInst(V);
1379 // Otherwise, constants can always be exported.
1383 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1384 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1385 const MachineBasicBlock *Dst) const {
1386 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1389 const BasicBlock *SrcBB = Src->getBasicBlock();
1390 const BasicBlock *DstBB = Dst->getBasicBlock();
1391 return BPI->getEdgeWeight(SrcBB, DstBB);
1394 void SelectionDAGBuilder::
1395 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1396 uint32_t Weight /* = 0 */) {
1398 Weight = getEdgeWeight(Src, Dst);
1399 Src->addSuccessor(Dst, Weight);
1403 static bool InBlock(const Value *V, const BasicBlock *BB) {
1404 if (const Instruction *I = dyn_cast<Instruction>(V))
1405 return I->getParent() == BB;
1409 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1410 /// This function emits a branch and is used at the leaves of an OR or an
1411 /// AND operator tree.
1414 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1415 MachineBasicBlock *TBB,
1416 MachineBasicBlock *FBB,
1417 MachineBasicBlock *CurBB,
1418 MachineBasicBlock *SwitchBB,
1421 const BasicBlock *BB = CurBB->getBasicBlock();
1423 // If the leaf of the tree is a comparison, merge the condition into
1425 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1426 // The operands of the cmp have to be in this block. We don't know
1427 // how to export them from some other block. If this is the first block
1428 // of the sequence, no exporting is needed.
1429 if (CurBB == SwitchBB ||
1430 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1431 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1432 ISD::CondCode Condition;
1433 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1434 Condition = getICmpCondCode(IC->getPredicate());
1435 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1436 Condition = getFCmpCondCode(FC->getPredicate());
1437 if (TM.Options.NoNaNsFPMath)
1438 Condition = getFCmpCodeWithoutNaN(Condition);
1440 (void)Condition; // silence warning.
1441 llvm_unreachable("Unknown compare instruction");
1444 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1445 TBB, FBB, CurBB, TWeight, FWeight);
1446 SwitchCases.push_back(CB);
1451 // Create a CaseBlock record representing this branch.
1452 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1453 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1454 SwitchCases.push_back(CB);
1457 /// Scale down both weights to fit into uint32_t.
1458 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1459 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1460 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1461 NewTrue = NewTrue / Scale;
1462 NewFalse = NewFalse / Scale;
1465 /// FindMergedConditions - If Cond is an expression like
1466 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1467 MachineBasicBlock *TBB,
1468 MachineBasicBlock *FBB,
1469 MachineBasicBlock *CurBB,
1470 MachineBasicBlock *SwitchBB,
1471 unsigned Opc, uint32_t TWeight,
1473 // If this node is not part of the or/and tree, emit it as a branch.
1474 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1475 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1476 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1477 BOp->getParent() != CurBB->getBasicBlock() ||
1478 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1479 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1480 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1485 // Create TmpBB after CurBB.
1486 MachineFunction::iterator BBI = CurBB;
1487 MachineFunction &MF = DAG.getMachineFunction();
1488 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1489 CurBB->getParent()->insert(++BBI, TmpBB);
1491 if (Opc == Instruction::Or) {
1492 // Codegen X | Y as:
1501 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1502 // The requirement is that
1503 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1504 // = TrueProb for orignal BB.
1505 // Assuming the orignal weights are A and B, one choice is to set BB1's
1506 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1508 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1509 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1510 // TmpBB, but the math is more complicated.
1512 uint64_t NewTrueWeight = TWeight;
1513 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1514 ScaleWeights(NewTrueWeight, NewFalseWeight);
1515 // Emit the LHS condition.
1516 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1517 NewTrueWeight, NewFalseWeight);
1519 NewTrueWeight = TWeight;
1520 NewFalseWeight = 2 * (uint64_t)FWeight;
1521 ScaleWeights(NewTrueWeight, NewFalseWeight);
1522 // Emit the RHS condition into TmpBB.
1523 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1524 NewTrueWeight, NewFalseWeight);
1526 assert(Opc == Instruction::And && "Unknown merge op!");
1527 // Codegen X & Y as:
1535 // This requires creation of TmpBB after CurBB.
1537 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1538 // The requirement is that
1539 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1540 // = FalseProb for orignal BB.
1541 // Assuming the orignal weights are A and B, one choice is to set BB1's
1542 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1544 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1546 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1547 uint64_t NewFalseWeight = FWeight;
1548 ScaleWeights(NewTrueWeight, NewFalseWeight);
1549 // Emit the LHS condition.
1550 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1551 NewTrueWeight, NewFalseWeight);
1553 NewTrueWeight = 2 * (uint64_t)TWeight;
1554 NewFalseWeight = FWeight;
1555 ScaleWeights(NewTrueWeight, NewFalseWeight);
1556 // Emit the RHS condition into TmpBB.
1557 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1558 NewTrueWeight, NewFalseWeight);
1562 /// If the set of cases should be emitted as a series of branches, return true.
1563 /// If we should emit this as a bunch of and/or'd together conditions, return
1566 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1567 if (Cases.size() != 2) return true;
1569 // If this is two comparisons of the same values or'd or and'd together, they
1570 // will get folded into a single comparison, so don't emit two blocks.
1571 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1572 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1573 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1574 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1578 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1579 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1580 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1581 Cases[0].CC == Cases[1].CC &&
1582 isa<Constant>(Cases[0].CmpRHS) &&
1583 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1584 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1586 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1593 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1594 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1596 // Update machine-CFG edges.
1597 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1599 if (I.isUnconditional()) {
1600 // Update machine-CFG edges.
1601 BrMBB->addSuccessor(Succ0MBB);
1603 // If this is not a fall-through branch or optimizations are switched off,
1605 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1606 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1607 MVT::Other, getControlRoot(),
1608 DAG.getBasicBlock(Succ0MBB)));
1613 // If this condition is one of the special cases we handle, do special stuff
1615 const Value *CondVal = I.getCondition();
1616 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1618 // If this is a series of conditions that are or'd or and'd together, emit
1619 // this as a sequence of branches instead of setcc's with and/or operations.
1620 // As long as jumps are not expensive, this should improve performance.
1621 // For example, instead of something like:
1634 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1635 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1636 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1637 BOp->getOpcode() == Instruction::Or)) {
1638 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1639 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1640 getEdgeWeight(BrMBB, Succ1MBB));
1641 // If the compares in later blocks need to use values not currently
1642 // exported from this block, export them now. This block should always
1643 // be the first entry.
1644 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1646 // Allow some cases to be rejected.
1647 if (ShouldEmitAsBranches(SwitchCases)) {
1648 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1649 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1650 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1653 // Emit the branch for this block.
1654 visitSwitchCase(SwitchCases[0], BrMBB);
1655 SwitchCases.erase(SwitchCases.begin());
1659 // Okay, we decided not to do this, remove any inserted MBB's and clear
1661 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1662 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1664 SwitchCases.clear();
1668 // Create a CaseBlock record representing this branch.
1669 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1670 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1672 // Use visitSwitchCase to actually insert the fast branch sequence for this
1674 visitSwitchCase(CB, BrMBB);
1677 /// visitSwitchCase - Emits the necessary code to represent a single node in
1678 /// the binary search tree resulting from lowering a switch instruction.
1679 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1680 MachineBasicBlock *SwitchBB) {
1682 SDValue CondLHS = getValue(CB.CmpLHS);
1683 SDLoc dl = getCurSDLoc();
1685 // Build the setcc now.
1687 // Fold "(X == true)" to X and "(X == false)" to !X to
1688 // handle common cases produced by branch lowering.
1689 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1690 CB.CC == ISD::SETEQ)
1692 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1693 CB.CC == ISD::SETEQ) {
1694 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1695 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1697 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1699 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1701 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1702 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1704 SDValue CmpOp = getValue(CB.CmpMHS);
1705 EVT VT = CmpOp.getValueType();
1707 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1708 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1711 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1712 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1713 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1714 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1718 // Update successor info
1719 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1720 // TrueBB and FalseBB are always different unless the incoming IR is
1721 // degenerate. This only happens when running llc on weird IR.
1722 if (CB.TrueBB != CB.FalseBB)
1723 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1725 // If the lhs block is the next block, invert the condition so that we can
1726 // fall through to the lhs instead of the rhs block.
1727 if (CB.TrueBB == NextBlock(SwitchBB)) {
1728 std::swap(CB.TrueBB, CB.FalseBB);
1729 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1730 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1733 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1734 MVT::Other, getControlRoot(), Cond,
1735 DAG.getBasicBlock(CB.TrueBB));
1737 // Insert the false branch. Do this even if it's a fall through branch,
1738 // this makes it easier to do DAG optimizations which require inverting
1739 // the branch condition.
1740 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1741 DAG.getBasicBlock(CB.FalseBB));
1743 DAG.setRoot(BrCond);
1746 /// visitJumpTable - Emit JumpTable node in the current MBB
1747 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1748 // Emit the code for the jump table
1749 assert(JT.Reg != -1U && "Should lower JT Header first!");
1750 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1751 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1753 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1754 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1755 MVT::Other, Index.getValue(1),
1757 DAG.setRoot(BrJumpTable);
1760 /// visitJumpTableHeader - This function emits necessary code to produce index
1761 /// in the JumpTable from switch case.
1762 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1763 JumpTableHeader &JTH,
1764 MachineBasicBlock *SwitchBB) {
1765 SDLoc dl = getCurSDLoc();
1767 // Subtract the lowest switch case value from the value being switched on and
1768 // conditional branch to default mbb if the result is greater than the
1769 // difference between smallest and largest cases.
1770 SDValue SwitchOp = getValue(JTH.SValue);
1771 EVT VT = SwitchOp.getValueType();
1772 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1773 DAG.getConstant(JTH.First, dl, VT));
1775 // The SDNode we just created, which holds the value being switched on minus
1776 // the smallest case value, needs to be copied to a virtual register so it
1777 // can be used as an index into the jump table in a subsequent basic block.
1778 // This value may be smaller or larger than the target's pointer type, and
1779 // therefore require extension or truncating.
1780 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1781 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy());
1783 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1784 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1785 JumpTableReg, SwitchOp);
1786 JT.Reg = JumpTableReg;
1788 // Emit the range check for the jump table, and branch to the default block
1789 // for the switch statement if the value being switched on exceeds the largest
1790 // case in the switch.
1792 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1793 Sub.getValueType()),
1794 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT),
1797 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1798 MVT::Other, CopyTo, CMP,
1799 DAG.getBasicBlock(JT.Default));
1801 // Avoid emitting unnecessary branches to the next block.
1802 if (JT.MBB != NextBlock(SwitchBB))
1803 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1804 DAG.getBasicBlock(JT.MBB));
1806 DAG.setRoot(BrCond);
1809 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1810 /// tail spliced into a stack protector check success bb.
1812 /// For a high level explanation of how this fits into the stack protector
1813 /// generation see the comment on the declaration of class
1814 /// StackProtectorDescriptor.
1815 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1816 MachineBasicBlock *ParentBB) {
1818 // First create the loads to the guard/stack slot for the comparison.
1819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1820 EVT PtrTy = TLI.getPointerTy();
1822 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1823 int FI = MFI->getStackProtectorIndex();
1825 const Value *IRGuard = SPD.getGuard();
1826 SDValue GuardPtr = getValue(IRGuard);
1827 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1830 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1833 SDLoc dl = getCurSDLoc();
1835 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1836 // guard value from the virtual register holding the value. Otherwise, emit a
1837 // volatile load to retrieve the stack guard value.
1838 unsigned GuardReg = SPD.getGuardReg();
1840 if (GuardReg && TLI.useLoadStackGuardNode())
1841 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1844 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1845 GuardPtr, MachinePointerInfo(IRGuard, 0),
1846 true, false, false, Align);
1848 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1850 MachinePointerInfo::getFixedStack(FI),
1851 true, false, false, Align);
1853 // Perform the comparison via a subtract/getsetcc.
1854 EVT VT = Guard.getValueType();
1855 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1858 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1859 Sub.getValueType()),
1860 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1862 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1863 // branch to failure MBB.
1864 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1865 MVT::Other, StackSlot.getOperand(0),
1866 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1867 // Otherwise branch to success MBB.
1868 SDValue Br = DAG.getNode(ISD::BR, dl,
1870 DAG.getBasicBlock(SPD.getSuccessMBB()));
1875 /// Codegen the failure basic block for a stack protector check.
1877 /// A failure stack protector machine basic block consists simply of a call to
1878 /// __stack_chk_fail().
1880 /// For a high level explanation of how this fits into the stack protector
1881 /// generation see the comment on the declaration of class
1882 /// StackProtectorDescriptor.
1884 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1885 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1887 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1888 nullptr, 0, false, getCurSDLoc(), false, false).second;
1892 /// visitBitTestHeader - This function emits necessary code to produce value
1893 /// suitable for "bit tests"
1894 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1895 MachineBasicBlock *SwitchBB) {
1896 SDLoc dl = getCurSDLoc();
1898 // Subtract the minimum value
1899 SDValue SwitchOp = getValue(B.SValue);
1900 EVT VT = SwitchOp.getValueType();
1901 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1902 DAG.getConstant(B.First, dl, VT));
1905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1907 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1908 Sub.getValueType()),
1909 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1911 // Determine the type of the test operands.
1912 bool UsePtrType = false;
1913 if (!TLI.isTypeLegal(VT))
1916 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1917 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1918 // Switch table case range are encoded into series of masks.
1919 // Just use pointer type, it's guaranteed to fit.
1925 VT = TLI.getPointerTy();
1926 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1929 B.RegVT = VT.getSimpleVT();
1930 B.Reg = FuncInfo.CreateReg(B.RegVT);
1931 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1933 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1935 addSuccessorWithWeight(SwitchBB, B.Default);
1936 addSuccessorWithWeight(SwitchBB, MBB);
1938 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1939 MVT::Other, CopyTo, RangeCmp,
1940 DAG.getBasicBlock(B.Default));
1942 // Avoid emitting unnecessary branches to the next block.
1943 if (MBB != NextBlock(SwitchBB))
1944 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1945 DAG.getBasicBlock(MBB));
1947 DAG.setRoot(BrRange);
1950 /// visitBitTestCase - this function produces one "bit test"
1951 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1952 MachineBasicBlock* NextMBB,
1953 uint32_t BranchWeightToNext,
1956 MachineBasicBlock *SwitchBB) {
1957 SDLoc dl = getCurSDLoc();
1959 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1961 unsigned PopCount = countPopulation(B.Mask);
1962 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1963 if (PopCount == 1) {
1964 // Testing for a single bit; just compare the shift count with what it
1965 // would need to be to shift a 1 bit in that position.
1967 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1968 DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), ISD::SETEQ);
1969 } else if (PopCount == BB.Range) {
1970 // There is only one zero bit in the range, test for it directly.
1972 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1973 DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), ISD::SETNE);
1975 // Make desired shift
1976 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1977 DAG.getConstant(1, dl, VT), ShiftOp);
1979 // Emit bit tests and jumps
1980 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1981 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1982 Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1983 DAG.getConstant(0, dl, VT), ISD::SETNE);
1986 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1987 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1988 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1989 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1991 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1992 MVT::Other, getControlRoot(),
1993 Cmp, DAG.getBasicBlock(B.TargetBB));
1995 // Avoid emitting unnecessary branches to the next block.
1996 if (NextMBB != NextBlock(SwitchBB))
1997 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1998 DAG.getBasicBlock(NextMBB));
2003 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2004 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2006 // Retrieve successors.
2007 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2008 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2010 const Value *Callee(I.getCalledValue());
2011 const Function *Fn = dyn_cast<Function>(Callee);
2012 if (isa<InlineAsm>(Callee))
2014 else if (Fn && Fn->isIntrinsic()) {
2015 switch (Fn->getIntrinsicID()) {
2017 llvm_unreachable("Cannot invoke this intrinsic");
2018 case Intrinsic::donothing:
2019 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2021 case Intrinsic::experimental_patchpoint_void:
2022 case Intrinsic::experimental_patchpoint_i64:
2023 visitPatchpoint(&I, LandingPad);
2025 case Intrinsic::experimental_gc_statepoint:
2026 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2030 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2032 // If the value of the invoke is used outside of its defining block, make it
2033 // available as a virtual register.
2034 // We already took care of the exported value for the statepoint instruction
2035 // during call to the LowerStatepoint.
2036 if (!isStatepoint(I)) {
2037 CopyToExportRegsIfNeeded(&I);
2040 // Update successor info
2041 addSuccessorWithWeight(InvokeMBB, Return);
2042 addSuccessorWithWeight(InvokeMBB, LandingPad);
2044 // Drop into normal successor.
2045 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2046 MVT::Other, getControlRoot(),
2047 DAG.getBasicBlock(Return)));
2050 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2051 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2054 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2055 assert(FuncInfo.MBB->isLandingPad() &&
2056 "Call to landingpad not in landing pad!");
2058 MachineBasicBlock *MBB = FuncInfo.MBB;
2059 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2060 AddLandingPadInfo(LP, MMI, MBB);
2062 // If there aren't registers to copy the values into (e.g., during SjLj
2063 // exceptions), then don't bother to create these DAG nodes.
2064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2065 if (TLI.getExceptionPointerRegister() == 0 &&
2066 TLI.getExceptionSelectorRegister() == 0)
2069 SmallVector<EVT, 2> ValueVTs;
2070 SDLoc dl = getCurSDLoc();
2071 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2072 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2074 // Get the two live-in registers as SDValues. The physregs have already been
2075 // copied into virtual registers.
2077 if (FuncInfo.ExceptionPointerVirtReg) {
2078 Ops[0] = DAG.getZExtOrTrunc(
2079 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2080 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2083 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy());
2085 Ops[1] = DAG.getZExtOrTrunc(
2086 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2087 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2091 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2092 DAG.getVTList(ValueVTs), Ops);
2097 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2098 MachineBasicBlock *LPadBB) {
2099 SDValue Chain = getControlRoot();
2100 SDLoc dl = getCurSDLoc();
2102 // Get the typeid that we will dispatch on later.
2103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2104 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2105 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2106 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2107 SDValue Sel = DAG.getConstant(TypeID, dl, TLI.getPointerTy());
2108 Chain = DAG.getCopyToReg(Chain, dl, VReg, Sel);
2110 // Branch to the main landing pad block.
2111 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2112 ClauseMBB->addSuccessor(LPadBB);
2113 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, Chain,
2114 DAG.getBasicBlock(LPadBB)));
2118 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2120 for (const CaseCluster &CC : Clusters)
2121 assert(CC.Low == CC.High && "Input clusters must be single-case");
2124 std::sort(Clusters.begin(), Clusters.end(),
2125 [](const CaseCluster &a, const CaseCluster &b) {
2126 return a.Low->getValue().slt(b.Low->getValue());
2129 // Merge adjacent clusters with the same destination.
2130 const unsigned N = Clusters.size();
2131 unsigned DstIndex = 0;
2132 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2133 CaseCluster &CC = Clusters[SrcIndex];
2134 const ConstantInt *CaseVal = CC.Low;
2135 MachineBasicBlock *Succ = CC.MBB;
2137 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2138 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2139 // If this case has the same successor and is a neighbour, merge it into
2140 // the previous cluster.
2141 Clusters[DstIndex - 1].High = CaseVal;
2142 Clusters[DstIndex - 1].Weight += CC.Weight;
2143 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2145 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2146 sizeof(Clusters[SrcIndex]));
2149 Clusters.resize(DstIndex);
2152 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2153 MachineBasicBlock *Last) {
2155 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2156 if (JTCases[i].first.HeaderBB == First)
2157 JTCases[i].first.HeaderBB = Last;
2159 // Update BitTestCases.
2160 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2161 if (BitTestCases[i].Parent == First)
2162 BitTestCases[i].Parent = Last;
2165 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2166 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2168 // Update machine-CFG edges with unique successors.
2169 SmallSet<BasicBlock*, 32> Done;
2170 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2171 BasicBlock *BB = I.getSuccessor(i);
2172 bool Inserted = Done.insert(BB).second;
2176 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2177 addSuccessorWithWeight(IndirectBrMBB, Succ);
2180 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2181 MVT::Other, getControlRoot(),
2182 getValue(I.getAddress())));
2185 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2186 if (DAG.getTarget().Options.TrapUnreachable)
2187 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2190 void SelectionDAGBuilder::visitFSub(const User &I) {
2191 // -0.0 - X --> fneg
2192 Type *Ty = I.getType();
2193 if (isa<Constant>(I.getOperand(0)) &&
2194 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2195 SDValue Op2 = getValue(I.getOperand(1));
2196 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2197 Op2.getValueType(), Op2));
2201 visitBinary(I, ISD::FSUB);
2204 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2205 SDValue Op1 = getValue(I.getOperand(0));
2206 SDValue Op2 = getValue(I.getOperand(1));
2211 if (const OverflowingBinaryOperator *OFBinOp =
2212 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2213 nuw = OFBinOp->hasNoUnsignedWrap();
2214 nsw = OFBinOp->hasNoSignedWrap();
2216 if (const PossiblyExactOperator *ExactOp =
2217 dyn_cast<const PossiblyExactOperator>(&I))
2218 exact = ExactOp->isExact();
2220 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2221 Op1, Op2, nuw, nsw, exact);
2222 setValue(&I, BinNodeValue);
2225 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2226 SDValue Op1 = getValue(I.getOperand(0));
2227 SDValue Op2 = getValue(I.getOperand(1));
2230 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2232 // Coerce the shift amount to the right type if we can.
2233 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2234 unsigned ShiftSize = ShiftTy.getSizeInBits();
2235 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2236 SDLoc DL = getCurSDLoc();
2238 // If the operand is smaller than the shift count type, promote it.
2239 if (ShiftSize > Op2Size)
2240 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2242 // If the operand is larger than the shift count type but the shift
2243 // count type has enough bits to represent any shift value, truncate
2244 // it now. This is a common case and it exposes the truncate to
2245 // optimization early.
2246 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2247 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2248 // Otherwise we'll need to temporarily settle for some other convenient
2249 // type. Type legalization will make adjustments once the shiftee is split.
2251 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2258 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2260 if (const OverflowingBinaryOperator *OFBinOp =
2261 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2262 nuw = OFBinOp->hasNoUnsignedWrap();
2263 nsw = OFBinOp->hasNoSignedWrap();
2265 if (const PossiblyExactOperator *ExactOp =
2266 dyn_cast<const PossiblyExactOperator>(&I))
2267 exact = ExactOp->isExact();
2270 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2275 void SelectionDAGBuilder::visitSDiv(const User &I) {
2276 SDValue Op1 = getValue(I.getOperand(0));
2277 SDValue Op2 = getValue(I.getOperand(1));
2279 // Turn exact SDivs into multiplications.
2280 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2282 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2283 !isa<ConstantSDNode>(Op1) &&
2284 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2285 setValue(&I, DAG.getTargetLoweringInfo()
2286 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2288 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2292 void SelectionDAGBuilder::visitICmp(const User &I) {
2293 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2294 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2295 predicate = IC->getPredicate();
2296 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2297 predicate = ICmpInst::Predicate(IC->getPredicate());
2298 SDValue Op1 = getValue(I.getOperand(0));
2299 SDValue Op2 = getValue(I.getOperand(1));
2300 ISD::CondCode Opcode = getICmpCondCode(predicate);
2302 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2303 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2306 void SelectionDAGBuilder::visitFCmp(const User &I) {
2307 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2308 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2309 predicate = FC->getPredicate();
2310 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2311 predicate = FCmpInst::Predicate(FC->getPredicate());
2312 SDValue Op1 = getValue(I.getOperand(0));
2313 SDValue Op2 = getValue(I.getOperand(1));
2314 ISD::CondCode Condition = getFCmpCondCode(predicate);
2315 if (TM.Options.NoNaNsFPMath)
2316 Condition = getFCmpCodeWithoutNaN(Condition);
2317 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2318 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2321 void SelectionDAGBuilder::visitSelect(const User &I) {
2322 SmallVector<EVT, 4> ValueVTs;
2323 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2324 unsigned NumValues = ValueVTs.size();
2325 if (NumValues == 0) return;
2327 SmallVector<SDValue, 4> Values(NumValues);
2328 SDValue Cond = getValue(I.getOperand(0));
2329 SDValue TrueVal = getValue(I.getOperand(1));
2330 SDValue FalseVal = getValue(I.getOperand(2));
2331 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2332 ISD::VSELECT : ISD::SELECT;
2334 for (unsigned i = 0; i != NumValues; ++i)
2335 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2336 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2338 SDValue(TrueVal.getNode(),
2339 TrueVal.getResNo() + i),
2340 SDValue(FalseVal.getNode(),
2341 FalseVal.getResNo() + i));
2343 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2344 DAG.getVTList(ValueVTs), Values));
2347 void SelectionDAGBuilder::visitTrunc(const User &I) {
2348 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2349 SDValue N = getValue(I.getOperand(0));
2350 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2351 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2354 void SelectionDAGBuilder::visitZExt(const User &I) {
2355 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2356 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2357 SDValue N = getValue(I.getOperand(0));
2358 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2359 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2362 void SelectionDAGBuilder::visitSExt(const User &I) {
2363 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2364 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2365 SDValue N = getValue(I.getOperand(0));
2366 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2367 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2370 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2371 // FPTrunc is never a no-op cast, no need to check
2372 SDValue N = getValue(I.getOperand(0));
2373 SDLoc dl = getCurSDLoc();
2374 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2375 EVT DestVT = TLI.getValueType(I.getType());
2376 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2377 DAG.getTargetConstant(0, dl, TLI.getPointerTy())));
2380 void SelectionDAGBuilder::visitFPExt(const User &I) {
2381 // FPExt is never a no-op cast, no need to check
2382 SDValue N = getValue(I.getOperand(0));
2383 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2384 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2387 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2388 // FPToUI is never a no-op cast, no need to check
2389 SDValue N = getValue(I.getOperand(0));
2390 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2391 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2394 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2395 // FPToSI is never a no-op cast, no need to check
2396 SDValue N = getValue(I.getOperand(0));
2397 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2398 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2401 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2402 // UIToFP is never a no-op cast, no need to check
2403 SDValue N = getValue(I.getOperand(0));
2404 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2405 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2408 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2409 // SIToFP is never a no-op cast, no need to check
2410 SDValue N = getValue(I.getOperand(0));
2411 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2412 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2415 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2416 // What to do depends on the size of the integer and the size of the pointer.
2417 // We can either truncate, zero extend, or no-op, accordingly.
2418 SDValue N = getValue(I.getOperand(0));
2419 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2420 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2423 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2424 // What to do depends on the size of the integer and the size of the pointer.
2425 // We can either truncate, zero extend, or no-op, accordingly.
2426 SDValue N = getValue(I.getOperand(0));
2427 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2428 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2431 void SelectionDAGBuilder::visitBitCast(const User &I) {
2432 SDValue N = getValue(I.getOperand(0));
2433 SDLoc dl = getCurSDLoc();
2434 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2436 // BitCast assures us that source and destination are the same size so this is
2437 // either a BITCAST or a no-op.
2438 if (DestVT != N.getValueType())
2439 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2440 DestVT, N)); // convert types.
2441 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2442 // might fold any kind of constant expression to an integer constant and that
2443 // is not what we are looking for. Only regcognize a bitcast of a genuine
2444 // constant integer as an opaque constant.
2445 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2446 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2449 setValue(&I, N); // noop cast.
2452 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2454 const Value *SV = I.getOperand(0);
2455 SDValue N = getValue(SV);
2456 EVT DestVT = TLI.getValueType(I.getType());
2458 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2459 unsigned DestAS = I.getType()->getPointerAddressSpace();
2461 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2462 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2467 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2469 SDValue InVec = getValue(I.getOperand(0));
2470 SDValue InVal = getValue(I.getOperand(1));
2471 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2472 getCurSDLoc(), TLI.getVectorIdxTy());
2473 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2474 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
2477 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2479 SDValue InVec = getValue(I.getOperand(0));
2480 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2481 getCurSDLoc(), TLI.getVectorIdxTy());
2482 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2483 TLI.getValueType(I.getType()), InVec, InIdx));
2486 // Utility for visitShuffleVector - Return true if every element in Mask,
2487 // beginning from position Pos and ending in Pos+Size, falls within the
2488 // specified sequential range [L, L+Pos). or is undef.
2489 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2490 unsigned Pos, unsigned Size, int Low) {
2491 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2492 if (Mask[i] >= 0 && Mask[i] != Low)
2497 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2498 SDValue Src1 = getValue(I.getOperand(0));
2499 SDValue Src2 = getValue(I.getOperand(1));
2501 SmallVector<int, 8> Mask;
2502 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2503 unsigned MaskNumElts = Mask.size();
2505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2506 EVT VT = TLI.getValueType(I.getType());
2507 EVT SrcVT = Src1.getValueType();
2508 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2510 if (SrcNumElts == MaskNumElts) {
2511 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2516 // Normalize the shuffle vector since mask and vector length don't match.
2517 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2518 // Mask is longer than the source vectors and is a multiple of the source
2519 // vectors. We can use concatenate vector to make the mask and vectors
2521 if (SrcNumElts*2 == MaskNumElts) {
2522 // First check for Src1 in low and Src2 in high
2523 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2524 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2525 // The shuffle is concatenating two vectors together.
2526 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2530 // Then check for Src2 in low and Src1 in high
2531 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2532 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2533 // The shuffle is concatenating two vectors together.
2534 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2540 // Pad both vectors with undefs to make them the same length as the mask.
2541 unsigned NumConcat = MaskNumElts / SrcNumElts;
2542 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2543 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2544 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2546 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2547 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2551 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2552 getCurSDLoc(), VT, MOps1);
2553 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2554 getCurSDLoc(), VT, MOps2);
2556 // Readjust mask for new input vector length.
2557 SmallVector<int, 8> MappedOps;
2558 for (unsigned i = 0; i != MaskNumElts; ++i) {
2560 if (Idx >= (int)SrcNumElts)
2561 Idx -= SrcNumElts - MaskNumElts;
2562 MappedOps.push_back(Idx);
2565 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2570 if (SrcNumElts > MaskNumElts) {
2571 // Analyze the access pattern of the vector to see if we can extract
2572 // two subvectors and do the shuffle. The analysis is done by calculating
2573 // the range of elements the mask access on both vectors.
2574 int MinRange[2] = { static_cast<int>(SrcNumElts),
2575 static_cast<int>(SrcNumElts)};
2576 int MaxRange[2] = {-1, -1};
2578 for (unsigned i = 0; i != MaskNumElts; ++i) {
2584 if (Idx >= (int)SrcNumElts) {
2588 if (Idx > MaxRange[Input])
2589 MaxRange[Input] = Idx;
2590 if (Idx < MinRange[Input])
2591 MinRange[Input] = Idx;
2594 // Check if the access is smaller than the vector size and can we find
2595 // a reasonable extract index.
2596 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2598 int StartIdx[2]; // StartIdx to extract from
2599 for (unsigned Input = 0; Input < 2; ++Input) {
2600 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2601 RangeUse[Input] = 0; // Unused
2602 StartIdx[Input] = 0;
2606 // Find a good start index that is a multiple of the mask length. Then
2607 // see if the rest of the elements are in range.
2608 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2609 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2610 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2611 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2614 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2615 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2618 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2619 // Extract appropriate subvector and generate a vector shuffle
2620 for (unsigned Input = 0; Input < 2; ++Input) {
2621 SDValue &Src = Input == 0 ? Src1 : Src2;
2622 if (RangeUse[Input] == 0)
2623 Src = DAG.getUNDEF(VT);
2625 SDLoc dl = getCurSDLoc();
2627 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2628 DAG.getConstant(StartIdx[Input], dl, TLI.getVectorIdxTy()));
2632 // Calculate new mask.
2633 SmallVector<int, 8> MappedOps;
2634 for (unsigned i = 0; i != MaskNumElts; ++i) {
2637 if (Idx < (int)SrcNumElts)
2640 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2642 MappedOps.push_back(Idx);
2645 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2651 // We can't use either concat vectors or extract subvectors so fall back to
2652 // replacing the shuffle with extract and build vector.
2653 // to insert and build vector.
2654 EVT EltVT = VT.getVectorElementType();
2655 EVT IdxVT = TLI.getVectorIdxTy();
2656 SDLoc dl = getCurSDLoc();
2657 SmallVector<SDValue,8> Ops;
2658 for (unsigned i = 0; i != MaskNumElts; ++i) {
2663 Res = DAG.getUNDEF(EltVT);
2665 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2666 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2668 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2669 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2675 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2678 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2679 const Value *Op0 = I.getOperand(0);
2680 const Value *Op1 = I.getOperand(1);
2681 Type *AggTy = I.getType();
2682 Type *ValTy = Op1->getType();
2683 bool IntoUndef = isa<UndefValue>(Op0);
2684 bool FromUndef = isa<UndefValue>(Op1);
2686 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2688 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2689 SmallVector<EVT, 4> AggValueVTs;
2690 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2691 SmallVector<EVT, 4> ValValueVTs;
2692 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2694 unsigned NumAggValues = AggValueVTs.size();
2695 unsigned NumValValues = ValValueVTs.size();
2696 SmallVector<SDValue, 4> Values(NumAggValues);
2698 // Ignore an insertvalue that produces an empty object
2699 if (!NumAggValues) {
2700 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2704 SDValue Agg = getValue(Op0);
2706 // Copy the beginning value(s) from the original aggregate.
2707 for (; i != LinearIndex; ++i)
2708 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2709 SDValue(Agg.getNode(), Agg.getResNo() + i);
2710 // Copy values from the inserted value(s).
2712 SDValue Val = getValue(Op1);
2713 for (; i != LinearIndex + NumValValues; ++i)
2714 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2715 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2717 // Copy remaining value(s) from the original aggregate.
2718 for (; i != NumAggValues; ++i)
2719 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2720 SDValue(Agg.getNode(), Agg.getResNo() + i);
2722 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2723 DAG.getVTList(AggValueVTs), Values));
2726 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2727 const Value *Op0 = I.getOperand(0);
2728 Type *AggTy = Op0->getType();
2729 Type *ValTy = I.getType();
2730 bool OutOfUndef = isa<UndefValue>(Op0);
2732 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2735 SmallVector<EVT, 4> ValValueVTs;
2736 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2738 unsigned NumValValues = ValValueVTs.size();
2740 // Ignore a extractvalue that produces an empty object
2741 if (!NumValValues) {
2742 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2746 SmallVector<SDValue, 4> Values(NumValValues);
2748 SDValue Agg = getValue(Op0);
2749 // Copy out the selected value(s).
2750 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2751 Values[i - LinearIndex] =
2753 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2754 SDValue(Agg.getNode(), Agg.getResNo() + i);
2756 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2757 DAG.getVTList(ValValueVTs), Values));
2760 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2761 Value *Op0 = I.getOperand(0);
2762 // Note that the pointer operand may be a vector of pointers. Take the scalar
2763 // element which holds a pointer.
2764 Type *Ty = Op0->getType()->getScalarType();
2765 unsigned AS = Ty->getPointerAddressSpace();
2766 SDValue N = getValue(Op0);
2767 SDLoc dl = getCurSDLoc();
2769 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2771 const Value *Idx = *OI;
2772 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2773 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2776 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2777 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2778 DAG.getConstant(Offset, dl, N.getValueType()));
2781 Ty = StTy->getElementType(Field);
2783 Ty = cast<SequentialType>(Ty)->getElementType();
2784 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
2785 unsigned PtrSize = PtrTy.getSizeInBits();
2786 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2788 // If this is a constant subscript, handle it quickly.
2789 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
2792 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2793 SDValue OffsVal = DAG.getConstant(Offs, dl, PtrTy);
2794 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2798 // N = N + Idx * ElementSize;
2799 SDValue IdxN = getValue(Idx);
2801 // If the index is smaller or larger than intptr_t, truncate or extend
2803 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2805 // If this is a multiply by a power of two, turn it into a shl
2806 // immediately. This is a very common case.
2807 if (ElementSize != 1) {
2808 if (ElementSize.isPowerOf2()) {
2809 unsigned Amt = ElementSize.logBase2();
2810 IdxN = DAG.getNode(ISD::SHL, dl,
2811 N.getValueType(), IdxN,
2812 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2814 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2815 IdxN = DAG.getNode(ISD::MUL, dl,
2816 N.getValueType(), IdxN, Scale);
2820 N = DAG.getNode(ISD::ADD, dl,
2821 N.getValueType(), N, IdxN);
2828 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2829 // If this is a fixed sized alloca in the entry block of the function,
2830 // allocate it statically on the stack.
2831 if (FuncInfo.StaticAllocaMap.count(&I))
2832 return; // getValue will auto-populate this.
2834 SDLoc dl = getCurSDLoc();
2835 Type *Ty = I.getAllocatedType();
2836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2837 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
2839 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
2842 SDValue AllocSize = getValue(I.getArraySize());
2844 EVT IntPtr = TLI.getPointerTy();
2845 if (AllocSize.getValueType() != IntPtr)
2846 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2848 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2850 DAG.getConstant(TySize, dl, IntPtr));
2852 // Handle alignment. If the requested alignment is less than or equal to
2853 // the stack alignment, ignore it. If the size is greater than or equal to
2854 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2855 unsigned StackAlign =
2856 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2857 if (Align <= StackAlign)
2860 // Round the size of the allocation up to the stack alignment size
2861 // by add SA-1 to the size.
2862 AllocSize = DAG.getNode(ISD::ADD, dl,
2863 AllocSize.getValueType(), AllocSize,
2864 DAG.getIntPtrConstant(StackAlign - 1, dl));
2866 // Mask out the low bits for alignment purposes.
2867 AllocSize = DAG.getNode(ISD::AND, dl,
2868 AllocSize.getValueType(), AllocSize,
2869 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2872 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2873 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2874 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2876 DAG.setRoot(DSA.getValue(1));
2878 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2881 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2883 return visitAtomicLoad(I);
2885 const Value *SV = I.getOperand(0);
2886 SDValue Ptr = getValue(SV);
2888 Type *Ty = I.getType();
2890 bool isVolatile = I.isVolatile();
2891 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2892 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
2893 unsigned Alignment = I.getAlignment();
2896 I.getAAMetadata(AAInfo);
2897 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2899 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2900 SmallVector<EVT, 4> ValueVTs;
2901 SmallVector<uint64_t, 4> Offsets;
2902 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2903 unsigned NumValues = ValueVTs.size();
2908 bool ConstantMemory = false;
2909 if (isVolatile || NumValues > MaxParallelChains)
2910 // Serialize volatile loads with other side effects.
2912 else if (AA->pointsToConstantMemory(
2913 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2914 // Do not serialize (non-volatile) loads of constant memory with anything.
2915 Root = DAG.getEntryNode();
2916 ConstantMemory = true;
2918 // Do not serialize non-volatile loads against each other.
2919 Root = DAG.getRoot();
2922 SDLoc dl = getCurSDLoc();
2925 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2927 SmallVector<SDValue, 4> Values(NumValues);
2928 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2930 EVT PtrVT = Ptr.getValueType();
2931 unsigned ChainI = 0;
2932 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2933 // Serializing loads here may result in excessive register pressure, and
2934 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2935 // could recover a bit by hoisting nodes upward in the chain by recognizing
2936 // they are side-effect free or do not alias. The optimizer should really
2937 // avoid this case by converting large object/array copies to llvm.memcpy
2938 // (MaxParallelChains should always remain as failsafe).
2939 if (ChainI == MaxParallelChains) {
2940 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2941 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2942 makeArrayRef(Chains.data(), ChainI));
2946 SDValue A = DAG.getNode(ISD::ADD, dl,
2948 DAG.getConstant(Offsets[i], dl, PtrVT));
2949 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2950 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2951 isNonTemporal, isInvariant, Alignment, AAInfo,
2955 Chains[ChainI] = L.getValue(1);
2958 if (!ConstantMemory) {
2959 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2960 makeArrayRef(Chains.data(), ChainI));
2964 PendingLoads.push_back(Chain);
2967 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
2968 DAG.getVTList(ValueVTs), Values));
2971 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2973 return visitAtomicStore(I);
2975 const Value *SrcV = I.getOperand(0);
2976 const Value *PtrV = I.getOperand(1);
2978 SmallVector<EVT, 4> ValueVTs;
2979 SmallVector<uint64_t, 4> Offsets;
2980 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
2981 ValueVTs, &Offsets);
2982 unsigned NumValues = ValueVTs.size();
2986 // Get the lowered operands. Note that we do this after
2987 // checking if NumResults is zero, because with zero results
2988 // the operands won't have values in the map.
2989 SDValue Src = getValue(SrcV);
2990 SDValue Ptr = getValue(PtrV);
2992 SDValue Root = getRoot();
2993 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2995 EVT PtrVT = Ptr.getValueType();
2996 bool isVolatile = I.isVolatile();
2997 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2998 unsigned Alignment = I.getAlignment();
2999 SDLoc dl = getCurSDLoc();
3002 I.getAAMetadata(AAInfo);
3004 unsigned ChainI = 0;
3005 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3006 // See visitLoad comments.
3007 if (ChainI == MaxParallelChains) {
3008 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3009 makeArrayRef(Chains.data(), ChainI));
3013 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3014 DAG.getConstant(Offsets[i], dl, PtrVT));
3015 SDValue St = DAG.getStore(Root, dl,
3016 SDValue(Src.getNode(), Src.getResNo() + i),
3017 Add, MachinePointerInfo(PtrV, Offsets[i]),
3018 isVolatile, isNonTemporal, Alignment, AAInfo);
3019 Chains[ChainI] = St;
3022 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3023 makeArrayRef(Chains.data(), ChainI));
3024 DAG.setRoot(StoreNode);
3027 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3028 SDLoc sdl = getCurSDLoc();
3030 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3031 Value *PtrOperand = I.getArgOperand(1);
3032 SDValue Ptr = getValue(PtrOperand);
3033 SDValue Src0 = getValue(I.getArgOperand(0));
3034 SDValue Mask = getValue(I.getArgOperand(3));
3035 EVT VT = Src0.getValueType();
3036 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3038 Alignment = DAG.getEVTAlignment(VT);
3041 I.getAAMetadata(AAInfo);
3043 MachineMemOperand *MMO =
3044 DAG.getMachineFunction().
3045 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3046 MachineMemOperand::MOStore, VT.getStoreSize(),
3048 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3050 DAG.setRoot(StoreNode);
3051 setValue(&I, StoreNode);
3054 // Gather/scatter receive a vector of pointers.
3055 // This vector of pointers may be represented as a base pointer + vector of
3056 // indices, it depends on GEP and instruction preceeding GEP
3057 // that calculates indices
3058 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3059 SelectionDAGBuilder* SDB) {
3061 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3062 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3063 if (!Gep || Gep->getNumOperands() > 2)
3065 ShuffleVectorInst *ShuffleInst =
3066 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3067 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3068 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3069 Instruction::InsertElement)
3072 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3074 SelectionDAG& DAG = SDB->DAG;
3075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3076 // Check is the Ptr is inside current basic block
3077 // If not, look for the shuffle instruction
3078 if (SDB->findValue(Ptr))
3079 Base = SDB->getValue(Ptr);
3080 else if (SDB->findValue(ShuffleInst)) {
3081 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3082 SDLoc sdl = ShuffleNode;
3083 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
3084 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3085 DAG.getConstant(0, sdl, TLI.getVectorIdxTy()));
3086 SDB->setValue(Ptr, Base);
3091 Value *IndexVal = Gep->getOperand(1);
3092 if (SDB->findValue(IndexVal)) {
3093 Index = SDB->getValue(IndexVal);
3095 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3096 IndexVal = Sext->getOperand(0);
3097 if (SDB->findValue(IndexVal))
3098 Index = SDB->getValue(IndexVal);
3105 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3106 SDLoc sdl = getCurSDLoc();
3108 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3109 Value *Ptr = I.getArgOperand(1);
3110 SDValue Src0 = getValue(I.getArgOperand(0));
3111 SDValue Mask = getValue(I.getArgOperand(3));
3112 EVT VT = Src0.getValueType();
3113 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3115 Alignment = DAG.getEVTAlignment(VT);
3116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3119 I.getAAMetadata(AAInfo);
3123 Value *BasePtr = Ptr;
3124 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3126 Value *MemOpBasePtr = UniformBase ? BasePtr : NULL;
3127 MachineMemOperand *MMO = DAG.getMachineFunction().
3128 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3129 MachineMemOperand::MOStore, VT.getStoreSize(),
3132 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3133 Index = getValue(Ptr);
3135 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3136 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3138 DAG.setRoot(Scatter);
3139 setValue(&I, Scatter);
3142 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3143 SDLoc sdl = getCurSDLoc();
3145 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3146 Value *PtrOperand = I.getArgOperand(0);
3147 SDValue Ptr = getValue(PtrOperand);
3148 SDValue Src0 = getValue(I.getArgOperand(3));
3149 SDValue Mask = getValue(I.getArgOperand(2));
3151 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3152 EVT VT = TLI.getValueType(I.getType());
3153 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3155 Alignment = DAG.getEVTAlignment(VT);
3158 I.getAAMetadata(AAInfo);
3159 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3161 SDValue InChain = DAG.getRoot();
3162 if (AA->pointsToConstantMemory(
3163 AliasAnalysis::Location(PtrOperand,
3164 AA->getTypeStoreSize(I.getType()),
3166 // Do not serialize (non-volatile) loads of constant memory with anything.
3167 InChain = DAG.getEntryNode();
3170 MachineMemOperand *MMO =
3171 DAG.getMachineFunction().
3172 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3173 MachineMemOperand::MOLoad, VT.getStoreSize(),
3174 Alignment, AAInfo, Ranges);
3176 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3178 SDValue OutChain = Load.getValue(1);
3179 DAG.setRoot(OutChain);
3183 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3184 SDLoc sdl = getCurSDLoc();
3186 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3187 Value *Ptr = I.getArgOperand(0);
3188 SDValue Src0 = getValue(I.getArgOperand(3));
3189 SDValue Mask = getValue(I.getArgOperand(2));
3191 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3192 EVT VT = TLI.getValueType(I.getType());
3193 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3195 Alignment = DAG.getEVTAlignment(VT);
3198 I.getAAMetadata(AAInfo);
3199 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3201 SDValue Root = DAG.getRoot();
3204 Value *BasePtr = Ptr;
3205 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3206 bool ConstantMemory = false;
3207 if (UniformBase && AA->pointsToConstantMemory(
3208 AliasAnalysis::Location(BasePtr,
3209 AA->getTypeStoreSize(I.getType()),
3211 // Do not serialize (non-volatile) loads of constant memory with anything.
3212 Root = DAG.getEntryNode();
3213 ConstantMemory = true;
3216 MachineMemOperand *MMO =
3217 DAG.getMachineFunction().
3218 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : NULL),
3219 MachineMemOperand::MOLoad, VT.getStoreSize(),
3220 Alignment, AAInfo, Ranges);
3223 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3224 Index = getValue(Ptr);
3227 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3228 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3231 SDValue OutChain = Gather.getValue(1);
3232 if (!ConstantMemory)
3233 PendingLoads.push_back(OutChain);
3234 setValue(&I, Gather);
3237 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3238 SDLoc dl = getCurSDLoc();
3239 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3240 AtomicOrdering FailureOrder = I.getFailureOrdering();
3241 SynchronizationScope Scope = I.getSynchScope();
3243 SDValue InChain = getRoot();
3245 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3246 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3247 SDValue L = DAG.getAtomicCmpSwap(
3248 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3249 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3250 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3251 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3253 SDValue OutChain = L.getValue(2);
3256 DAG.setRoot(OutChain);
3259 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3260 SDLoc dl = getCurSDLoc();
3262 switch (I.getOperation()) {
3263 default: llvm_unreachable("Unknown atomicrmw operation");
3264 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3265 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3266 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3267 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3268 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3269 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3270 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3271 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3272 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3273 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3274 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3276 AtomicOrdering Order = I.getOrdering();
3277 SynchronizationScope Scope = I.getSynchScope();
3279 SDValue InChain = getRoot();
3282 DAG.getAtomic(NT, dl,
3283 getValue(I.getValOperand()).getSimpleValueType(),
3285 getValue(I.getPointerOperand()),
3286 getValue(I.getValOperand()),
3287 I.getPointerOperand(),
3288 /* Alignment=*/ 0, Order, Scope);
3290 SDValue OutChain = L.getValue(1);
3293 DAG.setRoot(OutChain);
3296 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3297 SDLoc dl = getCurSDLoc();
3298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3301 Ops[1] = DAG.getConstant(I.getOrdering(), dl, TLI.getPointerTy());
3302 Ops[2] = DAG.getConstant(I.getSynchScope(), dl, TLI.getPointerTy());
3303 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3306 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3307 SDLoc dl = getCurSDLoc();
3308 AtomicOrdering Order = I.getOrdering();
3309 SynchronizationScope Scope = I.getSynchScope();
3311 SDValue InChain = getRoot();
3313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3314 EVT VT = TLI.getValueType(I.getType());
3316 if (I.getAlignment() < VT.getSizeInBits() / 8)
3317 report_fatal_error("Cannot generate unaligned atomic load");
3319 MachineMemOperand *MMO =
3320 DAG.getMachineFunction().
3321 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3322 MachineMemOperand::MOVolatile |
3323 MachineMemOperand::MOLoad,
3325 I.getAlignment() ? I.getAlignment() :
3326 DAG.getEVTAlignment(VT));
3328 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3330 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3331 getValue(I.getPointerOperand()), MMO,
3334 SDValue OutChain = L.getValue(1);
3337 DAG.setRoot(OutChain);
3340 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3341 SDLoc dl = getCurSDLoc();
3343 AtomicOrdering Order = I.getOrdering();
3344 SynchronizationScope Scope = I.getSynchScope();
3346 SDValue InChain = getRoot();
3348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3349 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3351 if (I.getAlignment() < VT.getSizeInBits() / 8)
3352 report_fatal_error("Cannot generate unaligned atomic store");
3355 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3357 getValue(I.getPointerOperand()),
3358 getValue(I.getValueOperand()),
3359 I.getPointerOperand(), I.getAlignment(),
3362 DAG.setRoot(OutChain);
3365 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3367 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3368 unsigned Intrinsic) {
3369 bool HasChain = !I.doesNotAccessMemory();
3370 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3372 // Build the operand list.
3373 SmallVector<SDValue, 8> Ops;
3374 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3376 // We don't need to serialize loads against other loads.
3377 Ops.push_back(DAG.getRoot());
3379 Ops.push_back(getRoot());
3383 // Info is set by getTgtMemInstrinsic
3384 TargetLowering::IntrinsicInfo Info;
3385 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3386 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3388 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3389 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3390 Info.opc == ISD::INTRINSIC_W_CHAIN)
3391 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3392 TLI.getPointerTy()));
3394 // Add all operands of the call to the operand list.
3395 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3396 SDValue Op = getValue(I.getArgOperand(i));
3400 SmallVector<EVT, 4> ValueVTs;
3401 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3404 ValueVTs.push_back(MVT::Other);
3406 SDVTList VTs = DAG.getVTList(ValueVTs);
3410 if (IsTgtIntrinsic) {
3411 // This is target intrinsic that touches memory
3412 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3413 VTs, Ops, Info.memVT,
3414 MachinePointerInfo(Info.ptrVal, Info.offset),
3415 Info.align, Info.vol,
3416 Info.readMem, Info.writeMem, Info.size);
3417 } else if (!HasChain) {
3418 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3419 } else if (!I.getType()->isVoidTy()) {
3420 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3422 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3426 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3428 PendingLoads.push_back(Chain);
3433 if (!I.getType()->isVoidTy()) {
3434 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3435 EVT VT = TLI.getValueType(PTy);
3436 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3439 setValue(&I, Result);
3443 /// GetSignificand - Get the significand and build it into a floating-point
3444 /// number with exponent of 1:
3446 /// Op = (Op & 0x007fffff) | 0x3f800000;
3448 /// where Op is the hexadecimal representation of floating point value.
3450 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3451 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3452 DAG.getConstant(0x007fffff, dl, MVT::i32));
3453 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3454 DAG.getConstant(0x3f800000, dl, MVT::i32));
3455 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3458 /// GetExponent - Get the exponent:
3460 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3462 /// where Op is the hexadecimal representation of floating point value.
3464 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3466 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3467 DAG.getConstant(0x7f800000, dl, MVT::i32));
3468 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3469 DAG.getConstant(23, dl, TLI.getPointerTy()));
3470 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3471 DAG.getConstant(127, dl, MVT::i32));
3472 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3475 /// getF32Constant - Get 32-bit floating point constant.
3477 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3478 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3482 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3483 SelectionDAG &DAG) {
3484 // IntegerPartOfX = ((int32_t)(t0);
3485 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3487 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3488 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3489 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3491 // IntegerPartOfX <<= 23;
3492 IntegerPartOfX = DAG.getNode(
3493 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3494 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy()));
3496 SDValue TwoToFractionalPartOfX;
3497 if (LimitFloatPrecision <= 6) {
3498 // For floating-point precision of 6:
3500 // TwoToFractionalPartOfX =
3502 // (0.735607626f + 0.252464424f * x) * x;
3504 // error 0.0144103317, which is 6 bits
3505 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3506 getF32Constant(DAG, 0x3e814304, dl));
3507 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3508 getF32Constant(DAG, 0x3f3c50c8, dl));
3509 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3510 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3511 getF32Constant(DAG, 0x3f7f5e7e, dl));
3512 } else if (LimitFloatPrecision <= 12) {
3513 // For floating-point precision of 12:
3515 // TwoToFractionalPartOfX =
3518 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3520 // error 0.000107046256, which is 13 to 14 bits
3521 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3522 getF32Constant(DAG, 0x3da235e3, dl));
3523 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3524 getF32Constant(DAG, 0x3e65b8f3, dl));
3525 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3526 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3527 getF32Constant(DAG, 0x3f324b07, dl));
3528 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3529 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3530 getF32Constant(DAG, 0x3f7ff8fd, dl));
3531 } else { // LimitFloatPrecision <= 18
3532 // For floating-point precision of 18:
3534 // TwoToFractionalPartOfX =
3538 // (0.554906021e-1f +
3539 // (0.961591928e-2f +
3540 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3541 // error 2.47208000*10^(-7), which is better than 18 bits
3542 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3543 getF32Constant(DAG, 0x3924b03e, dl));
3544 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3545 getF32Constant(DAG, 0x3ab24b87, dl));
3546 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3547 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3548 getF32Constant(DAG, 0x3c1d8c17, dl));
3549 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3550 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3551 getF32Constant(DAG, 0x3d634a1d, dl));
3552 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3553 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3554 getF32Constant(DAG, 0x3e75fe14, dl));
3555 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3556 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3557 getF32Constant(DAG, 0x3f317234, dl));
3558 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3559 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3560 getF32Constant(DAG, 0x3f800000, dl));
3563 // Add the exponent into the result in integer domain.
3564 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3565 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3566 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3569 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3570 /// limited-precision mode.
3571 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3572 const TargetLowering &TLI) {
3573 if (Op.getValueType() == MVT::f32 &&
3574 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3576 // Put the exponent in the right bit position for later addition to the
3579 // #define LOG2OFe 1.4426950f
3580 // t0 = Op * LOG2OFe
3581 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3582 getF32Constant(DAG, 0x3fb8aa3b, dl));
3583 return getLimitedPrecisionExp2(t0, dl, DAG);
3586 // No special expansion.
3587 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3590 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3591 /// limited-precision mode.
3592 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3593 const TargetLowering &TLI) {
3594 if (Op.getValueType() == MVT::f32 &&
3595 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3596 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3598 // Scale the exponent by log(2) [0.69314718f].
3599 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3600 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3601 getF32Constant(DAG, 0x3f317218, dl));
3603 // Get the significand and build it into a floating-point number with
3605 SDValue X = GetSignificand(DAG, Op1, dl);
3607 SDValue LogOfMantissa;
3608 if (LimitFloatPrecision <= 6) {
3609 // For floating-point precision of 6:
3613 // (1.4034025f - 0.23903021f * x) * x;
3615 // error 0.0034276066, which is better than 8 bits
3616 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3617 getF32Constant(DAG, 0xbe74c456, dl));
3618 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3619 getF32Constant(DAG, 0x3fb3a2b1, dl));
3620 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3621 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3622 getF32Constant(DAG, 0x3f949a29, dl));
3623 } else if (LimitFloatPrecision <= 12) {
3624 // For floating-point precision of 12:
3630 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3632 // error 0.000061011436, which is 14 bits
3633 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3634 getF32Constant(DAG, 0xbd67b6d6, dl));
3635 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3636 getF32Constant(DAG, 0x3ee4f4b8, dl));
3637 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3638 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3639 getF32Constant(DAG, 0x3fbc278b, dl));
3640 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3641 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3642 getF32Constant(DAG, 0x40348e95, dl));
3643 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3644 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3645 getF32Constant(DAG, 0x3fdef31a, dl));
3646 } else { // LimitFloatPrecision <= 18
3647 // For floating-point precision of 18:
3655 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3657 // error 0.0000023660568, which is better than 18 bits
3658 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3659 getF32Constant(DAG, 0xbc91e5ac, dl));
3660 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3661 getF32Constant(DAG, 0x3e4350aa, dl));
3662 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3663 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3664 getF32Constant(DAG, 0x3f60d3e3, dl));
3665 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3666 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3667 getF32Constant(DAG, 0x4011cdf0, dl));
3668 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3669 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3670 getF32Constant(DAG, 0x406cfd1c, dl));
3671 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3672 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3673 getF32Constant(DAG, 0x408797cb, dl));
3674 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3675 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3676 getF32Constant(DAG, 0x4006dcab, dl));
3679 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3682 // No special expansion.
3683 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3686 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3687 /// limited-precision mode.
3688 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3689 const TargetLowering &TLI) {
3690 if (Op.getValueType() == MVT::f32 &&
3691 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3692 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3694 // Get the exponent.
3695 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3697 // Get the significand and build it into a floating-point number with
3699 SDValue X = GetSignificand(DAG, Op1, dl);
3701 // Different possible minimax approximations of significand in
3702 // floating-point for various degrees of accuracy over [1,2].
3703 SDValue Log2ofMantissa;
3704 if (LimitFloatPrecision <= 6) {
3705 // For floating-point precision of 6:
3707 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3709 // error 0.0049451742, which is more than 7 bits
3710 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3711 getF32Constant(DAG, 0xbeb08fe0, dl));
3712 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3713 getF32Constant(DAG, 0x40019463, dl));
3714 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3715 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3716 getF32Constant(DAG, 0x3fd6633d, dl));
3717 } else if (LimitFloatPrecision <= 12) {
3718 // For floating-point precision of 12:
3724 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3726 // error 0.0000876136000, which is better than 13 bits
3727 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3728 getF32Constant(DAG, 0xbda7262e, dl));
3729 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3730 getF32Constant(DAG, 0x3f25280b, dl));
3731 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3732 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3733 getF32Constant(DAG, 0x4007b923, dl));
3734 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3735 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3736 getF32Constant(DAG, 0x40823e2f, dl));
3737 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3738 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3739 getF32Constant(DAG, 0x4020d29c, dl));
3740 } else { // LimitFloatPrecision <= 18
3741 // For floating-point precision of 18:
3750 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3752 // error 0.0000018516, which is better than 18 bits
3753 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3754 getF32Constant(DAG, 0xbcd2769e, dl));
3755 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3756 getF32Constant(DAG, 0x3e8ce0b9, dl));
3757 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3758 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3759 getF32Constant(DAG, 0x3fa22ae7, dl));
3760 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3761 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3762 getF32Constant(DAG, 0x40525723, dl));
3763 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3764 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3765 getF32Constant(DAG, 0x40aaf200, dl));
3766 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3767 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3768 getF32Constant(DAG, 0x40c39dad, dl));
3769 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3770 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3771 getF32Constant(DAG, 0x4042902c, dl));
3774 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3777 // No special expansion.
3778 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3781 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3782 /// limited-precision mode.
3783 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3784 const TargetLowering &TLI) {
3785 if (Op.getValueType() == MVT::f32 &&
3786 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3787 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3789 // Scale the exponent by log10(2) [0.30102999f].
3790 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3791 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3792 getF32Constant(DAG, 0x3e9a209a, dl));
3794 // Get the significand and build it into a floating-point number with
3796 SDValue X = GetSignificand(DAG, Op1, dl);
3798 SDValue Log10ofMantissa;
3799 if (LimitFloatPrecision <= 6) {
3800 // For floating-point precision of 6:
3802 // Log10ofMantissa =
3804 // (0.60948995f - 0.10380950f * x) * x;
3806 // error 0.0014886165, which is 6 bits
3807 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3808 getF32Constant(DAG, 0xbdd49a13, dl));
3809 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3810 getF32Constant(DAG, 0x3f1c0789, dl));
3811 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3812 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3813 getF32Constant(DAG, 0x3f011300, dl));
3814 } else if (LimitFloatPrecision <= 12) {
3815 // For floating-point precision of 12:
3817 // Log10ofMantissa =
3820 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3822 // error 0.00019228036, which is better than 12 bits
3823 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3824 getF32Constant(DAG, 0x3d431f31, dl));
3825 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3826 getF32Constant(DAG, 0x3ea21fb2, dl));
3827 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3828 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3829 getF32Constant(DAG, 0x3f6ae232, dl));
3830 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3831 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3832 getF32Constant(DAG, 0x3f25f7c3, dl));
3833 } else { // LimitFloatPrecision <= 18
3834 // For floating-point precision of 18:
3836 // Log10ofMantissa =
3841 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3843 // error 0.0000037995730, which is better than 18 bits
3844 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3845 getF32Constant(DAG, 0x3c5d51ce, dl));
3846 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3847 getF32Constant(DAG, 0x3e00685a, dl));
3848 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3849 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3850 getF32Constant(DAG, 0x3efb6798, dl));
3851 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3852 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3853 getF32Constant(DAG, 0x3f88d192, dl));
3854 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3855 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3856 getF32Constant(DAG, 0x3fc4316c, dl));
3857 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3858 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3859 getF32Constant(DAG, 0x3f57ce70, dl));
3862 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3865 // No special expansion.
3866 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3869 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3870 /// limited-precision mode.
3871 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3872 const TargetLowering &TLI) {
3873 if (Op.getValueType() == MVT::f32 &&
3874 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3875 return getLimitedPrecisionExp2(Op, dl, DAG);
3877 // No special expansion.
3878 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3881 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3882 /// limited-precision mode with x == 10.0f.
3883 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3884 SelectionDAG &DAG, const TargetLowering &TLI) {
3885 bool IsExp10 = false;
3886 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3887 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3888 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3890 IsExp10 = LHSC->isExactlyValue(Ten);
3895 // Put the exponent in the right bit position for later addition to the
3898 // #define LOG2OF10 3.3219281f
3899 // t0 = Op * LOG2OF10;
3900 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3901 getF32Constant(DAG, 0x40549a78, dl));
3902 return getLimitedPrecisionExp2(t0, dl, DAG);
3905 // No special expansion.
3906 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3910 /// ExpandPowI - Expand a llvm.powi intrinsic.
3911 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3912 SelectionDAG &DAG) {
3913 // If RHS is a constant, we can expand this out to a multiplication tree,
3914 // otherwise we end up lowering to a call to __powidf2 (for example). When
3915 // optimizing for size, we only want to do this if the expansion would produce
3916 // a small number of multiplies, otherwise we do the full expansion.
3917 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3918 // Get the exponent as a positive value.
3919 unsigned Val = RHSC->getSExtValue();
3920 if ((int)Val < 0) Val = -Val;
3922 // powi(x, 0) -> 1.0
3924 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3926 const Function *F = DAG.getMachineFunction().getFunction();
3927 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3928 // If optimizing for size, don't insert too many multiplies. This
3929 // inserts up to 5 multiplies.
3930 countPopulation(Val) + Log2_32(Val) < 7) {
3931 // We use the simple binary decomposition method to generate the multiply
3932 // sequence. There are more optimal ways to do this (for example,
3933 // powi(x,15) generates one more multiply than it should), but this has
3934 // the benefit of being both really simple and much better than a libcall.
3935 SDValue Res; // Logically starts equal to 1.0
3936 SDValue CurSquare = LHS;
3940 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3942 Res = CurSquare; // 1.0*CurSquare.
3945 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3946 CurSquare, CurSquare);
3950 // If the original was negative, invert the result, producing 1/(x*x*x).
3951 if (RHSC->getSExtValue() < 0)
3952 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3953 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
3958 // Otherwise, expand to a libcall.
3959 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3962 // getTruncatedArgReg - Find underlying register used for an truncated
3964 static unsigned getTruncatedArgReg(const SDValue &N) {
3965 if (N.getOpcode() != ISD::TRUNCATE)
3968 const SDValue &Ext = N.getOperand(0);
3969 if (Ext.getOpcode() == ISD::AssertZext ||
3970 Ext.getOpcode() == ISD::AssertSext) {
3971 const SDValue &CFR = Ext.getOperand(0);
3972 if (CFR.getOpcode() == ISD::CopyFromReg)
3973 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3974 if (CFR.getOpcode() == ISD::TRUNCATE)
3975 return getTruncatedArgReg(CFR);
3980 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3981 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3982 /// At the end of instruction selection, they will be inserted to the entry BB.
3983 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
3984 const Value *V, MDLocalVariable *Variable, MDExpression *Expr,
3985 MDLocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
3986 const Argument *Arg = dyn_cast<Argument>(V);
3990 MachineFunction &MF = DAG.getMachineFunction();
3991 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
3993 // Ignore inlined function arguments here.
3995 // FIXME: Should we be checking DL->inlinedAt() to determine this?
3996 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
3999 Optional<MachineOperand> Op;
4000 // Some arguments' frame index is recorded during argument lowering.
4001 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4002 Op = MachineOperand::CreateFI(FI);
4004 if (!Op && N.getNode()) {
4006 if (N.getOpcode() == ISD::CopyFromReg)
4007 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4009 Reg = getTruncatedArgReg(N);
4010 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4011 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4012 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4017 Op = MachineOperand::CreateReg(Reg, false);
4021 // Check if ValueMap has reg number.
4022 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4023 if (VMI != FuncInfo.ValueMap.end())
4024 Op = MachineOperand::CreateReg(VMI->second, false);
4027 if (!Op && N.getNode())
4028 // Check if frame index is available.
4029 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4030 if (FrameIndexSDNode *FINode =
4031 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4032 Op = MachineOperand::CreateFI(FINode->getIndex());
4037 assert(Variable->isValidLocationForIntrinsic(DL) &&
4038 "Expected inlined-at fields to agree");
4040 FuncInfo.ArgDbgValues.push_back(
4041 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4042 Op->getReg(), Offset, Variable, Expr));
4044 FuncInfo.ArgDbgValues.push_back(
4045 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4048 .addMetadata(Variable)
4049 .addMetadata(Expr));
4054 // VisualStudio defines setjmp as _setjmp
4055 #if defined(_MSC_VER) && defined(setjmp) && \
4056 !defined(setjmp_undefined_for_msvc)
4057 # pragma push_macro("setjmp")
4059 # define setjmp_undefined_for_msvc
4062 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4063 /// we want to emit this as a call to a named external function, return the name
4064 /// otherwise lower it and return null.
4066 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4068 SDLoc sdl = getCurSDLoc();
4069 DebugLoc dl = getCurDebugLoc();
4072 switch (Intrinsic) {
4074 // By default, turn this into a target intrinsic node.
4075 visitTargetIntrinsic(I, Intrinsic);
4077 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4078 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4079 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4080 case Intrinsic::returnaddress:
4081 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4082 getValue(I.getArgOperand(0))));
4084 case Intrinsic::frameaddress:
4085 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4086 getValue(I.getArgOperand(0))));
4088 case Intrinsic::read_register: {
4089 Value *Reg = I.getArgOperand(0);
4091 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4092 EVT VT = TLI.getValueType(I.getType());
4093 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4096 case Intrinsic::write_register: {
4097 Value *Reg = I.getArgOperand(0);
4098 Value *RegValue = I.getArgOperand(1);
4099 SDValue Chain = getValue(RegValue).getOperand(0);
4101 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4102 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4103 RegName, getValue(RegValue)));
4106 case Intrinsic::setjmp:
4107 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4108 case Intrinsic::longjmp:
4109 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4110 case Intrinsic::memcpy: {
4111 // FIXME: this definition of "user defined address space" is x86-specific
4112 // Assert for address < 256 since we support only user defined address
4114 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4116 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4118 "Unknown address space");
4119 SDValue Op1 = getValue(I.getArgOperand(0));
4120 SDValue Op2 = getValue(I.getArgOperand(1));
4121 SDValue Op3 = getValue(I.getArgOperand(2));
4122 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4124 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4125 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4126 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4127 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4129 MachinePointerInfo(I.getArgOperand(0)),
4130 MachinePointerInfo(I.getArgOperand(1)));
4131 updateDAGForMaybeTailCall(MC);
4134 case Intrinsic::memset: {
4135 // FIXME: this definition of "user defined address space" is x86-specific
4136 // Assert for address < 256 since we support only user defined address
4138 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4140 "Unknown address space");
4141 SDValue Op1 = getValue(I.getArgOperand(0));
4142 SDValue Op2 = getValue(I.getArgOperand(1));
4143 SDValue Op3 = getValue(I.getArgOperand(2));
4144 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4146 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4147 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4148 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4149 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4150 isTC, MachinePointerInfo(I.getArgOperand(0)));
4151 updateDAGForMaybeTailCall(MS);
4154 case Intrinsic::memmove: {
4155 // FIXME: this definition of "user defined address space" is x86-specific
4156 // Assert for address < 256 since we support only user defined address
4158 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4160 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4162 "Unknown address space");
4163 SDValue Op1 = getValue(I.getArgOperand(0));
4164 SDValue Op2 = getValue(I.getArgOperand(1));
4165 SDValue Op3 = getValue(I.getArgOperand(2));
4166 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4168 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4169 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4170 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4171 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4172 isTC, MachinePointerInfo(I.getArgOperand(0)),
4173 MachinePointerInfo(I.getArgOperand(1)));
4174 updateDAGForMaybeTailCall(MM);
4177 case Intrinsic::dbg_declare: {
4178 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4179 MDLocalVariable *Variable = DI.getVariable();
4180 MDExpression *Expression = DI.getExpression();
4181 const Value *Address = DI.getAddress();
4182 assert(Variable && "Missing variable");
4184 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4188 // Check if address has undef value.
4189 if (isa<UndefValue>(Address) ||
4190 (Address->use_empty() && !isa<Argument>(Address))) {
4191 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4195 SDValue &N = NodeMap[Address];
4196 if (!N.getNode() && isa<Argument>(Address))
4197 // Check unused arguments map.
4198 N = UnusedArgNodeMap[Address];
4201 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4202 Address = BCI->getOperand(0);
4203 // Parameters are handled specially.
4204 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4205 isa<Argument>(Address);
4207 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4209 if (isParameter && !AI) {
4210 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4212 // Byval parameter. We have a frame index at this point.
4213 SDV = DAG.getFrameIndexDbgValue(
4214 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4216 // Address is an argument, so try to emit its dbg value using
4217 // virtual register info from the FuncInfo.ValueMap.
4218 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4223 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4224 true, 0, dl, SDNodeOrder);
4226 // Can't do anything with other non-AI cases yet.
4227 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4228 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4229 DEBUG(Address->dump());
4232 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4234 // If Address is an argument then try to emit its dbg value using
4235 // virtual register info from the FuncInfo.ValueMap.
4236 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4238 // If variable is pinned by a alloca in dominating bb then
4239 // use StaticAllocaMap.
4240 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4241 if (AI->getParent() != DI.getParent()) {
4242 DenseMap<const AllocaInst*, int>::iterator SI =
4243 FuncInfo.StaticAllocaMap.find(AI);
4244 if (SI != FuncInfo.StaticAllocaMap.end()) {
4245 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4246 0, dl, SDNodeOrder);
4247 DAG.AddDbgValue(SDV, nullptr, false);
4252 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4257 case Intrinsic::dbg_value: {
4258 const DbgValueInst &DI = cast<DbgValueInst>(I);
4259 assert(DI.getVariable() && "Missing variable");
4261 MDLocalVariable *Variable = DI.getVariable();
4262 MDExpression *Expression = DI.getExpression();
4263 uint64_t Offset = DI.getOffset();
4264 const Value *V = DI.getValue();
4269 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4270 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4272 DAG.AddDbgValue(SDV, nullptr, false);
4274 // Do not use getValue() in here; we don't want to generate code at
4275 // this point if it hasn't been done yet.
4276 SDValue N = NodeMap[V];
4277 if (!N.getNode() && isa<Argument>(V))
4278 // Check unused arguments map.
4279 N = UnusedArgNodeMap[V];
4281 // A dbg.value for an alloca is always indirect.
4282 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4283 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4285 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4286 IsIndirect, Offset, dl, SDNodeOrder);
4287 DAG.AddDbgValue(SDV, N.getNode(), false);
4289 } else if (!V->use_empty() ) {
4290 // Do not call getValue(V) yet, as we don't want to generate code.
4291 // Remember it for later.
4292 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4293 DanglingDebugInfoMap[V] = DDI;
4295 // We may expand this to cover more cases. One case where we have no
4296 // data available is an unreferenced parameter.
4297 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4301 // Build a debug info table entry.
4302 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4303 V = BCI->getOperand(0);
4304 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4305 // Don't handle byval struct arguments or VLAs, for example.
4307 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4308 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4311 DenseMap<const AllocaInst*, int>::iterator SI =
4312 FuncInfo.StaticAllocaMap.find(AI);
4313 if (SI == FuncInfo.StaticAllocaMap.end())
4314 return nullptr; // VLAs.
4318 case Intrinsic::eh_typeid_for: {
4319 // Find the type id for the given typeinfo.
4320 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4321 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4322 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4327 case Intrinsic::eh_return_i32:
4328 case Intrinsic::eh_return_i64:
4329 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4330 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4333 getValue(I.getArgOperand(0)),
4334 getValue(I.getArgOperand(1))));
4336 case Intrinsic::eh_unwind_init:
4337 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4339 case Intrinsic::eh_dwarf_cfa: {
4340 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4341 TLI.getPointerTy());
4342 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4343 CfaArg.getValueType(),
4344 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4345 CfaArg.getValueType()),
4347 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4348 DAG.getConstant(0, sdl, TLI.getPointerTy()));
4349 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4353 case Intrinsic::eh_sjlj_callsite: {
4354 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4355 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4356 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4357 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4359 MMI.setCurrentCallSite(CI->getZExtValue());
4362 case Intrinsic::eh_sjlj_functioncontext: {
4363 // Get and store the index of the function context.
4364 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4366 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4367 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4368 MFI->setFunctionContextIndex(FI);
4371 case Intrinsic::eh_sjlj_setjmp: {
4374 Ops[1] = getValue(I.getArgOperand(0));
4375 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4376 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4377 setValue(&I, Op.getValue(0));
4378 DAG.setRoot(Op.getValue(1));
4381 case Intrinsic::eh_sjlj_longjmp: {
4382 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4383 getRoot(), getValue(I.getArgOperand(0))));
4387 case Intrinsic::masked_gather:
4388 visitMaskedGather(I);
4389 case Intrinsic::masked_load:
4392 case Intrinsic::masked_scatter:
4393 visitMaskedScatter(I);
4394 case Intrinsic::masked_store:
4395 visitMaskedStore(I);
4397 case Intrinsic::x86_mmx_pslli_w:
4398 case Intrinsic::x86_mmx_pslli_d:
4399 case Intrinsic::x86_mmx_pslli_q:
4400 case Intrinsic::x86_mmx_psrli_w:
4401 case Intrinsic::x86_mmx_psrli_d:
4402 case Intrinsic::x86_mmx_psrli_q:
4403 case Intrinsic::x86_mmx_psrai_w:
4404 case Intrinsic::x86_mmx_psrai_d: {
4405 SDValue ShAmt = getValue(I.getArgOperand(1));
4406 if (isa<ConstantSDNode>(ShAmt)) {
4407 visitTargetIntrinsic(I, Intrinsic);
4410 unsigned NewIntrinsic = 0;
4411 EVT ShAmtVT = MVT::v2i32;
4412 switch (Intrinsic) {
4413 case Intrinsic::x86_mmx_pslli_w:
4414 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4416 case Intrinsic::x86_mmx_pslli_d:
4417 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4419 case Intrinsic::x86_mmx_pslli_q:
4420 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4422 case Intrinsic::x86_mmx_psrli_w:
4423 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4425 case Intrinsic::x86_mmx_psrli_d:
4426 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4428 case Intrinsic::x86_mmx_psrli_q:
4429 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4431 case Intrinsic::x86_mmx_psrai_w:
4432 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4434 case Intrinsic::x86_mmx_psrai_d:
4435 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4437 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4440 // The vector shift intrinsics with scalars uses 32b shift amounts but
4441 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4443 // We must do this early because v2i32 is not a legal type.
4446 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4447 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4448 EVT DestVT = TLI.getValueType(I.getType());
4449 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4450 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4451 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4452 getValue(I.getArgOperand(0)), ShAmt);
4456 case Intrinsic::convertff:
4457 case Intrinsic::convertfsi:
4458 case Intrinsic::convertfui:
4459 case Intrinsic::convertsif:
4460 case Intrinsic::convertuif:
4461 case Intrinsic::convertss:
4462 case Intrinsic::convertsu:
4463 case Intrinsic::convertus:
4464 case Intrinsic::convertuu: {
4465 ISD::CvtCode Code = ISD::CVT_INVALID;
4466 switch (Intrinsic) {
4467 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4468 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4469 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4470 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4471 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4472 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4473 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4474 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4475 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4476 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4478 EVT DestVT = TLI.getValueType(I.getType());
4479 const Value *Op1 = I.getArgOperand(0);
4480 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4481 DAG.getValueType(DestVT),
4482 DAG.getValueType(getValue(Op1).getValueType()),
4483 getValue(I.getArgOperand(1)),
4484 getValue(I.getArgOperand(2)),
4489 case Intrinsic::powi:
4490 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4491 getValue(I.getArgOperand(1)), DAG));
4493 case Intrinsic::log:
4494 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4496 case Intrinsic::log2:
4497 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4499 case Intrinsic::log10:
4500 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4502 case Intrinsic::exp:
4503 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4505 case Intrinsic::exp2:
4506 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4508 case Intrinsic::pow:
4509 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4510 getValue(I.getArgOperand(1)), DAG, TLI));
4512 case Intrinsic::sqrt:
4513 case Intrinsic::fabs:
4514 case Intrinsic::sin:
4515 case Intrinsic::cos:
4516 case Intrinsic::floor:
4517 case Intrinsic::ceil:
4518 case Intrinsic::trunc:
4519 case Intrinsic::rint:
4520 case Intrinsic::nearbyint:
4521 case Intrinsic::round: {
4523 switch (Intrinsic) {
4524 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4525 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4526 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4527 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4528 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4529 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4530 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4531 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4532 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4533 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4534 case Intrinsic::round: Opcode = ISD::FROUND; break;
4537 setValue(&I, DAG.getNode(Opcode, sdl,
4538 getValue(I.getArgOperand(0)).getValueType(),
4539 getValue(I.getArgOperand(0))));
4542 case Intrinsic::minnum:
4543 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4544 getValue(I.getArgOperand(0)).getValueType(),
4545 getValue(I.getArgOperand(0)),
4546 getValue(I.getArgOperand(1))));
4548 case Intrinsic::maxnum:
4549 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4550 getValue(I.getArgOperand(0)).getValueType(),
4551 getValue(I.getArgOperand(0)),
4552 getValue(I.getArgOperand(1))));
4554 case Intrinsic::copysign:
4555 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4556 getValue(I.getArgOperand(0)).getValueType(),
4557 getValue(I.getArgOperand(0)),
4558 getValue(I.getArgOperand(1))));
4560 case Intrinsic::fma:
4561 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4562 getValue(I.getArgOperand(0)).getValueType(),
4563 getValue(I.getArgOperand(0)),
4564 getValue(I.getArgOperand(1)),
4565 getValue(I.getArgOperand(2))));
4567 case Intrinsic::fmuladd: {
4568 EVT VT = TLI.getValueType(I.getType());
4569 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4570 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4571 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4572 getValue(I.getArgOperand(0)).getValueType(),
4573 getValue(I.getArgOperand(0)),
4574 getValue(I.getArgOperand(1)),
4575 getValue(I.getArgOperand(2))));
4577 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4578 getValue(I.getArgOperand(0)).getValueType(),
4579 getValue(I.getArgOperand(0)),
4580 getValue(I.getArgOperand(1)));
4581 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4582 getValue(I.getArgOperand(0)).getValueType(),
4584 getValue(I.getArgOperand(2)));
4589 case Intrinsic::convert_to_fp16:
4590 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4591 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4592 getValue(I.getArgOperand(0)),
4593 DAG.getTargetConstant(0, sdl,
4596 case Intrinsic::convert_from_fp16:
4598 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
4599 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4600 getValue(I.getArgOperand(0)))));
4602 case Intrinsic::pcmarker: {
4603 SDValue Tmp = getValue(I.getArgOperand(0));
4604 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4607 case Intrinsic::readcyclecounter: {
4608 SDValue Op = getRoot();
4609 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4610 DAG.getVTList(MVT::i64, MVT::Other), Op);
4612 DAG.setRoot(Res.getValue(1));
4615 case Intrinsic::bswap:
4616 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4617 getValue(I.getArgOperand(0)).getValueType(),
4618 getValue(I.getArgOperand(0))));
4620 case Intrinsic::cttz: {
4621 SDValue Arg = getValue(I.getArgOperand(0));
4622 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4623 EVT Ty = Arg.getValueType();
4624 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4628 case Intrinsic::ctlz: {
4629 SDValue Arg = getValue(I.getArgOperand(0));
4630 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4631 EVT Ty = Arg.getValueType();
4632 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4636 case Intrinsic::ctpop: {
4637 SDValue Arg = getValue(I.getArgOperand(0));
4638 EVT Ty = Arg.getValueType();
4639 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4642 case Intrinsic::stacksave: {
4643 SDValue Op = getRoot();
4644 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4645 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
4647 DAG.setRoot(Res.getValue(1));
4650 case Intrinsic::stackrestore: {
4651 Res = getValue(I.getArgOperand(0));
4652 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4655 case Intrinsic::stackprotector: {
4656 // Emit code into the DAG to store the stack guard onto the stack.
4657 MachineFunction &MF = DAG.getMachineFunction();
4658 MachineFrameInfo *MFI = MF.getFrameInfo();
4659 EVT PtrTy = TLI.getPointerTy();
4660 SDValue Src, Chain = getRoot();
4661 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4662 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4664 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4665 // global variable __stack_chk_guard.
4667 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4668 if (BC->getOpcode() == Instruction::BitCast)
4669 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4671 if (GV && TLI.useLoadStackGuardNode()) {
4672 // Emit a LOAD_STACK_GUARD node.
4673 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4675 MachinePointerInfo MPInfo(GV);
4676 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4677 unsigned Flags = MachineMemOperand::MOLoad |
4678 MachineMemOperand::MOInvariant;
4679 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4680 PtrTy.getSizeInBits() / 8,
4681 DAG.getEVTAlignment(PtrTy));
4682 Node->setMemRefs(MemRefs, MemRefs + 1);
4684 // Copy the guard value to a virtual register so that it can be
4685 // retrieved in the epilogue.
4686 Src = SDValue(Node, 0);
4687 const TargetRegisterClass *RC =
4688 TLI.getRegClassFor(Src.getSimpleValueType());
4689 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4691 SPDescriptor.setGuardReg(Reg);
4692 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4694 Src = getValue(I.getArgOperand(0)); // The guard's value.
4697 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4699 int FI = FuncInfo.StaticAllocaMap[Slot];
4700 MFI->setStackProtectorIndex(FI);
4702 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4704 // Store the stack protector onto the stack.
4705 Res = DAG.getStore(Chain, sdl, Src, FIN,
4706 MachinePointerInfo::getFixedStack(FI),
4712 case Intrinsic::objectsize: {
4713 // If we don't know by now, we're never going to know.
4714 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4716 assert(CI && "Non-constant type in __builtin_object_size?");
4718 SDValue Arg = getValue(I.getCalledValue());
4719 EVT Ty = Arg.getValueType();
4722 Res = DAG.getConstant(-1ULL, sdl, Ty);
4724 Res = DAG.getConstant(0, sdl, Ty);
4729 case Intrinsic::annotation:
4730 case Intrinsic::ptr_annotation:
4731 // Drop the intrinsic, but forward the value
4732 setValue(&I, getValue(I.getOperand(0)));
4734 case Intrinsic::assume:
4735 case Intrinsic::var_annotation:
4736 // Discard annotate attributes and assumptions
4739 case Intrinsic::init_trampoline: {
4740 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4744 Ops[1] = getValue(I.getArgOperand(0));
4745 Ops[2] = getValue(I.getArgOperand(1));
4746 Ops[3] = getValue(I.getArgOperand(2));
4747 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4748 Ops[5] = DAG.getSrcValue(F);
4750 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4755 case Intrinsic::adjust_trampoline: {
4756 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4758 getValue(I.getArgOperand(0))));
4761 case Intrinsic::gcroot:
4763 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4764 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4766 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4767 GFI->addStackRoot(FI->getIndex(), TypeMap);
4770 case Intrinsic::gcread:
4771 case Intrinsic::gcwrite:
4772 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4773 case Intrinsic::flt_rounds:
4774 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4777 case Intrinsic::expect: {
4778 // Just replace __builtin_expect(exp, c) with EXP.
4779 setValue(&I, getValue(I.getArgOperand(0)));
4783 case Intrinsic::debugtrap:
4784 case Intrinsic::trap: {
4785 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
4786 if (TrapFuncName.empty()) {
4787 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4788 ISD::TRAP : ISD::DEBUGTRAP;
4789 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4792 TargetLowering::ArgListTy Args;
4794 TargetLowering::CallLoweringInfo CLI(DAG);
4795 CLI.setDebugLoc(sdl).setChain(getRoot())
4796 .setCallee(CallingConv::C, I.getType(),
4797 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4798 std::move(Args), 0);
4800 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4801 DAG.setRoot(Result.second);
4805 case Intrinsic::uadd_with_overflow:
4806 case Intrinsic::sadd_with_overflow:
4807 case Intrinsic::usub_with_overflow:
4808 case Intrinsic::ssub_with_overflow:
4809 case Intrinsic::umul_with_overflow:
4810 case Intrinsic::smul_with_overflow: {
4812 switch (Intrinsic) {
4813 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4814 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4815 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4816 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4817 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4818 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4819 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4821 SDValue Op1 = getValue(I.getArgOperand(0));
4822 SDValue Op2 = getValue(I.getArgOperand(1));
4824 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4825 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4828 case Intrinsic::prefetch: {
4830 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4832 Ops[1] = getValue(I.getArgOperand(0));
4833 Ops[2] = getValue(I.getArgOperand(1));
4834 Ops[3] = getValue(I.getArgOperand(2));
4835 Ops[4] = getValue(I.getArgOperand(3));
4836 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4837 DAG.getVTList(MVT::Other), Ops,
4838 EVT::getIntegerVT(*Context, 8),
4839 MachinePointerInfo(I.getArgOperand(0)),
4841 false, /* volatile */
4843 rw==1)); /* write */
4846 case Intrinsic::lifetime_start:
4847 case Intrinsic::lifetime_end: {
4848 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4849 // Stack coloring is not enabled in O0, discard region information.
4850 if (TM.getOptLevel() == CodeGenOpt::None)
4853 SmallVector<Value *, 4> Allocas;
4854 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4856 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4857 E = Allocas.end(); Object != E; ++Object) {
4858 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4860 // Could not find an Alloca.
4861 if (!LifetimeObject)
4864 // First check that the Alloca is static, otherwise it won't have a
4865 // valid frame index.
4866 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4867 if (SI == FuncInfo.StaticAllocaMap.end())
4870 int FI = SI->second;
4874 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
4875 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4877 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4882 case Intrinsic::invariant_start:
4883 // Discard region information.
4884 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4886 case Intrinsic::invariant_end:
4887 // Discard region information.
4889 case Intrinsic::stackprotectorcheck: {
4890 // Do not actually emit anything for this basic block. Instead we initialize
4891 // the stack protector descriptor and export the guard variable so we can
4892 // access it in FinishBasicBlock.
4893 const BasicBlock *BB = I.getParent();
4894 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4895 ExportFromCurrentBlock(SPDescriptor.getGuard());
4897 // Flush our exports since we are going to process a terminator.
4898 (void)getControlRoot();
4901 case Intrinsic::clear_cache:
4902 return TLI.getClearCacheBuiltinName();
4903 case Intrinsic::eh_actions:
4904 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4906 case Intrinsic::donothing:
4909 case Intrinsic::experimental_stackmap: {
4913 case Intrinsic::experimental_patchpoint_void:
4914 case Intrinsic::experimental_patchpoint_i64: {
4915 visitPatchpoint(&I);
4918 case Intrinsic::experimental_gc_statepoint: {
4922 case Intrinsic::experimental_gc_result_int:
4923 case Intrinsic::experimental_gc_result_float:
4924 case Intrinsic::experimental_gc_result_ptr:
4925 case Intrinsic::experimental_gc_result: {
4929 case Intrinsic::experimental_gc_relocate: {
4933 case Intrinsic::instrprof_increment:
4934 llvm_unreachable("instrprof failed to lower an increment");
4936 case Intrinsic::frameescape: {
4937 MachineFunction &MF = DAG.getMachineFunction();
4938 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4940 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
4941 // is the same on all targets.
4942 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4943 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4944 if (isa<ConstantPointerNull>(Arg))
4945 continue; // Skip null pointers. They represent a hole in index space.
4946 AllocaInst *Slot = cast<AllocaInst>(Arg);
4947 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4948 "can only escape static allocas");
4949 int FI = FuncInfo.StaticAllocaMap[Slot];
4950 MCSymbol *FrameAllocSym =
4951 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4952 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4953 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4954 TII->get(TargetOpcode::FRAME_ALLOC))
4955 .addSym(FrameAllocSym)
4962 case Intrinsic::framerecover: {
4963 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
4964 MachineFunction &MF = DAG.getMachineFunction();
4965 MVT PtrVT = TLI.getPointerTy(0);
4967 // Get the symbol that defines the frame offset.
4968 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
4969 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
4970 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
4971 MCSymbol *FrameAllocSym =
4972 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4973 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
4975 // Create a TargetExternalSymbol for the label to avoid any target lowering
4976 // that would make this PC relative.
4977 StringRef Name = FrameAllocSym->getName();
4978 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
4979 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
4981 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
4983 // Add the offset to the FP.
4984 Value *FP = I.getArgOperand(1);
4985 SDValue FPVal = getValue(FP);
4986 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
4991 case Intrinsic::eh_begincatch:
4992 case Intrinsic::eh_endcatch:
4993 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
4994 case Intrinsic::eh_exceptioncode: {
4995 unsigned Reg = TLI.getExceptionPointerRegister();
4996 assert(Reg && "cannot get exception code on this platform");
4997 MVT PtrVT = TLI.getPointerTy();
4998 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
4999 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5001 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5002 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5009 std::pair<SDValue, SDValue>
5010 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5011 MachineBasicBlock *LandingPad) {
5012 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5013 MCSymbol *BeginLabel = nullptr;
5016 // Insert a label before the invoke call to mark the try range. This can be
5017 // used to detect deletion of the invoke via the MachineModuleInfo.
5018 BeginLabel = MMI.getContext().CreateTempSymbol();
5020 // For SjLj, keep track of which landing pads go with which invokes
5021 // so as to maintain the ordering of pads in the LSDA.
5022 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5023 if (CallSiteIndex) {
5024 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5025 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5027 // Now that the call site is handled, stop tracking it.
5028 MMI.setCurrentCallSite(0);
5031 // Both PendingLoads and PendingExports must be flushed here;
5032 // this call might not return.
5034 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5036 CLI.setChain(getRoot());
5038 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5039 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5041 assert((CLI.IsTailCall || Result.second.getNode()) &&
5042 "Non-null chain expected with non-tail call!");
5043 assert((Result.second.getNode() || !Result.first.getNode()) &&
5044 "Null value expected with tail call!");
5046 if (!Result.second.getNode()) {
5047 // As a special case, a null chain means that a tail call has been emitted
5048 // and the DAG root is already updated.
5051 // Since there's no actual continuation from this block, nothing can be
5052 // relying on us setting vregs for them.
5053 PendingExports.clear();
5055 DAG.setRoot(Result.second);
5059 // Insert a label at the end of the invoke call to mark the try range. This
5060 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5061 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5062 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5064 // Inform MachineModuleInfo of range.
5065 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5071 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5073 MachineBasicBlock *LandingPad) {
5074 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5075 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5076 Type *RetTy = FTy->getReturnType();
5078 TargetLowering::ArgListTy Args;
5079 TargetLowering::ArgListEntry Entry;
5080 Args.reserve(CS.arg_size());
5082 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5084 const Value *V = *i;
5087 if (V->getType()->isEmptyTy())
5090 SDValue ArgNode = getValue(V);
5091 Entry.Node = ArgNode; Entry.Ty = V->getType();
5093 // Skip the first return-type Attribute to get to params.
5094 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5095 Args.push_back(Entry);
5097 // If we have an explicit sret argument that is an Instruction, (i.e., it
5098 // might point to function-local memory), we can't meaningfully tail-call.
5099 if (Entry.isSRet && isa<Instruction>(V))
5103 // Check if target-independent constraints permit a tail call here.
5104 // Target-dependent constraints are checked within TLI->LowerCallTo.
5105 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5108 TargetLowering::CallLoweringInfo CLI(DAG);
5109 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5110 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5111 .setTailCall(isTailCall);
5112 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5114 if (Result.first.getNode())
5115 setValue(CS.getInstruction(), Result.first);
5118 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5119 /// value is equal or not-equal to zero.
5120 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5121 for (const User *U : V->users()) {
5122 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5123 if (IC->isEquality())
5124 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5125 if (C->isNullValue())
5127 // Unknown instruction.
5133 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5135 SelectionDAGBuilder &Builder) {
5137 // Check to see if this load can be trivially constant folded, e.g. if the
5138 // input is from a string literal.
5139 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5140 // Cast pointer to the type we really want to load.
5141 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5142 PointerType::getUnqual(LoadTy));
5144 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5145 const_cast<Constant *>(LoadInput), *Builder.DL))
5146 return Builder.getValue(LoadCst);
5149 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5150 // still constant memory, the input chain can be the entry node.
5152 bool ConstantMemory = false;
5154 // Do not serialize (non-volatile) loads of constant memory with anything.
5155 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5156 Root = Builder.DAG.getEntryNode();
5157 ConstantMemory = true;
5159 // Do not serialize non-volatile loads against each other.
5160 Root = Builder.DAG.getRoot();
5163 SDValue Ptr = Builder.getValue(PtrVal);
5164 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5165 Ptr, MachinePointerInfo(PtrVal),
5167 false /*nontemporal*/,
5168 false /*isinvariant*/, 1 /* align=1 */);
5170 if (!ConstantMemory)
5171 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5175 /// processIntegerCallValue - Record the value for an instruction that
5176 /// produces an integer result, converting the type where necessary.
5177 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5180 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5182 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5184 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5185 setValue(&I, Value);
5188 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5189 /// If so, return true and lower it, otherwise return false and it will be
5190 /// lowered like a normal call.
5191 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5192 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5193 if (I.getNumArgOperands() != 3)
5196 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5197 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5198 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5199 !I.getType()->isIntegerTy())
5202 const Value *Size = I.getArgOperand(2);
5203 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5204 if (CSize && CSize->getZExtValue() == 0) {
5205 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5206 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5210 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5211 std::pair<SDValue, SDValue> Res =
5212 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5213 getValue(LHS), getValue(RHS), getValue(Size),
5214 MachinePointerInfo(LHS),
5215 MachinePointerInfo(RHS));
5216 if (Res.first.getNode()) {
5217 processIntegerCallValue(I, Res.first, true);
5218 PendingLoads.push_back(Res.second);
5222 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5223 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5224 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5225 bool ActuallyDoIt = true;
5228 switch (CSize->getZExtValue()) {
5230 LoadVT = MVT::Other;
5232 ActuallyDoIt = false;
5236 LoadTy = Type::getInt16Ty(CSize->getContext());
5240 LoadTy = Type::getInt32Ty(CSize->getContext());
5244 LoadTy = Type::getInt64Ty(CSize->getContext());
5248 LoadVT = MVT::v4i32;
5249 LoadTy = Type::getInt32Ty(CSize->getContext());
5250 LoadTy = VectorType::get(LoadTy, 4);
5255 // This turns into unaligned loads. We only do this if the target natively
5256 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5257 // we'll only produce a small number of byte loads.
5259 // Require that we can find a legal MVT, and only do this if the target
5260 // supports unaligned loads of that type. Expanding into byte loads would
5262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5263 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5264 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5265 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5266 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5267 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5268 // TODO: Check alignment of src and dest ptrs.
5269 if (!TLI.isTypeLegal(LoadVT) ||
5270 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5271 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5272 ActuallyDoIt = false;
5276 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5277 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5279 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5281 processIntegerCallValue(I, Res, false);
5290 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5291 /// form. If so, return true and lower it, otherwise return false and it
5292 /// will be lowered like a normal call.
5293 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5294 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5295 if (I.getNumArgOperands() != 3)
5298 const Value *Src = I.getArgOperand(0);
5299 const Value *Char = I.getArgOperand(1);
5300 const Value *Length = I.getArgOperand(2);
5301 if (!Src->getType()->isPointerTy() ||
5302 !Char->getType()->isIntegerTy() ||
5303 !Length->getType()->isIntegerTy() ||
5304 !I.getType()->isPointerTy())
5307 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5308 std::pair<SDValue, SDValue> Res =
5309 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5310 getValue(Src), getValue(Char), getValue(Length),
5311 MachinePointerInfo(Src));
5312 if (Res.first.getNode()) {
5313 setValue(&I, Res.first);
5314 PendingLoads.push_back(Res.second);
5321 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5322 /// optimized form. If so, return true and lower it, otherwise return false
5323 /// and it will be lowered like a normal call.
5324 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5325 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5326 if (I.getNumArgOperands() != 2)
5329 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5330 if (!Arg0->getType()->isPointerTy() ||
5331 !Arg1->getType()->isPointerTy() ||
5332 !I.getType()->isPointerTy())
5335 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5336 std::pair<SDValue, SDValue> Res =
5337 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5338 getValue(Arg0), getValue(Arg1),
5339 MachinePointerInfo(Arg0),
5340 MachinePointerInfo(Arg1), isStpcpy);
5341 if (Res.first.getNode()) {
5342 setValue(&I, Res.first);
5343 DAG.setRoot(Res.second);
5350 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5351 /// If so, return true and lower it, otherwise return false and it will be
5352 /// lowered like a normal call.
5353 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5354 // Verify that the prototype makes sense. int strcmp(void*,void*)
5355 if (I.getNumArgOperands() != 2)
5358 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5359 if (!Arg0->getType()->isPointerTy() ||
5360 !Arg1->getType()->isPointerTy() ||
5361 !I.getType()->isIntegerTy())
5364 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5365 std::pair<SDValue, SDValue> Res =
5366 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5367 getValue(Arg0), getValue(Arg1),
5368 MachinePointerInfo(Arg0),
5369 MachinePointerInfo(Arg1));
5370 if (Res.first.getNode()) {
5371 processIntegerCallValue(I, Res.first, true);
5372 PendingLoads.push_back(Res.second);
5379 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5380 /// form. If so, return true and lower it, otherwise return false and it
5381 /// will be lowered like a normal call.
5382 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5383 // Verify that the prototype makes sense. size_t strlen(char *)
5384 if (I.getNumArgOperands() != 1)
5387 const Value *Arg0 = I.getArgOperand(0);
5388 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5391 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5392 std::pair<SDValue, SDValue> Res =
5393 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5394 getValue(Arg0), MachinePointerInfo(Arg0));
5395 if (Res.first.getNode()) {
5396 processIntegerCallValue(I, Res.first, false);
5397 PendingLoads.push_back(Res.second);
5404 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5405 /// form. If so, return true and lower it, otherwise return false and it
5406 /// will be lowered like a normal call.
5407 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5408 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5409 if (I.getNumArgOperands() != 2)
5412 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5413 if (!Arg0->getType()->isPointerTy() ||
5414 !Arg1->getType()->isIntegerTy() ||
5415 !I.getType()->isIntegerTy())
5418 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5419 std::pair<SDValue, SDValue> Res =
5420 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5421 getValue(Arg0), getValue(Arg1),
5422 MachinePointerInfo(Arg0));
5423 if (Res.first.getNode()) {
5424 processIntegerCallValue(I, Res.first, false);
5425 PendingLoads.push_back(Res.second);
5432 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5433 /// operation (as expected), translate it to an SDNode with the specified opcode
5434 /// and return true.
5435 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5437 // Sanity check that it really is a unary floating-point call.
5438 if (I.getNumArgOperands() != 1 ||
5439 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5440 I.getType() != I.getArgOperand(0)->getType() ||
5441 !I.onlyReadsMemory())
5444 SDValue Tmp = getValue(I.getArgOperand(0));
5445 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5449 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5450 /// operation (as expected), translate it to an SDNode with the specified opcode
5451 /// and return true.
5452 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5454 // Sanity check that it really is a binary floating-point call.
5455 if (I.getNumArgOperands() != 2 ||
5456 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5457 I.getType() != I.getArgOperand(0)->getType() ||
5458 I.getType() != I.getArgOperand(1)->getType() ||
5459 !I.onlyReadsMemory())
5462 SDValue Tmp0 = getValue(I.getArgOperand(0));
5463 SDValue Tmp1 = getValue(I.getArgOperand(1));
5464 EVT VT = Tmp0.getValueType();
5465 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5469 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5470 // Handle inline assembly differently.
5471 if (isa<InlineAsm>(I.getCalledValue())) {
5476 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5477 ComputeUsesVAFloatArgument(I, &MMI);
5479 const char *RenameFn = nullptr;
5480 if (Function *F = I.getCalledFunction()) {
5481 if (F->isDeclaration()) {
5482 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5483 if (unsigned IID = II->getIntrinsicID(F)) {
5484 RenameFn = visitIntrinsicCall(I, IID);
5489 if (unsigned IID = F->getIntrinsicID()) {
5490 RenameFn = visitIntrinsicCall(I, IID);
5496 // Check for well-known libc/libm calls. If the function is internal, it
5497 // can't be a library call.
5499 if (!F->hasLocalLinkage() && F->hasName() &&
5500 LibInfo->getLibFunc(F->getName(), Func) &&
5501 LibInfo->hasOptimizedCodeGen(Func)) {
5504 case LibFunc::copysign:
5505 case LibFunc::copysignf:
5506 case LibFunc::copysignl:
5507 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5508 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5509 I.getType() == I.getArgOperand(0)->getType() &&
5510 I.getType() == I.getArgOperand(1)->getType() &&
5511 I.onlyReadsMemory()) {
5512 SDValue LHS = getValue(I.getArgOperand(0));
5513 SDValue RHS = getValue(I.getArgOperand(1));
5514 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5515 LHS.getValueType(), LHS, RHS));
5520 case LibFunc::fabsf:
5521 case LibFunc::fabsl:
5522 if (visitUnaryFloatCall(I, ISD::FABS))
5526 case LibFunc::fminf:
5527 case LibFunc::fminl:
5528 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5532 case LibFunc::fmaxf:
5533 case LibFunc::fmaxl:
5534 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5540 if (visitUnaryFloatCall(I, ISD::FSIN))
5546 if (visitUnaryFloatCall(I, ISD::FCOS))
5550 case LibFunc::sqrtf:
5551 case LibFunc::sqrtl:
5552 case LibFunc::sqrt_finite:
5553 case LibFunc::sqrtf_finite:
5554 case LibFunc::sqrtl_finite:
5555 if (visitUnaryFloatCall(I, ISD::FSQRT))
5558 case LibFunc::floor:
5559 case LibFunc::floorf:
5560 case LibFunc::floorl:
5561 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5564 case LibFunc::nearbyint:
5565 case LibFunc::nearbyintf:
5566 case LibFunc::nearbyintl:
5567 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5571 case LibFunc::ceilf:
5572 case LibFunc::ceill:
5573 if (visitUnaryFloatCall(I, ISD::FCEIL))
5577 case LibFunc::rintf:
5578 case LibFunc::rintl:
5579 if (visitUnaryFloatCall(I, ISD::FRINT))
5582 case LibFunc::round:
5583 case LibFunc::roundf:
5584 case LibFunc::roundl:
5585 if (visitUnaryFloatCall(I, ISD::FROUND))
5588 case LibFunc::trunc:
5589 case LibFunc::truncf:
5590 case LibFunc::truncl:
5591 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5595 case LibFunc::log2f:
5596 case LibFunc::log2l:
5597 if (visitUnaryFloatCall(I, ISD::FLOG2))
5601 case LibFunc::exp2f:
5602 case LibFunc::exp2l:
5603 if (visitUnaryFloatCall(I, ISD::FEXP2))
5606 case LibFunc::memcmp:
5607 if (visitMemCmpCall(I))
5610 case LibFunc::memchr:
5611 if (visitMemChrCall(I))
5614 case LibFunc::strcpy:
5615 if (visitStrCpyCall(I, false))
5618 case LibFunc::stpcpy:
5619 if (visitStrCpyCall(I, true))
5622 case LibFunc::strcmp:
5623 if (visitStrCmpCall(I))
5626 case LibFunc::strlen:
5627 if (visitStrLenCall(I))
5630 case LibFunc::strnlen:
5631 if (visitStrNLenCall(I))
5640 Callee = getValue(I.getCalledValue());
5642 Callee = DAG.getExternalSymbol(RenameFn,
5643 DAG.getTargetLoweringInfo().getPointerTy());
5645 // Check if we can potentially perform a tail call. More detailed checking is
5646 // be done within LowerCallTo, after more information about the call is known.
5647 LowerCallTo(&I, Callee, I.isTailCall());
5652 /// AsmOperandInfo - This contains information for each constraint that we are
5654 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5656 /// CallOperand - If this is the result output operand or a clobber
5657 /// this is null, otherwise it is the incoming operand to the CallInst.
5658 /// This gets modified as the asm is processed.
5659 SDValue CallOperand;
5661 /// AssignedRegs - If this is a register or register class operand, this
5662 /// contains the set of register corresponding to the operand.
5663 RegsForValue AssignedRegs;
5665 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5666 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5669 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5670 /// corresponds to. If there is no Value* for this operand, it returns
5672 EVT getCallOperandValEVT(LLVMContext &Context,
5673 const TargetLowering &TLI,
5674 const DataLayout *DL) const {
5675 if (!CallOperandVal) return MVT::Other;
5677 if (isa<BasicBlock>(CallOperandVal))
5678 return TLI.getPointerTy();
5680 llvm::Type *OpTy = CallOperandVal->getType();
5682 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5683 // If this is an indirect operand, the operand is a pointer to the
5686 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5688 report_fatal_error("Indirect operand for inline asm not a pointer!");
5689 OpTy = PtrTy->getElementType();
5692 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5693 if (StructType *STy = dyn_cast<StructType>(OpTy))
5694 if (STy->getNumElements() == 1)
5695 OpTy = STy->getElementType(0);
5697 // If OpTy is not a single value, it may be a struct/union that we
5698 // can tile with integers.
5699 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5700 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
5709 OpTy = IntegerType::get(Context, BitSize);
5714 return TLI.getValueType(OpTy, true);
5718 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5720 } // end anonymous namespace
5722 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5723 /// specified operand. We prefer to assign virtual registers, to allow the
5724 /// register allocator to handle the assignment process. However, if the asm
5725 /// uses features that we can't model on machineinstrs, we have SDISel do the
5726 /// allocation. This produces generally horrible, but correct, code.
5728 /// OpInfo describes the operand.
5730 static void GetRegistersForValue(SelectionDAG &DAG,
5731 const TargetLowering &TLI,
5733 SDISelAsmOperandInfo &OpInfo) {
5734 LLVMContext &Context = *DAG.getContext();
5736 MachineFunction &MF = DAG.getMachineFunction();
5737 SmallVector<unsigned, 4> Regs;
5739 // If this is a constraint for a single physreg, or a constraint for a
5740 // register class, find it.
5741 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5742 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5743 OpInfo.ConstraintCode,
5744 OpInfo.ConstraintVT);
5746 unsigned NumRegs = 1;
5747 if (OpInfo.ConstraintVT != MVT::Other) {
5748 // If this is a FP input in an integer register (or visa versa) insert a bit
5749 // cast of the input value. More generally, handle any case where the input
5750 // value disagrees with the register class we plan to stick this in.
5751 if (OpInfo.Type == InlineAsm::isInput &&
5752 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5753 // Try to convert to the first EVT that the reg class contains. If the
5754 // types are identical size, use a bitcast to convert (e.g. two differing
5756 MVT RegVT = *PhysReg.second->vt_begin();
5757 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5758 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5759 RegVT, OpInfo.CallOperand);
5760 OpInfo.ConstraintVT = RegVT;
5761 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5762 // If the input is a FP value and we want it in FP registers, do a
5763 // bitcast to the corresponding integer type. This turns an f64 value
5764 // into i64, which can be passed with two i32 values on a 32-bit
5766 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5767 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5768 RegVT, OpInfo.CallOperand);
5769 OpInfo.ConstraintVT = RegVT;
5773 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5777 EVT ValueVT = OpInfo.ConstraintVT;
5779 // If this is a constraint for a specific physical register, like {r17},
5781 if (unsigned AssignedReg = PhysReg.first) {
5782 const TargetRegisterClass *RC = PhysReg.second;
5783 if (OpInfo.ConstraintVT == MVT::Other)
5784 ValueVT = *RC->vt_begin();
5786 // Get the actual register value type. This is important, because the user
5787 // may have asked for (e.g.) the AX register in i32 type. We need to
5788 // remember that AX is actually i16 to get the right extension.
5789 RegVT = *RC->vt_begin();
5791 // This is a explicit reference to a physical register.
5792 Regs.push_back(AssignedReg);
5794 // If this is an expanded reference, add the rest of the regs to Regs.
5796 TargetRegisterClass::iterator I = RC->begin();
5797 for (; *I != AssignedReg; ++I)
5798 assert(I != RC->end() && "Didn't find reg!");
5800 // Already added the first reg.
5802 for (; NumRegs; --NumRegs, ++I) {
5803 assert(I != RC->end() && "Ran out of registers to allocate!");
5808 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5812 // Otherwise, if this was a reference to an LLVM register class, create vregs
5813 // for this reference.
5814 if (const TargetRegisterClass *RC = PhysReg.second) {
5815 RegVT = *RC->vt_begin();
5816 if (OpInfo.ConstraintVT == MVT::Other)
5819 // Create the appropriate number of virtual registers.
5820 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5821 for (; NumRegs; --NumRegs)
5822 Regs.push_back(RegInfo.createVirtualRegister(RC));
5824 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5828 // Otherwise, we couldn't allocate enough registers for this.
5831 /// visitInlineAsm - Handle a call to an InlineAsm object.
5833 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5834 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5836 /// ConstraintOperands - Information about all of the constraints.
5837 SDISelAsmOperandInfoVector ConstraintOperands;
5839 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5840 TargetLowering::AsmOperandInfoVector TargetConstraints =
5841 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
5843 bool hasMemory = false;
5845 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5846 unsigned ResNo = 0; // ResNo - The result number of the next output.
5847 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5848 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5849 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5851 MVT OpVT = MVT::Other;
5853 // Compute the value type for each operand.
5854 switch (OpInfo.Type) {
5855 case InlineAsm::isOutput:
5856 // Indirect outputs just consume an argument.
5857 if (OpInfo.isIndirect) {
5858 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5862 // The return value of the call is this value. As such, there is no
5863 // corresponding argument.
5864 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5865 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5866 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5868 assert(ResNo == 0 && "Asm only has one result!");
5869 OpVT = TLI.getSimpleValueType(CS.getType());
5873 case InlineAsm::isInput:
5874 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5876 case InlineAsm::isClobber:
5881 // If this is an input or an indirect output, process the call argument.
5882 // BasicBlocks are labels, currently appearing only in asm's.
5883 if (OpInfo.CallOperandVal) {
5884 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5885 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5887 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5891 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
5894 OpInfo.ConstraintVT = OpVT;
5896 // Indirect operand accesses access memory.
5897 if (OpInfo.isIndirect)
5900 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5901 TargetLowering::ConstraintType
5902 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5903 if (CType == TargetLowering::C_Memory) {
5911 SDValue Chain, Flag;
5913 // We won't need to flush pending loads if this asm doesn't touch
5914 // memory and is nonvolatile.
5915 if (hasMemory || IA->hasSideEffects())
5918 Chain = DAG.getRoot();
5920 // Second pass over the constraints: compute which constraint option to use
5921 // and assign registers to constraints that want a specific physreg.
5922 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5923 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5925 // If this is an output operand with a matching input operand, look up the
5926 // matching input. If their types mismatch, e.g. one is an integer, the
5927 // other is floating point, or their sizes are different, flag it as an
5929 if (OpInfo.hasMatchingInput()) {
5930 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5932 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5933 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5934 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5935 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5936 OpInfo.ConstraintVT);
5937 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5938 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5939 Input.ConstraintVT);
5940 if ((OpInfo.ConstraintVT.isInteger() !=
5941 Input.ConstraintVT.isInteger()) ||
5942 (MatchRC.second != InputRC.second)) {
5943 report_fatal_error("Unsupported asm: input constraint"
5944 " with a matching output constraint of"
5945 " incompatible type!");
5947 Input.ConstraintVT = OpInfo.ConstraintVT;
5951 // Compute the constraint code and ConstraintType to use.
5952 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5954 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5955 OpInfo.Type == InlineAsm::isClobber)
5958 // If this is a memory input, and if the operand is not indirect, do what we
5959 // need to to provide an address for the memory input.
5960 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5961 !OpInfo.isIndirect) {
5962 assert((OpInfo.isMultipleAlternative ||
5963 (OpInfo.Type == InlineAsm::isInput)) &&
5964 "Can only indirectify direct input operands!");
5966 // Memory operands really want the address of the value. If we don't have
5967 // an indirect input, put it in the constpool if we can, otherwise spill
5968 // it to a stack slot.
5969 // TODO: This isn't quite right. We need to handle these according to
5970 // the addressing mode that the constraint wants. Also, this may take
5971 // an additional register for the computation and we don't want that
5974 // If the operand is a float, integer, or vector constant, spill to a
5975 // constant pool entry to get its address.
5976 const Value *OpVal = OpInfo.CallOperandVal;
5977 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5978 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5979 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5980 TLI.getPointerTy());
5982 // Otherwise, create a stack slot and emit a store to it before the
5984 Type *Ty = OpVal->getType();
5985 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5986 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5987 MachineFunction &MF = DAG.getMachineFunction();
5988 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5989 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5990 Chain = DAG.getStore(Chain, getCurSDLoc(),
5991 OpInfo.CallOperand, StackSlot,
5992 MachinePointerInfo::getFixedStack(SSFI),
5994 OpInfo.CallOperand = StackSlot;
5997 // There is no longer a Value* corresponding to this operand.
5998 OpInfo.CallOperandVal = nullptr;
6000 // It is now an indirect operand.
6001 OpInfo.isIndirect = true;
6004 // If this constraint is for a specific register, allocate it before
6006 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6007 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6010 // Second pass - Loop over all of the operands, assigning virtual or physregs
6011 // to register class operands.
6012 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6013 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6015 // C_Register operands have already been allocated, Other/Memory don't need
6017 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6018 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6021 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6022 std::vector<SDValue> AsmNodeOperands;
6023 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6024 AsmNodeOperands.push_back(
6025 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6026 TLI.getPointerTy()));
6028 // If we have a !srcloc metadata node associated with it, we want to attach
6029 // this to the ultimately generated inline asm machineinstr. To do this, we
6030 // pass in the third operand as this (potentially null) inline asm MDNode.
6031 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6032 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6034 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6035 // bits as operand 3.
6036 unsigned ExtraInfo = 0;
6037 if (IA->hasSideEffects())
6038 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6039 if (IA->isAlignStack())
6040 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6041 // Set the asm dialect.
6042 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6044 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6045 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6046 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6048 // Compute the constraint code and ConstraintType to use.
6049 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6051 // Ideally, we would only check against memory constraints. However, the
6052 // meaning of an other constraint can be target-specific and we can't easily
6053 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6054 // for other constriants as well.
6055 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6056 OpInfo.ConstraintType == TargetLowering::C_Other) {
6057 if (OpInfo.Type == InlineAsm::isInput)
6058 ExtraInfo |= InlineAsm::Extra_MayLoad;
6059 else if (OpInfo.Type == InlineAsm::isOutput)
6060 ExtraInfo |= InlineAsm::Extra_MayStore;
6061 else if (OpInfo.Type == InlineAsm::isClobber)
6062 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6066 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, getCurSDLoc(),
6067 TLI.getPointerTy()));
6069 // Loop over all of the inputs, copying the operand values into the
6070 // appropriate registers and processing the output regs.
6071 RegsForValue RetValRegs;
6073 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6074 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6076 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6077 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6079 switch (OpInfo.Type) {
6080 case InlineAsm::isOutput: {
6081 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6082 OpInfo.ConstraintType != TargetLowering::C_Register) {
6083 // Memory output, or 'other' output (e.g. 'X' constraint).
6084 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6086 unsigned ConstraintID =
6087 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6088 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6089 "Failed to convert memory constraint code to constraint id.");
6091 // Add information to the INLINEASM node to know about this output.
6092 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6093 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6094 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6096 AsmNodeOperands.push_back(OpInfo.CallOperand);
6100 // Otherwise, this is a register or register class output.
6102 // Copy the output from the appropriate register. Find a register that
6104 if (OpInfo.AssignedRegs.Regs.empty()) {
6105 LLVMContext &Ctx = *DAG.getContext();
6106 Ctx.emitError(CS.getInstruction(),
6107 "couldn't allocate output register for constraint '" +
6108 Twine(OpInfo.ConstraintCode) + "'");
6112 // If this is an indirect operand, store through the pointer after the
6114 if (OpInfo.isIndirect) {
6115 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6116 OpInfo.CallOperandVal));
6118 // This is the result value of the call.
6119 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6120 // Concatenate this output onto the outputs list.
6121 RetValRegs.append(OpInfo.AssignedRegs);
6124 // Add information to the INLINEASM node to know that this register is
6127 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6128 ? InlineAsm::Kind_RegDefEarlyClobber
6129 : InlineAsm::Kind_RegDef,
6130 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6133 case InlineAsm::isInput: {
6134 SDValue InOperandVal = OpInfo.CallOperand;
6136 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6137 // If this is required to match an output register we have already set,
6138 // just use its register.
6139 unsigned OperandNo = OpInfo.getMatchedOperand();
6141 // Scan until we find the definition we already emitted of this operand.
6142 // When we find it, create a RegsForValue operand.
6143 unsigned CurOp = InlineAsm::Op_FirstOperand;
6144 for (; OperandNo; --OperandNo) {
6145 // Advance to the next operand.
6147 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6148 assert((InlineAsm::isRegDefKind(OpFlag) ||
6149 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6150 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6151 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6155 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6156 if (InlineAsm::isRegDefKind(OpFlag) ||
6157 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6158 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6159 if (OpInfo.isIndirect) {
6160 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6161 LLVMContext &Ctx = *DAG.getContext();
6162 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6163 " don't know how to handle tied "
6164 "indirect register inputs");
6168 RegsForValue MatchedRegs;
6169 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6170 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6171 MatchedRegs.RegVTs.push_back(RegVT);
6172 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6173 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6175 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6176 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6178 LLVMContext &Ctx = *DAG.getContext();
6179 Ctx.emitError(CS.getInstruction(),
6180 "inline asm error: This value"
6181 " type register class is not natively supported!");
6185 SDLoc dl = getCurSDLoc();
6186 // Use the produced MatchedRegs object to
6187 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6188 Chain, &Flag, CS.getInstruction());
6189 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6190 true, OpInfo.getMatchedOperand(), dl,
6191 DAG, AsmNodeOperands);
6195 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6196 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6197 "Unexpected number of operands");
6198 // Add information to the INLINEASM node to know about this input.
6199 // See InlineAsm.h isUseOperandTiedToDef.
6200 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6201 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6202 OpInfo.getMatchedOperand());
6203 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, getCurSDLoc(),
6204 TLI.getPointerTy()));
6205 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6209 // Treat indirect 'X' constraint as memory.
6210 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6212 OpInfo.ConstraintType = TargetLowering::C_Memory;
6214 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6215 std::vector<SDValue> Ops;
6216 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6219 LLVMContext &Ctx = *DAG.getContext();
6220 Ctx.emitError(CS.getInstruction(),
6221 "invalid operand for inline asm constraint '" +
6222 Twine(OpInfo.ConstraintCode) + "'");
6226 // Add information to the INLINEASM node to know about this input.
6227 unsigned ResOpType =
6228 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6229 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6231 TLI.getPointerTy()));
6232 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6236 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6237 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6238 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6239 "Memory operands expect pointer values");
6241 unsigned ConstraintID =
6242 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6243 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6244 "Failed to convert memory constraint code to constraint id.");
6246 // Add information to the INLINEASM node to know about this input.
6247 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6248 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6249 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6252 AsmNodeOperands.push_back(InOperandVal);
6256 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6257 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6258 "Unknown constraint type!");
6260 // TODO: Support this.
6261 if (OpInfo.isIndirect) {
6262 LLVMContext &Ctx = *DAG.getContext();
6263 Ctx.emitError(CS.getInstruction(),
6264 "Don't know how to handle indirect register inputs yet "
6265 "for constraint '" +
6266 Twine(OpInfo.ConstraintCode) + "'");
6270 // Copy the input into the appropriate registers.
6271 if (OpInfo.AssignedRegs.Regs.empty()) {
6272 LLVMContext &Ctx = *DAG.getContext();
6273 Ctx.emitError(CS.getInstruction(),
6274 "couldn't allocate input reg for constraint '" +
6275 Twine(OpInfo.ConstraintCode) + "'");
6279 SDLoc dl = getCurSDLoc();
6281 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6282 Chain, &Flag, CS.getInstruction());
6284 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6285 dl, DAG, AsmNodeOperands);
6288 case InlineAsm::isClobber: {
6289 // Add the clobbered value to the operand list, so that the register
6290 // allocator is aware that the physreg got clobbered.
6291 if (!OpInfo.AssignedRegs.Regs.empty())
6292 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6293 false, 0, getCurSDLoc(), DAG,
6300 // Finish up input operands. Set the input chain and add the flag last.
6301 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6302 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6304 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6305 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6306 Flag = Chain.getValue(1);
6308 // If this asm returns a register value, copy the result from that register
6309 // and set it as the value of the call.
6310 if (!RetValRegs.Regs.empty()) {
6311 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6312 Chain, &Flag, CS.getInstruction());
6314 // FIXME: Why don't we do this for inline asms with MRVs?
6315 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6316 EVT ResultType = TLI.getValueType(CS.getType());
6318 // If any of the results of the inline asm is a vector, it may have the
6319 // wrong width/num elts. This can happen for register classes that can
6320 // contain multiple different value types. The preg or vreg allocated may
6321 // not have the same VT as was expected. Convert it to the right type
6322 // with bit_convert.
6323 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6324 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6327 } else if (ResultType != Val.getValueType() &&
6328 ResultType.isInteger() && Val.getValueType().isInteger()) {
6329 // If a result value was tied to an input value, the computed result may
6330 // have a wider width than the expected result. Extract the relevant
6332 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6335 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6338 setValue(CS.getInstruction(), Val);
6339 // Don't need to use this as a chain in this case.
6340 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6344 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6346 // Process indirect outputs, first output all of the flagged copies out of
6348 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6349 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6350 const Value *Ptr = IndirectStoresToEmit[i].second;
6351 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6353 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6356 // Emit the non-flagged stores from the physregs.
6357 SmallVector<SDValue, 8> OutChains;
6358 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6359 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6360 StoresToEmit[i].first,
6361 getValue(StoresToEmit[i].second),
6362 MachinePointerInfo(StoresToEmit[i].second),
6364 OutChains.push_back(Val);
6367 if (!OutChains.empty())
6368 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6373 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6374 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6375 MVT::Other, getRoot(),
6376 getValue(I.getArgOperand(0)),
6377 DAG.getSrcValue(I.getArgOperand(0))));
6380 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6382 const DataLayout &DL = *TLI.getDataLayout();
6383 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6384 getRoot(), getValue(I.getOperand(0)),
6385 DAG.getSrcValue(I.getOperand(0)),
6386 DL.getABITypeAlignment(I.getType()));
6388 DAG.setRoot(V.getValue(1));
6391 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6392 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6393 MVT::Other, getRoot(),
6394 getValue(I.getArgOperand(0)),
6395 DAG.getSrcValue(I.getArgOperand(0))));
6398 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6399 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6400 MVT::Other, getRoot(),
6401 getValue(I.getArgOperand(0)),
6402 getValue(I.getArgOperand(1)),
6403 DAG.getSrcValue(I.getArgOperand(0)),
6404 DAG.getSrcValue(I.getArgOperand(1))));
6407 /// \brief Lower an argument list according to the target calling convention.
6409 /// \return A tuple of <return-value, token-chain>
6411 /// This is a helper for lowering intrinsics that follow a target calling
6412 /// convention or require stack pointer adjustment. Only a subset of the
6413 /// intrinsic's operands need to participate in the calling convention.
6414 std::pair<SDValue, SDValue>
6415 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6416 unsigned NumArgs, SDValue Callee,
6418 MachineBasicBlock *LandingPad,
6419 bool IsPatchPoint) {
6420 TargetLowering::ArgListTy Args;
6421 Args.reserve(NumArgs);
6423 // Populate the argument list.
6424 // Attributes for args start at offset 1, after the return attribute.
6425 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6426 ArgI != ArgE; ++ArgI) {
6427 const Value *V = CS->getOperand(ArgI);
6429 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6431 TargetLowering::ArgListEntry Entry;
6432 Entry.Node = getValue(V);
6433 Entry.Ty = V->getType();
6434 Entry.setAttributes(&CS, AttrI);
6435 Args.push_back(Entry);
6438 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6439 TargetLowering::CallLoweringInfo CLI(DAG);
6440 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6441 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6442 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6444 return lowerInvokable(CLI, LandingPad);
6447 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6448 /// or patchpoint target node's operand list.
6450 /// Constants are converted to TargetConstants purely as an optimization to
6451 /// avoid constant materialization and register allocation.
6453 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6454 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6455 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6456 /// address materialization and register allocation, but may also be required
6457 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6458 /// alloca in the entry block, then the runtime may assume that the alloca's
6459 /// StackMap location can be read immediately after compilation and that the
6460 /// location is valid at any point during execution (this is similar to the
6461 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6462 /// only available in a register, then the runtime would need to trap when
6463 /// execution reaches the StackMap in order to read the alloca's location.
6464 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6465 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6466 SelectionDAGBuilder &Builder) {
6467 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6468 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6469 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6471 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6473 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6474 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6475 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6477 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6479 Ops.push_back(OpVal);
6483 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6484 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6485 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6486 // [live variables...])
6488 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6490 SDValue Chain, InFlag, Callee, NullPtr;
6491 SmallVector<SDValue, 32> Ops;
6493 SDLoc DL = getCurSDLoc();
6494 Callee = getValue(CI.getCalledValue());
6495 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6497 // The stackmap intrinsic only records the live variables (the arguemnts
6498 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6499 // intrinsic, this won't be lowered to a function call. This means we don't
6500 // have to worry about calling conventions and target specific lowering code.
6501 // Instead we perform the call lowering right here.
6503 // chain, flag = CALLSEQ_START(chain, 0)
6504 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6505 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6507 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6508 InFlag = Chain.getValue(1);
6510 // Add the <id> and <numBytes> constants.
6511 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6512 Ops.push_back(DAG.getTargetConstant(
6513 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6514 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6515 Ops.push_back(DAG.getTargetConstant(
6516 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6519 // Push live variables for the stack map.
6520 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6522 // We are not pushing any register mask info here on the operands list,
6523 // because the stackmap doesn't clobber anything.
6525 // Push the chain and the glue flag.
6526 Ops.push_back(Chain);
6527 Ops.push_back(InFlag);
6529 // Create the STACKMAP node.
6530 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6531 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6532 Chain = SDValue(SM, 0);
6533 InFlag = Chain.getValue(1);
6535 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6537 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6539 // Set the root to the target-lowered call chain.
6542 // Inform the Frame Information that we have a stackmap in this function.
6543 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6546 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6547 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6548 MachineBasicBlock *LandingPad) {
6549 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6554 // [live variables...])
6556 CallingConv::ID CC = CS.getCallingConv();
6557 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6558 bool HasDef = !CS->getType()->isVoidTy();
6559 SDLoc dl = getCurSDLoc();
6560 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6562 // Handle immediate and symbolic callees.
6563 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6564 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6566 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6567 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6568 SDLoc(SymbolicCallee),
6569 SymbolicCallee->getValueType(0));
6571 // Get the real number of arguments participating in the call <numArgs>
6572 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6573 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6575 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6576 // Intrinsics include all meta-operands up to but not including CC.
6577 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6578 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6579 "Not enough arguments provided to the patchpoint intrinsic");
6581 // For AnyRegCC the arguments are lowered later on manually.
6582 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6583 std::pair<SDValue, SDValue> Result =
6584 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
6587 SDNode *CallEnd = Result.second.getNode();
6588 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6589 CallEnd = CallEnd->getOperand(0).getNode();
6591 /// Get a call instruction from the call sequence chain.
6592 /// Tail calls are not allowed.
6593 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6594 "Expected a callseq node.");
6595 SDNode *Call = CallEnd->getOperand(0).getNode();
6596 bool HasGlue = Call->getGluedNode();
6598 // Replace the target specific call node with the patchable intrinsic.
6599 SmallVector<SDValue, 8> Ops;
6601 // Add the <id> and <numBytes> constants.
6602 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6603 Ops.push_back(DAG.getTargetConstant(
6604 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6605 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6606 Ops.push_back(DAG.getTargetConstant(
6607 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6611 Ops.push_back(Callee);
6613 // Adjust <numArgs> to account for any arguments that have been passed on the
6615 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6616 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6617 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6618 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6620 // Add the calling convention
6621 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6623 // Add the arguments we omitted previously. The register allocator should
6624 // place these in any free register.
6626 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6627 Ops.push_back(getValue(CS.getArgument(i)));
6629 // Push the arguments from the call instruction up to the register mask.
6630 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6631 Ops.append(Call->op_begin() + 2, e);
6633 // Push live variables for the stack map.
6634 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6636 // Push the register mask info.
6638 Ops.push_back(*(Call->op_end()-2));
6640 Ops.push_back(*(Call->op_end()-1));
6642 // Push the chain (this is originally the first operand of the call, but
6643 // becomes now the last or second to last operand).
6644 Ops.push_back(*(Call->op_begin()));
6646 // Push the glue flag (last operand).
6648 Ops.push_back(*(Call->op_end()-1));
6651 if (IsAnyRegCC && HasDef) {
6652 // Create the return types based on the intrinsic definition
6653 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6654 SmallVector<EVT, 3> ValueVTs;
6655 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
6656 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6658 // There is always a chain and a glue type at the end
6659 ValueVTs.push_back(MVT::Other);
6660 ValueVTs.push_back(MVT::Glue);
6661 NodeTys = DAG.getVTList(ValueVTs);
6663 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6665 // Replace the target specific call node with a PATCHPOINT node.
6666 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6669 // Update the NodeMap.
6672 setValue(CS.getInstruction(), SDValue(MN, 0));
6674 setValue(CS.getInstruction(), Result.first);
6677 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6678 // call sequence. Furthermore the location of the chain and glue can change
6679 // when the AnyReg calling convention is used and the intrinsic returns a
6681 if (IsAnyRegCC && HasDef) {
6682 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6683 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6684 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6686 DAG.ReplaceAllUsesWith(Call, MN);
6687 DAG.DeleteNode(Call);
6689 // Inform the Frame Information that we have a patchpoint in this function.
6690 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6693 /// Returns an AttributeSet representing the attributes applied to the return
6694 /// value of the given call.
6695 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6696 SmallVector<Attribute::AttrKind, 2> Attrs;
6698 Attrs.push_back(Attribute::SExt);
6700 Attrs.push_back(Attribute::ZExt);
6702 Attrs.push_back(Attribute::InReg);
6704 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6708 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6709 /// implementation, which just calls LowerCall.
6710 /// FIXME: When all targets are
6711 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6712 std::pair<SDValue, SDValue>
6713 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6714 // Handle the incoming return values from the call.
6716 Type *OrigRetTy = CLI.RetTy;
6717 SmallVector<EVT, 4> RetTys;
6718 SmallVector<uint64_t, 4> Offsets;
6719 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
6721 SmallVector<ISD::OutputArg, 4> Outs;
6722 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
6724 bool CanLowerReturn =
6725 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6726 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6728 SDValue DemoteStackSlot;
6729 int DemoteStackIdx = -100;
6730 if (!CanLowerReturn) {
6731 // FIXME: equivalent assert?
6732 // assert(!CS.hasInAllocaArgument() &&
6733 // "sret demotion is incompatible with inalloca");
6734 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
6735 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
6736 MachineFunction &MF = CLI.DAG.getMachineFunction();
6737 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6738 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6740 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
6742 Entry.Node = DemoteStackSlot;
6743 Entry.Ty = StackSlotPtrType;
6744 Entry.isSExt = false;
6745 Entry.isZExt = false;
6746 Entry.isInReg = false;
6747 Entry.isSRet = true;
6748 Entry.isNest = false;
6749 Entry.isByVal = false;
6750 Entry.isReturned = false;
6751 Entry.Alignment = Align;
6752 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6753 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6755 // sret demotion isn't compatible with tail-calls, since the sret argument
6756 // points into the callers stack frame.
6757 CLI.IsTailCall = false;
6759 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6761 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6762 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6763 for (unsigned i = 0; i != NumRegs; ++i) {
6764 ISD::InputArg MyFlags;
6765 MyFlags.VT = RegisterVT;
6767 MyFlags.Used = CLI.IsReturnValueUsed;
6769 MyFlags.Flags.setSExt();
6771 MyFlags.Flags.setZExt();
6773 MyFlags.Flags.setInReg();
6774 CLI.Ins.push_back(MyFlags);
6779 // Handle all of the outgoing arguments.
6781 CLI.OutVals.clear();
6782 ArgListTy &Args = CLI.getArgs();
6783 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6784 SmallVector<EVT, 4> ValueVTs;
6785 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6786 Type *FinalType = Args[i].Ty;
6787 if (Args[i].isByVal)
6788 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6789 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6790 FinalType, CLI.CallConv, CLI.IsVarArg);
6791 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6793 EVT VT = ValueVTs[Value];
6794 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6795 SDValue Op = SDValue(Args[i].Node.getNode(),
6796 Args[i].Node.getResNo() + Value);
6797 ISD::ArgFlagsTy Flags;
6798 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
6804 if (Args[i].isInReg)
6808 if (Args[i].isByVal)
6810 if (Args[i].isInAlloca) {
6811 Flags.setInAlloca();
6812 // Set the byval flag for CCAssignFn callbacks that don't know about
6813 // inalloca. This way we can know how many bytes we should've allocated
6814 // and how many bytes a callee cleanup function will pop. If we port
6815 // inalloca to more targets, we'll have to add custom inalloca handling
6816 // in the various CC lowering callbacks.
6819 if (Args[i].isByVal || Args[i].isInAlloca) {
6820 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6821 Type *ElementTy = Ty->getElementType();
6822 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6823 // For ByVal, alignment should come from FE. BE will guess if this
6824 // info is not there but there are cases it cannot get right.
6825 unsigned FrameAlign;
6826 if (Args[i].Alignment)
6827 FrameAlign = Args[i].Alignment;
6829 FrameAlign = getByValTypeAlignment(ElementTy);
6830 Flags.setByValAlign(FrameAlign);
6835 Flags.setInConsecutiveRegs();
6836 Flags.setOrigAlign(OriginalAlignment);
6838 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6839 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6840 SmallVector<SDValue, 4> Parts(NumParts);
6841 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6844 ExtendKind = ISD::SIGN_EXTEND;
6845 else if (Args[i].isZExt)
6846 ExtendKind = ISD::ZERO_EXTEND;
6848 // Conservatively only handle 'returned' on non-vectors for now
6849 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6850 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6851 "unexpected use of 'returned'");
6852 // Before passing 'returned' to the target lowering code, ensure that
6853 // either the register MVT and the actual EVT are the same size or that
6854 // the return value and argument are extended in the same way; in these
6855 // cases it's safe to pass the argument register value unchanged as the
6856 // return register value (although it's at the target's option whether
6858 // TODO: allow code generation to take advantage of partially preserved
6859 // registers rather than clobbering the entire register when the
6860 // parameter extension method is not compatible with the return
6862 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6863 (ExtendKind != ISD::ANY_EXTEND &&
6864 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6865 Flags.setReturned();
6868 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6869 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6871 for (unsigned j = 0; j != NumParts; ++j) {
6872 // if it isn't first piece, alignment must be 1
6873 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6874 i < CLI.NumFixedArgs,
6875 i, j*Parts[j].getValueType().getStoreSize());
6876 if (NumParts > 1 && j == 0)
6877 MyFlags.Flags.setSplit();
6879 MyFlags.Flags.setOrigAlign(1);
6881 CLI.Outs.push_back(MyFlags);
6882 CLI.OutVals.push_back(Parts[j]);
6885 if (NeedsRegBlock && Value == NumValues - 1)
6886 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6890 SmallVector<SDValue, 4> InVals;
6891 CLI.Chain = LowerCall(CLI, InVals);
6893 // Verify that the target's LowerCall behaved as expected.
6894 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6895 "LowerCall didn't return a valid chain!");
6896 assert((!CLI.IsTailCall || InVals.empty()) &&
6897 "LowerCall emitted a return value for a tail call!");
6898 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6899 "LowerCall didn't emit the correct number of values!");
6901 // For a tail call, the return value is merely live-out and there aren't
6902 // any nodes in the DAG representing it. Return a special value to
6903 // indicate that a tail call has been emitted and no more Instructions
6904 // should be processed in the current block.
6905 if (CLI.IsTailCall) {
6906 CLI.DAG.setRoot(CLI.Chain);
6907 return std::make_pair(SDValue(), SDValue());
6910 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6911 assert(InVals[i].getNode() &&
6912 "LowerCall emitted a null value!");
6913 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6914 "LowerCall emitted a value with the wrong type!");
6917 SmallVector<SDValue, 4> ReturnValues;
6918 if (!CanLowerReturn) {
6919 // The instruction result is the result of loading from the
6920 // hidden sret parameter.
6921 SmallVector<EVT, 1> PVTs;
6922 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6924 ComputeValueVTs(*this, PtrRetTy, PVTs);
6925 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6926 EVT PtrVT = PVTs[0];
6928 unsigned NumValues = RetTys.size();
6929 ReturnValues.resize(NumValues);
6930 SmallVector<SDValue, 4> Chains(NumValues);
6932 for (unsigned i = 0; i < NumValues; ++i) {
6933 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6934 CLI.DAG.getConstant(Offsets[i], CLI.DL,
6936 SDValue L = CLI.DAG.getLoad(
6937 RetTys[i], CLI.DL, CLI.Chain, Add,
6938 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6940 ReturnValues[i] = L;
6941 Chains[i] = L.getValue(1);
6944 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6946 // Collect the legal value parts into potentially illegal values
6947 // that correspond to the original function's return values.
6948 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6950 AssertOp = ISD::AssertSext;
6951 else if (CLI.RetZExt)
6952 AssertOp = ISD::AssertZext;
6953 unsigned CurReg = 0;
6954 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6956 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6957 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6959 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6960 NumRegs, RegisterVT, VT, nullptr,
6965 // For a function returning void, there is no return value. We can't create
6966 // such a node, so we just return a null return value in that case. In
6967 // that case, nothing will actually look at the value.
6968 if (ReturnValues.empty())
6969 return std::make_pair(SDValue(), CLI.Chain);
6972 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6973 CLI.DAG.getVTList(RetTys), ReturnValues);
6974 return std::make_pair(Res, CLI.Chain);
6977 void TargetLowering::LowerOperationWrapper(SDNode *N,
6978 SmallVectorImpl<SDValue> &Results,
6979 SelectionDAG &DAG) const {
6980 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6982 Results.push_back(Res);
6985 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6986 llvm_unreachable("LowerOperation not implemented for this target!");
6990 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6991 SDValue Op = getNonRegisterValue(V);
6992 assert((Op.getOpcode() != ISD::CopyFromReg ||
6993 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6994 "Copy from a reg to the same reg!");
6995 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6998 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6999 SDValue Chain = DAG.getEntryNode();
7001 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7002 FuncInfo.PreferredExtendType.end())
7004 : FuncInfo.PreferredExtendType[V];
7005 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7006 PendingExports.push_back(Chain);
7009 #include "llvm/CodeGen/SelectionDAGISel.h"
7011 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7012 /// entry block, return true. This includes arguments used by switches, since
7013 /// the switch may expand into multiple basic blocks.
7014 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7015 // With FastISel active, we may be splitting blocks, so force creation
7016 // of virtual registers for all non-dead arguments.
7018 return A->use_empty();
7020 const BasicBlock *Entry = A->getParent()->begin();
7021 for (const User *U : A->users())
7022 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7023 return false; // Use not in entry block.
7028 void SelectionDAGISel::LowerArguments(const Function &F) {
7029 SelectionDAG &DAG = SDB->DAG;
7030 SDLoc dl = SDB->getCurSDLoc();
7031 const DataLayout *DL = TLI->getDataLayout();
7032 SmallVector<ISD::InputArg, 16> Ins;
7034 if (!FuncInfo->CanLowerReturn) {
7035 // Put in an sret pointer parameter before all the other parameters.
7036 SmallVector<EVT, 1> ValueVTs;
7037 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7039 // NOTE: Assuming that a pointer will never break down to more than one VT
7041 ISD::ArgFlagsTy Flags;
7043 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7044 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7045 ISD::InputArg::NoArgIndex, 0);
7046 Ins.push_back(RetArg);
7049 // Set up the incoming argument description vector.
7051 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7052 I != E; ++I, ++Idx) {
7053 SmallVector<EVT, 4> ValueVTs;
7054 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7055 bool isArgValueUsed = !I->use_empty();
7056 unsigned PartBase = 0;
7057 Type *FinalType = I->getType();
7058 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7059 FinalType = cast<PointerType>(FinalType)->getElementType();
7060 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7061 FinalType, F.getCallingConv(), F.isVarArg());
7062 for (unsigned Value = 0, NumValues = ValueVTs.size();
7063 Value != NumValues; ++Value) {
7064 EVT VT = ValueVTs[Value];
7065 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7066 ISD::ArgFlagsTy Flags;
7067 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7069 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7071 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7073 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7075 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7077 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7079 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7080 Flags.setInAlloca();
7081 // Set the byval flag for CCAssignFn callbacks that don't know about
7082 // inalloca. This way we can know how many bytes we should've allocated
7083 // and how many bytes a callee cleanup function will pop. If we port
7084 // inalloca to more targets, we'll have to add custom inalloca handling
7085 // in the various CC lowering callbacks.
7088 if (Flags.isByVal() || Flags.isInAlloca()) {
7089 PointerType *Ty = cast<PointerType>(I->getType());
7090 Type *ElementTy = Ty->getElementType();
7091 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7092 // For ByVal, alignment should be passed from FE. BE will guess if
7093 // this info is not there but there are cases it cannot get right.
7094 unsigned FrameAlign;
7095 if (F.getParamAlignment(Idx))
7096 FrameAlign = F.getParamAlignment(Idx);
7098 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7099 Flags.setByValAlign(FrameAlign);
7101 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7104 Flags.setInConsecutiveRegs();
7105 Flags.setOrigAlign(OriginalAlignment);
7107 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7108 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7109 for (unsigned i = 0; i != NumRegs; ++i) {
7110 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7111 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7112 if (NumRegs > 1 && i == 0)
7113 MyFlags.Flags.setSplit();
7114 // if it isn't first piece, alignment must be 1
7116 MyFlags.Flags.setOrigAlign(1);
7117 Ins.push_back(MyFlags);
7119 if (NeedsRegBlock && Value == NumValues - 1)
7120 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7121 PartBase += VT.getStoreSize();
7125 // Call the target to set up the argument values.
7126 SmallVector<SDValue, 8> InVals;
7127 SDValue NewRoot = TLI->LowerFormalArguments(
7128 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7130 // Verify that the target's LowerFormalArguments behaved as expected.
7131 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7132 "LowerFormalArguments didn't return a valid chain!");
7133 assert(InVals.size() == Ins.size() &&
7134 "LowerFormalArguments didn't emit the correct number of values!");
7136 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7137 assert(InVals[i].getNode() &&
7138 "LowerFormalArguments emitted a null value!");
7139 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7140 "LowerFormalArguments emitted a value with the wrong type!");
7144 // Update the DAG with the new chain value resulting from argument lowering.
7145 DAG.setRoot(NewRoot);
7147 // Set up the argument values.
7150 if (!FuncInfo->CanLowerReturn) {
7151 // Create a virtual register for the sret pointer, and put in a copy
7152 // from the sret argument into it.
7153 SmallVector<EVT, 1> ValueVTs;
7154 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7155 MVT VT = ValueVTs[0].getSimpleVT();
7156 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7157 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7158 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7159 RegVT, VT, nullptr, AssertOp);
7161 MachineFunction& MF = SDB->DAG.getMachineFunction();
7162 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7163 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7164 FuncInfo->DemoteRegister = SRetReg;
7166 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7167 DAG.setRoot(NewRoot);
7169 // i indexes lowered arguments. Bump it past the hidden sret argument.
7170 // Idx indexes LLVM arguments. Don't touch it.
7174 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7176 SmallVector<SDValue, 4> ArgValues;
7177 SmallVector<EVT, 4> ValueVTs;
7178 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7179 unsigned NumValues = ValueVTs.size();
7181 // If this argument is unused then remember its value. It is used to generate
7182 // debugging information.
7183 if (I->use_empty() && NumValues) {
7184 SDB->setUnusedArgValue(I, InVals[i]);
7186 // Also remember any frame index for use in FastISel.
7187 if (FrameIndexSDNode *FI =
7188 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7189 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7192 for (unsigned Val = 0; Val != NumValues; ++Val) {
7193 EVT VT = ValueVTs[Val];
7194 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7195 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7197 if (!I->use_empty()) {
7198 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7199 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7200 AssertOp = ISD::AssertSext;
7201 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7202 AssertOp = ISD::AssertZext;
7204 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7205 NumParts, PartVT, VT,
7206 nullptr, AssertOp));
7212 // We don't need to do anything else for unused arguments.
7213 if (ArgValues.empty())
7216 // Note down frame index.
7217 if (FrameIndexSDNode *FI =
7218 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7219 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7221 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7222 SDB->getCurSDLoc());
7224 SDB->setValue(I, Res);
7225 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7226 if (LoadSDNode *LNode =
7227 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7228 if (FrameIndexSDNode *FI =
7229 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7230 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7233 // If this argument is live outside of the entry block, insert a copy from
7234 // wherever we got it to the vreg that other BB's will reference it as.
7235 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7236 // If we can, though, try to skip creating an unnecessary vreg.
7237 // FIXME: This isn't very clean... it would be nice to make this more
7238 // general. It's also subtly incompatible with the hacks FastISel
7240 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7241 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7242 FuncInfo->ValueMap[I] = Reg;
7246 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7247 FuncInfo->InitializeRegForValue(I);
7248 SDB->CopyToExportRegsIfNeeded(I);
7252 assert(i == InVals.size() && "Argument register count mismatch!");
7254 // Finally, if the target has anything special to do, allow it to do so.
7255 EmitFunctionEntryCode();
7258 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7259 /// ensure constants are generated when needed. Remember the virtual registers
7260 /// that need to be added to the Machine PHI nodes as input. We cannot just
7261 /// directly add them, because expansion might result in multiple MBB's for one
7262 /// BB. As such, the start of the BB might correspond to a different MBB than
7266 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7267 const TerminatorInst *TI = LLVMBB->getTerminator();
7269 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7271 // Check PHI nodes in successors that expect a value to be available from this
7273 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7274 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7275 if (!isa<PHINode>(SuccBB->begin())) continue;
7276 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7278 // If this terminator has multiple identical successors (common for
7279 // switches), only handle each succ once.
7280 if (!SuccsHandled.insert(SuccMBB).second)
7283 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7285 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7286 // nodes and Machine PHI nodes, but the incoming operands have not been
7288 for (BasicBlock::const_iterator I = SuccBB->begin();
7289 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7290 // Ignore dead phi's.
7291 if (PN->use_empty()) continue;
7294 if (PN->getType()->isEmptyTy())
7298 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7300 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7301 unsigned &RegOut = ConstantsOut[C];
7303 RegOut = FuncInfo.CreateRegs(C->getType());
7304 CopyValueToVirtualRegister(C, RegOut);
7308 DenseMap<const Value *, unsigned>::iterator I =
7309 FuncInfo.ValueMap.find(PHIOp);
7310 if (I != FuncInfo.ValueMap.end())
7313 assert(isa<AllocaInst>(PHIOp) &&
7314 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7315 "Didn't codegen value into a register!??");
7316 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7317 CopyValueToVirtualRegister(PHIOp, Reg);
7321 // Remember that this register needs to added to the machine PHI node as
7322 // the input for this MBB.
7323 SmallVector<EVT, 4> ValueVTs;
7324 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7325 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7326 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7327 EVT VT = ValueVTs[vti];
7328 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7329 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7330 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7331 Reg += NumRegisters;
7336 ConstantsOut.clear();
7339 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7342 SelectionDAGBuilder::StackProtectorDescriptor::
7343 AddSuccessorMBB(const BasicBlock *BB,
7344 MachineBasicBlock *ParentMBB,
7346 MachineBasicBlock *SuccMBB) {
7347 // If SuccBB has not been created yet, create it.
7349 MachineFunction *MF = ParentMBB->getParent();
7350 MachineFunction::iterator BBI = ParentMBB;
7351 SuccMBB = MF->CreateMachineBasicBlock(BB);
7352 MF->insert(++BBI, SuccMBB);
7354 // Add it as a successor of ParentMBB.
7355 ParentMBB->addSuccessor(
7356 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7360 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7361 MachineFunction::iterator I = MBB;
7362 if (++I == FuncInfo.MF->end())
7367 /// During lowering new call nodes can be created (such as memset, etc.).
7368 /// Those will become new roots of the current DAG, but complications arise
7369 /// when they are tail calls. In such cases, the call lowering will update
7370 /// the root, but the builder still needs to know that a tail call has been
7371 /// lowered in order to avoid generating an additional return.
7372 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7373 // If the node is null, we do have a tail call.
7374 if (MaybeTC.getNode() != nullptr)
7375 DAG.setRoot(MaybeTC);
7380 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7381 unsigned *TotalCases, unsigned First,
7383 assert(Last >= First);
7384 assert(TotalCases[Last] >= TotalCases[First]);
7386 APInt LowCase = Clusters[First].Low->getValue();
7387 APInt HighCase = Clusters[Last].High->getValue();
7388 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7390 // FIXME: A range of consecutive cases has 100% density, but only requires one
7391 // comparison to lower. We should discriminate against such consecutive ranges
7394 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7395 uint64_t Range = Diff + 1;
7398 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7400 assert(NumCases < UINT64_MAX / 100);
7401 assert(Range >= NumCases);
7403 return NumCases * 100 >= Range * MinJumpTableDensity;
7406 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7407 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7408 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7411 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7412 unsigned First, unsigned Last,
7413 const SwitchInst *SI,
7414 MachineBasicBlock *DefaultMBB,
7415 CaseCluster &JTCluster) {
7416 assert(First <= Last);
7418 uint32_t Weight = 0;
7419 unsigned NumCmps = 0;
7420 std::vector<MachineBasicBlock*> Table;
7421 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7422 for (unsigned I = First; I <= Last; ++I) {
7423 assert(Clusters[I].Kind == CC_Range);
7424 Weight += Clusters[I].Weight;
7425 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7426 APInt Low = Clusters[I].Low->getValue();
7427 APInt High = Clusters[I].High->getValue();
7428 NumCmps += (Low == High) ? 1 : 2;
7430 // Fill the gap between this and the previous cluster.
7431 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7432 assert(PreviousHigh.slt(Low));
7433 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7434 for (uint64_t J = 0; J < Gap; J++)
7435 Table.push_back(DefaultMBB);
7437 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7438 for (uint64_t J = 0; J < ClusterSize; ++J)
7439 Table.push_back(Clusters[I].MBB);
7440 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7443 unsigned NumDests = JTWeights.size();
7444 if (isSuitableForBitTests(NumDests, NumCmps,
7445 Clusters[First].Low->getValue(),
7446 Clusters[Last].High->getValue())) {
7447 // Clusters[First..Last] should be lowered as bit tests instead.
7451 // Create the MBB that will load from and jump through the table.
7452 // Note: We create it here, but it's not inserted into the function yet.
7453 MachineFunction *CurMF = FuncInfo.MF;
7454 MachineBasicBlock *JumpTableMBB =
7455 CurMF->CreateMachineBasicBlock(SI->getParent());
7457 // Add successors. Note: use table order for determinism.
7458 SmallPtrSet<MachineBasicBlock *, 8> Done;
7459 for (MachineBasicBlock *Succ : Table) {
7460 if (Done.count(Succ))
7462 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7466 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7467 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7468 ->createJumpTableIndex(Table);
7470 // Set up the jump table info.
7471 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7472 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7473 Clusters[Last].High->getValue(), SI->getCondition(),
7475 JTCases.push_back(JumpTableBlock(JTH, JT));
7477 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7478 JTCases.size() - 1, Weight);
7482 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7483 const SwitchInst *SI,
7484 MachineBasicBlock *DefaultMBB) {
7486 // Clusters must be non-empty, sorted, and only contain Range clusters.
7487 assert(!Clusters.empty());
7488 for (CaseCluster &C : Clusters)
7489 assert(C.Kind == CC_Range);
7490 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7491 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7494 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7495 if (!areJTsAllowed(TLI))
7498 const int64_t N = Clusters.size();
7499 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7501 // Split Clusters into minimum number of dense partitions. The algorithm uses
7502 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7503 // for the Case Statement'" (1994), but builds the MinPartitions array in
7504 // reverse order to make it easier to reconstruct the partitions in ascending
7505 // order. In the choice between two optimal partitionings, it picks the one
7506 // which yields more jump tables.
7508 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7509 SmallVector<unsigned, 8> MinPartitions(N);
7510 // LastElement[i] is the last element of the partition starting at i.
7511 SmallVector<unsigned, 8> LastElement(N);
7512 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7513 SmallVector<unsigned, 8> NumTables(N);
7514 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7515 SmallVector<unsigned, 8> TotalCases(N);
7517 for (unsigned i = 0; i < N; ++i) {
7518 APInt Hi = Clusters[i].High->getValue();
7519 APInt Lo = Clusters[i].Low->getValue();
7520 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7522 TotalCases[i] += TotalCases[i - 1];
7525 // Base case: There is only one way to partition Clusters[N-1].
7526 MinPartitions[N - 1] = 1;
7527 LastElement[N - 1] = N - 1;
7528 assert(MinJumpTableSize > 1);
7529 NumTables[N - 1] = 0;
7531 // Note: loop indexes are signed to avoid underflow.
7532 for (int64_t i = N - 2; i >= 0; i--) {
7533 // Find optimal partitioning of Clusters[i..N-1].
7534 // Baseline: Put Clusters[i] into a partition on its own.
7535 MinPartitions[i] = MinPartitions[i + 1] + 1;
7537 NumTables[i] = NumTables[i + 1];
7539 // Search for a solution that results in fewer partitions.
7540 for (int64_t j = N - 1; j > i; j--) {
7541 // Try building a partition from Clusters[i..j].
7542 if (isDense(Clusters, &TotalCases[0], i, j)) {
7543 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7544 bool IsTable = j - i + 1 >= MinJumpTableSize;
7545 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7547 // If this j leads to fewer partitions, or same number of partitions
7548 // with more lookup tables, it is a better partitioning.
7549 if (NumPartitions < MinPartitions[i] ||
7550 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7551 MinPartitions[i] = NumPartitions;
7553 NumTables[i] = Tables;
7559 // Iterate over the partitions, replacing some with jump tables in-place.
7560 unsigned DstIndex = 0;
7561 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7562 Last = LastElement[First];
7563 assert(Last >= First);
7564 assert(DstIndex <= First);
7565 unsigned NumClusters = Last - First + 1;
7567 CaseCluster JTCluster;
7568 if (NumClusters >= MinJumpTableSize &&
7569 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7570 Clusters[DstIndex++] = JTCluster;
7572 for (unsigned I = First; I <= Last; ++I)
7573 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7576 Clusters.resize(DstIndex);
7579 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7580 // FIXME: Using the pointer type doesn't seem ideal.
7581 uint64_t BW = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7582 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7586 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7589 const APInt &High) {
7590 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7591 // range of cases both require only one branch to lower. Just looking at the
7592 // number of clusters and destinations should be enough to decide whether to
7595 // To lower a range with bit tests, the range must fit the bitwidth of a
7597 if (!rangeFitsInWord(Low, High))
7600 // Decide whether it's profitable to lower this range with bit tests. Each
7601 // destination requires a bit test and branch, and there is an overall range
7602 // check branch. For a small number of clusters, separate comparisons might be
7603 // cheaper, and for many destinations, splitting the range might be better.
7604 return (NumDests == 1 && NumCmps >= 3) ||
7605 (NumDests == 2 && NumCmps >= 5) ||
7606 (NumDests == 3 && NumCmps >= 6);
7609 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7610 unsigned First, unsigned Last,
7611 const SwitchInst *SI,
7612 CaseCluster &BTCluster) {
7613 assert(First <= Last);
7617 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7618 unsigned NumCmps = 0;
7619 for (int64_t I = First; I <= Last; ++I) {
7620 assert(Clusters[I].Kind == CC_Range);
7621 Dests.set(Clusters[I].MBB->getNumber());
7622 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7624 unsigned NumDests = Dests.count();
7626 APInt Low = Clusters[First].Low->getValue();
7627 APInt High = Clusters[Last].High->getValue();
7628 assert(Low.slt(High));
7630 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7636 const int BitWidth =
7637 DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7638 assert((High - Low + 1).sle(BitWidth) && "Case range must fit in bit mask!");
7640 if (Low.isNonNegative() && High.slt(BitWidth)) {
7641 // Optimize the case where all the case values fit in a
7642 // word without having to subtract minValue. In this case,
7643 // we can optimize away the subtraction.
7644 LowBound = APInt::getNullValue(Low.getBitWidth());
7648 CmpRange = High - Low;
7652 uint32_t TotalWeight = 0;
7653 for (unsigned i = First; i <= Last; ++i) {
7654 // Find the CaseBits for this destination.
7656 for (j = 0; j < CBV.size(); ++j)
7657 if (CBV[j].BB == Clusters[i].MBB)
7659 if (j == CBV.size())
7660 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7661 CaseBits *CB = &CBV[j];
7663 // Update Mask, Bits and ExtraWeight.
7664 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7665 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7666 for (uint64_t j = Lo; j <= Hi; ++j) {
7667 CB->Mask |= 1ULL << j;
7670 CB->ExtraWeight += Clusters[i].Weight;
7671 TotalWeight += Clusters[i].Weight;
7672 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7676 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7677 // Sort by weight first, number of bits second.
7678 if (a.ExtraWeight != b.ExtraWeight)
7679 return a.ExtraWeight > b.ExtraWeight;
7680 return a.Bits > b.Bits;
7683 for (auto &CB : CBV) {
7684 MachineBasicBlock *BitTestBB =
7685 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7686 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7688 BitTestCases.push_back(BitTestBlock(LowBound, CmpRange, SI->getCondition(),
7689 -1U, MVT::Other, false, nullptr,
7690 nullptr, std::move(BTI)));
7692 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7693 BitTestCases.size() - 1, TotalWeight);
7697 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7698 const SwitchInst *SI) {
7699 // Partition Clusters into as few subsets as possible, where each subset has a
7700 // range that fits in a machine word and has <= 3 unique destinations.
7703 // Clusters must be sorted and contain Range or JumpTable clusters.
7704 assert(!Clusters.empty());
7705 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7706 for (const CaseCluster &C : Clusters)
7707 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7708 for (unsigned i = 1; i < Clusters.size(); ++i)
7709 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7712 // If target does not have legal shift left, do not emit bit tests at all.
7713 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7714 EVT PTy = TLI.getPointerTy();
7715 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7718 int BitWidth = PTy.getSizeInBits();
7719 const int64_t N = Clusters.size();
7721 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7722 SmallVector<unsigned, 8> MinPartitions(N);
7723 // LastElement[i] is the last element of the partition starting at i.
7724 SmallVector<unsigned, 8> LastElement(N);
7726 // FIXME: This might not be the best algorithm for finding bit test clusters.
7728 // Base case: There is only one way to partition Clusters[N-1].
7729 MinPartitions[N - 1] = 1;
7730 LastElement[N - 1] = N - 1;
7732 // Note: loop indexes are signed to avoid underflow.
7733 for (int64_t i = N - 2; i >= 0; --i) {
7734 // Find optimal partitioning of Clusters[i..N-1].
7735 // Baseline: Put Clusters[i] into a partition on its own.
7736 MinPartitions[i] = MinPartitions[i + 1] + 1;
7739 // Search for a solution that results in fewer partitions.
7740 // Note: the search is limited by BitWidth, reducing time complexity.
7741 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7742 // Try building a partition from Clusters[i..j].
7745 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7746 Clusters[j].High->getValue()))
7749 // Check nbr of destinations and cluster types.
7750 // FIXME: This works, but doesn't seem very efficient.
7751 bool RangesOnly = true;
7752 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7753 for (int64_t k = i; k <= j; k++) {
7754 if (Clusters[k].Kind != CC_Range) {
7758 Dests.set(Clusters[k].MBB->getNumber());
7760 if (!RangesOnly || Dests.count() > 3)
7763 // Check if it's a better partition.
7764 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7765 if (NumPartitions < MinPartitions[i]) {
7766 // Found a better partition.
7767 MinPartitions[i] = NumPartitions;
7773 // Iterate over the partitions, replacing with bit-test clusters in-place.
7774 unsigned DstIndex = 0;
7775 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7776 Last = LastElement[First];
7777 assert(First <= Last);
7778 assert(DstIndex <= First);
7780 CaseCluster BitTestCluster;
7781 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7782 Clusters[DstIndex++] = BitTestCluster;
7784 for (unsigned I = First; I <= Last; ++I)
7785 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7788 Clusters.resize(DstIndex);
7791 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7792 MachineBasicBlock *SwitchMBB,
7793 MachineBasicBlock *DefaultMBB) {
7794 MachineFunction *CurMF = FuncInfo.MF;
7795 MachineBasicBlock *NextMBB = nullptr;
7796 MachineFunction::iterator BBI = W.MBB;
7797 if (++BBI != FuncInfo.MF->end())
7800 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7802 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7804 if (Size == 2 && W.MBB == SwitchMBB) {
7805 // If any two of the cases has the same destination, and if one value
7806 // is the same as the other, but has one bit unset that the other has set,
7807 // use bit manipulation to do two compares at once. For example:
7808 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7809 // TODO: This could be extended to merge any 2 cases in switches with 3
7811 // TODO: Handle cases where W.CaseBB != SwitchBB.
7812 CaseCluster &Small = *W.FirstCluster;
7813 CaseCluster &Big = *W.LastCluster;
7815 if (Small.Low == Small.High && Big.Low == Big.High &&
7816 Small.MBB == Big.MBB) {
7817 const APInt &SmallValue = Small.Low->getValue();
7818 const APInt &BigValue = Big.Low->getValue();
7820 // Check that there is only one bit different.
7821 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
7822 (SmallValue | BigValue) == BigValue) {
7823 // Isolate the common bit.
7824 APInt CommonBit = BigValue & ~SmallValue;
7825 assert((SmallValue | CommonBit) == BigValue &&
7826 CommonBit.countPopulation() == 1 && "Not a common bit?");
7828 SDValue CondLHS = getValue(Cond);
7829 EVT VT = CondLHS.getValueType();
7830 SDLoc DL = getCurSDLoc();
7832 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7833 DAG.getConstant(CommonBit, DL, VT));
7834 SDValue Cond = DAG.getSetCC(DL, MVT::i1, Or,
7835 DAG.getConstant(BigValue, DL, VT),
7838 // Update successor info.
7839 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7840 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7841 addSuccessorWithWeight(
7842 SwitchMBB, DefaultMBB,
7843 // The default destination is the first successor in IR.
7844 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7847 // Insert the true branch.
7849 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7850 DAG.getBasicBlock(Small.MBB));
7851 // Insert the false branch.
7852 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7853 DAG.getBasicBlock(DefaultMBB));
7855 DAG.setRoot(BrCond);
7861 if (TM.getOptLevel() != CodeGenOpt::None) {
7862 // Order cases by weight so the most likely case will be checked first.
7863 std::sort(W.FirstCluster, W.LastCluster + 1,
7864 [](const CaseCluster &a, const CaseCluster &b) {
7865 return a.Weight > b.Weight;
7868 // Rearrange the case blocks so that the last one falls through if possible
7869 // without without changing the order of weights.
7870 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7872 if (I->Weight > W.LastCluster->Weight)
7874 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7875 std::swap(*I, *W.LastCluster);
7881 // Compute total weight.
7882 uint32_t UnhandledWeights = 0;
7883 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7884 UnhandledWeights += I->Weight;
7885 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7888 MachineBasicBlock *CurMBB = W.MBB;
7889 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7890 MachineBasicBlock *Fallthrough;
7891 if (I == W.LastCluster) {
7892 // For the last cluster, fall through to the default destination.
7893 Fallthrough = DefaultMBB;
7895 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7896 CurMF->insert(BBI, Fallthrough);
7897 // Put Cond in a virtual register to make it available from the new blocks.
7898 ExportFromCurrentBlock(Cond);
7902 case CC_JumpTable: {
7903 // FIXME: Optimize away range check based on pivot comparisons.
7904 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7905 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7907 // The jump block hasn't been inserted yet; insert it here.
7908 MachineBasicBlock *JumpMBB = JT->MBB;
7909 CurMF->insert(BBI, JumpMBB);
7910 addSuccessorWithWeight(CurMBB, Fallthrough);
7911 addSuccessorWithWeight(CurMBB, JumpMBB);
7913 // The jump table header will be inserted in our current block, do the
7914 // range check, and fall through to our fallthrough block.
7915 JTH->HeaderBB = CurMBB;
7916 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7918 // If we're in the right place, emit the jump table header right now.
7919 if (CurMBB == SwitchMBB) {
7920 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7921 JTH->Emitted = true;
7926 // FIXME: Optimize away range check based on pivot comparisons.
7927 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7929 // The bit test blocks haven't been inserted yet; insert them here.
7930 for (BitTestCase &BTC : BTB->Cases)
7931 CurMF->insert(BBI, BTC.ThisBB);
7933 // Fill in fields of the BitTestBlock.
7934 BTB->Parent = CurMBB;
7935 BTB->Default = Fallthrough;
7937 // If we're in the right place, emit the bit test header header right now.
7938 if (CurMBB ==SwitchMBB) {
7939 visitBitTestHeader(*BTB, SwitchMBB);
7940 BTB->Emitted = true;
7945 const Value *RHS, *LHS, *MHS;
7947 if (I->Low == I->High) {
7948 // Check Cond == I->Low.
7954 // Check I->Low <= Cond <= I->High.
7961 // The false weight is the sum of all unhandled cases.
7962 UnhandledWeights -= I->Weight;
7963 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
7966 if (CurMBB == SwitchMBB)
7967 visitSwitchCase(CB, SwitchMBB);
7969 SwitchCases.push_back(CB);
7974 CurMBB = Fallthrough;
7978 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
7979 const SwitchWorkListItem &W,
7981 MachineBasicBlock *SwitchMBB) {
7982 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
7983 "Clusters not sorted?");
7985 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
7986 assert(NumClusters >= 2 && "Too small to split!");
7988 // FIXME: When we have profile info, we might want to balance the tree based
7989 // on weights instead of node count.
7991 CaseClusterIt PivotCluster = W.FirstCluster + NumClusters / 2;
7992 CaseClusterIt FirstLeft = W.FirstCluster;
7993 CaseClusterIt LastLeft = PivotCluster - 1;
7994 CaseClusterIt FirstRight = PivotCluster;
7995 CaseClusterIt LastRight = W.LastCluster;
7996 const ConstantInt *Pivot = PivotCluster->Low;
7998 // New blocks will be inserted immediately after the current one.
7999 MachineFunction::iterator BBI = W.MBB;
8002 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8003 // we can branch to its destination directly if it's squeezed exactly in
8004 // between the known lower bound and Pivot - 1.
8005 MachineBasicBlock *LeftMBB;
8006 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8007 FirstLeft->Low == W.GE &&
8008 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8009 LeftMBB = FirstLeft->MBB;
8011 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8012 FuncInfo.MF->insert(BBI, LeftMBB);
8013 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8014 // Put Cond in a virtual register to make it available from the new blocks.
8015 ExportFromCurrentBlock(Cond);
8018 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8019 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8020 // directly if RHS.High equals the current upper bound.
8021 MachineBasicBlock *RightMBB;
8022 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8023 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8024 RightMBB = FirstRight->MBB;
8026 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8027 FuncInfo.MF->insert(BBI, RightMBB);
8028 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8029 // Put Cond in a virtual register to make it available from the new blocks.
8030 ExportFromCurrentBlock(Cond);
8033 // Create the CaseBlock record that will be used to lower the branch.
8034 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB);
8036 if (W.MBB == SwitchMBB)
8037 visitSwitchCase(CB, SwitchMBB);
8039 SwitchCases.push_back(CB);
8042 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8043 // Extract cases from the switch.
8044 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8045 CaseClusterVector Clusters;
8046 Clusters.reserve(SI.getNumCases());
8047 for (auto I : SI.cases()) {
8048 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8049 const ConstantInt *CaseVal = I.getCaseValue();
8050 uint32_t Weight = 0; // FIXME: Use 1 instead?
8052 Weight = BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex());
8053 assert(Weight <= UINT32_MAX / SI.getNumSuccessors());
8055 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8058 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8060 if (TM.getOptLevel() != CodeGenOpt::None) {
8061 // Cluster adjacent cases with the same destination.
8062 sortAndRangeify(Clusters);
8064 // Replace an unreachable default with the most popular destination.
8065 // FIXME: Exploit unreachable default more aggressively.
8066 bool UnreachableDefault =
8067 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8068 if (UnreachableDefault && !Clusters.empty()) {
8069 DenseMap<const BasicBlock *, unsigned> Popularity;
8070 unsigned MaxPop = 0;
8071 const BasicBlock *MaxBB = nullptr;
8072 for (auto I : SI.cases()) {
8073 const BasicBlock *BB = I.getCaseSuccessor();
8074 if (++Popularity[BB] > MaxPop) {
8075 MaxPop = Popularity[BB];
8080 assert(MaxPop > 0 && MaxBB);
8081 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8083 // Remove cases that were pointing to the destination that is now the
8085 CaseClusterVector New;
8086 New.reserve(Clusters.size());
8087 for (CaseCluster &CC : Clusters) {
8088 if (CC.MBB != DefaultMBB)
8091 Clusters = std::move(New);
8095 // If there is only the default destination, jump there directly.
8096 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8097 if (Clusters.empty()) {
8098 SwitchMBB->addSuccessor(DefaultMBB);
8099 if (DefaultMBB != NextBlock(SwitchMBB)) {
8100 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8101 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8106 if (TM.getOptLevel() != CodeGenOpt::None) {
8107 findJumpTables(Clusters, &SI, DefaultMBB);
8108 findBitTestClusters(Clusters, &SI);
8113 dbgs() << "Case clusters: ";
8114 for (const CaseCluster &C : Clusters) {
8115 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8116 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8118 C.Low->getValue().print(dbgs(), true);
8119 if (C.Low != C.High) {
8121 C.High->getValue().print(dbgs(), true);
8128 assert(!Clusters.empty());
8129 SwitchWorkList WorkList;
8130 CaseClusterIt First = Clusters.begin();
8131 CaseClusterIt Last = Clusters.end() - 1;
8132 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8134 while (!WorkList.empty()) {
8135 SwitchWorkListItem W = WorkList.back();
8136 WorkList.pop_back();
8137 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8139 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8140 // For optimized builds, lower large range as a balanced binary tree.
8141 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8145 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);