1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
60 #include "llvm/Target/TargetSelectionDAGInfo.h"
61 #include "llvm/Target/TargetSubtargetInfo.h"
65 #define DEBUG_TYPE "isel"
67 /// LimitFloatPrecision - Generate low-precision inline sequences for
68 /// some float libcalls (6, 8 or 12 bits).
69 static unsigned LimitFloatPrecision;
71 static cl::opt<unsigned, true>
72 LimitFPPrecision("limit-float-precision",
73 cl::desc("Generate low-precision inline sequences "
74 "for some float libcalls"),
75 cl::location(LimitFloatPrecision),
78 // Limit the width of DAG chains. This is important in general to prevent
79 // prevent DAG-based analysis from blowing up. For example, alias analysis and
80 // load clustering may not complete in reasonable time. It is difficult to
81 // recognize and avoid this situation within each individual analysis, and
82 // future analyses are likely to have the same behavior. Limiting DAG width is
83 // the safe approach, and will be especially important with global DAGs.
85 // MaxParallelChains default is arbitrarily high to avoid affecting
86 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
87 // sequence over this should have been converted to llvm.memcpy by the
88 // frontend. It easy to induce this behavior with .ll code such as:
89 // %buffer = alloca [4096 x i8]
90 // %data = load [4096 x i8]* %argPtr
91 // store [4096 x i8] %data, [4096 x i8]* %buffer
92 static const unsigned MaxParallelChains = 64;
94 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
95 const SDValue *Parts, unsigned NumParts,
96 MVT PartVT, EVT ValueVT, const Value *V);
98 /// getCopyFromParts - Create a value that contains the specified legal parts
99 /// combined into the value they represent. If the parts combine to a type
100 /// larger then ValueVT then AssertOp can be used to specify whether the extra
101 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
102 /// (ISD::AssertSext).
103 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts,
105 unsigned NumParts, MVT PartVT, EVT ValueVT,
107 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
108 if (ValueVT.isVector())
109 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
112 assert(NumParts > 0 && "No parts to assemble!");
113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
114 SDValue Val = Parts[0];
117 // Assemble the value from multiple parts.
118 if (ValueVT.isInteger()) {
119 unsigned PartBits = PartVT.getSizeInBits();
120 unsigned ValueBits = ValueVT.getSizeInBits();
122 // Assemble the power of 2 part.
123 unsigned RoundParts = NumParts & (NumParts - 1) ?
124 1 << Log2_32(NumParts) : NumParts;
125 unsigned RoundBits = PartBits * RoundParts;
126 EVT RoundVT = RoundBits == ValueBits ?
127 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
130 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
132 if (RoundParts > 2) {
133 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
135 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
136 RoundParts / 2, PartVT, HalfVT, V);
138 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
139 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
142 if (TLI.isBigEndian())
145 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
147 if (RoundParts < NumParts) {
148 // Assemble the trailing non-power-of-2 part.
149 unsigned OddParts = NumParts - RoundParts;
150 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
151 Hi = getCopyFromParts(DAG, DL,
152 Parts + RoundParts, OddParts, PartVT, OddVT, V);
154 // Combine the round and odd parts.
156 if (TLI.isBigEndian())
158 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
159 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
160 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
161 DAG.getConstant(Lo.getValueType().getSizeInBits(),
162 TLI.getPointerTy()));
163 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
164 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
166 } else if (PartVT.isFloatingPoint()) {
167 // FP split into multiple FP parts (for ppcf128)
168 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
171 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
172 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
173 if (TLI.hasBigEndianPartOrdering(ValueVT))
175 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
177 // FP split into integer parts (soft fp)
178 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
179 !PartVT.isVector() && "Unexpected split");
180 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
181 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
185 // There is now one part, held in Val. Correct it to match ValueVT.
186 EVT PartEVT = Val.getValueType();
188 if (PartEVT == ValueVT)
191 if (PartEVT.isInteger() && ValueVT.isInteger()) {
192 if (ValueVT.bitsLT(PartEVT)) {
193 // For a truncate, see if we have any information to
194 // indicate whether the truncated bits will always be
195 // zero or sign-extension.
196 if (AssertOp != ISD::DELETED_NODE)
197 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
198 DAG.getValueType(ValueVT));
199 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
201 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
204 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
205 // FP_ROUND's are always exact here.
206 if (ValueVT.bitsLT(Val.getValueType()))
207 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
208 DAG.getTargetConstant(1, TLI.getPointerTy()));
210 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
214 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
216 llvm_unreachable("Unknown mismatch!");
219 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
220 const Twine &ErrMsg) {
221 const Instruction *I = dyn_cast_or_null<Instruction>(V);
223 return Ctx.emitError(ErrMsg);
225 const char *AsmError = ", possible invalid constraint for vector type";
226 if (const CallInst *CI = dyn_cast<CallInst>(I))
227 if (isa<InlineAsm>(CI->getCalledValue()))
228 return Ctx.emitError(I, ErrMsg + AsmError);
230 return Ctx.emitError(I, ErrMsg);
233 /// getCopyFromPartsVector - Create a value that contains the specified legal
234 /// parts combined into the value they represent. If the parts combine to a
235 /// type larger then ValueVT then AssertOp can be used to specify whether the
236 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
237 /// ValueVT (ISD::AssertSext).
238 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
239 const SDValue *Parts, unsigned NumParts,
240 MVT PartVT, EVT ValueVT, const Value *V) {
241 assert(ValueVT.isVector() && "Not a vector value");
242 assert(NumParts > 0 && "No parts to assemble!");
243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
244 SDValue Val = Parts[0];
246 // Handle a multi-element vector.
250 unsigned NumIntermediates;
252 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
253 NumIntermediates, RegisterVT);
254 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
255 NumParts = NumRegs; // Silence a compiler warning.
256 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
257 assert(RegisterVT == Parts[0].getSimpleValueType() &&
258 "Part type doesn't match part!");
260 // Assemble the parts into intermediate operands.
261 SmallVector<SDValue, 8> Ops(NumIntermediates);
262 if (NumIntermediates == NumParts) {
263 // If the register was not expanded, truncate or copy the value,
265 for (unsigned i = 0; i != NumParts; ++i)
266 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
267 PartVT, IntermediateVT, V);
268 } else if (NumParts > 0) {
269 // If the intermediate type was expanded, build the intermediate
270 // operands from the parts.
271 assert(NumParts % NumIntermediates == 0 &&
272 "Must expand into a divisible number of parts!");
273 unsigned Factor = NumParts / NumIntermediates;
274 for (unsigned i = 0; i != NumIntermediates; ++i)
275 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
276 PartVT, IntermediateVT, V);
279 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
280 // intermediate operands.
281 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
286 // There is now one part, held in Val. Correct it to match ValueVT.
287 EVT PartEVT = Val.getValueType();
289 if (PartEVT == ValueVT)
292 if (PartEVT.isVector()) {
293 // If the element type of the source/dest vectors are the same, but the
294 // parts vector has more elements than the value vector, then we have a
295 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
297 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
298 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
299 "Cannot narrow, it would be a lossy transformation");
300 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
301 DAG.getConstant(0, TLI.getVectorIdxTy()));
304 // Vector/Vector bitcast.
305 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
306 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
308 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
309 "Cannot handle this kind of promotion");
310 // Promoted vector extract
311 bool Smaller = ValueVT.bitsLE(PartEVT);
312 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
317 // Trivial bitcast if the types are the same size and the destination
318 // vector type is legal.
319 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
320 TLI.isTypeLegal(ValueVT))
321 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
323 // Handle cases such as i8 -> <1 x i1>
324 if (ValueVT.getVectorNumElements() != 1) {
325 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
326 "non-trivial scalar-to-vector conversion");
327 return DAG.getUNDEF(ValueVT);
330 if (ValueVT.getVectorNumElements() == 1 &&
331 ValueVT.getVectorElementType() != PartEVT) {
332 bool Smaller = ValueVT.bitsLE(PartEVT);
333 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
334 DL, ValueVT.getScalarType(), Val);
337 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
340 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
341 SDValue Val, SDValue *Parts, unsigned NumParts,
342 MVT PartVT, const Value *V);
344 /// getCopyToParts - Create a series of nodes that contain the specified value
345 /// split into legal parts. If the parts contain more bits than Val, then, for
346 /// integers, ExtendKind can be used to specify how to generate the extra bits.
347 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V,
350 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
351 EVT ValueVT = Val.getValueType();
353 // Handle the vector case separately.
354 if (ValueVT.isVector())
355 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
358 unsigned PartBits = PartVT.getSizeInBits();
359 unsigned OrigNumParts = NumParts;
360 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
365 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
366 EVT PartEVT = PartVT;
367 if (PartEVT == ValueVT) {
368 assert(NumParts == 1 && "No-op copy with multiple parts!");
373 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
374 // If the parts cover more bits than the value has, promote the value.
375 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
376 assert(NumParts == 1 && "Do not know what to promote to!");
377 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
379 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
380 ValueVT.isInteger() &&
381 "Unknown mismatch!");
382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
383 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
384 if (PartVT == MVT::x86mmx)
385 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
387 } else if (PartBits == ValueVT.getSizeInBits()) {
388 // Different types of the same size.
389 assert(NumParts == 1 && PartEVT != ValueVT);
390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
392 // If the parts cover less bits than value has, truncate the value.
393 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
394 ValueVT.isInteger() &&
395 "Unknown mismatch!");
396 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
397 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
398 if (PartVT == MVT::x86mmx)
399 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
402 // The value may have changed - recompute ValueVT.
403 ValueVT = Val.getValueType();
404 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
405 "Failed to tile the value with PartVT!");
408 if (PartEVT != ValueVT)
409 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
410 "scalar-to-vector conversion failed");
416 // Expand the value into multiple parts.
417 if (NumParts & (NumParts - 1)) {
418 // The number of parts is not a power of 2. Split off and copy the tail.
419 assert(PartVT.isInteger() && ValueVT.isInteger() &&
420 "Do not know what to expand to!");
421 unsigned RoundParts = 1 << Log2_32(NumParts);
422 unsigned RoundBits = RoundParts * PartBits;
423 unsigned OddParts = NumParts - RoundParts;
424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
425 DAG.getIntPtrConstant(RoundBits));
426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
428 if (TLI.isBigEndian())
429 // The odd parts were reversed by getCopyToParts - unreverse them.
430 std::reverse(Parts + RoundParts, Parts + NumParts);
432 NumParts = RoundParts;
433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
437 // The number of parts is a power of 2. Repeatedly bisect the value using
439 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
440 EVT::getIntegerVT(*DAG.getContext(),
441 ValueVT.getSizeInBits()),
444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
445 for (unsigned i = 0; i < NumParts; i += StepSize) {
446 unsigned ThisBits = StepSize * PartBits / 2;
447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
448 SDValue &Part0 = Parts[i];
449 SDValue &Part1 = Parts[i+StepSize/2];
451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(1));
453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(0));
456 if (ThisBits == PartBits && ThisVT != PartVT) {
457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
468 /// getCopyToPartsVector - Create a series of nodes that contain the specified
469 /// value split into legal parts.
470 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
471 SDValue Val, SDValue *Parts, unsigned NumParts,
472 MVT PartVT, const Value *V) {
473 EVT ValueVT = Val.getValueType();
474 assert(ValueVT.isVector() && "Not a vector");
475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
478 EVT PartEVT = PartVT;
479 if (PartEVT == ValueVT) {
481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
482 // Bitconvert vector->vector case.
483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
484 } else if (PartVT.isVector() &&
485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
487 EVT ElementVT = PartVT.getVectorElementType();
488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
490 SmallVector<SDValue, 16> Ops;
491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
493 ElementVT, Val, DAG.getConstant(i,
494 TLI.getVectorIdxTy())));
496 for (unsigned i = ValueVT.getVectorNumElements(),
497 e = PartVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getUNDEF(ElementVT));
500 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
502 // FIXME: Use CONCAT for 2x -> 4x.
504 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
505 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType().bitsGE(
508 ValueVT.getVectorElementType()) &&
509 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
511 // Promoted vector extract
512 bool Smaller = PartEVT.bitsLE(ValueVT);
513 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
516 // Vector -> scalar conversion.
517 assert(ValueVT.getVectorNumElements() == 1 &&
518 "Only trivial vector-to-scalar conversions should get here!");
519 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
520 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
522 bool Smaller = ValueVT.bitsLE(PartVT);
523 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
531 // Handle a multi-element vector.
534 unsigned NumIntermediates;
535 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
537 NumIntermediates, RegisterVT);
538 unsigned NumElements = ValueVT.getVectorNumElements();
540 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
541 NumParts = NumRegs; // Silence a compiler warning.
542 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
544 // Split the vector into intermediate operands.
545 SmallVector<SDValue, 8> Ops(NumIntermediates);
546 for (unsigned i = 0; i != NumIntermediates; ++i) {
547 if (IntermediateVT.isVector())
548 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
550 DAG.getConstant(i * (NumElements / NumIntermediates),
551 TLI.getVectorIdxTy()));
553 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
555 DAG.getConstant(i, TLI.getVectorIdxTy()));
558 // Split the intermediate operands into legal parts.
559 if (NumParts == NumIntermediates) {
560 // If the register was not expanded, promote or copy the value,
562 for (unsigned i = 0; i != NumParts; ++i)
563 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
564 } else if (NumParts > 0) {
565 // If the intermediate type was expanded, split each the value into
567 assert(NumParts % NumIntermediates == 0 &&
568 "Must expand into a divisible number of parts!");
569 unsigned Factor = NumParts / NumIntermediates;
570 for (unsigned i = 0; i != NumIntermediates; ++i)
571 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
576 /// RegsForValue - This struct represents the registers (physical or virtual)
577 /// that a particular set of values is assigned, and the type information
578 /// about the value. The most common situation is to represent one value at a
579 /// time, but struct or array values are handled element-wise as multiple
580 /// values. The splitting of aggregates is performed recursively, so that we
581 /// never have aggregate-typed registers. The values at this point do not
582 /// necessarily have legal types, so each value may require one or more
583 /// registers of some legal type.
585 struct RegsForValue {
586 /// ValueVTs - The value types of the values, which may not be legal, and
587 /// may need be promoted or synthesized from one or more registers.
589 SmallVector<EVT, 4> ValueVTs;
591 /// RegVTs - The value types of the registers. This is the same size as
592 /// ValueVTs and it records, for each value, what the type of the assigned
593 /// register or registers are. (Individual values are never synthesized
594 /// from more than one type of register.)
596 /// With virtual registers, the contents of RegVTs is redundant with TLI's
597 /// getRegisterType member function, however when with physical registers
598 /// it is necessary to have a separate record of the types.
600 SmallVector<MVT, 4> RegVTs;
602 /// Regs - This list holds the registers assigned to the values.
603 /// Each legal or promoted value requires one register, and each
604 /// expanded value requires multiple registers.
606 SmallVector<unsigned, 4> Regs;
610 RegsForValue(const SmallVector<unsigned, 4> ®s,
611 MVT regvt, EVT valuevt)
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
614 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
615 unsigned Reg, Type *Ty) {
616 ComputeValueVTs(tli, Ty, ValueVTs);
618 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
621 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
622 for (unsigned i = 0; i != NumRegs; ++i)
623 Regs.push_back(Reg + i);
624 RegVTs.push_back(RegisterVT);
629 /// append - Add the specified values to this one.
630 void append(const RegsForValue &RHS) {
631 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
632 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
633 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
636 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
637 /// this value and returns the result as a ValueVTs value. This uses
638 /// Chain/Flag as the input and updates them for the output Chain/Flag.
639 /// If the Flag pointer is NULL, no flag is used.
640 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
642 SDValue &Chain, SDValue *Flag,
643 const Value *V = nullptr) const;
645 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
646 /// specified value into the registers specified by this object. This uses
647 /// Chain/Flag as the input and updates them for the output Chain/Flag.
648 /// If the Flag pointer is NULL, no flag is used.
649 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
650 SDValue &Chain, SDValue *Flag, const Value *V) const;
652 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
653 /// operand list. This adds the code marker, matching input operand index
654 /// (if applicable), and includes the number of values added into it.
655 void AddInlineAsmOperands(unsigned Kind,
656 bool HasMatching, unsigned MatchingIdx,
658 std::vector<SDValue> &Ops) const;
662 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
663 /// this value and returns the result as a ValueVT value. This uses
664 /// Chain/Flag as the input and updates them for the output Chain/Flag.
665 /// If the Flag pointer is NULL, no flag is used.
666 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
667 FunctionLoweringInfo &FuncInfo,
669 SDValue &Chain, SDValue *Flag,
670 const Value *V) const {
671 // A Value with type {} or [0 x %t] needs no registers.
672 if (ValueVTs.empty())
675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
677 // Assemble the legal parts into the final values.
678 SmallVector<SDValue, 4> Values(ValueVTs.size());
679 SmallVector<SDValue, 8> Parts;
680 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
681 // Copy the legal parts from the registers.
682 EVT ValueVT = ValueVTs[Value];
683 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
684 MVT RegisterVT = RegVTs[Value];
686 Parts.resize(NumRegs);
687 for (unsigned i = 0; i != NumRegs; ++i) {
690 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
692 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
693 *Flag = P.getValue(2);
696 Chain = P.getValue(1);
699 // If the source register was virtual and if we know something about it,
700 // add an assert node.
701 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
702 !RegisterVT.isInteger() || RegisterVT.isVector())
705 const FunctionLoweringInfo::LiveOutInfo *LOI =
706 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
710 unsigned RegSize = RegisterVT.getSizeInBits();
711 unsigned NumSignBits = LOI->NumSignBits;
712 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
714 if (NumZeroBits == RegSize) {
715 // The current value is a zero.
716 // Explicitly express that as it would be easier for
717 // optimizations to kick in.
718 Parts[i] = DAG.getConstant(0, RegisterVT);
722 // FIXME: We capture more information than the dag can represent. For
723 // now, just use the tightest assertzext/assertsext possible.
725 EVT FromVT(MVT::Other);
726 if (NumSignBits == RegSize)
727 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
728 else if (NumZeroBits >= RegSize-1)
729 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
730 else if (NumSignBits > RegSize-8)
731 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
732 else if (NumZeroBits >= RegSize-8)
733 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
734 else if (NumSignBits > RegSize-16)
735 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
736 else if (NumZeroBits >= RegSize-16)
737 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
738 else if (NumSignBits > RegSize-32)
739 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
740 else if (NumZeroBits >= RegSize-32)
741 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
745 // Add an assertion node.
746 assert(FromVT != MVT::Other);
747 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
748 RegisterVT, P, DAG.getValueType(FromVT));
751 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
752 NumRegs, RegisterVT, ValueVT, V);
757 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
760 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
761 /// specified value into the registers specified by this object. This uses
762 /// Chain/Flag as the input and updates them for the output Chain/Flag.
763 /// If the Flag pointer is NULL, no flag is used.
764 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
765 SDValue &Chain, SDValue *Flag,
766 const Value *V) const {
767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
769 // Get the list of the values's legal parts.
770 unsigned NumRegs = Regs.size();
771 SmallVector<SDValue, 8> Parts(NumRegs);
772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
773 EVT ValueVT = ValueVTs[Value];
774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
775 MVT RegisterVT = RegVTs[Value];
776 ISD::NodeType ExtendKind =
777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
784 // Copy the parts into the registers.
785 SmallVector<SDValue, 8> Chains(NumRegs);
786 for (unsigned i = 0; i != NumRegs; ++i) {
789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
792 *Flag = Part.getValue(1);
795 Chains[i] = Part.getValue(0);
798 if (NumRegs == 1 || Flag)
799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
800 // flagged to it. That is the CopyToReg nodes and the user are considered
801 // a single scheduling unit. If we create a TokenFactor and return it as
802 // chain, then the TokenFactor is both a predecessor (operand) of the
803 // user as well as a successor (the TF operands are flagged to the user).
804 // c1, f1 = CopyToReg
805 // c2, f2 = CopyToReg
806 // c3 = TokenFactor c1, c2
809 Chain = Chains[NumRegs-1];
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
814 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
815 /// operand list. This adds the code marker and includes the number of
816 /// values added into it.
817 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
818 unsigned MatchingIdx,
820 std::vector<SDValue> &Ops) const {
821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
826 else if (!Regs.empty() &&
827 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
828 // Put the register class of the virtual registers in the flag word. That
829 // way, later passes can recompute register class constraints for inline
830 // assembly as well as normal instructions.
831 // Don't do this for tied operands that can use the regclass information
833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
841 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
842 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
843 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
844 MVT RegisterVT = RegVTs[Value];
845 for (unsigned i = 0; i != NumRegs; ++i) {
846 assert(Reg < Regs.size() && "Mismatch in # registers expected");
847 unsigned TheReg = Regs[Reg++];
848 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
850 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
851 // If we clobbered the stack pointer, MFI should know about it.
852 assert(DAG.getMachineFunction().getFrameInfo()->
853 hasInlineAsmWithSPAdjust());
859 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
860 const TargetLibraryInfo *li) {
864 DL = DAG.getSubtarget().getDataLayout();
865 Context = DAG.getContext();
866 LPadToCallSiteMap.clear();
869 /// clear - Clear out the current SelectionDAG and the associated
870 /// state and prepare this SelectionDAGBuilder object to be used
871 /// for a new block. This doesn't clear out information about
872 /// additional blocks that are needed to complete switch lowering
873 /// or PHI node updating; that information is cleared out as it is
875 void SelectionDAGBuilder::clear() {
877 UnusedArgNodeMap.clear();
878 PendingLoads.clear();
879 PendingExports.clear();
882 SDNodeOrder = LowestSDNodeOrder;
885 /// clearDanglingDebugInfo - Clear the dangling debug information
886 /// map. This function is separated from the clear so that debug
887 /// information that is dangling in a basic block can be properly
888 /// resolved in a different basic block. This allows the
889 /// SelectionDAG to resolve dangling debug information attached
891 void SelectionDAGBuilder::clearDanglingDebugInfo() {
892 DanglingDebugInfoMap.clear();
895 /// getRoot - Return the current virtual root of the Selection DAG,
896 /// flushing any PendingLoad items. This must be done before emitting
897 /// a store or any other node that may need to be ordered after any
898 /// prior load instructions.
900 SDValue SelectionDAGBuilder::getRoot() {
901 if (PendingLoads.empty())
902 return DAG.getRoot();
904 if (PendingLoads.size() == 1) {
905 SDValue Root = PendingLoads[0];
907 PendingLoads.clear();
911 // Otherwise, we have to make a token factor node.
912 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
914 PendingLoads.clear();
919 /// getControlRoot - Similar to getRoot, but instead of flushing all the
920 /// PendingLoad items, flush all the PendingExports items. It is necessary
921 /// to do this before emitting a terminator instruction.
923 SDValue SelectionDAGBuilder::getControlRoot() {
924 SDValue Root = DAG.getRoot();
926 if (PendingExports.empty())
929 // Turn all of the CopyToReg chains into one factored node.
930 if (Root.getOpcode() != ISD::EntryToken) {
931 unsigned i = 0, e = PendingExports.size();
932 for (; i != e; ++i) {
933 assert(PendingExports[i].getNode()->getNumOperands() > 1);
934 if (PendingExports[i].getNode()->getOperand(0) == Root)
935 break; // Don't add the root if we already indirectly depend on it.
939 PendingExports.push_back(Root);
942 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
944 PendingExports.clear();
949 void SelectionDAGBuilder::visit(const Instruction &I) {
950 // Set up outgoing PHI node register values before emitting the terminator.
951 if (isa<TerminatorInst>(&I))
952 HandlePHINodesInSuccessorBlocks(I.getParent());
958 visit(I.getOpcode(), I);
960 if (!isa<TerminatorInst>(&I) && !HasTailCall)
961 CopyToExportRegsIfNeeded(&I);
966 void SelectionDAGBuilder::visitPHI(const PHINode &) {
967 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
970 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
971 // Note: this doesn't use InstVisitor, because it has to work with
972 // ConstantExpr's in addition to instructions.
974 default: llvm_unreachable("Unknown instruction type encountered!");
975 // Build the switch statement using the Instruction.def file.
976 #define HANDLE_INST(NUM, OPCODE, CLASS) \
977 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
978 #include "llvm/IR/Instruction.def"
982 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
983 // generate the debug data structures now that we've seen its definition.
984 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
986 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
988 const DbgValueInst *DI = DDI.getDI();
989 DebugLoc dl = DDI.getdl();
990 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
991 MDNode *Variable = DI->getVariable();
992 uint64_t Offset = DI->getOffset();
993 // A dbg.value for an alloca is always indirect.
994 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
997 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, Val)) {
998 SDV = DAG.getDbgValue(Variable, Val.getNode(),
999 Val.getResNo(), IsIndirect,
1000 Offset, dl, DbgSDNodeOrder);
1001 DAG.AddDbgValue(SDV, Val.getNode(), false);
1004 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1005 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1009 /// getValue - Return an SDValue for the given Value.
1010 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1011 // If we already have an SDValue for this value, use it. It's important
1012 // to do this first, so that we don't create a CopyFromReg if we already
1013 // have a regular SDValue.
1014 SDValue &N = NodeMap[V];
1015 if (N.getNode()) return N;
1017 // If there's a virtual register allocated and initialized for this
1019 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1020 if (It != FuncInfo.ValueMap.end()) {
1021 unsigned InReg = It->second;
1022 RegsForValue RFV(*DAG.getContext(),
1023 *TM.getSubtargetImpl()->getTargetLowering(), InReg,
1025 SDValue Chain = DAG.getEntryNode();
1026 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1027 resolveDanglingDebugInfo(V, N);
1031 // Otherwise create a new SDValue and remember it.
1032 SDValue Val = getValueImpl(V);
1034 resolveDanglingDebugInfo(V, Val);
1038 /// getNonRegisterValue - Return an SDValue for the given Value, but
1039 /// don't look in FuncInfo.ValueMap for a virtual register.
1040 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1041 // If we already have an SDValue for this value, use it.
1042 SDValue &N = NodeMap[V];
1043 if (N.getNode()) return N;
1045 // Otherwise create a new SDValue and remember it.
1046 SDValue Val = getValueImpl(V);
1048 resolveDanglingDebugInfo(V, Val);
1052 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1053 /// Create an SDValue for the given value.
1054 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1055 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1057 if (const Constant *C = dyn_cast<Constant>(V)) {
1058 EVT VT = TLI->getValueType(V->getType(), true);
1060 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1061 return DAG.getConstant(*CI, VT);
1063 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1064 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1066 if (isa<ConstantPointerNull>(C)) {
1067 unsigned AS = V->getType()->getPointerAddressSpace();
1068 return DAG.getConstant(0, TLI->getPointerTy(AS));
1071 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1072 return DAG.getConstantFP(*CFP, VT);
1074 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1075 return DAG.getUNDEF(VT);
1077 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1078 visit(CE->getOpcode(), *CE);
1079 SDValue N1 = NodeMap[V];
1080 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1084 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1085 SmallVector<SDValue, 4> Constants;
1086 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1088 SDNode *Val = getValue(*OI).getNode();
1089 // If the operand is an empty aggregate, there are no values.
1091 // Add each leaf value from the operand to the Constants list
1092 // to form a flattened list of all the values.
1093 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1094 Constants.push_back(SDValue(Val, i));
1097 return DAG.getMergeValues(Constants, getCurSDLoc());
1100 if (const ConstantDataSequential *CDS =
1101 dyn_cast<ConstantDataSequential>(C)) {
1102 SmallVector<SDValue, 4> Ops;
1103 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1104 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1105 // Add each leaf value from the operand to the Constants list
1106 // to form a flattened list of all the values.
1107 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1108 Ops.push_back(SDValue(Val, i));
1111 if (isa<ArrayType>(CDS->getType()))
1112 return DAG.getMergeValues(Ops, getCurSDLoc());
1113 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1117 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1118 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1119 "Unknown struct or array constant!");
1121 SmallVector<EVT, 4> ValueVTs;
1122 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1123 unsigned NumElts = ValueVTs.size();
1125 return SDValue(); // empty struct
1126 SmallVector<SDValue, 4> Constants(NumElts);
1127 for (unsigned i = 0; i != NumElts; ++i) {
1128 EVT EltVT = ValueVTs[i];
1129 if (isa<UndefValue>(C))
1130 Constants[i] = DAG.getUNDEF(EltVT);
1131 else if (EltVT.isFloatingPoint())
1132 Constants[i] = DAG.getConstantFP(0, EltVT);
1134 Constants[i] = DAG.getConstant(0, EltVT);
1137 return DAG.getMergeValues(Constants, getCurSDLoc());
1140 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1141 return DAG.getBlockAddress(BA, VT);
1143 VectorType *VecTy = cast<VectorType>(V->getType());
1144 unsigned NumElements = VecTy->getNumElements();
1146 // Now that we know the number and type of the elements, get that number of
1147 // elements into the Ops array based on what kind of constant it is.
1148 SmallVector<SDValue, 16> Ops;
1149 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1150 for (unsigned i = 0; i != NumElements; ++i)
1151 Ops.push_back(getValue(CV->getOperand(i)));
1153 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1154 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1157 if (EltVT.isFloatingPoint())
1158 Op = DAG.getConstantFP(0, EltVT);
1160 Op = DAG.getConstant(0, EltVT);
1161 Ops.assign(NumElements, Op);
1164 // Create a BUILD_VECTOR node.
1165 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1168 // If this is a static alloca, generate it as the frameindex instead of
1170 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1171 DenseMap<const AllocaInst*, int>::iterator SI =
1172 FuncInfo.StaticAllocaMap.find(AI);
1173 if (SI != FuncInfo.StaticAllocaMap.end())
1174 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1177 // If this is an instruction which fast-isel has deferred, select it now.
1178 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1179 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1180 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1181 SDValue Chain = DAG.getEntryNode();
1182 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1185 llvm_unreachable("Can't get register for value!");
1188 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1189 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1190 SDValue Chain = getControlRoot();
1191 SmallVector<ISD::OutputArg, 8> Outs;
1192 SmallVector<SDValue, 8> OutVals;
1194 if (!FuncInfo.CanLowerReturn) {
1195 unsigned DemoteReg = FuncInfo.DemoteRegister;
1196 const Function *F = I.getParent()->getParent();
1198 // Emit a store of the return value through the virtual register.
1199 // Leave Outs empty so that LowerReturn won't try to load return
1200 // registers the usual way.
1201 SmallVector<EVT, 1> PtrValueVTs;
1202 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1205 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1206 SDValue RetOp = getValue(I.getOperand(0));
1208 SmallVector<EVT, 4> ValueVTs;
1209 SmallVector<uint64_t, 4> Offsets;
1210 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1211 unsigned NumValues = ValueVTs.size();
1213 SmallVector<SDValue, 4> Chains(NumValues);
1214 for (unsigned i = 0; i != NumValues; ++i) {
1215 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1216 RetPtr.getValueType(), RetPtr,
1217 DAG.getIntPtrConstant(Offsets[i]));
1219 DAG.getStore(Chain, getCurSDLoc(),
1220 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1221 // FIXME: better loc info would be nice.
1222 Add, MachinePointerInfo(), false, false, 0);
1225 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1226 MVT::Other, Chains);
1227 } else if (I.getNumOperands() != 0) {
1228 SmallVector<EVT, 4> ValueVTs;
1229 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1230 unsigned NumValues = ValueVTs.size();
1232 SDValue RetOp = getValue(I.getOperand(0));
1233 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1234 EVT VT = ValueVTs[j];
1236 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1238 const Function *F = I.getParent()->getParent();
1239 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241 ExtendKind = ISD::SIGN_EXTEND;
1242 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1244 ExtendKind = ISD::ZERO_EXTEND;
1246 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1247 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1249 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1250 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1251 SmallVector<SDValue, 4> Parts(NumParts);
1252 getCopyToParts(DAG, getCurSDLoc(),
1253 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1254 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1256 // 'inreg' on function refers to return value
1257 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1258 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1262 // Propagate extension type if any
1263 if (ExtendKind == ISD::SIGN_EXTEND)
1265 else if (ExtendKind == ISD::ZERO_EXTEND)
1268 for (unsigned i = 0; i < NumParts; ++i) {
1269 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1270 VT, /*isfixed=*/true, 0, 0));
1271 OutVals.push_back(Parts[i]);
1277 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1278 CallingConv::ID CallConv =
1279 DAG.getMachineFunction().getFunction()->getCallingConv();
1280 Chain = TM.getSubtargetImpl()->getTargetLowering()->LowerReturn(
1281 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1283 // Verify that the target's LowerReturn behaved as expected.
1284 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1285 "LowerReturn didn't return a valid chain!");
1287 // Update the DAG with the new chain value resulting from return lowering.
1291 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1292 /// created for it, emit nodes to copy the value into the virtual
1294 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1296 if (V->getType()->isEmptyTy())
1299 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1300 if (VMI != FuncInfo.ValueMap.end()) {
1301 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1302 CopyValueToVirtualRegister(V, VMI->second);
1306 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1307 /// the current basic block, add it to ValueMap now so that we'll get a
1309 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1310 // No need to export constants.
1311 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1313 // Already exported?
1314 if (FuncInfo.isExportedInst(V)) return;
1316 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1317 CopyValueToVirtualRegister(V, Reg);
1320 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1321 const BasicBlock *FromBB) {
1322 // The operands of the setcc have to be in this block. We don't know
1323 // how to export them from some other block.
1324 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1325 // Can export from current BB.
1326 if (VI->getParent() == FromBB)
1329 // Is already exported, noop.
1330 return FuncInfo.isExportedInst(V);
1333 // If this is an argument, we can export it if the BB is the entry block or
1334 // if it is already exported.
1335 if (isa<Argument>(V)) {
1336 if (FromBB == &FromBB->getParent()->getEntryBlock())
1339 // Otherwise, can only export this if it is already exported.
1340 return FuncInfo.isExportedInst(V);
1343 // Otherwise, constants can always be exported.
1347 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1348 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1349 const MachineBasicBlock *Dst) const {
1350 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1353 const BasicBlock *SrcBB = Src->getBasicBlock();
1354 const BasicBlock *DstBB = Dst->getBasicBlock();
1355 return BPI->getEdgeWeight(SrcBB, DstBB);
1358 void SelectionDAGBuilder::
1359 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1360 uint32_t Weight /* = 0 */) {
1362 Weight = getEdgeWeight(Src, Dst);
1363 Src->addSuccessor(Dst, Weight);
1367 static bool InBlock(const Value *V, const BasicBlock *BB) {
1368 if (const Instruction *I = dyn_cast<Instruction>(V))
1369 return I->getParent() == BB;
1373 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1374 /// This function emits a branch and is used at the leaves of an OR or an
1375 /// AND operator tree.
1378 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1379 MachineBasicBlock *TBB,
1380 MachineBasicBlock *FBB,
1381 MachineBasicBlock *CurBB,
1382 MachineBasicBlock *SwitchBB,
1385 const BasicBlock *BB = CurBB->getBasicBlock();
1387 // If the leaf of the tree is a comparison, merge the condition into
1389 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1390 // The operands of the cmp have to be in this block. We don't know
1391 // how to export them from some other block. If this is the first block
1392 // of the sequence, no exporting is needed.
1393 if (CurBB == SwitchBB ||
1394 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1395 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1396 ISD::CondCode Condition;
1397 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1398 Condition = getICmpCondCode(IC->getPredicate());
1399 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1400 Condition = getFCmpCondCode(FC->getPredicate());
1401 if (TM.Options.NoNaNsFPMath)
1402 Condition = getFCmpCodeWithoutNaN(Condition);
1404 Condition = ISD::SETEQ; // silence warning.
1405 llvm_unreachable("Unknown compare instruction");
1408 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1409 TBB, FBB, CurBB, TWeight, FWeight);
1410 SwitchCases.push_back(CB);
1415 // Create a CaseBlock record representing this branch.
1416 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1417 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1418 SwitchCases.push_back(CB);
1421 /// Scale down both weights to fit into uint32_t.
1422 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1423 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1424 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1425 NewTrue = NewTrue / Scale;
1426 NewFalse = NewFalse / Scale;
1429 /// FindMergedConditions - If Cond is an expression like
1430 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1431 MachineBasicBlock *TBB,
1432 MachineBasicBlock *FBB,
1433 MachineBasicBlock *CurBB,
1434 MachineBasicBlock *SwitchBB,
1435 unsigned Opc, uint32_t TWeight,
1437 // If this node is not part of the or/and tree, emit it as a branch.
1438 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1439 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1440 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1441 BOp->getParent() != CurBB->getBasicBlock() ||
1442 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1443 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1444 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1449 // Create TmpBB after CurBB.
1450 MachineFunction::iterator BBI = CurBB;
1451 MachineFunction &MF = DAG.getMachineFunction();
1452 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1453 CurBB->getParent()->insert(++BBI, TmpBB);
1455 if (Opc == Instruction::Or) {
1456 // Codegen X | Y as:
1465 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1466 // The requirement is that
1467 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1468 // = TrueProb for orignal BB.
1469 // Assuming the orignal weights are A and B, one choice is to set BB1's
1470 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1472 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1473 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1474 // TmpBB, but the math is more complicated.
1476 uint64_t NewTrueWeight = TWeight;
1477 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1478 ScaleWeights(NewTrueWeight, NewFalseWeight);
1479 // Emit the LHS condition.
1480 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1481 NewTrueWeight, NewFalseWeight);
1483 NewTrueWeight = TWeight;
1484 NewFalseWeight = 2 * (uint64_t)FWeight;
1485 ScaleWeights(NewTrueWeight, NewFalseWeight);
1486 // Emit the RHS condition into TmpBB.
1487 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1488 NewTrueWeight, NewFalseWeight);
1490 assert(Opc == Instruction::And && "Unknown merge op!");
1491 // Codegen X & Y as:
1499 // This requires creation of TmpBB after CurBB.
1501 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1502 // The requirement is that
1503 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1504 // = FalseProb for orignal BB.
1505 // Assuming the orignal weights are A and B, one choice is to set BB1's
1506 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1508 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1510 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1511 uint64_t NewFalseWeight = FWeight;
1512 ScaleWeights(NewTrueWeight, NewFalseWeight);
1513 // Emit the LHS condition.
1514 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1515 NewTrueWeight, NewFalseWeight);
1517 NewTrueWeight = 2 * (uint64_t)TWeight;
1518 NewFalseWeight = FWeight;
1519 ScaleWeights(NewTrueWeight, NewFalseWeight);
1520 // Emit the RHS condition into TmpBB.
1521 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1522 NewTrueWeight, NewFalseWeight);
1526 /// If the set of cases should be emitted as a series of branches, return true.
1527 /// If we should emit this as a bunch of and/or'd together conditions, return
1530 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1531 if (Cases.size() != 2) return true;
1533 // If this is two comparisons of the same values or'd or and'd together, they
1534 // will get folded into a single comparison, so don't emit two blocks.
1535 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1536 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1537 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1538 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1542 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1543 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1544 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1545 Cases[0].CC == Cases[1].CC &&
1546 isa<Constant>(Cases[0].CmpRHS) &&
1547 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1548 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1550 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1557 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1558 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1560 // Update machine-CFG edges.
1561 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1563 // Figure out which block is immediately after the current one.
1564 MachineBasicBlock *NextBlock = nullptr;
1565 MachineFunction::iterator BBI = BrMBB;
1566 if (++BBI != FuncInfo.MF->end())
1569 if (I.isUnconditional()) {
1570 // Update machine-CFG edges.
1571 BrMBB->addSuccessor(Succ0MBB);
1573 // If this is not a fall-through branch or optimizations are switched off,
1575 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1576 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1577 MVT::Other, getControlRoot(),
1578 DAG.getBasicBlock(Succ0MBB)));
1583 // If this condition is one of the special cases we handle, do special stuff
1585 const Value *CondVal = I.getCondition();
1586 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1588 // If this is a series of conditions that are or'd or and'd together, emit
1589 // this as a sequence of branches instead of setcc's with and/or operations.
1590 // As long as jumps are not expensive, this should improve performance.
1591 // For example, instead of something like:
1604 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1605 if (!TM.getSubtargetImpl()->getTargetLowering()->isJumpExpensive() &&
1606 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1607 BOp->getOpcode() == Instruction::Or)) {
1608 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1609 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1610 getEdgeWeight(BrMBB, Succ1MBB));
1611 // If the compares in later blocks need to use values not currently
1612 // exported from this block, export them now. This block should always
1613 // be the first entry.
1614 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1616 // Allow some cases to be rejected.
1617 if (ShouldEmitAsBranches(SwitchCases)) {
1618 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1619 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1620 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1623 // Emit the branch for this block.
1624 visitSwitchCase(SwitchCases[0], BrMBB);
1625 SwitchCases.erase(SwitchCases.begin());
1629 // Okay, we decided not to do this, remove any inserted MBB's and clear
1631 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1632 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1634 SwitchCases.clear();
1638 // Create a CaseBlock record representing this branch.
1639 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1640 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1642 // Use visitSwitchCase to actually insert the fast branch sequence for this
1644 visitSwitchCase(CB, BrMBB);
1647 /// visitSwitchCase - Emits the necessary code to represent a single node in
1648 /// the binary search tree resulting from lowering a switch instruction.
1649 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1650 MachineBasicBlock *SwitchBB) {
1652 SDValue CondLHS = getValue(CB.CmpLHS);
1653 SDLoc dl = getCurSDLoc();
1655 // Build the setcc now.
1657 // Fold "(X == true)" to X and "(X == false)" to !X to
1658 // handle common cases produced by branch lowering.
1659 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1660 CB.CC == ISD::SETEQ)
1662 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1663 CB.CC == ISD::SETEQ) {
1664 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1665 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1667 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1669 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1671 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1672 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1674 SDValue CmpOp = getValue(CB.CmpMHS);
1675 EVT VT = CmpOp.getValueType();
1677 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1678 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1681 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1682 VT, CmpOp, DAG.getConstant(Low, VT));
1683 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1684 DAG.getConstant(High-Low, VT), ISD::SETULE);
1688 // Update successor info
1689 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1690 // TrueBB and FalseBB are always different unless the incoming IR is
1691 // degenerate. This only happens when running llc on weird IR.
1692 if (CB.TrueBB != CB.FalseBB)
1693 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1695 // Set NextBlock to be the MBB immediately after the current one, if any.
1696 // This is used to avoid emitting unnecessary branches to the next block.
1697 MachineBasicBlock *NextBlock = nullptr;
1698 MachineFunction::iterator BBI = SwitchBB;
1699 if (++BBI != FuncInfo.MF->end())
1702 // If the lhs block is the next block, invert the condition so that we can
1703 // fall through to the lhs instead of the rhs block.
1704 if (CB.TrueBB == NextBlock) {
1705 std::swap(CB.TrueBB, CB.FalseBB);
1706 SDValue True = DAG.getConstant(1, Cond.getValueType());
1707 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1710 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1711 MVT::Other, getControlRoot(), Cond,
1712 DAG.getBasicBlock(CB.TrueBB));
1714 // Insert the false branch. Do this even if it's a fall through branch,
1715 // this makes it easier to do DAG optimizations which require inverting
1716 // the branch condition.
1717 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1718 DAG.getBasicBlock(CB.FalseBB));
1720 DAG.setRoot(BrCond);
1723 /// visitJumpTable - Emit JumpTable node in the current MBB
1724 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1725 // Emit the code for the jump table
1726 assert(JT.Reg != -1U && "Should lower JT Header first!");
1727 EVT PTy = TM.getSubtargetImpl()->getTargetLowering()->getPointerTy();
1728 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1730 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1731 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1732 MVT::Other, Index.getValue(1),
1734 DAG.setRoot(BrJumpTable);
1737 /// visitJumpTableHeader - This function emits necessary code to produce index
1738 /// in the JumpTable from switch case.
1739 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1740 JumpTableHeader &JTH,
1741 MachineBasicBlock *SwitchBB) {
1742 // Subtract the lowest switch case value from the value being switched on and
1743 // conditional branch to default mbb if the result is greater than the
1744 // difference between smallest and largest cases.
1745 SDValue SwitchOp = getValue(JTH.SValue);
1746 EVT VT = SwitchOp.getValueType();
1747 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1748 DAG.getConstant(JTH.First, VT));
1750 // The SDNode we just created, which holds the value being switched on minus
1751 // the smallest case value, needs to be copied to a virtual register so it
1752 // can be used as an index into the jump table in a subsequent basic block.
1753 // This value may be smaller or larger than the target's pointer type, and
1754 // therefore require extension or truncating.
1755 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1756 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1758 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1759 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1760 JumpTableReg, SwitchOp);
1761 JT.Reg = JumpTableReg;
1763 // Emit the range check for the jump table, and branch to the default block
1764 // for the switch statement if the value being switched on exceeds the largest
1765 // case in the switch.
1766 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1767 TLI->getSetCCResultType(*DAG.getContext(),
1768 Sub.getValueType()),
1770 DAG.getConstant(JTH.Last - JTH.First,VT),
1773 // Set NextBlock to be the MBB immediately after the current one, if any.
1774 // This is used to avoid emitting unnecessary branches to the next block.
1775 MachineBasicBlock *NextBlock = nullptr;
1776 MachineFunction::iterator BBI = SwitchBB;
1778 if (++BBI != FuncInfo.MF->end())
1781 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1782 MVT::Other, CopyTo, CMP,
1783 DAG.getBasicBlock(JT.Default));
1785 if (JT.MBB != NextBlock)
1786 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1787 DAG.getBasicBlock(JT.MBB));
1789 DAG.setRoot(BrCond);
1792 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1793 /// tail spliced into a stack protector check success bb.
1795 /// For a high level explanation of how this fits into the stack protector
1796 /// generation see the comment on the declaration of class
1797 /// StackProtectorDescriptor.
1798 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1799 MachineBasicBlock *ParentBB) {
1801 // First create the loads to the guard/stack slot for the comparison.
1802 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1803 EVT PtrTy = TLI->getPointerTy();
1805 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1806 int FI = MFI->getStackProtectorIndex();
1808 const Value *IRGuard = SPD.getGuard();
1809 SDValue GuardPtr = getValue(IRGuard);
1810 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1813 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1817 // If useLoadStackGuardNode returns true, retrieve the guard value from
1818 // the virtual register holding the value. Otherwise, emit a volatile load
1819 // to retrieve the stack guard value.
1820 if (TLI->useLoadStackGuardNode())
1821 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1822 SPD.getGuardReg(), PtrTy);
1824 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1825 GuardPtr, MachinePointerInfo(IRGuard, 0),
1826 true, false, false, Align);
1828 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1830 MachinePointerInfo::getFixedStack(FI),
1831 true, false, false, Align);
1833 // Perform the comparison via a subtract/getsetcc.
1834 EVT VT = Guard.getValueType();
1835 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1837 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1838 TLI->getSetCCResultType(*DAG.getContext(),
1839 Sub.getValueType()),
1840 Sub, DAG.getConstant(0, VT),
1843 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1844 // branch to failure MBB.
1845 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1846 MVT::Other, StackSlot.getOperand(0),
1847 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1848 // Otherwise branch to success MBB.
1849 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1851 DAG.getBasicBlock(SPD.getSuccessMBB()));
1856 /// Codegen the failure basic block for a stack protector check.
1858 /// A failure stack protector machine basic block consists simply of a call to
1859 /// __stack_chk_fail().
1861 /// For a high level explanation of how this fits into the stack protector
1862 /// generation see the comment on the declaration of class
1863 /// StackProtectorDescriptor.
1865 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1866 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1867 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1868 MVT::isVoid, nullptr, 0, false,
1869 getCurSDLoc(), false, false).second;
1873 /// visitBitTestHeader - This function emits necessary code to produce value
1874 /// suitable for "bit tests"
1875 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1876 MachineBasicBlock *SwitchBB) {
1877 // Subtract the minimum value
1878 SDValue SwitchOp = getValue(B.SValue);
1879 EVT VT = SwitchOp.getValueType();
1880 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1881 DAG.getConstant(B.First, VT));
1884 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1885 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1886 TLI->getSetCCResultType(*DAG.getContext(),
1887 Sub.getValueType()),
1888 Sub, DAG.getConstant(B.Range, VT),
1891 // Determine the type of the test operands.
1892 bool UsePtrType = false;
1893 if (!TLI->isTypeLegal(VT))
1896 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1897 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1898 // Switch table case range are encoded into series of masks.
1899 // Just use pointer type, it's guaranteed to fit.
1905 VT = TLI->getPointerTy();
1906 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1909 B.RegVT = VT.getSimpleVT();
1910 B.Reg = FuncInfo.CreateReg(B.RegVT);
1911 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1914 // Set NextBlock to be the MBB immediately after the current one, if any.
1915 // This is used to avoid emitting unnecessary branches to the next block.
1916 MachineBasicBlock *NextBlock = nullptr;
1917 MachineFunction::iterator BBI = SwitchBB;
1918 if (++BBI != FuncInfo.MF->end())
1921 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1923 addSuccessorWithWeight(SwitchBB, B.Default);
1924 addSuccessorWithWeight(SwitchBB, MBB);
1926 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1927 MVT::Other, CopyTo, RangeCmp,
1928 DAG.getBasicBlock(B.Default));
1930 if (MBB != NextBlock)
1931 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1932 DAG.getBasicBlock(MBB));
1934 DAG.setRoot(BrRange);
1937 /// visitBitTestCase - this function produces one "bit test"
1938 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1939 MachineBasicBlock* NextMBB,
1940 uint32_t BranchWeightToNext,
1943 MachineBasicBlock *SwitchBB) {
1945 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1948 unsigned PopCount = CountPopulation_64(B.Mask);
1949 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1950 if (PopCount == 1) {
1951 // Testing for a single bit; just compare the shift count with what it
1952 // would need to be to shift a 1 bit in that position.
1953 Cmp = DAG.getSetCC(getCurSDLoc(),
1954 TLI->getSetCCResultType(*DAG.getContext(), VT),
1956 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1958 } else if (PopCount == BB.Range) {
1959 // There is only one zero bit in the range, test for it directly.
1960 Cmp = DAG.getSetCC(getCurSDLoc(),
1961 TLI->getSetCCResultType(*DAG.getContext(), VT),
1963 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1966 // Make desired shift
1967 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1968 DAG.getConstant(1, VT), ShiftOp);
1970 // Emit bit tests and jumps
1971 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1972 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1973 Cmp = DAG.getSetCC(getCurSDLoc(),
1974 TLI->getSetCCResultType(*DAG.getContext(), VT),
1975 AndOp, DAG.getConstant(0, VT),
1979 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1980 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1981 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1982 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1984 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1985 MVT::Other, getControlRoot(),
1986 Cmp, DAG.getBasicBlock(B.TargetBB));
1988 // Set NextBlock to be the MBB immediately after the current one, if any.
1989 // This is used to avoid emitting unnecessary branches to the next block.
1990 MachineBasicBlock *NextBlock = nullptr;
1991 MachineFunction::iterator BBI = SwitchBB;
1992 if (++BBI != FuncInfo.MF->end())
1995 if (NextMBB != NextBlock)
1996 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1997 DAG.getBasicBlock(NextMBB));
2002 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2003 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2005 // Retrieve successors.
2006 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2007 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2009 const Value *Callee(I.getCalledValue());
2010 const Function *Fn = dyn_cast<Function>(Callee);
2011 if (isa<InlineAsm>(Callee))
2013 else if (Fn && Fn->isIntrinsic()) {
2014 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2015 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2017 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2019 // If the value of the invoke is used outside of its defining block, make it
2020 // available as a virtual register.
2021 CopyToExportRegsIfNeeded(&I);
2023 // Update successor info
2024 addSuccessorWithWeight(InvokeMBB, Return);
2025 addSuccessorWithWeight(InvokeMBB, LandingPad);
2027 // Drop into normal successor.
2028 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2029 MVT::Other, getControlRoot(),
2030 DAG.getBasicBlock(Return)));
2033 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2034 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2037 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2038 assert(FuncInfo.MBB->isLandingPad() &&
2039 "Call to landingpad not in landing pad!");
2041 MachineBasicBlock *MBB = FuncInfo.MBB;
2042 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2043 AddLandingPadInfo(LP, MMI, MBB);
2045 // If there aren't registers to copy the values into (e.g., during SjLj
2046 // exceptions), then don't bother to create these DAG nodes.
2047 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2048 if (TLI->getExceptionPointerRegister() == 0 &&
2049 TLI->getExceptionSelectorRegister() == 0)
2052 SmallVector<EVT, 2> ValueVTs;
2053 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2054 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2056 // Get the two live-in registers as SDValues. The physregs have already been
2057 // copied into virtual registers.
2059 Ops[0] = DAG.getZExtOrTrunc(
2060 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2061 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2062 getCurSDLoc(), ValueVTs[0]);
2063 Ops[1] = DAG.getZExtOrTrunc(
2064 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2065 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2066 getCurSDLoc(), ValueVTs[1]);
2069 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2070 DAG.getVTList(ValueVTs), Ops);
2074 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2075 /// small case ranges).
2076 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2077 CaseRecVector& WorkList,
2079 MachineBasicBlock *Default,
2080 MachineBasicBlock *SwitchBB) {
2081 // Size is the number of Cases represented by this range.
2082 size_t Size = CR.Range.second - CR.Range.first;
2086 // Get the MachineFunction which holds the current MBB. This is used when
2087 // inserting any additional MBBs necessary to represent the switch.
2088 MachineFunction *CurMF = FuncInfo.MF;
2090 // Figure out which block is immediately after the current one.
2091 MachineBasicBlock *NextBlock = nullptr;
2092 MachineFunction::iterator BBI = CR.CaseBB;
2094 if (++BBI != FuncInfo.MF->end())
2097 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2098 // If any two of the cases has the same destination, and if one value
2099 // is the same as the other, but has one bit unset that the other has set,
2100 // use bit manipulation to do two compares at once. For example:
2101 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2102 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2103 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2104 if (Size == 2 && CR.CaseBB == SwitchBB) {
2105 Case &Small = *CR.Range.first;
2106 Case &Big = *(CR.Range.second-1);
2108 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2109 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2110 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2112 // Check that there is only one bit different.
2113 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2114 (SmallValue | BigValue) == BigValue) {
2115 // Isolate the common bit.
2116 APInt CommonBit = BigValue & ~SmallValue;
2117 assert((SmallValue | CommonBit) == BigValue &&
2118 CommonBit.countPopulation() == 1 && "Not a common bit?");
2120 SDValue CondLHS = getValue(SV);
2121 EVT VT = CondLHS.getValueType();
2122 SDLoc DL = getCurSDLoc();
2124 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2125 DAG.getConstant(CommonBit, VT));
2126 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2127 Or, DAG.getConstant(BigValue, VT),
2130 // Update successor info.
2131 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2132 addSuccessorWithWeight(SwitchBB, Small.BB,
2133 Small.ExtraWeight + Big.ExtraWeight);
2134 addSuccessorWithWeight(SwitchBB, Default,
2135 // The default destination is the first successor in IR.
2136 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2138 // Insert the true branch.
2139 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2140 getControlRoot(), Cond,
2141 DAG.getBasicBlock(Small.BB));
2143 // Insert the false branch.
2144 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2145 DAG.getBasicBlock(Default));
2147 DAG.setRoot(BrCond);
2153 // Order cases by weight so the most likely case will be checked first.
2154 uint32_t UnhandledWeights = 0;
2156 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2157 uint32_t IWeight = I->ExtraWeight;
2158 UnhandledWeights += IWeight;
2159 for (CaseItr J = CR.Range.first; J < I; ++J) {
2160 uint32_t JWeight = J->ExtraWeight;
2161 if (IWeight > JWeight)
2166 // Rearrange the case blocks so that the last one falls through if possible.
2167 Case &BackCase = *(CR.Range.second-1);
2169 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2170 // The last case block won't fall through into 'NextBlock' if we emit the
2171 // branches in this order. See if rearranging a case value would help.
2172 // We start at the bottom as it's the case with the least weight.
2173 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2174 if (I->BB == NextBlock) {
2175 std::swap(*I, BackCase);
2180 // Create a CaseBlock record representing a conditional branch to
2181 // the Case's target mbb if the value being switched on SV is equal
2183 MachineBasicBlock *CurBlock = CR.CaseBB;
2184 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2185 MachineBasicBlock *FallThrough;
2187 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2188 CurMF->insert(BBI, FallThrough);
2190 // Put SV in a virtual register to make it available from the new blocks.
2191 ExportFromCurrentBlock(SV);
2193 // If the last case doesn't match, go to the default block.
2194 FallThrough = Default;
2197 const Value *RHS, *LHS, *MHS;
2199 if (I->High == I->Low) {
2200 // This is just small small case range :) containing exactly 1 case
2202 LHS = SV; RHS = I->High; MHS = nullptr;
2205 LHS = I->Low; MHS = SV; RHS = I->High;
2208 // The false weight should be sum of all un-handled cases.
2209 UnhandledWeights -= I->ExtraWeight;
2210 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2212 /* trueweight */ I->ExtraWeight,
2213 /* falseweight */ UnhandledWeights);
2215 // If emitting the first comparison, just call visitSwitchCase to emit the
2216 // code into the current block. Otherwise, push the CaseBlock onto the
2217 // vector to be later processed by SDISel, and insert the node's MBB
2218 // before the next MBB.
2219 if (CurBlock == SwitchBB)
2220 visitSwitchCase(CB, SwitchBB);
2222 SwitchCases.push_back(CB);
2224 CurBlock = FallThrough;
2230 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2231 return TLI.supportJumpTables() &&
2232 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2233 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2236 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2237 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2238 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2239 return (LastExt - FirstExt + 1ULL);
2242 /// handleJTSwitchCase - Emit jumptable for current switch case range
2243 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2244 CaseRecVector &WorkList,
2246 MachineBasicBlock *Default,
2247 MachineBasicBlock *SwitchBB) {
2248 Case& FrontCase = *CR.Range.first;
2249 Case& BackCase = *(CR.Range.second-1);
2251 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2252 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2254 APInt TSize(First.getBitWidth(), 0);
2255 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2258 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2259 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2262 APInt Range = ComputeRange(First, Last);
2263 // The density is TSize / Range. Require at least 40%.
2264 // It should not be possible for IntTSize to saturate for sane code, but make
2265 // sure we handle Range saturation correctly.
2266 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2267 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2268 if (IntTSize * 10 < IntRange * 4)
2271 DEBUG(dbgs() << "Lowering jump table\n"
2272 << "First entry: " << First << ". Last entry: " << Last << '\n'
2273 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2275 // Get the MachineFunction which holds the current MBB. This is used when
2276 // inserting any additional MBBs necessary to represent the switch.
2277 MachineFunction *CurMF = FuncInfo.MF;
2279 // Figure out which block is immediately after the current one.
2280 MachineFunction::iterator BBI = CR.CaseBB;
2283 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2285 // Create a new basic block to hold the code for loading the address
2286 // of the jump table, and jumping to it. Update successor information;
2287 // we will either branch to the default case for the switch, or the jump
2289 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2290 CurMF->insert(BBI, JumpTableBB);
2292 addSuccessorWithWeight(CR.CaseBB, Default);
2293 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2295 // Build a vector of destination BBs, corresponding to each target
2296 // of the jump table. If the value of the jump table slot corresponds to
2297 // a case statement, push the case's BB onto the vector, otherwise, push
2299 std::vector<MachineBasicBlock*> DestBBs;
2301 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2302 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2303 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2305 if (Low.sle(TEI) && TEI.sle(High)) {
2306 DestBBs.push_back(I->BB);
2310 DestBBs.push_back(Default);
2314 // Calculate weight for each unique destination in CR.
2315 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2317 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2318 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2319 DestWeights.find(I->BB);
2320 if (Itr != DestWeights.end())
2321 Itr->second += I->ExtraWeight;
2323 DestWeights[I->BB] = I->ExtraWeight;
2326 // Update successor info. Add one edge to each unique successor.
2327 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2328 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2329 E = DestBBs.end(); I != E; ++I) {
2330 if (!SuccsHandled[(*I)->getNumber()]) {
2331 SuccsHandled[(*I)->getNumber()] = true;
2332 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2333 DestWeights.find(*I);
2334 addSuccessorWithWeight(JumpTableBB, *I,
2335 Itr != DestWeights.end() ? Itr->second : 0);
2339 // Create a jump table index for this jump table.
2340 unsigned JTEncoding = TLI->getJumpTableEncoding();
2341 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2342 ->createJumpTableIndex(DestBBs);
2344 // Set the jump table information so that we can codegen it as a second
2345 // MachineBasicBlock
2346 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2347 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2348 if (CR.CaseBB == SwitchBB)
2349 visitJumpTableHeader(JT, JTH, SwitchBB);
2351 JTCases.push_back(JumpTableBlock(JTH, JT));
2355 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2357 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2358 CaseRecVector& WorkList,
2360 MachineBasicBlock* Default,
2361 MachineBasicBlock* SwitchBB) {
2362 // Get the MachineFunction which holds the current MBB. This is used when
2363 // inserting any additional MBBs necessary to represent the switch.
2364 MachineFunction *CurMF = FuncInfo.MF;
2366 // Figure out which block is immediately after the current one.
2367 MachineFunction::iterator BBI = CR.CaseBB;
2370 Case& FrontCase = *CR.Range.first;
2371 Case& BackCase = *(CR.Range.second-1);
2372 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2374 // Size is the number of Cases represented by this range.
2375 unsigned Size = CR.Range.second - CR.Range.first;
2377 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2378 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2380 CaseItr Pivot = CR.Range.first + Size/2;
2382 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2383 // (heuristically) allow us to emit JumpTable's later.
2384 APInt TSize(First.getBitWidth(), 0);
2385 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2389 APInt LSize = FrontCase.size();
2390 APInt RSize = TSize-LSize;
2391 DEBUG(dbgs() << "Selecting best pivot: \n"
2392 << "First: " << First << ", Last: " << Last <<'\n'
2393 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2394 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2396 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2397 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2398 APInt Range = ComputeRange(LEnd, RBegin);
2399 assert((Range - 2ULL).isNonNegative() &&
2400 "Invalid case distance");
2401 // Use volatile double here to avoid excess precision issues on some hosts,
2402 // e.g. that use 80-bit X87 registers.
2403 volatile double LDensity =
2404 (double)LSize.roundToDouble() /
2405 (LEnd - First + 1ULL).roundToDouble();
2406 volatile double RDensity =
2407 (double)RSize.roundToDouble() /
2408 (Last - RBegin + 1ULL).roundToDouble();
2409 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2410 // Should always split in some non-trivial place
2411 DEBUG(dbgs() <<"=>Step\n"
2412 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2413 << "LDensity: " << LDensity
2414 << ", RDensity: " << RDensity << '\n'
2415 << "Metric: " << Metric << '\n');
2416 if (FMetric < Metric) {
2419 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2426 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2427 if (areJTsAllowed(*TLI)) {
2428 // If our case is dense we *really* should handle it earlier!
2429 assert((FMetric > 0) && "Should handle dense range earlier!");
2431 Pivot = CR.Range.first + Size/2;
2434 CaseRange LHSR(CR.Range.first, Pivot);
2435 CaseRange RHSR(Pivot, CR.Range.second);
2436 const Constant *C = Pivot->Low;
2437 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2439 // We know that we branch to the LHS if the Value being switched on is
2440 // less than the Pivot value, C. We use this to optimize our binary
2441 // tree a bit, by recognizing that if SV is greater than or equal to the
2442 // LHS's Case Value, and that Case Value is exactly one less than the
2443 // Pivot's Value, then we can branch directly to the LHS's Target,
2444 // rather than creating a leaf node for it.
2445 if ((LHSR.second - LHSR.first) == 1 &&
2446 LHSR.first->High == CR.GE &&
2447 cast<ConstantInt>(C)->getValue() ==
2448 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2449 TrueBB = LHSR.first->BB;
2451 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2452 CurMF->insert(BBI, TrueBB);
2453 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2455 // Put SV in a virtual register to make it available from the new blocks.
2456 ExportFromCurrentBlock(SV);
2459 // Similar to the optimization above, if the Value being switched on is
2460 // known to be less than the Constant CR.LT, and the current Case Value
2461 // is CR.LT - 1, then we can branch directly to the target block for
2462 // the current Case Value, rather than emitting a RHS leaf node for it.
2463 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2464 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2465 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2466 FalseBB = RHSR.first->BB;
2468 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2469 CurMF->insert(BBI, FalseBB);
2470 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2472 // Put SV in a virtual register to make it available from the new blocks.
2473 ExportFromCurrentBlock(SV);
2476 // Create a CaseBlock record representing a conditional branch to
2477 // the LHS node if the value being switched on SV is less than C.
2478 // Otherwise, branch to LHS.
2479 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2481 if (CR.CaseBB == SwitchBB)
2482 visitSwitchCase(CB, SwitchBB);
2484 SwitchCases.push_back(CB);
2489 /// handleBitTestsSwitchCase - if current case range has few destination and
2490 /// range span less, than machine word bitwidth, encode case range into series
2491 /// of masks and emit bit tests with these masks.
2492 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2493 CaseRecVector& WorkList,
2495 MachineBasicBlock* Default,
2496 MachineBasicBlock* SwitchBB) {
2497 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2498 EVT PTy = TLI->getPointerTy();
2499 unsigned IntPtrBits = PTy.getSizeInBits();
2501 Case& FrontCase = *CR.Range.first;
2502 Case& BackCase = *(CR.Range.second-1);
2504 // Get the MachineFunction which holds the current MBB. This is used when
2505 // inserting any additional MBBs necessary to represent the switch.
2506 MachineFunction *CurMF = FuncInfo.MF;
2508 // If target does not have legal shift left, do not emit bit tests at all.
2509 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2513 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2515 // Single case counts one, case range - two.
2516 numCmps += (I->Low == I->High ? 1 : 2);
2519 // Count unique destinations
2520 SmallSet<MachineBasicBlock*, 4> Dests;
2521 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2522 Dests.insert(I->BB);
2523 if (Dests.size() > 3)
2524 // Don't bother the code below, if there are too much unique destinations
2527 DEBUG(dbgs() << "Total number of unique destinations: "
2528 << Dests.size() << '\n'
2529 << "Total number of comparisons: " << numCmps << '\n');
2531 // Compute span of values.
2532 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2533 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2534 APInt cmpRange = maxValue - minValue;
2536 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2537 << "Low bound: " << minValue << '\n'
2538 << "High bound: " << maxValue << '\n');
2540 if (cmpRange.uge(IntPtrBits) ||
2541 (!(Dests.size() == 1 && numCmps >= 3) &&
2542 !(Dests.size() == 2 && numCmps >= 5) &&
2543 !(Dests.size() >= 3 && numCmps >= 6)))
2546 DEBUG(dbgs() << "Emitting bit tests\n");
2547 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2549 // Optimize the case where all the case values fit in a
2550 // word without having to subtract minValue. In this case,
2551 // we can optimize away the subtraction.
2552 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2553 cmpRange = maxValue;
2555 lowBound = minValue;
2558 CaseBitsVector CasesBits;
2559 unsigned i, count = 0;
2561 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2562 MachineBasicBlock* Dest = I->BB;
2563 for (i = 0; i < count; ++i)
2564 if (Dest == CasesBits[i].BB)
2568 assert((count < 3) && "Too much destinations to test!");
2569 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2573 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2574 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2576 uint64_t lo = (lowValue - lowBound).getZExtValue();
2577 uint64_t hi = (highValue - lowBound).getZExtValue();
2578 CasesBits[i].ExtraWeight += I->ExtraWeight;
2580 for (uint64_t j = lo; j <= hi; j++) {
2581 CasesBits[i].Mask |= 1ULL << j;
2582 CasesBits[i].Bits++;
2586 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2590 // Figure out which block is immediately after the current one.
2591 MachineFunction::iterator BBI = CR.CaseBB;
2594 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2596 DEBUG(dbgs() << "Cases:\n");
2597 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2598 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2599 << ", Bits: " << CasesBits[i].Bits
2600 << ", BB: " << CasesBits[i].BB << '\n');
2602 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2603 CurMF->insert(BBI, CaseBB);
2604 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2606 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2608 // Put SV in a virtual register to make it available from the new blocks.
2609 ExportFromCurrentBlock(SV);
2612 BitTestBlock BTB(lowBound, cmpRange, SV,
2613 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2614 CR.CaseBB, Default, BTC);
2616 if (CR.CaseBB == SwitchBB)
2617 visitBitTestHeader(BTB, SwitchBB);
2619 BitTestCases.push_back(BTB);
2624 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2625 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2626 const SwitchInst& SI) {
2629 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2630 // Start with "simple" cases
2631 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2633 const BasicBlock *SuccBB = i.getCaseSuccessor();
2634 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2636 uint32_t ExtraWeight =
2637 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2639 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2640 SMBB, ExtraWeight));
2642 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2644 // Merge case into clusters
2645 if (Cases.size() >= 2)
2646 // Must recompute end() each iteration because it may be
2647 // invalidated by erase if we hold on to it
2648 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2649 J != Cases.end(); ) {
2650 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2651 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2652 MachineBasicBlock* nextBB = J->BB;
2653 MachineBasicBlock* currentBB = I->BB;
2655 // If the two neighboring cases go to the same destination, merge them
2656 // into a single case.
2657 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2659 I->ExtraWeight += J->ExtraWeight;
2666 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2667 if (I->Low != I->High)
2668 // A range counts double, since it requires two compares.
2675 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2676 MachineBasicBlock *Last) {
2678 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2679 if (JTCases[i].first.HeaderBB == First)
2680 JTCases[i].first.HeaderBB = Last;
2682 // Update BitTestCases.
2683 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2684 if (BitTestCases[i].Parent == First)
2685 BitTestCases[i].Parent = Last;
2688 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2689 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2691 // Figure out which block is immediately after the current one.
2692 MachineBasicBlock *NextBlock = nullptr;
2693 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2695 // If there is only the default destination, branch to it if it is not the
2696 // next basic block. Otherwise, just fall through.
2697 if (!SI.getNumCases()) {
2698 // Update machine-CFG edges.
2700 // If this is not a fall-through branch, emit the branch.
2701 SwitchMBB->addSuccessor(Default);
2702 if (Default != NextBlock)
2703 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2704 MVT::Other, getControlRoot(),
2705 DAG.getBasicBlock(Default)));
2710 // If there are any non-default case statements, create a vector of Cases
2711 // representing each one, and sort the vector so that we can efficiently
2712 // create a binary search tree from them.
2714 size_t numCmps = Clusterify(Cases, SI);
2715 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2716 << ". Total compares: " << numCmps << '\n');
2719 // Get the Value to be switched on and default basic blocks, which will be
2720 // inserted into CaseBlock records, representing basic blocks in the binary
2722 const Value *SV = SI.getCondition();
2724 // Push the initial CaseRec onto the worklist
2725 CaseRecVector WorkList;
2726 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2727 CaseRange(Cases.begin(),Cases.end())));
2729 while (!WorkList.empty()) {
2730 // Grab a record representing a case range to process off the worklist
2731 CaseRec CR = WorkList.back();
2732 WorkList.pop_back();
2734 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2737 // If the range has few cases (two or less) emit a series of specific
2739 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2742 // If the switch has more than N blocks, and is at least 40% dense, and the
2743 // target supports indirect branches, then emit a jump table rather than
2744 // lowering the switch to a binary tree of conditional branches.
2745 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2746 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2749 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2750 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2751 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2755 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2756 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2758 // Update machine-CFG edges with unique successors.
2759 SmallSet<BasicBlock*, 32> Done;
2760 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2761 BasicBlock *BB = I.getSuccessor(i);
2762 bool Inserted = Done.insert(BB);
2766 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2767 addSuccessorWithWeight(IndirectBrMBB, Succ);
2770 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2771 MVT::Other, getControlRoot(),
2772 getValue(I.getAddress())));
2775 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2776 if (DAG.getTarget().Options.TrapUnreachable)
2777 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2780 void SelectionDAGBuilder::visitFSub(const User &I) {
2781 // -0.0 - X --> fneg
2782 Type *Ty = I.getType();
2783 if (isa<Constant>(I.getOperand(0)) &&
2784 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2785 SDValue Op2 = getValue(I.getOperand(1));
2786 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2787 Op2.getValueType(), Op2));
2791 visitBinary(I, ISD::FSUB);
2794 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2795 SDValue Op1 = getValue(I.getOperand(0));
2796 SDValue Op2 = getValue(I.getOperand(1));
2801 if (const OverflowingBinaryOperator *OFBinOp =
2802 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2803 nuw = OFBinOp->hasNoUnsignedWrap();
2804 nsw = OFBinOp->hasNoSignedWrap();
2806 if (const PossiblyExactOperator *ExactOp =
2807 dyn_cast<const PossiblyExactOperator>(&I))
2808 exact = ExactOp->isExact();
2810 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2811 Op1, Op2, nuw, nsw, exact);
2812 setValue(&I, BinNodeValue);
2815 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2816 SDValue Op1 = getValue(I.getOperand(0));
2817 SDValue Op2 = getValue(I.getOperand(1));
2819 EVT ShiftTy = TM.getSubtargetImpl()->getTargetLowering()->getShiftAmountTy(
2820 Op2.getValueType());
2822 // Coerce the shift amount to the right type if we can.
2823 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2824 unsigned ShiftSize = ShiftTy.getSizeInBits();
2825 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2826 SDLoc DL = getCurSDLoc();
2828 // If the operand is smaller than the shift count type, promote it.
2829 if (ShiftSize > Op2Size)
2830 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2832 // If the operand is larger than the shift count type but the shift
2833 // count type has enough bits to represent any shift value, truncate
2834 // it now. This is a common case and it exposes the truncate to
2835 // optimization early.
2836 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2837 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2838 // Otherwise we'll need to temporarily settle for some other convenient
2839 // type. Type legalization will make adjustments once the shiftee is split.
2841 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2848 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2850 if (const OverflowingBinaryOperator *OFBinOp =
2851 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2852 nuw = OFBinOp->hasNoUnsignedWrap();
2853 nsw = OFBinOp->hasNoSignedWrap();
2855 if (const PossiblyExactOperator *ExactOp =
2856 dyn_cast<const PossiblyExactOperator>(&I))
2857 exact = ExactOp->isExact();
2860 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2865 void SelectionDAGBuilder::visitSDiv(const User &I) {
2866 SDValue Op1 = getValue(I.getOperand(0));
2867 SDValue Op2 = getValue(I.getOperand(1));
2869 // Turn exact SDivs into multiplications.
2870 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2872 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2873 !isa<ConstantSDNode>(Op1) &&
2874 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2875 setValue(&I, TM.getSubtargetImpl()->getTargetLowering()->BuildExactSDIV(
2876 Op1, Op2, getCurSDLoc(), DAG));
2878 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2882 void SelectionDAGBuilder::visitICmp(const User &I) {
2883 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2884 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2885 predicate = IC->getPredicate();
2886 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2887 predicate = ICmpInst::Predicate(IC->getPredicate());
2888 SDValue Op1 = getValue(I.getOperand(0));
2889 SDValue Op2 = getValue(I.getOperand(1));
2890 ISD::CondCode Opcode = getICmpCondCode(predicate);
2893 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2894 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2897 void SelectionDAGBuilder::visitFCmp(const User &I) {
2898 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2899 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2900 predicate = FC->getPredicate();
2901 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2902 predicate = FCmpInst::Predicate(FC->getPredicate());
2903 SDValue Op1 = getValue(I.getOperand(0));
2904 SDValue Op2 = getValue(I.getOperand(1));
2905 ISD::CondCode Condition = getFCmpCondCode(predicate);
2906 if (TM.Options.NoNaNsFPMath)
2907 Condition = getFCmpCodeWithoutNaN(Condition);
2909 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2910 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2913 void SelectionDAGBuilder::visitSelect(const User &I) {
2914 SmallVector<EVT, 4> ValueVTs;
2915 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), I.getType(),
2917 unsigned NumValues = ValueVTs.size();
2918 if (NumValues == 0) return;
2920 SmallVector<SDValue, 4> Values(NumValues);
2921 SDValue Cond = getValue(I.getOperand(0));
2922 SDValue TrueVal = getValue(I.getOperand(1));
2923 SDValue FalseVal = getValue(I.getOperand(2));
2924 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2925 ISD::VSELECT : ISD::SELECT;
2927 for (unsigned i = 0; i != NumValues; ++i)
2928 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2929 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2931 SDValue(TrueVal.getNode(),
2932 TrueVal.getResNo() + i),
2933 SDValue(FalseVal.getNode(),
2934 FalseVal.getResNo() + i));
2936 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2937 DAG.getVTList(ValueVTs), Values));
2940 void SelectionDAGBuilder::visitTrunc(const User &I) {
2941 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2942 SDValue N = getValue(I.getOperand(0));
2944 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2945 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2948 void SelectionDAGBuilder::visitZExt(const User &I) {
2949 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2950 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2951 SDValue N = getValue(I.getOperand(0));
2953 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2954 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2957 void SelectionDAGBuilder::visitSExt(const User &I) {
2958 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2959 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2960 SDValue N = getValue(I.getOperand(0));
2962 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2963 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2966 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2967 // FPTrunc is never a no-op cast, no need to check
2968 SDValue N = getValue(I.getOperand(0));
2969 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2970 EVT DestVT = TLI->getValueType(I.getType());
2971 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2973 DAG.getTargetConstant(0, TLI->getPointerTy())));
2976 void SelectionDAGBuilder::visitFPExt(const User &I) {
2977 // FPExt is never a no-op cast, no need to check
2978 SDValue N = getValue(I.getOperand(0));
2980 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2981 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2984 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2985 // FPToUI is never a no-op cast, no need to check
2986 SDValue N = getValue(I.getOperand(0));
2988 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2989 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2992 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2993 // FPToSI is never a no-op cast, no need to check
2994 SDValue N = getValue(I.getOperand(0));
2996 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2997 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3000 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3001 // UIToFP is never a no-op cast, no need to check
3002 SDValue N = getValue(I.getOperand(0));
3004 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3005 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3008 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3009 // SIToFP is never a no-op cast, no need to check
3010 SDValue N = getValue(I.getOperand(0));
3012 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3013 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3016 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3017 // What to do depends on the size of the integer and the size of the pointer.
3018 // We can either truncate, zero extend, or no-op, accordingly.
3019 SDValue N = getValue(I.getOperand(0));
3021 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3022 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3025 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3026 // What to do depends on the size of the integer and the size of the pointer.
3027 // We can either truncate, zero extend, or no-op, accordingly.
3028 SDValue N = getValue(I.getOperand(0));
3030 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3031 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3034 void SelectionDAGBuilder::visitBitCast(const User &I) {
3035 SDValue N = getValue(I.getOperand(0));
3037 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3039 // BitCast assures us that source and destination are the same size so this is
3040 // either a BITCAST or a no-op.
3041 if (DestVT != N.getValueType())
3042 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3043 DestVT, N)); // convert types.
3044 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3045 // might fold any kind of constant expression to an integer constant and that
3046 // is not what we are looking for. Only regcognize a bitcast of a genuine
3047 // constant integer as an opaque constant.
3048 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3049 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3052 setValue(&I, N); // noop cast.
3055 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3056 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3057 const Value *SV = I.getOperand(0);
3058 SDValue N = getValue(SV);
3060 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3062 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3063 unsigned DestAS = I.getType()->getPointerAddressSpace();
3065 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3066 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3071 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3072 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3073 SDValue InVec = getValue(I.getOperand(0));
3074 SDValue InVal = getValue(I.getOperand(1));
3075 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3076 getCurSDLoc(), TLI.getVectorIdxTy());
3078 DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3079 TM.getSubtargetImpl()->getTargetLowering()->getValueType(
3081 InVec, InVal, InIdx));
3084 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3086 SDValue InVec = getValue(I.getOperand(0));
3087 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3088 getCurSDLoc(), TLI.getVectorIdxTy());
3090 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3091 TM.getSubtargetImpl()->getTargetLowering()->getValueType(
3096 // Utility for visitShuffleVector - Return true if every element in Mask,
3097 // beginning from position Pos and ending in Pos+Size, falls within the
3098 // specified sequential range [L, L+Pos). or is undef.
3099 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3100 unsigned Pos, unsigned Size, int Low) {
3101 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3102 if (Mask[i] >= 0 && Mask[i] != Low)
3107 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3108 SDValue Src1 = getValue(I.getOperand(0));
3109 SDValue Src2 = getValue(I.getOperand(1));
3111 SmallVector<int, 8> Mask;
3112 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3113 unsigned MaskNumElts = Mask.size();
3115 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3116 EVT VT = TLI->getValueType(I.getType());
3117 EVT SrcVT = Src1.getValueType();
3118 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3120 if (SrcNumElts == MaskNumElts) {
3121 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3126 // Normalize the shuffle vector since mask and vector length don't match.
3127 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3128 // Mask is longer than the source vectors and is a multiple of the source
3129 // vectors. We can use concatenate vector to make the mask and vectors
3131 if (SrcNumElts*2 == MaskNumElts) {
3132 // First check for Src1 in low and Src2 in high
3133 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3134 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3135 // The shuffle is concatenating two vectors together.
3136 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3140 // Then check for Src2 in low and Src1 in high
3141 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3142 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3143 // The shuffle is concatenating two vectors together.
3144 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3150 // Pad both vectors with undefs to make them the same length as the mask.
3151 unsigned NumConcat = MaskNumElts / SrcNumElts;
3152 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3153 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3154 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3156 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3157 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3161 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3162 getCurSDLoc(), VT, MOps1);
3163 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3164 getCurSDLoc(), VT, MOps2);
3166 // Readjust mask for new input vector length.
3167 SmallVector<int, 8> MappedOps;
3168 for (unsigned i = 0; i != MaskNumElts; ++i) {
3170 if (Idx >= (int)SrcNumElts)
3171 Idx -= SrcNumElts - MaskNumElts;
3172 MappedOps.push_back(Idx);
3175 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3180 if (SrcNumElts > MaskNumElts) {
3181 // Analyze the access pattern of the vector to see if we can extract
3182 // two subvectors and do the shuffle. The analysis is done by calculating
3183 // the range of elements the mask access on both vectors.
3184 int MinRange[2] = { static_cast<int>(SrcNumElts),
3185 static_cast<int>(SrcNumElts)};
3186 int MaxRange[2] = {-1, -1};
3188 for (unsigned i = 0; i != MaskNumElts; ++i) {
3194 if (Idx >= (int)SrcNumElts) {
3198 if (Idx > MaxRange[Input])
3199 MaxRange[Input] = Idx;
3200 if (Idx < MinRange[Input])
3201 MinRange[Input] = Idx;
3204 // Check if the access is smaller than the vector size and can we find
3205 // a reasonable extract index.
3206 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3208 int StartIdx[2]; // StartIdx to extract from
3209 for (unsigned Input = 0; Input < 2; ++Input) {
3210 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3211 RangeUse[Input] = 0; // Unused
3212 StartIdx[Input] = 0;
3216 // Find a good start index that is a multiple of the mask length. Then
3217 // see if the rest of the elements are in range.
3218 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3219 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3220 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3221 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3224 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3225 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3228 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3229 // Extract appropriate subvector and generate a vector shuffle
3230 for (unsigned Input = 0; Input < 2; ++Input) {
3231 SDValue &Src = Input == 0 ? Src1 : Src2;
3232 if (RangeUse[Input] == 0)
3233 Src = DAG.getUNDEF(VT);
3235 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3236 Src, DAG.getConstant(StartIdx[Input],
3237 TLI->getVectorIdxTy()));
3240 // Calculate new mask.
3241 SmallVector<int, 8> MappedOps;
3242 for (unsigned i = 0; i != MaskNumElts; ++i) {
3245 if (Idx < (int)SrcNumElts)
3248 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3250 MappedOps.push_back(Idx);
3253 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3259 // We can't use either concat vectors or extract subvectors so fall back to
3260 // replacing the shuffle with extract and build vector.
3261 // to insert and build vector.
3262 EVT EltVT = VT.getVectorElementType();
3263 EVT IdxVT = TLI->getVectorIdxTy();
3264 SmallVector<SDValue,8> Ops;
3265 for (unsigned i = 0; i != MaskNumElts; ++i) {
3270 Res = DAG.getUNDEF(EltVT);
3272 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3273 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3275 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3276 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3282 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3285 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3286 const Value *Op0 = I.getOperand(0);
3287 const Value *Op1 = I.getOperand(1);
3288 Type *AggTy = I.getType();
3289 Type *ValTy = Op1->getType();
3290 bool IntoUndef = isa<UndefValue>(Op0);
3291 bool FromUndef = isa<UndefValue>(Op1);
3293 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3295 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3296 SmallVector<EVT, 4> AggValueVTs;
3297 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3298 SmallVector<EVT, 4> ValValueVTs;
3299 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3301 unsigned NumAggValues = AggValueVTs.size();
3302 unsigned NumValValues = ValValueVTs.size();
3303 SmallVector<SDValue, 4> Values(NumAggValues);
3305 SDValue Agg = getValue(Op0);
3307 // Copy the beginning value(s) from the original aggregate.
3308 for (; i != LinearIndex; ++i)
3309 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3310 SDValue(Agg.getNode(), Agg.getResNo() + i);
3311 // Copy values from the inserted value(s).
3313 SDValue Val = getValue(Op1);
3314 for (; i != LinearIndex + NumValValues; ++i)
3315 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3316 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3318 // Copy remaining value(s) from the original aggregate.
3319 for (; i != NumAggValues; ++i)
3320 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3321 SDValue(Agg.getNode(), Agg.getResNo() + i);
3323 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3324 DAG.getVTList(AggValueVTs), Values));
3327 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3328 const Value *Op0 = I.getOperand(0);
3329 Type *AggTy = Op0->getType();
3330 Type *ValTy = I.getType();
3331 bool OutOfUndef = isa<UndefValue>(Op0);
3333 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3335 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3336 SmallVector<EVT, 4> ValValueVTs;
3337 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3339 unsigned NumValValues = ValValueVTs.size();
3341 // Ignore a extractvalue that produces an empty object
3342 if (!NumValValues) {
3343 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3347 SmallVector<SDValue, 4> Values(NumValValues);
3349 SDValue Agg = getValue(Op0);
3350 // Copy out the selected value(s).
3351 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3352 Values[i - LinearIndex] =
3354 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3355 SDValue(Agg.getNode(), Agg.getResNo() + i);
3357 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3358 DAG.getVTList(ValValueVTs), Values));
3361 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3362 Value *Op0 = I.getOperand(0);
3363 // Note that the pointer operand may be a vector of pointers. Take the scalar
3364 // element which holds a pointer.
3365 Type *Ty = Op0->getType()->getScalarType();
3366 unsigned AS = Ty->getPointerAddressSpace();
3367 SDValue N = getValue(Op0);
3369 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3371 const Value *Idx = *OI;
3372 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3373 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3376 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3377 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3378 DAG.getConstant(Offset, N.getValueType()));
3381 Ty = StTy->getElementType(Field);
3383 Ty = cast<SequentialType>(Ty)->getElementType();
3385 // If this is a constant subscript, handle it quickly.
3386 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3387 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3388 if (CI->isZero()) continue;
3390 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3392 EVT PTy = TLI->getPointerTy(AS);
3393 unsigned PtrBits = PTy.getSizeInBits();
3395 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3396 DAG.getConstant(Offs, MVT::i64));
3398 OffsVal = DAG.getConstant(Offs, PTy);
3400 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3405 // N = N + Idx * ElementSize;
3406 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3407 DL->getTypeAllocSize(Ty));
3408 SDValue IdxN = getValue(Idx);
3410 // If the index is smaller or larger than intptr_t, truncate or extend
3412 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3414 // If this is a multiply by a power of two, turn it into a shl
3415 // immediately. This is a very common case.
3416 if (ElementSize != 1) {
3417 if (ElementSize.isPowerOf2()) {
3418 unsigned Amt = ElementSize.logBase2();
3419 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3420 N.getValueType(), IdxN,
3421 DAG.getConstant(Amt, IdxN.getValueType()));
3423 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3424 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3425 N.getValueType(), IdxN, Scale);
3429 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3430 N.getValueType(), N, IdxN);
3437 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3438 // If this is a fixed sized alloca in the entry block of the function,
3439 // allocate it statically on the stack.
3440 if (FuncInfo.StaticAllocaMap.count(&I))
3441 return; // getValue will auto-populate this.
3443 Type *Ty = I.getAllocatedType();
3444 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3445 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3447 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3450 SDValue AllocSize = getValue(I.getArraySize());
3452 EVT IntPtr = TLI->getPointerTy();
3453 if (AllocSize.getValueType() != IntPtr)
3454 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3456 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3458 DAG.getConstant(TySize, IntPtr));
3460 // Handle alignment. If the requested alignment is less than or equal to
3461 // the stack alignment, ignore it. If the size is greater than or equal to
3462 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3463 unsigned StackAlign =
3464 TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
3465 if (Align <= StackAlign)
3468 // Round the size of the allocation up to the stack alignment size
3469 // by add SA-1 to the size.
3470 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3471 AllocSize.getValueType(), AllocSize,
3472 DAG.getIntPtrConstant(StackAlign-1));
3474 // Mask out the low bits for alignment purposes.
3475 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3476 AllocSize.getValueType(), AllocSize,
3477 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3479 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3480 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3481 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3483 DAG.setRoot(DSA.getValue(1));
3485 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3488 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3490 return visitAtomicLoad(I);
3492 const Value *SV = I.getOperand(0);
3493 SDValue Ptr = getValue(SV);
3495 Type *Ty = I.getType();
3497 bool isVolatile = I.isVolatile();
3498 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3499 bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3500 unsigned Alignment = I.getAlignment();
3503 I.getAAMetadata(AAInfo);
3504 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3506 SmallVector<EVT, 4> ValueVTs;
3507 SmallVector<uint64_t, 4> Offsets;
3508 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), Ty, ValueVTs,
3510 unsigned NumValues = ValueVTs.size();
3515 bool ConstantMemory = false;
3516 if (isVolatile || NumValues > MaxParallelChains)
3517 // Serialize volatile loads with other side effects.
3519 else if (AA->pointsToConstantMemory(
3520 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3521 // Do not serialize (non-volatile) loads of constant memory with anything.
3522 Root = DAG.getEntryNode();
3523 ConstantMemory = true;
3525 // Do not serialize non-volatile loads against each other.
3526 Root = DAG.getRoot();
3529 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3531 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3533 SmallVector<SDValue, 4> Values(NumValues);
3534 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3536 EVT PtrVT = Ptr.getValueType();
3537 unsigned ChainI = 0;
3538 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3539 // Serializing loads here may result in excessive register pressure, and
3540 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3541 // could recover a bit by hoisting nodes upward in the chain by recognizing
3542 // they are side-effect free or do not alias. The optimizer should really
3543 // avoid this case by converting large object/array copies to llvm.memcpy
3544 // (MaxParallelChains should always remain as failsafe).
3545 if (ChainI == MaxParallelChains) {
3546 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3547 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3548 makeArrayRef(Chains.data(), ChainI));
3552 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3554 DAG.getConstant(Offsets[i], PtrVT));
3555 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3556 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3557 isNonTemporal, isInvariant, Alignment, AAInfo,
3561 Chains[ChainI] = L.getValue(1);
3564 if (!ConstantMemory) {
3565 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3566 makeArrayRef(Chains.data(), ChainI));
3570 PendingLoads.push_back(Chain);
3573 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3574 DAG.getVTList(ValueVTs), Values));
3577 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3579 return visitAtomicStore(I);
3581 const Value *SrcV = I.getOperand(0);
3582 const Value *PtrV = I.getOperand(1);
3584 SmallVector<EVT, 4> ValueVTs;
3585 SmallVector<uint64_t, 4> Offsets;
3586 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), SrcV->getType(),
3587 ValueVTs, &Offsets);
3588 unsigned NumValues = ValueVTs.size();
3592 // Get the lowered operands. Note that we do this after
3593 // checking if NumResults is zero, because with zero results
3594 // the operands won't have values in the map.
3595 SDValue Src = getValue(SrcV);
3596 SDValue Ptr = getValue(PtrV);
3598 SDValue Root = getRoot();
3599 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3601 EVT PtrVT = Ptr.getValueType();
3602 bool isVolatile = I.isVolatile();
3603 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3604 unsigned Alignment = I.getAlignment();
3607 I.getAAMetadata(AAInfo);
3609 unsigned ChainI = 0;
3610 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3611 // See visitLoad comments.
3612 if (ChainI == MaxParallelChains) {
3613 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3614 makeArrayRef(Chains.data(), ChainI));
3618 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3619 DAG.getConstant(Offsets[i], PtrVT));
3620 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3621 SDValue(Src.getNode(), Src.getResNo() + i),
3622 Add, MachinePointerInfo(PtrV, Offsets[i]),
3623 isVolatile, isNonTemporal, Alignment, AAInfo);
3624 Chains[ChainI] = St;
3627 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3628 makeArrayRef(Chains.data(), ChainI));
3629 DAG.setRoot(StoreNode);
3632 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3633 SynchronizationScope Scope,
3634 bool Before, SDLoc dl,
3636 const TargetLowering &TLI) {
3637 // Fence, if necessary
3639 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3641 else if (Order == Acquire || Order == Monotonic || Order == Unordered)
3644 if (Order == AcquireRelease)
3646 else if (Order == Release || Order == Monotonic || Order == Unordered)
3651 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3652 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3653 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops);
3656 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3657 SDLoc dl = getCurSDLoc();
3658 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3659 AtomicOrdering FailureOrder = I.getFailureOrdering();
3660 SynchronizationScope Scope = I.getSynchScope();
3662 SDValue InChain = getRoot();
3664 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3665 if (TLI->getInsertFencesForAtomic())
3666 InChain = InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl,
3669 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3670 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3671 SDValue L = DAG.getAtomicCmpSwap(
3672 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3673 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3674 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3676 TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3677 TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder, Scope);
3679 SDValue OutChain = L.getValue(2);
3681 if (TLI->getInsertFencesForAtomic())
3682 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3686 DAG.setRoot(OutChain);
3689 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3690 SDLoc dl = getCurSDLoc();
3692 switch (I.getOperation()) {
3693 default: llvm_unreachable("Unknown atomicrmw operation");
3694 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3695 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3696 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3697 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3698 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3699 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3700 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3701 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3702 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3703 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3704 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3706 AtomicOrdering Order = I.getOrdering();
3707 SynchronizationScope Scope = I.getSynchScope();
3709 SDValue InChain = getRoot();
3711 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3712 if (TLI->getInsertFencesForAtomic())
3713 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3717 DAG.getAtomic(NT, dl,
3718 getValue(I.getValOperand()).getSimpleValueType(),
3720 getValue(I.getPointerOperand()),
3721 getValue(I.getValOperand()),
3722 I.getPointerOperand(), 0 /* Alignment */,
3723 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3726 SDValue OutChain = L.getValue(1);
3728 if (TLI->getInsertFencesForAtomic())
3729 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3733 DAG.setRoot(OutChain);
3736 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3737 SDLoc dl = getCurSDLoc();
3738 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3741 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3742 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3743 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3746 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3747 SDLoc dl = getCurSDLoc();
3748 AtomicOrdering Order = I.getOrdering();
3749 SynchronizationScope Scope = I.getSynchScope();
3751 SDValue InChain = getRoot();
3753 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3754 EVT VT = TLI->getValueType(I.getType());
3756 if (I.getAlignment() < VT.getSizeInBits() / 8)
3757 report_fatal_error("Cannot generate unaligned atomic load");
3759 MachineMemOperand *MMO =
3760 DAG.getMachineFunction().
3761 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3762 MachineMemOperand::MOVolatile |
3763 MachineMemOperand::MOLoad,
3765 I.getAlignment() ? I.getAlignment() :
3766 DAG.getEVTAlignment(VT));
3768 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3770 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3771 getValue(I.getPointerOperand()), MMO,
3772 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3775 SDValue OutChain = L.getValue(1);
3777 if (TLI->getInsertFencesForAtomic())
3778 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3782 DAG.setRoot(OutChain);
3785 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3786 SDLoc dl = getCurSDLoc();
3788 AtomicOrdering Order = I.getOrdering();
3789 SynchronizationScope Scope = I.getSynchScope();
3791 SDValue InChain = getRoot();
3793 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3794 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3796 if (I.getAlignment() < VT.getSizeInBits() / 8)
3797 report_fatal_error("Cannot generate unaligned atomic store");
3799 if (TLI->getInsertFencesForAtomic())
3800 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3804 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3806 getValue(I.getPointerOperand()),
3807 getValue(I.getValueOperand()),
3808 I.getPointerOperand(), I.getAlignment(),
3809 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3812 if (TLI->getInsertFencesForAtomic())
3813 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3816 DAG.setRoot(OutChain);
3819 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3821 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3822 unsigned Intrinsic) {
3823 bool HasChain = !I.doesNotAccessMemory();
3824 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3826 // Build the operand list.
3827 SmallVector<SDValue, 8> Ops;
3828 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3830 // We don't need to serialize loads against other loads.
3831 Ops.push_back(DAG.getRoot());
3833 Ops.push_back(getRoot());
3837 // Info is set by getTgtMemInstrinsic
3838 TargetLowering::IntrinsicInfo Info;
3839 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3840 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3842 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3843 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3844 Info.opc == ISD::INTRINSIC_W_CHAIN)
3845 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3847 // Add all operands of the call to the operand list.
3848 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3849 SDValue Op = getValue(I.getArgOperand(i));
3853 SmallVector<EVT, 4> ValueVTs;
3854 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3857 ValueVTs.push_back(MVT::Other);
3859 SDVTList VTs = DAG.getVTList(ValueVTs);
3863 if (IsTgtIntrinsic) {
3864 // This is target intrinsic that touches memory
3865 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3866 VTs, Ops, Info.memVT,
3867 MachinePointerInfo(Info.ptrVal, Info.offset),
3868 Info.align, Info.vol,
3869 Info.readMem, Info.writeMem);
3870 } else if (!HasChain) {
3871 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3872 } else if (!I.getType()->isVoidTy()) {
3873 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3875 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3879 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3881 PendingLoads.push_back(Chain);
3886 if (!I.getType()->isVoidTy()) {
3887 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3888 EVT VT = TLI->getValueType(PTy);
3889 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3892 setValue(&I, Result);
3896 /// GetSignificand - Get the significand and build it into a floating-point
3897 /// number with exponent of 1:
3899 /// Op = (Op & 0x007fffff) | 0x3f800000;
3901 /// where Op is the hexadecimal representation of floating point value.
3903 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3904 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3905 DAG.getConstant(0x007fffff, MVT::i32));
3906 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3907 DAG.getConstant(0x3f800000, MVT::i32));
3908 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3911 /// GetExponent - Get the exponent:
3913 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3915 /// where Op is the hexadecimal representation of floating point value.
3917 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3919 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3920 DAG.getConstant(0x7f800000, MVT::i32));
3921 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3922 DAG.getConstant(23, TLI.getPointerTy()));
3923 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3924 DAG.getConstant(127, MVT::i32));
3925 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3928 /// getF32Constant - Get 32-bit floating point constant.
3930 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3931 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3935 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3936 /// limited-precision mode.
3937 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3938 const TargetLowering &TLI) {
3939 if (Op.getValueType() == MVT::f32 &&
3940 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3942 // Put the exponent in the right bit position for later addition to the
3945 // #define LOG2OFe 1.4426950f
3946 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3947 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3948 getF32Constant(DAG, 0x3fb8aa3b));
3949 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3951 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3952 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3953 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3955 // IntegerPartOfX <<= 23;
3956 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3957 DAG.getConstant(23, TLI.getPointerTy()));
3959 SDValue TwoToFracPartOfX;
3960 if (LimitFloatPrecision <= 6) {
3961 // For floating-point precision of 6:
3963 // TwoToFractionalPartOfX =
3965 // (0.735607626f + 0.252464424f * x) * x;
3967 // error 0.0144103317, which is 6 bits
3968 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3969 getF32Constant(DAG, 0x3e814304));
3970 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3971 getF32Constant(DAG, 0x3f3c50c8));
3972 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3973 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3974 getF32Constant(DAG, 0x3f7f5e7e));
3975 } else if (LimitFloatPrecision <= 12) {
3976 // For floating-point precision of 12:
3978 // TwoToFractionalPartOfX =
3981 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3983 // 0.000107046256 error, which is 13 to 14 bits
3984 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3985 getF32Constant(DAG, 0x3da235e3));
3986 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3987 getF32Constant(DAG, 0x3e65b8f3));
3988 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3989 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3990 getF32Constant(DAG, 0x3f324b07));
3991 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3992 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3993 getF32Constant(DAG, 0x3f7ff8fd));
3994 } else { // LimitFloatPrecision <= 18
3995 // For floating-point precision of 18:
3997 // TwoToFractionalPartOfX =
4001 // (0.554906021e-1f +
4002 // (0.961591928e-2f +
4003 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4005 // error 2.47208000*10^(-7), which is better than 18 bits
4006 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4007 getF32Constant(DAG, 0x3924b03e));
4008 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4009 getF32Constant(DAG, 0x3ab24b87));
4010 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4011 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4012 getF32Constant(DAG, 0x3c1d8c17));
4013 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4014 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4015 getF32Constant(DAG, 0x3d634a1d));
4016 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4017 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4018 getF32Constant(DAG, 0x3e75fe14));
4019 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4020 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4021 getF32Constant(DAG, 0x3f317234));
4022 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4023 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4024 getF32Constant(DAG, 0x3f800000));
4027 // Add the exponent into the result in integer domain.
4028 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
4029 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4030 DAG.getNode(ISD::ADD, dl, MVT::i32,
4031 t13, IntegerPartOfX));
4034 // No special expansion.
4035 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4038 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4039 /// limited-precision mode.
4040 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4041 const TargetLowering &TLI) {
4042 if (Op.getValueType() == MVT::f32 &&
4043 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4044 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4046 // Scale the exponent by log(2) [0.69314718f].
4047 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4048 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4049 getF32Constant(DAG, 0x3f317218));
4051 // Get the significand and build it into a floating-point number with
4053 SDValue X = GetSignificand(DAG, Op1, dl);
4055 SDValue LogOfMantissa;
4056 if (LimitFloatPrecision <= 6) {
4057 // For floating-point precision of 6:
4061 // (1.4034025f - 0.23903021f * x) * x;
4063 // error 0.0034276066, which is better than 8 bits
4064 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4065 getF32Constant(DAG, 0xbe74c456));
4066 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4067 getF32Constant(DAG, 0x3fb3a2b1));
4068 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4069 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4070 getF32Constant(DAG, 0x3f949a29));
4071 } else if (LimitFloatPrecision <= 12) {
4072 // For floating-point precision of 12:
4078 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4080 // error 0.000061011436, which is 14 bits
4081 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4082 getF32Constant(DAG, 0xbd67b6d6));
4083 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4084 getF32Constant(DAG, 0x3ee4f4b8));
4085 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4086 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4087 getF32Constant(DAG, 0x3fbc278b));
4088 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4089 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4090 getF32Constant(DAG, 0x40348e95));
4091 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4092 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4093 getF32Constant(DAG, 0x3fdef31a));
4094 } else { // LimitFloatPrecision <= 18
4095 // For floating-point precision of 18:
4103 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4105 // error 0.0000023660568, which is better than 18 bits
4106 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4107 getF32Constant(DAG, 0xbc91e5ac));
4108 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4109 getF32Constant(DAG, 0x3e4350aa));
4110 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4111 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4112 getF32Constant(DAG, 0x3f60d3e3));
4113 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4114 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4115 getF32Constant(DAG, 0x4011cdf0));
4116 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4117 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4118 getF32Constant(DAG, 0x406cfd1c));
4119 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4120 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4121 getF32Constant(DAG, 0x408797cb));
4122 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4123 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4124 getF32Constant(DAG, 0x4006dcab));
4127 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4130 // No special expansion.
4131 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4134 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4135 /// limited-precision mode.
4136 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4137 const TargetLowering &TLI) {
4138 if (Op.getValueType() == MVT::f32 &&
4139 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4140 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4142 // Get the exponent.
4143 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4145 // Get the significand and build it into a floating-point number with
4147 SDValue X = GetSignificand(DAG, Op1, dl);
4149 // Different possible minimax approximations of significand in
4150 // floating-point for various degrees of accuracy over [1,2].
4151 SDValue Log2ofMantissa;
4152 if (LimitFloatPrecision <= 6) {
4153 // For floating-point precision of 6:
4155 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4157 // error 0.0049451742, which is more than 7 bits
4158 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4159 getF32Constant(DAG, 0xbeb08fe0));
4160 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4161 getF32Constant(DAG, 0x40019463));
4162 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4163 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4164 getF32Constant(DAG, 0x3fd6633d));
4165 } else if (LimitFloatPrecision <= 12) {
4166 // For floating-point precision of 12:
4172 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4174 // error 0.0000876136000, which is better than 13 bits
4175 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4176 getF32Constant(DAG, 0xbda7262e));
4177 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4178 getF32Constant(DAG, 0x3f25280b));
4179 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4180 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4181 getF32Constant(DAG, 0x4007b923));
4182 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4183 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4184 getF32Constant(DAG, 0x40823e2f));
4185 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4186 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4187 getF32Constant(DAG, 0x4020d29c));
4188 } else { // LimitFloatPrecision <= 18
4189 // For floating-point precision of 18:
4198 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4200 // error 0.0000018516, which is better than 18 bits
4201 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4202 getF32Constant(DAG, 0xbcd2769e));
4203 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4204 getF32Constant(DAG, 0x3e8ce0b9));
4205 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4206 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4207 getF32Constant(DAG, 0x3fa22ae7));
4208 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4209 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4210 getF32Constant(DAG, 0x40525723));
4211 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4212 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4213 getF32Constant(DAG, 0x40aaf200));
4214 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4215 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4216 getF32Constant(DAG, 0x40c39dad));
4217 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4218 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4219 getF32Constant(DAG, 0x4042902c));
4222 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4225 // No special expansion.
4226 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4229 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4230 /// limited-precision mode.
4231 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4232 const TargetLowering &TLI) {
4233 if (Op.getValueType() == MVT::f32 &&
4234 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4235 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4237 // Scale the exponent by log10(2) [0.30102999f].
4238 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4239 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4240 getF32Constant(DAG, 0x3e9a209a));
4242 // Get the significand and build it into a floating-point number with
4244 SDValue X = GetSignificand(DAG, Op1, dl);
4246 SDValue Log10ofMantissa;
4247 if (LimitFloatPrecision <= 6) {
4248 // For floating-point precision of 6:
4250 // Log10ofMantissa =
4252 // (0.60948995f - 0.10380950f * x) * x;
4254 // error 0.0014886165, which is 6 bits
4255 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4256 getF32Constant(DAG, 0xbdd49a13));
4257 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4258 getF32Constant(DAG, 0x3f1c0789));
4259 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4260 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4261 getF32Constant(DAG, 0x3f011300));
4262 } else if (LimitFloatPrecision <= 12) {
4263 // For floating-point precision of 12:
4265 // Log10ofMantissa =
4268 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4270 // error 0.00019228036, which is better than 12 bits
4271 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4272 getF32Constant(DAG, 0x3d431f31));
4273 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4274 getF32Constant(DAG, 0x3ea21fb2));
4275 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4276 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4277 getF32Constant(DAG, 0x3f6ae232));
4278 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4279 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4280 getF32Constant(DAG, 0x3f25f7c3));
4281 } else { // LimitFloatPrecision <= 18
4282 // For floating-point precision of 18:
4284 // Log10ofMantissa =
4289 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4291 // error 0.0000037995730, which is better than 18 bits
4292 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4293 getF32Constant(DAG, 0x3c5d51ce));
4294 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4295 getF32Constant(DAG, 0x3e00685a));
4296 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4297 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4298 getF32Constant(DAG, 0x3efb6798));
4299 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4300 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4301 getF32Constant(DAG, 0x3f88d192));
4302 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4303 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4304 getF32Constant(DAG, 0x3fc4316c));
4305 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4306 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4307 getF32Constant(DAG, 0x3f57ce70));
4310 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4313 // No special expansion.
4314 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4317 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4318 /// limited-precision mode.
4319 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4320 const TargetLowering &TLI) {
4321 if (Op.getValueType() == MVT::f32 &&
4322 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4323 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4325 // FractionalPartOfX = x - (float)IntegerPartOfX;
4326 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4327 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4329 // IntegerPartOfX <<= 23;
4330 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4331 DAG.getConstant(23, TLI.getPointerTy()));
4333 SDValue TwoToFractionalPartOfX;
4334 if (LimitFloatPrecision <= 6) {
4335 // For floating-point precision of 6:
4337 // TwoToFractionalPartOfX =
4339 // (0.735607626f + 0.252464424f * x) * x;
4341 // error 0.0144103317, which is 6 bits
4342 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4343 getF32Constant(DAG, 0x3e814304));
4344 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4345 getF32Constant(DAG, 0x3f3c50c8));
4346 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4347 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4348 getF32Constant(DAG, 0x3f7f5e7e));
4349 } else if (LimitFloatPrecision <= 12) {
4350 // For floating-point precision of 12:
4352 // TwoToFractionalPartOfX =
4355 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4357 // error 0.000107046256, which is 13 to 14 bits
4358 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4359 getF32Constant(DAG, 0x3da235e3));
4360 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4361 getF32Constant(DAG, 0x3e65b8f3));
4362 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4363 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4364 getF32Constant(DAG, 0x3f324b07));
4365 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4366 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4367 getF32Constant(DAG, 0x3f7ff8fd));
4368 } else { // LimitFloatPrecision <= 18
4369 // For floating-point precision of 18:
4371 // TwoToFractionalPartOfX =
4375 // (0.554906021e-1f +
4376 // (0.961591928e-2f +
4377 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4378 // error 2.47208000*10^(-7), which is better than 18 bits
4379 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4380 getF32Constant(DAG, 0x3924b03e));
4381 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4382 getF32Constant(DAG, 0x3ab24b87));
4383 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4384 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4385 getF32Constant(DAG, 0x3c1d8c17));
4386 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4387 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4388 getF32Constant(DAG, 0x3d634a1d));
4389 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4390 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4391 getF32Constant(DAG, 0x3e75fe14));
4392 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4393 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4394 getF32Constant(DAG, 0x3f317234));
4395 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4396 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4397 getF32Constant(DAG, 0x3f800000));
4400 // Add the exponent into the result in integer domain.
4401 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4402 TwoToFractionalPartOfX);
4403 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4404 DAG.getNode(ISD::ADD, dl, MVT::i32,
4405 t13, IntegerPartOfX));
4408 // No special expansion.
4409 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4412 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4413 /// limited-precision mode with x == 10.0f.
4414 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4415 SelectionDAG &DAG, const TargetLowering &TLI) {
4416 bool IsExp10 = false;
4417 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4418 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4419 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4421 IsExp10 = LHSC->isExactlyValue(Ten);
4426 // Put the exponent in the right bit position for later addition to the
4429 // #define LOG2OF10 3.3219281f
4430 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4431 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4432 getF32Constant(DAG, 0x40549a78));
4433 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4435 // FractionalPartOfX = x - (float)IntegerPartOfX;
4436 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4437 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4439 // IntegerPartOfX <<= 23;
4440 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4441 DAG.getConstant(23, TLI.getPointerTy()));
4443 SDValue TwoToFractionalPartOfX;
4444 if (LimitFloatPrecision <= 6) {
4445 // For floating-point precision of 6:
4447 // twoToFractionalPartOfX =
4449 // (0.735607626f + 0.252464424f * x) * x;
4451 // error 0.0144103317, which is 6 bits
4452 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4453 getF32Constant(DAG, 0x3e814304));
4454 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4455 getF32Constant(DAG, 0x3f3c50c8));
4456 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4457 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4458 getF32Constant(DAG, 0x3f7f5e7e));
4459 } else if (LimitFloatPrecision <= 12) {
4460 // For floating-point precision of 12:
4462 // TwoToFractionalPartOfX =
4465 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4467 // error 0.000107046256, which is 13 to 14 bits
4468 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4469 getF32Constant(DAG, 0x3da235e3));
4470 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4471 getF32Constant(DAG, 0x3e65b8f3));
4472 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4473 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4474 getF32Constant(DAG, 0x3f324b07));
4475 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4476 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4477 getF32Constant(DAG, 0x3f7ff8fd));
4478 } else { // LimitFloatPrecision <= 18
4479 // For floating-point precision of 18:
4481 // TwoToFractionalPartOfX =
4485 // (0.554906021e-1f +
4486 // (0.961591928e-2f +
4487 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4488 // error 2.47208000*10^(-7), which is better than 18 bits
4489 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4490 getF32Constant(DAG, 0x3924b03e));
4491 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4492 getF32Constant(DAG, 0x3ab24b87));
4493 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4494 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4495 getF32Constant(DAG, 0x3c1d8c17));
4496 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4497 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4498 getF32Constant(DAG, 0x3d634a1d));
4499 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4500 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4501 getF32Constant(DAG, 0x3e75fe14));
4502 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4503 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4504 getF32Constant(DAG, 0x3f317234));
4505 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4506 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4507 getF32Constant(DAG, 0x3f800000));
4510 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4511 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4512 DAG.getNode(ISD::ADD, dl, MVT::i32,
4513 t13, IntegerPartOfX));
4516 // No special expansion.
4517 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4521 /// ExpandPowI - Expand a llvm.powi intrinsic.
4522 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4523 SelectionDAG &DAG) {
4524 // If RHS is a constant, we can expand this out to a multiplication tree,
4525 // otherwise we end up lowering to a call to __powidf2 (for example). When
4526 // optimizing for size, we only want to do this if the expansion would produce
4527 // a small number of multiplies, otherwise we do the full expansion.
4528 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4529 // Get the exponent as a positive value.
4530 unsigned Val = RHSC->getSExtValue();
4531 if ((int)Val < 0) Val = -Val;
4533 // powi(x, 0) -> 1.0
4535 return DAG.getConstantFP(1.0, LHS.getValueType());
4537 const Function *F = DAG.getMachineFunction().getFunction();
4538 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4539 Attribute::OptimizeForSize) ||
4540 // If optimizing for size, don't insert too many multiplies. This
4541 // inserts up to 5 multiplies.
4542 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4543 // We use the simple binary decomposition method to generate the multiply
4544 // sequence. There are more optimal ways to do this (for example,
4545 // powi(x,15) generates one more multiply than it should), but this has
4546 // the benefit of being both really simple and much better than a libcall.
4547 SDValue Res; // Logically starts equal to 1.0
4548 SDValue CurSquare = LHS;
4552 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4554 Res = CurSquare; // 1.0*CurSquare.
4557 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4558 CurSquare, CurSquare);
4562 // If the original was negative, invert the result, producing 1/(x*x*x).
4563 if (RHSC->getSExtValue() < 0)
4564 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4565 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4570 // Otherwise, expand to a libcall.
4571 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4574 // getTruncatedArgReg - Find underlying register used for an truncated
4576 static unsigned getTruncatedArgReg(const SDValue &N) {
4577 if (N.getOpcode() != ISD::TRUNCATE)
4580 const SDValue &Ext = N.getOperand(0);
4581 if (Ext.getOpcode() == ISD::AssertZext ||
4582 Ext.getOpcode() == ISD::AssertSext) {
4583 const SDValue &CFR = Ext.getOperand(0);
4584 if (CFR.getOpcode() == ISD::CopyFromReg)
4585 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4586 if (CFR.getOpcode() == ISD::TRUNCATE)
4587 return getTruncatedArgReg(CFR);
4592 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4593 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4594 /// At the end of instruction selection, they will be inserted to the entry BB.
4596 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4597 int64_t Offset, bool IsIndirect,
4599 const Argument *Arg = dyn_cast<Argument>(V);
4603 MachineFunction &MF = DAG.getMachineFunction();
4604 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4606 // Ignore inlined function arguments here.
4607 DIVariable DV(Variable);
4608 if (DV.isInlinedFnArgument(MF.getFunction()))
4611 Optional<MachineOperand> Op;
4612 // Some arguments' frame index is recorded during argument lowering.
4613 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4614 Op = MachineOperand::CreateFI(FI);
4616 if (!Op && N.getNode()) {
4618 if (N.getOpcode() == ISD::CopyFromReg)
4619 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4621 Reg = getTruncatedArgReg(N);
4622 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4623 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4624 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4629 Op = MachineOperand::CreateReg(Reg, false);
4633 // Check if ValueMap has reg number.
4634 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4635 if (VMI != FuncInfo.ValueMap.end())
4636 Op = MachineOperand::CreateReg(VMI->second, false);
4639 if (!Op && N.getNode())
4640 // Check if frame index is available.
4641 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4642 if (FrameIndexSDNode *FINode =
4643 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4644 Op = MachineOperand::CreateFI(FINode->getIndex());
4650 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
4651 TII->get(TargetOpcode::DBG_VALUE),
4653 Op->getReg(), Offset, Variable));
4655 FuncInfo.ArgDbgValues.push_back(
4656 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4657 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4662 // VisualStudio defines setjmp as _setjmp
4663 #if defined(_MSC_VER) && defined(setjmp) && \
4664 !defined(setjmp_undefined_for_msvc)
4665 # pragma push_macro("setjmp")
4667 # define setjmp_undefined_for_msvc
4670 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4671 /// we want to emit this as a call to a named external function, return the name
4672 /// otherwise lower it and return null.
4674 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4675 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
4676 SDLoc sdl = getCurSDLoc();
4677 DebugLoc dl = getCurDebugLoc();
4680 switch (Intrinsic) {
4682 // By default, turn this into a target intrinsic node.
4683 visitTargetIntrinsic(I, Intrinsic);
4685 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4686 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4687 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4688 case Intrinsic::returnaddress:
4689 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4690 getValue(I.getArgOperand(0))));
4692 case Intrinsic::frameaddress:
4693 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4694 getValue(I.getArgOperand(0))));
4696 case Intrinsic::read_register: {
4697 Value *Reg = I.getArgOperand(0);
4698 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4700 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
4701 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4704 case Intrinsic::write_register: {
4705 Value *Reg = I.getArgOperand(0);
4706 Value *RegValue = I.getArgOperand(1);
4707 SDValue Chain = getValue(RegValue).getOperand(0);
4708 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4709 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4710 RegName, getValue(RegValue)));
4713 case Intrinsic::setjmp:
4714 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4715 case Intrinsic::longjmp:
4716 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4717 case Intrinsic::memcpy: {
4718 // Assert for address < 256 since we support only user defined address
4720 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4722 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4724 "Unknown address space");
4725 SDValue Op1 = getValue(I.getArgOperand(0));
4726 SDValue Op2 = getValue(I.getArgOperand(1));
4727 SDValue Op3 = getValue(I.getArgOperand(2));
4728 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4730 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4731 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4732 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4733 MachinePointerInfo(I.getArgOperand(0)),
4734 MachinePointerInfo(I.getArgOperand(1))));
4737 case Intrinsic::memset: {
4738 // Assert for address < 256 since we support only user defined address
4740 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4742 "Unknown address space");
4743 SDValue Op1 = getValue(I.getArgOperand(0));
4744 SDValue Op2 = getValue(I.getArgOperand(1));
4745 SDValue Op3 = getValue(I.getArgOperand(2));
4746 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4748 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4749 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4750 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4751 MachinePointerInfo(I.getArgOperand(0))));
4754 case Intrinsic::memmove: {
4755 // Assert for address < 256 since we support only user defined address
4757 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4759 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4761 "Unknown address space");
4762 SDValue Op1 = getValue(I.getArgOperand(0));
4763 SDValue Op2 = getValue(I.getArgOperand(1));
4764 SDValue Op3 = getValue(I.getArgOperand(2));
4765 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4767 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4768 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4769 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4770 MachinePointerInfo(I.getArgOperand(0)),
4771 MachinePointerInfo(I.getArgOperand(1))));
4774 case Intrinsic::dbg_declare: {
4775 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4776 MDNode *Variable = DI.getVariable();
4777 const Value *Address = DI.getAddress();
4778 DIVariable DIVar(Variable);
4779 assert((!DIVar || DIVar.isVariable()) &&
4780 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4781 if (!Address || !DIVar) {
4782 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4786 // Check if address has undef value.
4787 if (isa<UndefValue>(Address) ||
4788 (Address->use_empty() && !isa<Argument>(Address))) {
4789 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4793 SDValue &N = NodeMap[Address];
4794 if (!N.getNode() && isa<Argument>(Address))
4795 // Check unused arguments map.
4796 N = UnusedArgNodeMap[Address];
4799 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4800 Address = BCI->getOperand(0);
4801 // Parameters are handled specially.
4803 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4804 isa<Argument>(Address));
4806 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4808 if (isParameter && !AI) {
4809 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4811 // Byval parameter. We have a frame index at this point.
4812 SDV = DAG.getFrameIndexDbgValue(Variable, FINode->getIndex(),
4813 0, dl, SDNodeOrder);
4815 // Address is an argument, so try to emit its dbg value using
4816 // virtual register info from the FuncInfo.ValueMap.
4817 EmitFuncArgumentDbgValue(Address, Variable, 0, false, N);
4821 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4822 true, 0, dl, SDNodeOrder);
4824 // Can't do anything with other non-AI cases yet.
4825 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4826 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4827 DEBUG(Address->dump());
4830 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4832 // If Address is an argument then try to emit its dbg value using
4833 // virtual register info from the FuncInfo.ValueMap.
4834 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, false, N)) {
4835 // If variable is pinned by a alloca in dominating bb then
4836 // use StaticAllocaMap.
4837 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4838 if (AI->getParent() != DI.getParent()) {
4839 DenseMap<const AllocaInst*, int>::iterator SI =
4840 FuncInfo.StaticAllocaMap.find(AI);
4841 if (SI != FuncInfo.StaticAllocaMap.end()) {
4842 SDV = DAG.getFrameIndexDbgValue(Variable, SI->second,
4843 0, dl, SDNodeOrder);
4844 DAG.AddDbgValue(SDV, nullptr, false);
4849 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4854 case Intrinsic::dbg_value: {
4855 const DbgValueInst &DI = cast<DbgValueInst>(I);
4856 DIVariable DIVar(DI.getVariable());
4857 assert((!DIVar || DIVar.isVariable()) &&
4858 "Variable in DbgValueInst should be either null or a DIVariable.");
4862 MDNode *Variable = DI.getVariable();
4863 uint64_t Offset = DI.getOffset();
4864 const Value *V = DI.getValue();
4869 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4870 SDV = DAG.getConstantDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4871 DAG.AddDbgValue(SDV, nullptr, false);
4873 // Do not use getValue() in here; we don't want to generate code at
4874 // this point if it hasn't been done yet.
4875 SDValue N = NodeMap[V];
4876 if (!N.getNode() && isa<Argument>(V))
4877 // Check unused arguments map.
4878 N = UnusedArgNodeMap[V];
4880 // A dbg.value for an alloca is always indirect.
4881 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4882 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, N)) {
4883 SDV = DAG.getDbgValue(Variable, N.getNode(),
4884 N.getResNo(), IsIndirect,
4885 Offset, dl, SDNodeOrder);
4886 DAG.AddDbgValue(SDV, N.getNode(), false);
4888 } else if (!V->use_empty() ) {
4889 // Do not call getValue(V) yet, as we don't want to generate code.
4890 // Remember it for later.
4891 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4892 DanglingDebugInfoMap[V] = DDI;
4894 // We may expand this to cover more cases. One case where we have no
4895 // data available is an unreferenced parameter.
4896 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4900 // Build a debug info table entry.
4901 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4902 V = BCI->getOperand(0);
4903 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4904 // Don't handle byval struct arguments or VLAs, for example.
4906 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4907 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4910 DenseMap<const AllocaInst*, int>::iterator SI =
4911 FuncInfo.StaticAllocaMap.find(AI);
4912 if (SI == FuncInfo.StaticAllocaMap.end())
4913 return nullptr; // VLAs.
4917 case Intrinsic::eh_typeid_for: {
4918 // Find the type id for the given typeinfo.
4919 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4920 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4921 Res = DAG.getConstant(TypeID, MVT::i32);
4926 case Intrinsic::eh_return_i32:
4927 case Intrinsic::eh_return_i64:
4928 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4929 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4932 getValue(I.getArgOperand(0)),
4933 getValue(I.getArgOperand(1))));
4935 case Intrinsic::eh_unwind_init:
4936 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4938 case Intrinsic::eh_dwarf_cfa: {
4939 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4940 TLI->getPointerTy());
4941 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4942 CfaArg.getValueType(),
4943 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4944 CfaArg.getValueType()),
4946 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4947 TLI->getPointerTy(),
4948 DAG.getConstant(0, TLI->getPointerTy()));
4949 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4953 case Intrinsic::eh_sjlj_callsite: {
4954 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4955 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4956 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4957 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4959 MMI.setCurrentCallSite(CI->getZExtValue());
4962 case Intrinsic::eh_sjlj_functioncontext: {
4963 // Get and store the index of the function context.
4964 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4966 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4967 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4968 MFI->setFunctionContextIndex(FI);
4971 case Intrinsic::eh_sjlj_setjmp: {
4974 Ops[1] = getValue(I.getArgOperand(0));
4975 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4976 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4977 setValue(&I, Op.getValue(0));
4978 DAG.setRoot(Op.getValue(1));
4981 case Intrinsic::eh_sjlj_longjmp: {
4982 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4983 getRoot(), getValue(I.getArgOperand(0))));
4987 case Intrinsic::x86_mmx_pslli_w:
4988 case Intrinsic::x86_mmx_pslli_d:
4989 case Intrinsic::x86_mmx_pslli_q:
4990 case Intrinsic::x86_mmx_psrli_w:
4991 case Intrinsic::x86_mmx_psrli_d:
4992 case Intrinsic::x86_mmx_psrli_q:
4993 case Intrinsic::x86_mmx_psrai_w:
4994 case Intrinsic::x86_mmx_psrai_d: {
4995 SDValue ShAmt = getValue(I.getArgOperand(1));
4996 if (isa<ConstantSDNode>(ShAmt)) {
4997 visitTargetIntrinsic(I, Intrinsic);
5000 unsigned NewIntrinsic = 0;
5001 EVT ShAmtVT = MVT::v2i32;
5002 switch (Intrinsic) {
5003 case Intrinsic::x86_mmx_pslli_w:
5004 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5006 case Intrinsic::x86_mmx_pslli_d:
5007 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5009 case Intrinsic::x86_mmx_pslli_q:
5010 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5012 case Intrinsic::x86_mmx_psrli_w:
5013 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5015 case Intrinsic::x86_mmx_psrli_d:
5016 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5018 case Intrinsic::x86_mmx_psrli_q:
5019 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5021 case Intrinsic::x86_mmx_psrai_w:
5022 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5024 case Intrinsic::x86_mmx_psrai_d:
5025 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5027 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5030 // The vector shift intrinsics with scalars uses 32b shift amounts but
5031 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5033 // We must do this early because v2i32 is not a legal type.
5036 ShOps[1] = DAG.getConstant(0, MVT::i32);
5037 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5038 EVT DestVT = TLI->getValueType(I.getType());
5039 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5040 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5041 DAG.getConstant(NewIntrinsic, MVT::i32),
5042 getValue(I.getArgOperand(0)), ShAmt);
5046 case Intrinsic::x86_avx_vinsertf128_pd_256:
5047 case Intrinsic::x86_avx_vinsertf128_ps_256:
5048 case Intrinsic::x86_avx_vinsertf128_si_256:
5049 case Intrinsic::x86_avx2_vinserti128: {
5050 EVT DestVT = TLI->getValueType(I.getType());
5051 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
5052 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5053 ElVT.getVectorNumElements();
5054 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5055 getValue(I.getArgOperand(0)),
5056 getValue(I.getArgOperand(1)),
5057 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5061 case Intrinsic::x86_avx_vextractf128_pd_256:
5062 case Intrinsic::x86_avx_vextractf128_ps_256:
5063 case Intrinsic::x86_avx_vextractf128_si_256:
5064 case Intrinsic::x86_avx2_vextracti128: {
5065 EVT DestVT = TLI->getValueType(I.getType());
5066 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5067 DestVT.getVectorNumElements();
5068 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5069 getValue(I.getArgOperand(0)),
5070 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5074 case Intrinsic::convertff:
5075 case Intrinsic::convertfsi:
5076 case Intrinsic::convertfui:
5077 case Intrinsic::convertsif:
5078 case Intrinsic::convertuif:
5079 case Intrinsic::convertss:
5080 case Intrinsic::convertsu:
5081 case Intrinsic::convertus:
5082 case Intrinsic::convertuu: {
5083 ISD::CvtCode Code = ISD::CVT_INVALID;
5084 switch (Intrinsic) {
5085 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5086 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5087 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5088 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5089 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5090 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5091 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5092 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5093 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5094 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5096 EVT DestVT = TLI->getValueType(I.getType());
5097 const Value *Op1 = I.getArgOperand(0);
5098 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5099 DAG.getValueType(DestVT),
5100 DAG.getValueType(getValue(Op1).getValueType()),
5101 getValue(I.getArgOperand(1)),
5102 getValue(I.getArgOperand(2)),
5107 case Intrinsic::powi:
5108 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5109 getValue(I.getArgOperand(1)), DAG));
5111 case Intrinsic::log:
5112 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5114 case Intrinsic::log2:
5115 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5117 case Intrinsic::log10:
5118 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5120 case Intrinsic::exp:
5121 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5123 case Intrinsic::exp2:
5124 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5126 case Intrinsic::pow:
5127 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5128 getValue(I.getArgOperand(1)), DAG, *TLI));
5130 case Intrinsic::sqrt:
5131 case Intrinsic::fabs:
5132 case Intrinsic::sin:
5133 case Intrinsic::cos:
5134 case Intrinsic::floor:
5135 case Intrinsic::ceil:
5136 case Intrinsic::trunc:
5137 case Intrinsic::rint:
5138 case Intrinsic::nearbyint:
5139 case Intrinsic::round: {
5141 switch (Intrinsic) {
5142 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5143 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5144 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5145 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5146 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5147 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5148 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5149 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5150 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5151 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5152 case Intrinsic::round: Opcode = ISD::FROUND; break;
5155 setValue(&I, DAG.getNode(Opcode, sdl,
5156 getValue(I.getArgOperand(0)).getValueType(),
5157 getValue(I.getArgOperand(0))));
5160 case Intrinsic::copysign:
5161 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5162 getValue(I.getArgOperand(0)).getValueType(),
5163 getValue(I.getArgOperand(0)),
5164 getValue(I.getArgOperand(1))));
5166 case Intrinsic::fma:
5167 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5168 getValue(I.getArgOperand(0)).getValueType(),
5169 getValue(I.getArgOperand(0)),
5170 getValue(I.getArgOperand(1)),
5171 getValue(I.getArgOperand(2))));
5173 case Intrinsic::fmuladd: {
5174 EVT VT = TLI->getValueType(I.getType());
5175 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5176 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5177 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5178 getValue(I.getArgOperand(0)).getValueType(),
5179 getValue(I.getArgOperand(0)),
5180 getValue(I.getArgOperand(1)),
5181 getValue(I.getArgOperand(2))));
5183 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5184 getValue(I.getArgOperand(0)).getValueType(),
5185 getValue(I.getArgOperand(0)),
5186 getValue(I.getArgOperand(1)));
5187 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5188 getValue(I.getArgOperand(0)).getValueType(),
5190 getValue(I.getArgOperand(2)));
5195 case Intrinsic::convert_to_fp16:
5196 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5197 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5198 getValue(I.getArgOperand(0)),
5199 DAG.getTargetConstant(0, MVT::i32))));
5201 case Intrinsic::convert_from_fp16:
5203 DAG.getNode(ISD::FP_EXTEND, sdl, TLI->getValueType(I.getType()),
5204 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5205 getValue(I.getArgOperand(0)))));
5207 case Intrinsic::pcmarker: {
5208 SDValue Tmp = getValue(I.getArgOperand(0));
5209 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5212 case Intrinsic::readcyclecounter: {
5213 SDValue Op = getRoot();
5214 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5215 DAG.getVTList(MVT::i64, MVT::Other), Op);
5217 DAG.setRoot(Res.getValue(1));
5220 case Intrinsic::bswap:
5221 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5222 getValue(I.getArgOperand(0)).getValueType(),
5223 getValue(I.getArgOperand(0))));
5225 case Intrinsic::cttz: {
5226 SDValue Arg = getValue(I.getArgOperand(0));
5227 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5228 EVT Ty = Arg.getValueType();
5229 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5233 case Intrinsic::ctlz: {
5234 SDValue Arg = getValue(I.getArgOperand(0));
5235 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5236 EVT Ty = Arg.getValueType();
5237 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5241 case Intrinsic::ctpop: {
5242 SDValue Arg = getValue(I.getArgOperand(0));
5243 EVT Ty = Arg.getValueType();
5244 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5247 case Intrinsic::stacksave: {
5248 SDValue Op = getRoot();
5249 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5250 DAG.getVTList(TLI->getPointerTy(), MVT::Other), Op);
5252 DAG.setRoot(Res.getValue(1));
5255 case Intrinsic::stackrestore: {
5256 Res = getValue(I.getArgOperand(0));
5257 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5260 case Intrinsic::stackprotector: {
5261 // Emit code into the DAG to store the stack guard onto the stack.
5262 MachineFunction &MF = DAG.getMachineFunction();
5263 MachineFrameInfo *MFI = MF.getFrameInfo();
5264 EVT PtrTy = TLI->getPointerTy();
5265 SDValue Src, Chain = getRoot();
5267 if (TLI->useLoadStackGuardNode()) {
5268 // Emit a LOAD_STACK_GUARD node.
5269 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5271 LoadInst *LI = cast<LoadInst>(I.getArgOperand(0));
5272 MachinePointerInfo MPInfo(LI->getPointerOperand());
5273 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5274 unsigned Flags = MachineMemOperand::MOLoad |
5275 MachineMemOperand::MOInvariant;
5276 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5277 PtrTy.getSizeInBits() / 8,
5278 DAG.getEVTAlignment(PtrTy));
5279 Node->setMemRefs(MemRefs, MemRefs + 1);
5281 // Copy the guard value to a virtual register so that it can be
5282 // retrieved in the epilogue.
5283 Src = SDValue(Node, 0);
5284 const TargetRegisterClass *RC =
5285 TLI->getRegClassFor(Src.getSimpleValueType());
5286 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5288 SPDescriptor.setGuardReg(Reg);
5289 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5291 Src = getValue(I.getArgOperand(0)); // The guard's value.
5294 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5296 int FI = FuncInfo.StaticAllocaMap[Slot];
5297 MFI->setStackProtectorIndex(FI);
5299 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5301 // Store the stack protector onto the stack.
5302 Res = DAG.getStore(Chain, sdl, Src, FIN,
5303 MachinePointerInfo::getFixedStack(FI),
5309 case Intrinsic::objectsize: {
5310 // If we don't know by now, we're never going to know.
5311 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5313 assert(CI && "Non-constant type in __builtin_object_size?");
5315 SDValue Arg = getValue(I.getCalledValue());
5316 EVT Ty = Arg.getValueType();
5319 Res = DAG.getConstant(-1ULL, Ty);
5321 Res = DAG.getConstant(0, Ty);
5326 case Intrinsic::annotation:
5327 case Intrinsic::ptr_annotation:
5328 // Drop the intrinsic, but forward the value
5329 setValue(&I, getValue(I.getOperand(0)));
5331 case Intrinsic::assume:
5332 case Intrinsic::var_annotation:
5333 // Discard annotate attributes and assumptions
5336 case Intrinsic::init_trampoline: {
5337 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5341 Ops[1] = getValue(I.getArgOperand(0));
5342 Ops[2] = getValue(I.getArgOperand(1));
5343 Ops[3] = getValue(I.getArgOperand(2));
5344 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5345 Ops[5] = DAG.getSrcValue(F);
5347 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5352 case Intrinsic::adjust_trampoline: {
5353 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5354 TLI->getPointerTy(),
5355 getValue(I.getArgOperand(0))));
5358 case Intrinsic::gcroot:
5360 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5361 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5363 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5364 GFI->addStackRoot(FI->getIndex(), TypeMap);
5367 case Intrinsic::gcread:
5368 case Intrinsic::gcwrite:
5369 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5370 case Intrinsic::flt_rounds:
5371 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5374 case Intrinsic::expect: {
5375 // Just replace __builtin_expect(exp, c) with EXP.
5376 setValue(&I, getValue(I.getArgOperand(0)));
5380 case Intrinsic::debugtrap:
5381 case Intrinsic::trap: {
5382 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5383 if (TrapFuncName.empty()) {
5384 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5385 ISD::TRAP : ISD::DEBUGTRAP;
5386 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5389 TargetLowering::ArgListTy Args;
5391 TargetLowering::CallLoweringInfo CLI(DAG);
5392 CLI.setDebugLoc(sdl).setChain(getRoot())
5393 .setCallee(CallingConv::C, I.getType(),
5394 DAG.getExternalSymbol(TrapFuncName.data(), TLI->getPointerTy()),
5395 std::move(Args), 0);
5397 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5398 DAG.setRoot(Result.second);
5402 case Intrinsic::uadd_with_overflow:
5403 case Intrinsic::sadd_with_overflow:
5404 case Intrinsic::usub_with_overflow:
5405 case Intrinsic::ssub_with_overflow:
5406 case Intrinsic::umul_with_overflow:
5407 case Intrinsic::smul_with_overflow: {
5409 switch (Intrinsic) {
5410 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5411 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5412 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5413 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5414 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5415 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5416 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5418 SDValue Op1 = getValue(I.getArgOperand(0));
5419 SDValue Op2 = getValue(I.getArgOperand(1));
5421 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5422 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5425 case Intrinsic::prefetch: {
5427 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5429 Ops[1] = getValue(I.getArgOperand(0));
5430 Ops[2] = getValue(I.getArgOperand(1));
5431 Ops[3] = getValue(I.getArgOperand(2));
5432 Ops[4] = getValue(I.getArgOperand(3));
5433 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5434 DAG.getVTList(MVT::Other), Ops,
5435 EVT::getIntegerVT(*Context, 8),
5436 MachinePointerInfo(I.getArgOperand(0)),
5438 false, /* volatile */
5440 rw==1)); /* write */
5443 case Intrinsic::lifetime_start:
5444 case Intrinsic::lifetime_end: {
5445 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5446 // Stack coloring is not enabled in O0, discard region information.
5447 if (TM.getOptLevel() == CodeGenOpt::None)
5450 SmallVector<Value *, 4> Allocas;
5451 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5453 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5454 E = Allocas.end(); Object != E; ++Object) {
5455 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5457 // Could not find an Alloca.
5458 if (!LifetimeObject)
5461 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5465 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5466 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5468 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5473 case Intrinsic::invariant_start:
5474 // Discard region information.
5475 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5477 case Intrinsic::invariant_end:
5478 // Discard region information.
5480 case Intrinsic::stackprotectorcheck: {
5481 // Do not actually emit anything for this basic block. Instead we initialize
5482 // the stack protector descriptor and export the guard variable so we can
5483 // access it in FinishBasicBlock.
5484 const BasicBlock *BB = I.getParent();
5485 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5486 ExportFromCurrentBlock(SPDescriptor.getGuard());
5488 // Flush our exports since we are going to process a terminator.
5489 (void)getControlRoot();
5492 case Intrinsic::clear_cache:
5493 return TLI->getClearCacheBuiltinName();
5494 case Intrinsic::donothing:
5497 case Intrinsic::experimental_stackmap: {
5501 case Intrinsic::experimental_patchpoint_void:
5502 case Intrinsic::experimental_patchpoint_i64: {
5509 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5511 MachineBasicBlock *LandingPad) {
5512 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5513 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5514 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5515 Type *RetTy = FTy->getReturnType();
5516 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5517 MCSymbol *BeginLabel = nullptr;
5519 TargetLowering::ArgListTy Args;
5520 TargetLowering::ArgListEntry Entry;
5521 Args.reserve(CS.arg_size());
5523 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5525 const Value *V = *i;
5528 if (V->getType()->isEmptyTy())
5531 SDValue ArgNode = getValue(V);
5532 Entry.Node = ArgNode; Entry.Ty = V->getType();
5534 // Skip the first return-type Attribute to get to params.
5535 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5536 Args.push_back(Entry);
5540 // Insert a label before the invoke call to mark the try range. This can be
5541 // used to detect deletion of the invoke via the MachineModuleInfo.
5542 BeginLabel = MMI.getContext().CreateTempSymbol();
5544 // For SjLj, keep track of which landing pads go with which invokes
5545 // so as to maintain the ordering of pads in the LSDA.
5546 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5547 if (CallSiteIndex) {
5548 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5549 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5551 // Now that the call site is handled, stop tracking it.
5552 MMI.setCurrentCallSite(0);
5555 // Both PendingLoads and PendingExports must be flushed here;
5556 // this call might not return.
5558 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5561 // Check if target-independent constraints permit a tail call here.
5562 // Target-dependent constraints are checked within TLI->LowerCallTo.
5563 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5566 TargetLowering::CallLoweringInfo CLI(DAG);
5567 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5568 .setCallee(RetTy, FTy, Callee, std::move(Args), CS).setTailCall(isTailCall);
5570 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5571 assert((isTailCall || Result.second.getNode()) &&
5572 "Non-null chain expected with non-tail call!");
5573 assert((Result.second.getNode() || !Result.first.getNode()) &&
5574 "Null value expected with tail call!");
5575 if (Result.first.getNode())
5576 setValue(CS.getInstruction(), Result.first);
5578 if (!Result.second.getNode()) {
5579 // As a special case, a null chain means that a tail call has been emitted
5580 // and the DAG root is already updated.
5583 // Since there's no actual continuation from this block, nothing can be
5584 // relying on us setting vregs for them.
5585 PendingExports.clear();
5587 DAG.setRoot(Result.second);
5591 // Insert a label at the end of the invoke call to mark the try range. This
5592 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5593 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5594 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5596 // Inform MachineModuleInfo of range.
5597 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5601 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5602 /// value is equal or not-equal to zero.
5603 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5604 for (const User *U : V->users()) {
5605 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5606 if (IC->isEquality())
5607 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5608 if (C->isNullValue())
5610 // Unknown instruction.
5616 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5618 SelectionDAGBuilder &Builder) {
5620 // Check to see if this load can be trivially constant folded, e.g. if the
5621 // input is from a string literal.
5622 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5623 // Cast pointer to the type we really want to load.
5624 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5625 PointerType::getUnqual(LoadTy));
5627 if (const Constant *LoadCst =
5628 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5630 return Builder.getValue(LoadCst);
5633 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5634 // still constant memory, the input chain can be the entry node.
5636 bool ConstantMemory = false;
5638 // Do not serialize (non-volatile) loads of constant memory with anything.
5639 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5640 Root = Builder.DAG.getEntryNode();
5641 ConstantMemory = true;
5643 // Do not serialize non-volatile loads against each other.
5644 Root = Builder.DAG.getRoot();
5647 SDValue Ptr = Builder.getValue(PtrVal);
5648 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5649 Ptr, MachinePointerInfo(PtrVal),
5651 false /*nontemporal*/,
5652 false /*isinvariant*/, 1 /* align=1 */);
5654 if (!ConstantMemory)
5655 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5659 /// processIntegerCallValue - Record the value for an instruction that
5660 /// produces an integer result, converting the type where necessary.
5661 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5664 EVT VT = TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType(),
5667 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5669 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5670 setValue(&I, Value);
5673 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5674 /// If so, return true and lower it, otherwise return false and it will be
5675 /// lowered like a normal call.
5676 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5677 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5678 if (I.getNumArgOperands() != 3)
5681 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5682 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5683 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5684 !I.getType()->isIntegerTy())
5687 const Value *Size = I.getArgOperand(2);
5688 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5689 if (CSize && CSize->getZExtValue() == 0) {
5690 EVT CallVT = TM.getSubtargetImpl()->getTargetLowering()->getValueType(
5692 setValue(&I, DAG.getConstant(0, CallVT));
5696 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5697 std::pair<SDValue, SDValue> Res =
5698 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5699 getValue(LHS), getValue(RHS), getValue(Size),
5700 MachinePointerInfo(LHS),
5701 MachinePointerInfo(RHS));
5702 if (Res.first.getNode()) {
5703 processIntegerCallValue(I, Res.first, true);
5704 PendingLoads.push_back(Res.second);
5708 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5709 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5710 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5711 bool ActuallyDoIt = true;
5714 switch (CSize->getZExtValue()) {
5716 LoadVT = MVT::Other;
5718 ActuallyDoIt = false;
5722 LoadTy = Type::getInt16Ty(CSize->getContext());
5726 LoadTy = Type::getInt32Ty(CSize->getContext());
5730 LoadTy = Type::getInt64Ty(CSize->getContext());
5734 LoadVT = MVT::v4i32;
5735 LoadTy = Type::getInt32Ty(CSize->getContext());
5736 LoadTy = VectorType::get(LoadTy, 4);
5741 // This turns into unaligned loads. We only do this if the target natively
5742 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5743 // we'll only produce a small number of byte loads.
5745 // Require that we can find a legal MVT, and only do this if the target
5746 // supports unaligned loads of that type. Expanding into byte loads would
5748 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5749 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5750 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5751 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5752 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5753 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5754 // TODO: Check alignment of src and dest ptrs.
5755 if (!TLI->isTypeLegal(LoadVT) ||
5756 !TLI->allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5757 !TLI->allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5758 ActuallyDoIt = false;
5762 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5763 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5765 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5767 processIntegerCallValue(I, Res, false);
5776 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5777 /// form. If so, return true and lower it, otherwise return false and it
5778 /// will be lowered like a normal call.
5779 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5780 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5781 if (I.getNumArgOperands() != 3)
5784 const Value *Src = I.getArgOperand(0);
5785 const Value *Char = I.getArgOperand(1);
5786 const Value *Length = I.getArgOperand(2);
5787 if (!Src->getType()->isPointerTy() ||
5788 !Char->getType()->isIntegerTy() ||
5789 !Length->getType()->isIntegerTy() ||
5790 !I.getType()->isPointerTy())
5793 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5794 std::pair<SDValue, SDValue> Res =
5795 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5796 getValue(Src), getValue(Char), getValue(Length),
5797 MachinePointerInfo(Src));
5798 if (Res.first.getNode()) {
5799 setValue(&I, Res.first);
5800 PendingLoads.push_back(Res.second);
5807 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5808 /// optimized form. If so, return true and lower it, otherwise return false
5809 /// and it will be lowered like a normal call.
5810 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5811 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5812 if (I.getNumArgOperands() != 2)
5815 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5816 if (!Arg0->getType()->isPointerTy() ||
5817 !Arg1->getType()->isPointerTy() ||
5818 !I.getType()->isPointerTy())
5821 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5822 std::pair<SDValue, SDValue> Res =
5823 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5824 getValue(Arg0), getValue(Arg1),
5825 MachinePointerInfo(Arg0),
5826 MachinePointerInfo(Arg1), isStpcpy);
5827 if (Res.first.getNode()) {
5828 setValue(&I, Res.first);
5829 DAG.setRoot(Res.second);
5836 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5837 /// If so, return true and lower it, otherwise return false and it will be
5838 /// lowered like a normal call.
5839 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5840 // Verify that the prototype makes sense. int strcmp(void*,void*)
5841 if (I.getNumArgOperands() != 2)
5844 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5845 if (!Arg0->getType()->isPointerTy() ||
5846 !Arg1->getType()->isPointerTy() ||
5847 !I.getType()->isIntegerTy())
5850 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5851 std::pair<SDValue, SDValue> Res =
5852 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5853 getValue(Arg0), getValue(Arg1),
5854 MachinePointerInfo(Arg0),
5855 MachinePointerInfo(Arg1));
5856 if (Res.first.getNode()) {
5857 processIntegerCallValue(I, Res.first, true);
5858 PendingLoads.push_back(Res.second);
5865 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5866 /// form. If so, return true and lower it, otherwise return false and it
5867 /// will be lowered like a normal call.
5868 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5869 // Verify that the prototype makes sense. size_t strlen(char *)
5870 if (I.getNumArgOperands() != 1)
5873 const Value *Arg0 = I.getArgOperand(0);
5874 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5877 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5878 std::pair<SDValue, SDValue> Res =
5879 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5880 getValue(Arg0), MachinePointerInfo(Arg0));
5881 if (Res.first.getNode()) {
5882 processIntegerCallValue(I, Res.first, false);
5883 PendingLoads.push_back(Res.second);
5890 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5891 /// form. If so, return true and lower it, otherwise return false and it
5892 /// will be lowered like a normal call.
5893 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5894 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5895 if (I.getNumArgOperands() != 2)
5898 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5899 if (!Arg0->getType()->isPointerTy() ||
5900 !Arg1->getType()->isIntegerTy() ||
5901 !I.getType()->isIntegerTy())
5904 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5905 std::pair<SDValue, SDValue> Res =
5906 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5907 getValue(Arg0), getValue(Arg1),
5908 MachinePointerInfo(Arg0));
5909 if (Res.first.getNode()) {
5910 processIntegerCallValue(I, Res.first, false);
5911 PendingLoads.push_back(Res.second);
5918 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5919 /// operation (as expected), translate it to an SDNode with the specified opcode
5920 /// and return true.
5921 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5923 // Sanity check that it really is a unary floating-point call.
5924 if (I.getNumArgOperands() != 1 ||
5925 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5926 I.getType() != I.getArgOperand(0)->getType() ||
5927 !I.onlyReadsMemory())
5930 SDValue Tmp = getValue(I.getArgOperand(0));
5931 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5935 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5936 // Handle inline assembly differently.
5937 if (isa<InlineAsm>(I.getCalledValue())) {
5942 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5943 ComputeUsesVAFloatArgument(I, &MMI);
5945 const char *RenameFn = nullptr;
5946 if (Function *F = I.getCalledFunction()) {
5947 if (F->isDeclaration()) {
5948 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5949 if (unsigned IID = II->getIntrinsicID(F)) {
5950 RenameFn = visitIntrinsicCall(I, IID);
5955 if (unsigned IID = F->getIntrinsicID()) {
5956 RenameFn = visitIntrinsicCall(I, IID);
5962 // Check for well-known libc/libm calls. If the function is internal, it
5963 // can't be a library call.
5965 if (!F->hasLocalLinkage() && F->hasName() &&
5966 LibInfo->getLibFunc(F->getName(), Func) &&
5967 LibInfo->hasOptimizedCodeGen(Func)) {
5970 case LibFunc::copysign:
5971 case LibFunc::copysignf:
5972 case LibFunc::copysignl:
5973 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5974 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5975 I.getType() == I.getArgOperand(0)->getType() &&
5976 I.getType() == I.getArgOperand(1)->getType() &&
5977 I.onlyReadsMemory()) {
5978 SDValue LHS = getValue(I.getArgOperand(0));
5979 SDValue RHS = getValue(I.getArgOperand(1));
5980 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5981 LHS.getValueType(), LHS, RHS));
5986 case LibFunc::fabsf:
5987 case LibFunc::fabsl:
5988 if (visitUnaryFloatCall(I, ISD::FABS))
5994 if (visitUnaryFloatCall(I, ISD::FSIN))
6000 if (visitUnaryFloatCall(I, ISD::FCOS))
6004 case LibFunc::sqrtf:
6005 case LibFunc::sqrtl:
6006 case LibFunc::sqrt_finite:
6007 case LibFunc::sqrtf_finite:
6008 case LibFunc::sqrtl_finite:
6009 if (visitUnaryFloatCall(I, ISD::FSQRT))
6012 case LibFunc::floor:
6013 case LibFunc::floorf:
6014 case LibFunc::floorl:
6015 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6018 case LibFunc::nearbyint:
6019 case LibFunc::nearbyintf:
6020 case LibFunc::nearbyintl:
6021 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6025 case LibFunc::ceilf:
6026 case LibFunc::ceill:
6027 if (visitUnaryFloatCall(I, ISD::FCEIL))
6031 case LibFunc::rintf:
6032 case LibFunc::rintl:
6033 if (visitUnaryFloatCall(I, ISD::FRINT))
6036 case LibFunc::round:
6037 case LibFunc::roundf:
6038 case LibFunc::roundl:
6039 if (visitUnaryFloatCall(I, ISD::FROUND))
6042 case LibFunc::trunc:
6043 case LibFunc::truncf:
6044 case LibFunc::truncl:
6045 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6049 case LibFunc::log2f:
6050 case LibFunc::log2l:
6051 if (visitUnaryFloatCall(I, ISD::FLOG2))
6055 case LibFunc::exp2f:
6056 case LibFunc::exp2l:
6057 if (visitUnaryFloatCall(I, ISD::FEXP2))
6060 case LibFunc::memcmp:
6061 if (visitMemCmpCall(I))
6064 case LibFunc::memchr:
6065 if (visitMemChrCall(I))
6068 case LibFunc::strcpy:
6069 if (visitStrCpyCall(I, false))
6072 case LibFunc::stpcpy:
6073 if (visitStrCpyCall(I, true))
6076 case LibFunc::strcmp:
6077 if (visitStrCmpCall(I))
6080 case LibFunc::strlen:
6081 if (visitStrLenCall(I))
6084 case LibFunc::strnlen:
6085 if (visitStrNLenCall(I))
6094 Callee = getValue(I.getCalledValue());
6096 Callee = DAG.getExternalSymbol(
6097 RenameFn, TM.getSubtargetImpl()->getTargetLowering()->getPointerTy());
6099 // Check if we can potentially perform a tail call. More detailed checking is
6100 // be done within LowerCallTo, after more information about the call is known.
6101 LowerCallTo(&I, Callee, I.isTailCall());
6106 /// AsmOperandInfo - This contains information for each constraint that we are
6108 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6110 /// CallOperand - If this is the result output operand or a clobber
6111 /// this is null, otherwise it is the incoming operand to the CallInst.
6112 /// This gets modified as the asm is processed.
6113 SDValue CallOperand;
6115 /// AssignedRegs - If this is a register or register class operand, this
6116 /// contains the set of register corresponding to the operand.
6117 RegsForValue AssignedRegs;
6119 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6120 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6123 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6124 /// corresponds to. If there is no Value* for this operand, it returns
6126 EVT getCallOperandValEVT(LLVMContext &Context,
6127 const TargetLowering &TLI,
6128 const DataLayout *DL) const {
6129 if (!CallOperandVal) return MVT::Other;
6131 if (isa<BasicBlock>(CallOperandVal))
6132 return TLI.getPointerTy();
6134 llvm::Type *OpTy = CallOperandVal->getType();
6136 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6137 // If this is an indirect operand, the operand is a pointer to the
6140 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6142 report_fatal_error("Indirect operand for inline asm not a pointer!");
6143 OpTy = PtrTy->getElementType();
6146 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6147 if (StructType *STy = dyn_cast<StructType>(OpTy))
6148 if (STy->getNumElements() == 1)
6149 OpTy = STy->getElementType(0);
6151 // If OpTy is not a single value, it may be a struct/union that we
6152 // can tile with integers.
6153 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6154 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6163 OpTy = IntegerType::get(Context, BitSize);
6168 return TLI.getValueType(OpTy, true);
6172 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6174 } // end anonymous namespace
6176 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6177 /// specified operand. We prefer to assign virtual registers, to allow the
6178 /// register allocator to handle the assignment process. However, if the asm
6179 /// uses features that we can't model on machineinstrs, we have SDISel do the
6180 /// allocation. This produces generally horrible, but correct, code.
6182 /// OpInfo describes the operand.
6184 static void GetRegistersForValue(SelectionDAG &DAG,
6185 const TargetLowering &TLI,
6187 SDISelAsmOperandInfo &OpInfo) {
6188 LLVMContext &Context = *DAG.getContext();
6190 MachineFunction &MF = DAG.getMachineFunction();
6191 SmallVector<unsigned, 4> Regs;
6193 // If this is a constraint for a single physreg, or a constraint for a
6194 // register class, find it.
6195 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6196 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6197 OpInfo.ConstraintVT);
6199 unsigned NumRegs = 1;
6200 if (OpInfo.ConstraintVT != MVT::Other) {
6201 // If this is a FP input in an integer register (or visa versa) insert a bit
6202 // cast of the input value. More generally, handle any case where the input
6203 // value disagrees with the register class we plan to stick this in.
6204 if (OpInfo.Type == InlineAsm::isInput &&
6205 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6206 // Try to convert to the first EVT that the reg class contains. If the
6207 // types are identical size, use a bitcast to convert (e.g. two differing
6209 MVT RegVT = *PhysReg.second->vt_begin();
6210 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6211 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6212 RegVT, OpInfo.CallOperand);
6213 OpInfo.ConstraintVT = RegVT;
6214 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6215 // If the input is a FP value and we want it in FP registers, do a
6216 // bitcast to the corresponding integer type. This turns an f64 value
6217 // into i64, which can be passed with two i32 values on a 32-bit
6219 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6220 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6221 RegVT, OpInfo.CallOperand);
6222 OpInfo.ConstraintVT = RegVT;
6226 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6230 EVT ValueVT = OpInfo.ConstraintVT;
6232 // If this is a constraint for a specific physical register, like {r17},
6234 if (unsigned AssignedReg = PhysReg.first) {
6235 const TargetRegisterClass *RC = PhysReg.second;
6236 if (OpInfo.ConstraintVT == MVT::Other)
6237 ValueVT = *RC->vt_begin();
6239 // Get the actual register value type. This is important, because the user
6240 // may have asked for (e.g.) the AX register in i32 type. We need to
6241 // remember that AX is actually i16 to get the right extension.
6242 RegVT = *RC->vt_begin();
6244 // This is a explicit reference to a physical register.
6245 Regs.push_back(AssignedReg);
6247 // If this is an expanded reference, add the rest of the regs to Regs.
6249 TargetRegisterClass::iterator I = RC->begin();
6250 for (; *I != AssignedReg; ++I)
6251 assert(I != RC->end() && "Didn't find reg!");
6253 // Already added the first reg.
6255 for (; NumRegs; --NumRegs, ++I) {
6256 assert(I != RC->end() && "Ran out of registers to allocate!");
6261 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6265 // Otherwise, if this was a reference to an LLVM register class, create vregs
6266 // for this reference.
6267 if (const TargetRegisterClass *RC = PhysReg.second) {
6268 RegVT = *RC->vt_begin();
6269 if (OpInfo.ConstraintVT == MVT::Other)
6272 // Create the appropriate number of virtual registers.
6273 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6274 for (; NumRegs; --NumRegs)
6275 Regs.push_back(RegInfo.createVirtualRegister(RC));
6277 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6281 // Otherwise, we couldn't allocate enough registers for this.
6284 /// visitInlineAsm - Handle a call to an InlineAsm object.
6286 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6287 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6289 /// ConstraintOperands - Information about all of the constraints.
6290 SDISelAsmOperandInfoVector ConstraintOperands;
6292 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6293 TargetLowering::AsmOperandInfoVector
6294 TargetConstraints = TLI->ParseConstraints(CS);
6296 bool hasMemory = false;
6298 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6299 unsigned ResNo = 0; // ResNo - The result number of the next output.
6300 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6301 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6302 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6304 MVT OpVT = MVT::Other;
6306 // Compute the value type for each operand.
6307 switch (OpInfo.Type) {
6308 case InlineAsm::isOutput:
6309 // Indirect outputs just consume an argument.
6310 if (OpInfo.isIndirect) {
6311 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6315 // The return value of the call is this value. As such, there is no
6316 // corresponding argument.
6317 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6318 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6319 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6321 assert(ResNo == 0 && "Asm only has one result!");
6322 OpVT = TLI->getSimpleValueType(CS.getType());
6326 case InlineAsm::isInput:
6327 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6329 case InlineAsm::isClobber:
6334 // If this is an input or an indirect output, process the call argument.
6335 // BasicBlocks are labels, currently appearing only in asm's.
6336 if (OpInfo.CallOperandVal) {
6337 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6338 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6340 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6343 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, DL).
6347 OpInfo.ConstraintVT = OpVT;
6349 // Indirect operand accesses access memory.
6350 if (OpInfo.isIndirect)
6353 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6354 TargetLowering::ConstraintType
6355 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6356 if (CType == TargetLowering::C_Memory) {
6364 SDValue Chain, Flag;
6366 // We won't need to flush pending loads if this asm doesn't touch
6367 // memory and is nonvolatile.
6368 if (hasMemory || IA->hasSideEffects())
6371 Chain = DAG.getRoot();
6373 // Second pass over the constraints: compute which constraint option to use
6374 // and assign registers to constraints that want a specific physreg.
6375 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6376 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6378 // If this is an output operand with a matching input operand, look up the
6379 // matching input. If their types mismatch, e.g. one is an integer, the
6380 // other is floating point, or their sizes are different, flag it as an
6382 if (OpInfo.hasMatchingInput()) {
6383 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6385 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6386 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6387 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6388 OpInfo.ConstraintVT);
6389 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6390 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6391 Input.ConstraintVT);
6392 if ((OpInfo.ConstraintVT.isInteger() !=
6393 Input.ConstraintVT.isInteger()) ||
6394 (MatchRC.second != InputRC.second)) {
6395 report_fatal_error("Unsupported asm: input constraint"
6396 " with a matching output constraint of"
6397 " incompatible type!");
6399 Input.ConstraintVT = OpInfo.ConstraintVT;
6403 // Compute the constraint code and ConstraintType to use.
6404 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6406 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6407 OpInfo.Type == InlineAsm::isClobber)
6410 // If this is a memory input, and if the operand is not indirect, do what we
6411 // need to to provide an address for the memory input.
6412 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6413 !OpInfo.isIndirect) {
6414 assert((OpInfo.isMultipleAlternative ||
6415 (OpInfo.Type == InlineAsm::isInput)) &&
6416 "Can only indirectify direct input operands!");
6418 // Memory operands really want the address of the value. If we don't have
6419 // an indirect input, put it in the constpool if we can, otherwise spill
6420 // it to a stack slot.
6421 // TODO: This isn't quite right. We need to handle these according to
6422 // the addressing mode that the constraint wants. Also, this may take
6423 // an additional register for the computation and we don't want that
6426 // If the operand is a float, integer, or vector constant, spill to a
6427 // constant pool entry to get its address.
6428 const Value *OpVal = OpInfo.CallOperandVal;
6429 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6430 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6431 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6432 TLI->getPointerTy());
6434 // Otherwise, create a stack slot and emit a store to it before the
6436 Type *Ty = OpVal->getType();
6437 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6438 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6439 MachineFunction &MF = DAG.getMachineFunction();
6440 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6441 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6442 Chain = DAG.getStore(Chain, getCurSDLoc(),
6443 OpInfo.CallOperand, StackSlot,
6444 MachinePointerInfo::getFixedStack(SSFI),
6446 OpInfo.CallOperand = StackSlot;
6449 // There is no longer a Value* corresponding to this operand.
6450 OpInfo.CallOperandVal = nullptr;
6452 // It is now an indirect operand.
6453 OpInfo.isIndirect = true;
6456 // If this constraint is for a specific register, allocate it before
6458 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6459 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6462 // Second pass - Loop over all of the operands, assigning virtual or physregs
6463 // to register class operands.
6464 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6465 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6467 // C_Register operands have already been allocated, Other/Memory don't need
6469 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6470 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6473 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6474 std::vector<SDValue> AsmNodeOperands;
6475 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6476 AsmNodeOperands.push_back(
6477 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6478 TLI->getPointerTy()));
6480 // If we have a !srcloc metadata node associated with it, we want to attach
6481 // this to the ultimately generated inline asm machineinstr. To do this, we
6482 // pass in the third operand as this (potentially null) inline asm MDNode.
6483 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6484 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6486 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6487 // bits as operand 3.
6488 unsigned ExtraInfo = 0;
6489 if (IA->hasSideEffects())
6490 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6491 if (IA->isAlignStack())
6492 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6493 // Set the asm dialect.
6494 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6496 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6497 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6498 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6500 // Compute the constraint code and ConstraintType to use.
6501 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6503 // Ideally, we would only check against memory constraints. However, the
6504 // meaning of an other constraint can be target-specific and we can't easily
6505 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6506 // for other constriants as well.
6507 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6508 OpInfo.ConstraintType == TargetLowering::C_Other) {
6509 if (OpInfo.Type == InlineAsm::isInput)
6510 ExtraInfo |= InlineAsm::Extra_MayLoad;
6511 else if (OpInfo.Type == InlineAsm::isOutput)
6512 ExtraInfo |= InlineAsm::Extra_MayStore;
6513 else if (OpInfo.Type == InlineAsm::isClobber)
6514 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6518 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6519 TLI->getPointerTy()));
6521 // Loop over all of the inputs, copying the operand values into the
6522 // appropriate registers and processing the output regs.
6523 RegsForValue RetValRegs;
6525 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6526 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6528 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6529 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6531 switch (OpInfo.Type) {
6532 case InlineAsm::isOutput: {
6533 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6534 OpInfo.ConstraintType != TargetLowering::C_Register) {
6535 // Memory output, or 'other' output (e.g. 'X' constraint).
6536 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6538 // Add information to the INLINEASM node to know about this output.
6539 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6540 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6541 TLI->getPointerTy()));
6542 AsmNodeOperands.push_back(OpInfo.CallOperand);
6546 // Otherwise, this is a register or register class output.
6548 // Copy the output from the appropriate register. Find a register that
6550 if (OpInfo.AssignedRegs.Regs.empty()) {
6551 LLVMContext &Ctx = *DAG.getContext();
6552 Ctx.emitError(CS.getInstruction(),
6553 "couldn't allocate output register for constraint '" +
6554 Twine(OpInfo.ConstraintCode) + "'");
6558 // If this is an indirect operand, store through the pointer after the
6560 if (OpInfo.isIndirect) {
6561 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6562 OpInfo.CallOperandVal));
6564 // This is the result value of the call.
6565 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6566 // Concatenate this output onto the outputs list.
6567 RetValRegs.append(OpInfo.AssignedRegs);
6570 // Add information to the INLINEASM node to know that this register is
6573 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6574 ? InlineAsm::Kind_RegDefEarlyClobber
6575 : InlineAsm::Kind_RegDef,
6576 false, 0, DAG, AsmNodeOperands);
6579 case InlineAsm::isInput: {
6580 SDValue InOperandVal = OpInfo.CallOperand;
6582 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6583 // If this is required to match an output register we have already set,
6584 // just use its register.
6585 unsigned OperandNo = OpInfo.getMatchedOperand();
6587 // Scan until we find the definition we already emitted of this operand.
6588 // When we find it, create a RegsForValue operand.
6589 unsigned CurOp = InlineAsm::Op_FirstOperand;
6590 for (; OperandNo; --OperandNo) {
6591 // Advance to the next operand.
6593 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6594 assert((InlineAsm::isRegDefKind(OpFlag) ||
6595 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6596 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6597 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6601 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6602 if (InlineAsm::isRegDefKind(OpFlag) ||
6603 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6604 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6605 if (OpInfo.isIndirect) {
6606 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6607 LLVMContext &Ctx = *DAG.getContext();
6608 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6609 " don't know how to handle tied "
6610 "indirect register inputs");
6614 RegsForValue MatchedRegs;
6615 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6616 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6617 MatchedRegs.RegVTs.push_back(RegVT);
6618 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6619 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6621 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6622 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6624 LLVMContext &Ctx = *DAG.getContext();
6625 Ctx.emitError(CS.getInstruction(),
6626 "inline asm error: This value"
6627 " type register class is not natively supported!");
6631 // Use the produced MatchedRegs object to
6632 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6633 Chain, &Flag, CS.getInstruction());
6634 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6635 true, OpInfo.getMatchedOperand(),
6636 DAG, AsmNodeOperands);
6640 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6641 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6642 "Unexpected number of operands");
6643 // Add information to the INLINEASM node to know about this input.
6644 // See InlineAsm.h isUseOperandTiedToDef.
6645 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6646 OpInfo.getMatchedOperand());
6647 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6648 TLI->getPointerTy()));
6649 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6653 // Treat indirect 'X' constraint as memory.
6654 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6656 OpInfo.ConstraintType = TargetLowering::C_Memory;
6658 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6659 std::vector<SDValue> Ops;
6660 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6663 LLVMContext &Ctx = *DAG.getContext();
6664 Ctx.emitError(CS.getInstruction(),
6665 "invalid operand for inline asm constraint '" +
6666 Twine(OpInfo.ConstraintCode) + "'");
6670 // Add information to the INLINEASM node to know about this input.
6671 unsigned ResOpType =
6672 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6673 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6674 TLI->getPointerTy()));
6675 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6679 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6680 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6681 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6682 "Memory operands expect pointer values");
6684 // Add information to the INLINEASM node to know about this input.
6685 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6686 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6687 TLI->getPointerTy()));
6688 AsmNodeOperands.push_back(InOperandVal);
6692 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6693 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6694 "Unknown constraint type!");
6696 // TODO: Support this.
6697 if (OpInfo.isIndirect) {
6698 LLVMContext &Ctx = *DAG.getContext();
6699 Ctx.emitError(CS.getInstruction(),
6700 "Don't know how to handle indirect register inputs yet "
6701 "for constraint '" +
6702 Twine(OpInfo.ConstraintCode) + "'");
6706 // Copy the input into the appropriate registers.
6707 if (OpInfo.AssignedRegs.Regs.empty()) {
6708 LLVMContext &Ctx = *DAG.getContext();
6709 Ctx.emitError(CS.getInstruction(),
6710 "couldn't allocate input reg for constraint '" +
6711 Twine(OpInfo.ConstraintCode) + "'");
6715 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6716 Chain, &Flag, CS.getInstruction());
6718 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6719 DAG, AsmNodeOperands);
6722 case InlineAsm::isClobber: {
6723 // Add the clobbered value to the operand list, so that the register
6724 // allocator is aware that the physreg got clobbered.
6725 if (!OpInfo.AssignedRegs.Regs.empty())
6726 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6734 // Finish up input operands. Set the input chain and add the flag last.
6735 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6736 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6738 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6739 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6740 Flag = Chain.getValue(1);
6742 // If this asm returns a register value, copy the result from that register
6743 // and set it as the value of the call.
6744 if (!RetValRegs.Regs.empty()) {
6745 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6746 Chain, &Flag, CS.getInstruction());
6748 // FIXME: Why don't we do this for inline asms with MRVs?
6749 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6750 EVT ResultType = TLI->getValueType(CS.getType());
6752 // If any of the results of the inline asm is a vector, it may have the
6753 // wrong width/num elts. This can happen for register classes that can
6754 // contain multiple different value types. The preg or vreg allocated may
6755 // not have the same VT as was expected. Convert it to the right type
6756 // with bit_convert.
6757 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6758 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6761 } else if (ResultType != Val.getValueType() &&
6762 ResultType.isInteger() && Val.getValueType().isInteger()) {
6763 // If a result value was tied to an input value, the computed result may
6764 // have a wider width than the expected result. Extract the relevant
6766 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6769 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6772 setValue(CS.getInstruction(), Val);
6773 // Don't need to use this as a chain in this case.
6774 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6778 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6780 // Process indirect outputs, first output all of the flagged copies out of
6782 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6783 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6784 const Value *Ptr = IndirectStoresToEmit[i].second;
6785 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6787 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6790 // Emit the non-flagged stores from the physregs.
6791 SmallVector<SDValue, 8> OutChains;
6792 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6793 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6794 StoresToEmit[i].first,
6795 getValue(StoresToEmit[i].second),
6796 MachinePointerInfo(StoresToEmit[i].second),
6798 OutChains.push_back(Val);
6801 if (!OutChains.empty())
6802 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6807 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6808 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6809 MVT::Other, getRoot(),
6810 getValue(I.getArgOperand(0)),
6811 DAG.getSrcValue(I.getArgOperand(0))));
6814 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6815 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6816 const DataLayout &DL = *TLI->getDataLayout();
6817 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6818 getRoot(), getValue(I.getOperand(0)),
6819 DAG.getSrcValue(I.getOperand(0)),
6820 DL.getABITypeAlignment(I.getType()));
6822 DAG.setRoot(V.getValue(1));
6825 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6826 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6827 MVT::Other, getRoot(),
6828 getValue(I.getArgOperand(0)),
6829 DAG.getSrcValue(I.getArgOperand(0))));
6832 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6833 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6834 MVT::Other, getRoot(),
6835 getValue(I.getArgOperand(0)),
6836 getValue(I.getArgOperand(1)),
6837 DAG.getSrcValue(I.getArgOperand(0)),
6838 DAG.getSrcValue(I.getArgOperand(1))));
6841 /// \brief Lower an argument list according to the target calling convention.
6843 /// \return A tuple of <return-value, token-chain>
6845 /// This is a helper for lowering intrinsics that follow a target calling
6846 /// convention or require stack pointer adjustment. Only a subset of the
6847 /// intrinsic's operands need to participate in the calling convention.
6848 std::pair<SDValue, SDValue>
6849 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6850 unsigned NumArgs, SDValue Callee,
6852 TargetLowering::ArgListTy Args;
6853 Args.reserve(NumArgs);
6855 // Populate the argument list.
6856 // Attributes for args start at offset 1, after the return attribute.
6857 ImmutableCallSite CS(&CI);
6858 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6859 ArgI != ArgE; ++ArgI) {
6860 const Value *V = CI.getOperand(ArgI);
6862 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6864 TargetLowering::ArgListEntry Entry;
6865 Entry.Node = getValue(V);
6866 Entry.Ty = V->getType();
6867 Entry.setAttributes(&CS, AttrI);
6868 Args.push_back(Entry);
6871 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6872 TargetLowering::CallLoweringInfo CLI(DAG);
6873 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6874 .setCallee(CI.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6875 .setDiscardResult(!CI.use_empty());
6877 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6878 return TLI->LowerCallTo(CLI);
6881 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6882 /// or patchpoint target node's operand list.
6884 /// Constants are converted to TargetConstants purely as an optimization to
6885 /// avoid constant materialization and register allocation.
6887 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6888 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6889 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6890 /// address materialization and register allocation, but may also be required
6891 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6892 /// alloca in the entry block, then the runtime may assume that the alloca's
6893 /// StackMap location can be read immediately after compilation and that the
6894 /// location is valid at any point during execution (this is similar to the
6895 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6896 /// only available in a register, then the runtime would need to trap when
6897 /// execution reaches the StackMap in order to read the alloca's location.
6898 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6899 SmallVectorImpl<SDValue> &Ops,
6900 SelectionDAGBuilder &Builder) {
6901 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6902 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6903 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6905 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6907 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6908 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6909 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6911 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6913 Ops.push_back(OpVal);
6917 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6918 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6919 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6920 // [live variables...])
6922 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6924 SDValue Chain, InFlag, Callee, NullPtr;
6925 SmallVector<SDValue, 32> Ops;
6927 SDLoc DL = getCurSDLoc();
6928 Callee = getValue(CI.getCalledValue());
6929 NullPtr = DAG.getIntPtrConstant(0, true);
6931 // The stackmap intrinsic only records the live variables (the arguemnts
6932 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6933 // intrinsic, this won't be lowered to a function call. This means we don't
6934 // have to worry about calling conventions and target specific lowering code.
6935 // Instead we perform the call lowering right here.
6937 // chain, flag = CALLSEQ_START(chain, 0)
6938 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6939 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6941 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6942 InFlag = Chain.getValue(1);
6944 // Add the <id> and <numBytes> constants.
6945 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6946 Ops.push_back(DAG.getTargetConstant(
6947 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6948 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6949 Ops.push_back(DAG.getTargetConstant(
6950 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6952 // Push live variables for the stack map.
6953 addStackMapLiveVars(CI, 2, Ops, *this);
6955 // We are not pushing any register mask info here on the operands list,
6956 // because the stackmap doesn't clobber anything.
6958 // Push the chain and the glue flag.
6959 Ops.push_back(Chain);
6960 Ops.push_back(InFlag);
6962 // Create the STACKMAP node.
6963 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6964 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6965 Chain = SDValue(SM, 0);
6966 InFlag = Chain.getValue(1);
6968 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6970 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6972 // Set the root to the target-lowered call chain.
6975 // Inform the Frame Information that we have a stackmap in this function.
6976 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6979 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6980 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6981 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6986 // [live variables...])
6988 CallingConv::ID CC = CI.getCallingConv();
6989 bool isAnyRegCC = CC == CallingConv::AnyReg;
6990 bool hasDef = !CI.getType()->isVoidTy();
6991 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6993 // Get the real number of arguments participating in the call <numArgs>
6994 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6995 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6997 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6998 // Intrinsics include all meta-operands up to but not including CC.
6999 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7000 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
7001 "Not enough arguments provided to the patchpoint intrinsic");
7003 // For AnyRegCC the arguments are lowered later on manually.
7004 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
7005 std::pair<SDValue, SDValue> Result =
7006 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
7008 // Set the root to the target-lowered call chain.
7009 SDValue Chain = Result.second;
7012 SDNode *CallEnd = Chain.getNode();
7013 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7014 CallEnd = CallEnd->getOperand(0).getNode();
7016 /// Get a call instruction from the call sequence chain.
7017 /// Tail calls are not allowed.
7018 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7019 "Expected a callseq node.");
7020 SDNode *Call = CallEnd->getOperand(0).getNode();
7021 bool hasGlue = Call->getGluedNode();
7023 // Replace the target specific call node with the patchable intrinsic.
7024 SmallVector<SDValue, 8> Ops;
7026 // Add the <id> and <numBytes> constants.
7027 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7028 Ops.push_back(DAG.getTargetConstant(
7029 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7030 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7031 Ops.push_back(DAG.getTargetConstant(
7032 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7034 // Assume that the Callee is a constant address.
7035 // FIXME: handle function symbols in the future.
7037 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7038 /*isTarget=*/true));
7040 // Adjust <numArgs> to account for any arguments that have been passed on the
7042 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7043 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7044 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7045 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7047 // Add the calling convention
7048 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7050 // Add the arguments we omitted previously. The register allocator should
7051 // place these in any free register.
7053 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7054 Ops.push_back(getValue(CI.getArgOperand(i)));
7056 // Push the arguments from the call instruction up to the register mask.
7057 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7058 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7061 // Push live variables for the stack map.
7062 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7064 // Push the register mask info.
7066 Ops.push_back(*(Call->op_end()-2));
7068 Ops.push_back(*(Call->op_end()-1));
7070 // Push the chain (this is originally the first operand of the call, but
7071 // becomes now the last or second to last operand).
7072 Ops.push_back(*(Call->op_begin()));
7074 // Push the glue flag (last operand).
7076 Ops.push_back(*(Call->op_end()-1));
7079 if (isAnyRegCC && hasDef) {
7080 // Create the return types based on the intrinsic definition
7081 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7082 SmallVector<EVT, 3> ValueVTs;
7083 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7084 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7086 // There is always a chain and a glue type at the end
7087 ValueVTs.push_back(MVT::Other);
7088 ValueVTs.push_back(MVT::Glue);
7089 NodeTys = DAG.getVTList(ValueVTs);
7091 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7093 // Replace the target specific call node with a PATCHPOINT node.
7094 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7095 getCurSDLoc(), NodeTys, Ops);
7097 // Update the NodeMap.
7100 setValue(&CI, SDValue(MN, 0));
7102 setValue(&CI, Result.first);
7105 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7106 // call sequence. Furthermore the location of the chain and glue can change
7107 // when the AnyReg calling convention is used and the intrinsic returns a
7109 if (isAnyRegCC && hasDef) {
7110 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7111 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7112 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7114 DAG.ReplaceAllUsesWith(Call, MN);
7115 DAG.DeleteNode(Call);
7117 // Inform the Frame Information that we have a patchpoint in this function.
7118 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7121 /// Returns an AttributeSet representing the attributes applied to the return
7122 /// value of the given call.
7123 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7124 SmallVector<Attribute::AttrKind, 2> Attrs;
7126 Attrs.push_back(Attribute::SExt);
7128 Attrs.push_back(Attribute::ZExt);
7130 Attrs.push_back(Attribute::InReg);
7132 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7136 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7137 /// implementation, which just calls LowerCall.
7138 /// FIXME: When all targets are
7139 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7140 std::pair<SDValue, SDValue>
7141 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7142 // Handle the incoming return values from the call.
7144 Type *OrigRetTy = CLI.RetTy;
7145 SmallVector<EVT, 4> RetTys;
7146 SmallVector<uint64_t, 4> Offsets;
7147 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7149 SmallVector<ISD::OutputArg, 4> Outs;
7150 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7152 bool CanLowerReturn =
7153 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7154 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7156 SDValue DemoteStackSlot;
7157 int DemoteStackIdx = -100;
7158 if (!CanLowerReturn) {
7159 // FIXME: equivalent assert?
7160 // assert(!CS.hasInAllocaArgument() &&
7161 // "sret demotion is incompatible with inalloca");
7162 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7163 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7164 MachineFunction &MF = CLI.DAG.getMachineFunction();
7165 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7166 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7168 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7170 Entry.Node = DemoteStackSlot;
7171 Entry.Ty = StackSlotPtrType;
7172 Entry.isSExt = false;
7173 Entry.isZExt = false;
7174 Entry.isInReg = false;
7175 Entry.isSRet = true;
7176 Entry.isNest = false;
7177 Entry.isByVal = false;
7178 Entry.isReturned = false;
7179 Entry.Alignment = Align;
7180 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7181 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7183 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7185 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7186 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7187 for (unsigned i = 0; i != NumRegs; ++i) {
7188 ISD::InputArg MyFlags;
7189 MyFlags.VT = RegisterVT;
7191 MyFlags.Used = CLI.IsReturnValueUsed;
7193 MyFlags.Flags.setSExt();
7195 MyFlags.Flags.setZExt();
7197 MyFlags.Flags.setInReg();
7198 CLI.Ins.push_back(MyFlags);
7203 // Handle all of the outgoing arguments.
7205 CLI.OutVals.clear();
7206 ArgListTy &Args = CLI.getArgs();
7207 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7208 SmallVector<EVT, 4> ValueVTs;
7209 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7210 Type *FinalType = Args[i].Ty;
7211 if (Args[i].isByVal)
7212 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7213 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7214 FinalType, CLI.CallConv, CLI.IsVarArg);
7215 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7217 EVT VT = ValueVTs[Value];
7218 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7219 SDValue Op = SDValue(Args[i].Node.getNode(),
7220 Args[i].Node.getResNo() + Value);
7221 ISD::ArgFlagsTy Flags;
7222 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7228 if (Args[i].isInReg)
7232 if (Args[i].isByVal)
7234 if (Args[i].isInAlloca) {
7235 Flags.setInAlloca();
7236 // Set the byval flag for CCAssignFn callbacks that don't know about
7237 // inalloca. This way we can know how many bytes we should've allocated
7238 // and how many bytes a callee cleanup function will pop. If we port
7239 // inalloca to more targets, we'll have to add custom inalloca handling
7240 // in the various CC lowering callbacks.
7243 if (Args[i].isByVal || Args[i].isInAlloca) {
7244 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7245 Type *ElementTy = Ty->getElementType();
7246 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7247 // For ByVal, alignment should come from FE. BE will guess if this
7248 // info is not there but there are cases it cannot get right.
7249 unsigned FrameAlign;
7250 if (Args[i].Alignment)
7251 FrameAlign = Args[i].Alignment;
7253 FrameAlign = getByValTypeAlignment(ElementTy);
7254 Flags.setByValAlign(FrameAlign);
7259 Flags.setInConsecutiveRegs();
7260 Flags.setOrigAlign(OriginalAlignment);
7262 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7263 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7264 SmallVector<SDValue, 4> Parts(NumParts);
7265 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7268 ExtendKind = ISD::SIGN_EXTEND;
7269 else if (Args[i].isZExt)
7270 ExtendKind = ISD::ZERO_EXTEND;
7272 // Conservatively only handle 'returned' on non-vectors for now
7273 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7274 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7275 "unexpected use of 'returned'");
7276 // Before passing 'returned' to the target lowering code, ensure that
7277 // either the register MVT and the actual EVT are the same size or that
7278 // the return value and argument are extended in the same way; in these
7279 // cases it's safe to pass the argument register value unchanged as the
7280 // return register value (although it's at the target's option whether
7282 // TODO: allow code generation to take advantage of partially preserved
7283 // registers rather than clobbering the entire register when the
7284 // parameter extension method is not compatible with the return
7286 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7287 (ExtendKind != ISD::ANY_EXTEND &&
7288 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7289 Flags.setReturned();
7292 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7293 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7295 for (unsigned j = 0; j != NumParts; ++j) {
7296 // if it isn't first piece, alignment must be 1
7297 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7298 i < CLI.NumFixedArgs,
7299 i, j*Parts[j].getValueType().getStoreSize());
7300 if (NumParts > 1 && j == 0)
7301 MyFlags.Flags.setSplit();
7303 MyFlags.Flags.setOrigAlign(1);
7305 // Only mark the end at the last register of the last value.
7306 if (NeedsRegBlock && Value == NumValues - 1 && j == NumParts - 1)
7307 MyFlags.Flags.setInConsecutiveRegsLast();
7309 CLI.Outs.push_back(MyFlags);
7310 CLI.OutVals.push_back(Parts[j]);
7315 SmallVector<SDValue, 4> InVals;
7316 CLI.Chain = LowerCall(CLI, InVals);
7318 // Verify that the target's LowerCall behaved as expected.
7319 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7320 "LowerCall didn't return a valid chain!");
7321 assert((!CLI.IsTailCall || InVals.empty()) &&
7322 "LowerCall emitted a return value for a tail call!");
7323 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7324 "LowerCall didn't emit the correct number of values!");
7326 // For a tail call, the return value is merely live-out and there aren't
7327 // any nodes in the DAG representing it. Return a special value to
7328 // indicate that a tail call has been emitted and no more Instructions
7329 // should be processed in the current block.
7330 if (CLI.IsTailCall) {
7331 CLI.DAG.setRoot(CLI.Chain);
7332 return std::make_pair(SDValue(), SDValue());
7335 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7336 assert(InVals[i].getNode() &&
7337 "LowerCall emitted a null value!");
7338 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7339 "LowerCall emitted a value with the wrong type!");
7342 SmallVector<SDValue, 4> ReturnValues;
7343 if (!CanLowerReturn) {
7344 // The instruction result is the result of loading from the
7345 // hidden sret parameter.
7346 SmallVector<EVT, 1> PVTs;
7347 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7349 ComputeValueVTs(*this, PtrRetTy, PVTs);
7350 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7351 EVT PtrVT = PVTs[0];
7353 unsigned NumValues = RetTys.size();
7354 ReturnValues.resize(NumValues);
7355 SmallVector<SDValue, 4> Chains(NumValues);
7357 for (unsigned i = 0; i < NumValues; ++i) {
7358 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7359 CLI.DAG.getConstant(Offsets[i], PtrVT));
7360 SDValue L = CLI.DAG.getLoad(
7361 RetTys[i], CLI.DL, CLI.Chain, Add,
7362 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7364 ReturnValues[i] = L;
7365 Chains[i] = L.getValue(1);
7368 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7370 // Collect the legal value parts into potentially illegal values
7371 // that correspond to the original function's return values.
7372 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7374 AssertOp = ISD::AssertSext;
7375 else if (CLI.RetZExt)
7376 AssertOp = ISD::AssertZext;
7377 unsigned CurReg = 0;
7378 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7380 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7381 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7383 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7384 NumRegs, RegisterVT, VT, nullptr,
7389 // For a function returning void, there is no return value. We can't create
7390 // such a node, so we just return a null return value in that case. In
7391 // that case, nothing will actually look at the value.
7392 if (ReturnValues.empty())
7393 return std::make_pair(SDValue(), CLI.Chain);
7396 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7397 CLI.DAG.getVTList(RetTys), ReturnValues);
7398 return std::make_pair(Res, CLI.Chain);
7401 void TargetLowering::LowerOperationWrapper(SDNode *N,
7402 SmallVectorImpl<SDValue> &Results,
7403 SelectionDAG &DAG) const {
7404 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7406 Results.push_back(Res);
7409 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7410 llvm_unreachable("LowerOperation not implemented for this target!");
7414 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7415 SDValue Op = getNonRegisterValue(V);
7416 assert((Op.getOpcode() != ISD::CopyFromReg ||
7417 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7418 "Copy from a reg to the same reg!");
7419 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7421 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
7422 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7423 SDValue Chain = DAG.getEntryNode();
7424 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V);
7425 PendingExports.push_back(Chain);
7428 #include "llvm/CodeGen/SelectionDAGISel.h"
7430 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7431 /// entry block, return true. This includes arguments used by switches, since
7432 /// the switch may expand into multiple basic blocks.
7433 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7434 // With FastISel active, we may be splitting blocks, so force creation
7435 // of virtual registers for all non-dead arguments.
7437 return A->use_empty();
7439 const BasicBlock *Entry = A->getParent()->begin();
7440 for (const User *U : A->users())
7441 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7442 return false; // Use not in entry block.
7447 void SelectionDAGISel::LowerArguments(const Function &F) {
7448 SelectionDAG &DAG = SDB->DAG;
7449 SDLoc dl = SDB->getCurSDLoc();
7450 const TargetLowering *TLI = getTargetLowering();
7451 const DataLayout *DL = TLI->getDataLayout();
7452 SmallVector<ISD::InputArg, 16> Ins;
7454 if (!FuncInfo->CanLowerReturn) {
7455 // Put in an sret pointer parameter before all the other parameters.
7456 SmallVector<EVT, 1> ValueVTs;
7457 ComputeValueVTs(*getTargetLowering(),
7458 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7460 // NOTE: Assuming that a pointer will never break down to more than one VT
7462 ISD::ArgFlagsTy Flags;
7464 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7465 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7466 Ins.push_back(RetArg);
7469 // Set up the incoming argument description vector.
7471 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7472 I != E; ++I, ++Idx) {
7473 SmallVector<EVT, 4> ValueVTs;
7474 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7475 bool isArgValueUsed = !I->use_empty();
7476 unsigned PartBase = 0;
7477 Type *FinalType = I->getType();
7478 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7479 FinalType = cast<PointerType>(FinalType)->getElementType();
7480 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7481 FinalType, F.getCallingConv(), F.isVarArg());
7482 for (unsigned Value = 0, NumValues = ValueVTs.size();
7483 Value != NumValues; ++Value) {
7484 EVT VT = ValueVTs[Value];
7485 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7486 ISD::ArgFlagsTy Flags;
7487 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7489 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7491 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7493 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7495 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7497 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7499 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7500 Flags.setInAlloca();
7501 // Set the byval flag for CCAssignFn callbacks that don't know about
7502 // inalloca. This way we can know how many bytes we should've allocated
7503 // and how many bytes a callee cleanup function will pop. If we port
7504 // inalloca to more targets, we'll have to add custom inalloca handling
7505 // in the various CC lowering callbacks.
7508 if (Flags.isByVal() || Flags.isInAlloca()) {
7509 PointerType *Ty = cast<PointerType>(I->getType());
7510 Type *ElementTy = Ty->getElementType();
7511 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7512 // For ByVal, alignment should be passed from FE. BE will guess if
7513 // this info is not there but there are cases it cannot get right.
7514 unsigned FrameAlign;
7515 if (F.getParamAlignment(Idx))
7516 FrameAlign = F.getParamAlignment(Idx);
7518 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7519 Flags.setByValAlign(FrameAlign);
7521 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7524 Flags.setInConsecutiveRegs();
7525 Flags.setOrigAlign(OriginalAlignment);
7527 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7528 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7529 for (unsigned i = 0; i != NumRegs; ++i) {
7530 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7531 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7532 if (NumRegs > 1 && i == 0)
7533 MyFlags.Flags.setSplit();
7534 // if it isn't first piece, alignment must be 1
7536 MyFlags.Flags.setOrigAlign(1);
7538 // Only mark the end at the last register of the last value.
7539 if (NeedsRegBlock && Value == NumValues - 1 && i == NumRegs - 1)
7540 MyFlags.Flags.setInConsecutiveRegsLast();
7542 Ins.push_back(MyFlags);
7544 PartBase += VT.getStoreSize();
7548 // Call the target to set up the argument values.
7549 SmallVector<SDValue, 8> InVals;
7550 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7554 // Verify that the target's LowerFormalArguments behaved as expected.
7555 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7556 "LowerFormalArguments didn't return a valid chain!");
7557 assert(InVals.size() == Ins.size() &&
7558 "LowerFormalArguments didn't emit the correct number of values!");
7560 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7561 assert(InVals[i].getNode() &&
7562 "LowerFormalArguments emitted a null value!");
7563 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7564 "LowerFormalArguments emitted a value with the wrong type!");
7568 // Update the DAG with the new chain value resulting from argument lowering.
7569 DAG.setRoot(NewRoot);
7571 // Set up the argument values.
7574 if (!FuncInfo->CanLowerReturn) {
7575 // Create a virtual register for the sret pointer, and put in a copy
7576 // from the sret argument into it.
7577 SmallVector<EVT, 1> ValueVTs;
7578 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7579 MVT VT = ValueVTs[0].getSimpleVT();
7580 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7581 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7582 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7583 RegVT, VT, nullptr, AssertOp);
7585 MachineFunction& MF = SDB->DAG.getMachineFunction();
7586 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7587 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7588 FuncInfo->DemoteRegister = SRetReg;
7589 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7591 DAG.setRoot(NewRoot);
7593 // i indexes lowered arguments. Bump it past the hidden sret argument.
7594 // Idx indexes LLVM arguments. Don't touch it.
7598 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7600 SmallVector<SDValue, 4> ArgValues;
7601 SmallVector<EVT, 4> ValueVTs;
7602 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7603 unsigned NumValues = ValueVTs.size();
7605 // If this argument is unused then remember its value. It is used to generate
7606 // debugging information.
7607 if (I->use_empty() && NumValues) {
7608 SDB->setUnusedArgValue(I, InVals[i]);
7610 // Also remember any frame index for use in FastISel.
7611 if (FrameIndexSDNode *FI =
7612 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7613 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7616 for (unsigned Val = 0; Val != NumValues; ++Val) {
7617 EVT VT = ValueVTs[Val];
7618 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7619 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7621 if (!I->use_empty()) {
7622 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7623 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7624 AssertOp = ISD::AssertSext;
7625 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7626 AssertOp = ISD::AssertZext;
7628 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7629 NumParts, PartVT, VT,
7630 nullptr, AssertOp));
7636 // We don't need to do anything else for unused arguments.
7637 if (ArgValues.empty())
7640 // Note down frame index.
7641 if (FrameIndexSDNode *FI =
7642 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7643 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7645 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7646 SDB->getCurSDLoc());
7648 SDB->setValue(I, Res);
7649 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7650 if (LoadSDNode *LNode =
7651 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7652 if (FrameIndexSDNode *FI =
7653 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7654 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7657 // If this argument is live outside of the entry block, insert a copy from
7658 // wherever we got it to the vreg that other BB's will reference it as.
7659 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7660 // If we can, though, try to skip creating an unnecessary vreg.
7661 // FIXME: This isn't very clean... it would be nice to make this more
7662 // general. It's also subtly incompatible with the hacks FastISel
7664 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7665 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7666 FuncInfo->ValueMap[I] = Reg;
7670 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7671 FuncInfo->InitializeRegForValue(I);
7672 SDB->CopyToExportRegsIfNeeded(I);
7676 assert(i == InVals.size() && "Argument register count mismatch!");
7678 // Finally, if the target has anything special to do, allow it to do so.
7679 // FIXME: this should insert code into the DAG!
7680 EmitFunctionEntryCode();
7683 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7684 /// ensure constants are generated when needed. Remember the virtual registers
7685 /// that need to be added to the Machine PHI nodes as input. We cannot just
7686 /// directly add them, because expansion might result in multiple MBB's for one
7687 /// BB. As such, the start of the BB might correspond to a different MBB than
7691 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7692 const TerminatorInst *TI = LLVMBB->getTerminator();
7694 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7696 // Check successor nodes' PHI nodes that expect a constant to be available
7698 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7699 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7700 if (!isa<PHINode>(SuccBB->begin())) continue;
7701 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7703 // If this terminator has multiple identical successors (common for
7704 // switches), only handle each succ once.
7705 if (!SuccsHandled.insert(SuccMBB)) continue;
7707 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7709 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7710 // nodes and Machine PHI nodes, but the incoming operands have not been
7712 for (BasicBlock::const_iterator I = SuccBB->begin();
7713 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7714 // Ignore dead phi's.
7715 if (PN->use_empty()) continue;
7718 if (PN->getType()->isEmptyTy())
7722 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7724 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7725 unsigned &RegOut = ConstantsOut[C];
7727 RegOut = FuncInfo.CreateRegs(C->getType());
7728 CopyValueToVirtualRegister(C, RegOut);
7732 DenseMap<const Value *, unsigned>::iterator I =
7733 FuncInfo.ValueMap.find(PHIOp);
7734 if (I != FuncInfo.ValueMap.end())
7737 assert(isa<AllocaInst>(PHIOp) &&
7738 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7739 "Didn't codegen value into a register!??");
7740 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7741 CopyValueToVirtualRegister(PHIOp, Reg);
7745 // Remember that this register needs to added to the machine PHI node as
7746 // the input for this MBB.
7747 SmallVector<EVT, 4> ValueVTs;
7748 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
7749 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7750 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7751 EVT VT = ValueVTs[vti];
7752 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7753 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7754 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7755 Reg += NumRegisters;
7760 ConstantsOut.clear();
7763 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7766 SelectionDAGBuilder::StackProtectorDescriptor::
7767 AddSuccessorMBB(const BasicBlock *BB,
7768 MachineBasicBlock *ParentMBB,
7769 MachineBasicBlock *SuccMBB) {
7770 // If SuccBB has not been created yet, create it.
7772 MachineFunction *MF = ParentMBB->getParent();
7773 MachineFunction::iterator BBI = ParentMBB;
7774 SuccMBB = MF->CreateMachineBasicBlock(BB);
7775 MF->insert(++BBI, SuccMBB);
7777 // Add it as a successor of ParentMBB.
7778 ParentMBB->addSuccessor(SuccMBB);