1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
82 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
83 cl::desc("Enable fast-math-flags for DAG nodes"));
85 // Limit the width of DAG chains. This is important in general to prevent
86 // DAG-based analysis from blowing up. For example, alias analysis and
87 // load clustering may not complete in reasonable time. It is difficult to
88 // recognize and avoid this situation within each individual analysis, and
89 // future analyses are likely to have the same behavior. Limiting DAG width is
90 // the safe approach and will be especially important with global DAGs.
92 // MaxParallelChains default is arbitrarily high to avoid affecting
93 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
94 // sequence over this should have been converted to llvm.memcpy by the
95 // frontend. It easy to induce this behavior with .ll code such as:
96 // %buffer = alloca [4096 x i8]
97 // %data = load [4096 x i8]* %argPtr
98 // store [4096 x i8] %data, [4096 x i8]* %buffer
99 static const unsigned MaxParallelChains = 64;
101 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts, unsigned NumParts,
103 MVT PartVT, EVT ValueVT, const Value *V);
105 /// getCopyFromParts - Create a value that contains the specified legal parts
106 /// combined into the value they represent. If the parts combine to a type
107 /// larger then ValueVT then AssertOp can be used to specify whether the extra
108 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
109 /// (ISD::AssertSext).
110 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
111 const SDValue *Parts,
112 unsigned NumParts, MVT PartVT, EVT ValueVT,
114 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
115 if (ValueVT.isVector())
116 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
119 assert(NumParts > 0 && "No parts to assemble!");
120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
121 SDValue Val = Parts[0];
124 // Assemble the value from multiple parts.
125 if (ValueVT.isInteger()) {
126 unsigned PartBits = PartVT.getSizeInBits();
127 unsigned ValueBits = ValueVT.getSizeInBits();
129 // Assemble the power of 2 part.
130 unsigned RoundParts = NumParts & (NumParts - 1) ?
131 1 << Log2_32(NumParts) : NumParts;
132 unsigned RoundBits = PartBits * RoundParts;
133 EVT RoundVT = RoundBits == ValueBits ?
134 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
137 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
139 if (RoundParts > 2) {
140 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
142 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
143 RoundParts / 2, PartVT, HalfVT, V);
145 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
146 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
149 if (DAG.getDataLayout().isBigEndian())
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
154 if (RoundParts < NumParts) {
155 // Assemble the trailing non-power-of-2 part.
156 unsigned OddParts = NumParts - RoundParts;
157 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
158 Hi = getCopyFromParts(DAG, DL,
159 Parts + RoundParts, OddParts, PartVT, OddVT, V);
161 // Combine the round and odd parts.
163 if (DAG.getDataLayout().isBigEndian())
165 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
166 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
168 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
169 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
170 TLI.getPointerTy(DAG.getDataLayout())));
171 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
172 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
174 } else if (PartVT.isFloatingPoint()) {
175 // FP split into multiple FP parts (for ppcf128)
176 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
179 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
180 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
181 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
183 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
185 // FP split into integer parts (soft fp)
186 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
187 !PartVT.isVector() && "Unexpected split");
188 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
189 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
193 // There is now one part, held in Val. Correct it to match ValueVT.
194 EVT PartEVT = Val.getValueType();
196 if (PartEVT == ValueVT)
199 if (PartEVT.isInteger() && ValueVT.isInteger()) {
200 if (ValueVT.bitsLT(PartEVT)) {
201 // For a truncate, see if we have any information to
202 // indicate whether the truncated bits will always be
203 // zero or sign-extension.
204 if (AssertOp != ISD::DELETED_NODE)
205 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
206 DAG.getValueType(ValueVT));
207 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
209 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
212 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
213 // FP_ROUND's are always exact here.
214 if (ValueVT.bitsLT(Val.getValueType()))
216 ISD::FP_ROUND, DL, ValueVT, Val,
217 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
219 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
223 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
225 llvm_unreachable("Unknown mismatch!");
228 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
229 const Twine &ErrMsg) {
230 const Instruction *I = dyn_cast_or_null<Instruction>(V);
232 return Ctx.emitError(ErrMsg);
234 const char *AsmError = ", possible invalid constraint for vector type";
235 if (const CallInst *CI = dyn_cast<CallInst>(I))
236 if (isa<InlineAsm>(CI->getCalledValue()))
237 return Ctx.emitError(I, ErrMsg + AsmError);
239 return Ctx.emitError(I, ErrMsg);
242 /// getCopyFromPartsVector - Create a value that contains the specified legal
243 /// parts combined into the value they represent. If the parts combine to a
244 /// type larger then ValueVT then AssertOp can be used to specify whether the
245 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
246 /// ValueVT (ISD::AssertSext).
247 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
248 const SDValue *Parts, unsigned NumParts,
249 MVT PartVT, EVT ValueVT, const Value *V) {
250 assert(ValueVT.isVector() && "Not a vector value");
251 assert(NumParts > 0 && "No parts to assemble!");
252 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
253 SDValue Val = Parts[0];
255 // Handle a multi-element vector.
259 unsigned NumIntermediates;
261 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
262 NumIntermediates, RegisterVT);
263 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
264 NumParts = NumRegs; // Silence a compiler warning.
265 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
266 assert(RegisterVT.getSizeInBits() ==
267 Parts[0].getSimpleValueType().getSizeInBits() &&
268 "Part type sizes don't match!");
270 // Assemble the parts into intermediate operands.
271 SmallVector<SDValue, 8> Ops(NumIntermediates);
272 if (NumIntermediates == NumParts) {
273 // If the register was not expanded, truncate or copy the value,
275 for (unsigned i = 0; i != NumParts; ++i)
276 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
277 PartVT, IntermediateVT, V);
278 } else if (NumParts > 0) {
279 // If the intermediate type was expanded, build the intermediate
280 // operands from the parts.
281 assert(NumParts % NumIntermediates == 0 &&
282 "Must expand into a divisible number of parts!");
283 unsigned Factor = NumParts / NumIntermediates;
284 for (unsigned i = 0; i != NumIntermediates; ++i)
285 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
286 PartVT, IntermediateVT, V);
289 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
290 // intermediate operands.
291 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
296 // There is now one part, held in Val. Correct it to match ValueVT.
297 EVT PartEVT = Val.getValueType();
299 if (PartEVT == ValueVT)
302 if (PartEVT.isVector()) {
303 // If the element type of the source/dest vectors are the same, but the
304 // parts vector has more elements than the value vector, then we have a
305 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
307 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
308 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
309 "Cannot narrow, it would be a lossy transformation");
311 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
312 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
315 // Vector/Vector bitcast.
316 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
317 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
319 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
320 "Cannot handle this kind of promotion");
321 // Promoted vector extract
322 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
326 // Trivial bitcast if the types are the same size and the destination
327 // vector type is legal.
328 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
329 TLI.isTypeLegal(ValueVT))
330 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
332 // Handle cases such as i8 -> <1 x i1>
333 if (ValueVT.getVectorNumElements() != 1) {
334 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
335 "non-trivial scalar-to-vector conversion");
336 return DAG.getUNDEF(ValueVT);
339 if (ValueVT.getVectorNumElements() == 1 &&
340 ValueVT.getVectorElementType() != PartEVT)
341 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
343 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
346 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
347 SDValue Val, SDValue *Parts, unsigned NumParts,
348 MVT PartVT, const Value *V);
350 /// getCopyToParts - Create a series of nodes that contain the specified value
351 /// split into legal parts. If the parts contain more bits than Val, then, for
352 /// integers, ExtendKind can be used to specify how to generate the extra bits.
353 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
354 SDValue Val, SDValue *Parts, unsigned NumParts,
355 MVT PartVT, const Value *V,
356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
357 EVT ValueVT = Val.getValueType();
359 // Handle the vector case separately.
360 if (ValueVT.isVector())
361 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
363 unsigned PartBits = PartVT.getSizeInBits();
364 unsigned OrigNumParts = NumParts;
365 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
366 "Copying to an illegal type!");
371 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
372 EVT PartEVT = PartVT;
373 if (PartEVT == ValueVT) {
374 assert(NumParts == 1 && "No-op copy with multiple parts!");
379 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
380 // If the parts cover more bits than the value has, promote the value.
381 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
382 assert(NumParts == 1 && "Do not know what to promote to!");
383 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
385 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
386 ValueVT.isInteger() &&
387 "Unknown mismatch!");
388 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
389 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
390 if (PartVT == MVT::x86mmx)
391 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
393 } else if (PartBits == ValueVT.getSizeInBits()) {
394 // Different types of the same size.
395 assert(NumParts == 1 && PartEVT != ValueVT);
396 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
397 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
398 // If the parts cover less bits than value has, truncate the value.
399 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
400 ValueVT.isInteger() &&
401 "Unknown mismatch!");
402 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
403 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
404 if (PartVT == MVT::x86mmx)
405 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
408 // The value may have changed - recompute ValueVT.
409 ValueVT = Val.getValueType();
410 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
411 "Failed to tile the value with PartVT!");
414 if (PartEVT != ValueVT)
415 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
416 "scalar-to-vector conversion failed");
422 // Expand the value into multiple parts.
423 if (NumParts & (NumParts - 1)) {
424 // The number of parts is not a power of 2. Split off and copy the tail.
425 assert(PartVT.isInteger() && ValueVT.isInteger() &&
426 "Do not know what to expand to!");
427 unsigned RoundParts = 1 << Log2_32(NumParts);
428 unsigned RoundBits = RoundParts * PartBits;
429 unsigned OddParts = NumParts - RoundParts;
430 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
431 DAG.getIntPtrConstant(RoundBits, DL));
432 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
434 if (DAG.getDataLayout().isBigEndian())
435 // The odd parts were reversed by getCopyToParts - unreverse them.
436 std::reverse(Parts + RoundParts, Parts + NumParts);
438 NumParts = RoundParts;
439 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
440 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
443 // The number of parts is a power of 2. Repeatedly bisect the value using
445 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
446 EVT::getIntegerVT(*DAG.getContext(),
447 ValueVT.getSizeInBits()),
450 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
451 for (unsigned i = 0; i < NumParts; i += StepSize) {
452 unsigned ThisBits = StepSize * PartBits / 2;
453 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
454 SDValue &Part0 = Parts[i];
455 SDValue &Part1 = Parts[i+StepSize/2];
457 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
458 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
459 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
460 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
462 if (ThisBits == PartBits && ThisVT != PartVT) {
463 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
464 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
469 if (DAG.getDataLayout().isBigEndian())
470 std::reverse(Parts, Parts + OrigNumParts);
474 /// getCopyToPartsVector - Create a series of nodes that contain the specified
475 /// value split into legal parts.
476 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
477 SDValue Val, SDValue *Parts, unsigned NumParts,
478 MVT PartVT, const Value *V) {
479 EVT ValueVT = Val.getValueType();
480 assert(ValueVT.isVector() && "Not a vector");
481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
484 EVT PartEVT = PartVT;
485 if (PartEVT == ValueVT) {
487 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
488 // Bitconvert vector->vector case.
489 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
490 } else if (PartVT.isVector() &&
491 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
492 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
493 EVT ElementVT = PartVT.getVectorElementType();
494 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
496 SmallVector<SDValue, 16> Ops;
497 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getNode(
499 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
500 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
502 for (unsigned i = ValueVT.getVectorNumElements(),
503 e = PartVT.getVectorNumElements(); i != e; ++i)
504 Ops.push_back(DAG.getUNDEF(ElementVT));
506 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
508 // FIXME: Use CONCAT for 2x -> 4x.
510 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
511 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
512 } else if (PartVT.isVector() &&
513 PartEVT.getVectorElementType().bitsGE(
514 ValueVT.getVectorElementType()) &&
515 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
517 // Promoted vector extract
518 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
520 // Vector -> scalar conversion.
521 assert(ValueVT.getVectorNumElements() == 1 &&
522 "Only trivial vector-to-scalar conversions should get here!");
524 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
525 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
527 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
552 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
553 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
554 TLI.getVectorIdxTy(DAG.getDataLayout())));
556 Ops[i] = DAG.getNode(
557 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
558 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
579 RegsForValue::RegsForValue() {}
581 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
585 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
586 const DataLayout &DL, unsigned Reg, Type *Ty) {
587 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
589 for (EVT ValueVT : ValueVTs) {
590 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
591 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
592 for (unsigned i = 0; i != NumRegs; ++i)
593 Regs.push_back(Reg + i);
594 RegVTs.push_back(RegisterVT);
599 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
600 /// this value and returns the result as a ValueVT value. This uses
601 /// Chain/Flag as the input and updates them for the output Chain/Flag.
602 /// If the Flag pointer is NULL, no flag is used.
603 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
604 FunctionLoweringInfo &FuncInfo,
606 SDValue &Chain, SDValue *Flag,
607 const Value *V) const {
608 // A Value with type {} or [0 x %t] needs no registers.
609 if (ValueVTs.empty())
612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
614 // Assemble the legal parts into the final values.
615 SmallVector<SDValue, 4> Values(ValueVTs.size());
616 SmallVector<SDValue, 8> Parts;
617 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
618 // Copy the legal parts from the registers.
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
621 MVT RegisterVT = RegVTs[Value];
623 Parts.resize(NumRegs);
624 for (unsigned i = 0; i != NumRegs; ++i) {
627 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
630 *Flag = P.getValue(2);
633 Chain = P.getValue(1);
636 // If the source register was virtual and if we know something about it,
637 // add an assert node.
638 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
639 !RegisterVT.isInteger() || RegisterVT.isVector())
642 const FunctionLoweringInfo::LiveOutInfo *LOI =
643 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
647 unsigned RegSize = RegisterVT.getSizeInBits();
648 unsigned NumSignBits = LOI->NumSignBits;
649 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
651 if (NumZeroBits == RegSize) {
652 // The current value is a zero.
653 // Explicitly express that as it would be easier for
654 // optimizations to kick in.
655 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
659 // FIXME: We capture more information than the dag can represent. For
660 // now, just use the tightest assertzext/assertsext possible.
662 EVT FromVT(MVT::Other);
663 if (NumSignBits == RegSize)
664 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
665 else if (NumZeroBits >= RegSize-1)
666 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
667 else if (NumSignBits > RegSize-8)
668 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
669 else if (NumZeroBits >= RegSize-8)
670 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
671 else if (NumSignBits > RegSize-16)
672 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
673 else if (NumZeroBits >= RegSize-16)
674 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
675 else if (NumSignBits > RegSize-32)
676 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
677 else if (NumZeroBits >= RegSize-32)
678 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
682 // Add an assertion node.
683 assert(FromVT != MVT::Other);
684 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
685 RegisterVT, P, DAG.getValueType(FromVT));
688 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
689 NumRegs, RegisterVT, ValueVT, V);
694 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
697 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
698 /// specified value into the registers specified by this object. This uses
699 /// Chain/Flag as the input and updates them for the output Chain/Flag.
700 /// If the Flag pointer is NULL, no flag is used.
701 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
702 SDValue &Chain, SDValue *Flag, const Value *V,
703 ISD::NodeType PreferredExtendType) const {
704 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
705 ISD::NodeType ExtendKind = PreferredExtendType;
707 // Get the list of the values's legal parts.
708 unsigned NumRegs = Regs.size();
709 SmallVector<SDValue, 8> Parts(NumRegs);
710 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
711 EVT ValueVT = ValueVTs[Value];
712 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
713 MVT RegisterVT = RegVTs[Value];
715 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
716 ExtendKind = ISD::ZERO_EXTEND;
718 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
719 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
723 // Copy the parts into the registers.
724 SmallVector<SDValue, 8> Chains(NumRegs);
725 for (unsigned i = 0; i != NumRegs; ++i) {
728 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
730 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
731 *Flag = Part.getValue(1);
734 Chains[i] = Part.getValue(0);
737 if (NumRegs == 1 || Flag)
738 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
739 // flagged to it. That is the CopyToReg nodes and the user are considered
740 // a single scheduling unit. If we create a TokenFactor and return it as
741 // chain, then the TokenFactor is both a predecessor (operand) of the
742 // user as well as a successor (the TF operands are flagged to the user).
743 // c1, f1 = CopyToReg
744 // c2, f2 = CopyToReg
745 // c3 = TokenFactor c1, c2
748 Chain = Chains[NumRegs-1];
750 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
753 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
754 /// operand list. This adds the code marker and includes the number of
755 /// values added into it.
756 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
757 unsigned MatchingIdx, SDLoc dl,
759 std::vector<SDValue> &Ops) const {
760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
762 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
764 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
765 else if (!Regs.empty() &&
766 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
767 // Put the register class of the virtual registers in the flag word. That
768 // way, later passes can recompute register class constraints for inline
769 // assembly as well as normal instructions.
770 // Don't do this for tied operands that can use the regclass information
772 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
773 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
774 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
777 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
780 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
781 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
782 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
783 MVT RegisterVT = RegVTs[Value];
784 for (unsigned i = 0; i != NumRegs; ++i) {
785 assert(Reg < Regs.size() && "Mismatch in # registers expected");
786 unsigned TheReg = Regs[Reg++];
787 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
789 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
790 // If we clobbered the stack pointer, MFI should know about it.
791 assert(DAG.getMachineFunction().getFrameInfo()->
792 hasOpaqueSPAdjustment());
798 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
799 const TargetLibraryInfo *li) {
803 DL = &DAG.getDataLayout();
804 Context = DAG.getContext();
805 LPadToCallSiteMap.clear();
808 /// clear - Clear out the current SelectionDAG and the associated
809 /// state and prepare this SelectionDAGBuilder object to be used
810 /// for a new block. This doesn't clear out information about
811 /// additional blocks that are needed to complete switch lowering
812 /// or PHI node updating; that information is cleared out as it is
814 void SelectionDAGBuilder::clear() {
816 UnusedArgNodeMap.clear();
817 PendingLoads.clear();
818 PendingExports.clear();
821 SDNodeOrder = LowestSDNodeOrder;
822 StatepointLowering.clear();
825 /// clearDanglingDebugInfo - Clear the dangling debug information
826 /// map. This function is separated from the clear so that debug
827 /// information that is dangling in a basic block can be properly
828 /// resolved in a different basic block. This allows the
829 /// SelectionDAG to resolve dangling debug information attached
831 void SelectionDAGBuilder::clearDanglingDebugInfo() {
832 DanglingDebugInfoMap.clear();
835 /// getRoot - Return the current virtual root of the Selection DAG,
836 /// flushing any PendingLoad items. This must be done before emitting
837 /// a store or any other node that may need to be ordered after any
838 /// prior load instructions.
840 SDValue SelectionDAGBuilder::getRoot() {
841 if (PendingLoads.empty())
842 return DAG.getRoot();
844 if (PendingLoads.size() == 1) {
845 SDValue Root = PendingLoads[0];
847 PendingLoads.clear();
851 // Otherwise, we have to make a token factor node.
852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
854 PendingLoads.clear();
859 /// getControlRoot - Similar to getRoot, but instead of flushing all the
860 /// PendingLoad items, flush all the PendingExports items. It is necessary
861 /// to do this before emitting a terminator instruction.
863 SDValue SelectionDAGBuilder::getControlRoot() {
864 SDValue Root = DAG.getRoot();
866 if (PendingExports.empty())
869 // Turn all of the CopyToReg chains into one factored node.
870 if (Root.getOpcode() != ISD::EntryToken) {
871 unsigned i = 0, e = PendingExports.size();
872 for (; i != e; ++i) {
873 assert(PendingExports[i].getNode()->getNumOperands() > 1);
874 if (PendingExports[i].getNode()->getOperand(0) == Root)
875 break; // Don't add the root if we already indirectly depend on it.
879 PendingExports.push_back(Root);
882 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
884 PendingExports.clear();
889 void SelectionDAGBuilder::visit(const Instruction &I) {
890 // Set up outgoing PHI node register values before emitting the terminator.
891 if (isa<TerminatorInst>(&I))
892 HandlePHINodesInSuccessorBlocks(I.getParent());
898 visit(I.getOpcode(), I);
900 if (!isa<TerminatorInst>(&I) && !HasTailCall)
901 CopyToExportRegsIfNeeded(&I);
906 void SelectionDAGBuilder::visitPHI(const PHINode &) {
907 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
910 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
911 // Note: this doesn't use InstVisitor, because it has to work with
912 // ConstantExpr's in addition to instructions.
914 default: llvm_unreachable("Unknown instruction type encountered!");
915 // Build the switch statement using the Instruction.def file.
916 #define HANDLE_INST(NUM, OPCODE, CLASS) \
917 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
918 #include "llvm/IR/Instruction.def"
922 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
923 // generate the debug data structures now that we've seen its definition.
924 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
926 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
928 const DbgValueInst *DI = DDI.getDI();
929 DebugLoc dl = DDI.getdl();
930 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
931 DILocalVariable *Variable = DI->getVariable();
932 DIExpression *Expr = DI->getExpression();
933 assert(Variable->isValidLocationForIntrinsic(dl) &&
934 "Expected inlined-at fields to agree");
935 uint64_t Offset = DI->getOffset();
936 // A dbg.value for an alloca is always indirect.
937 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
940 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
942 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
943 IsIndirect, Offset, dl, DbgSDNodeOrder);
944 DAG.AddDbgValue(SDV, Val.getNode(), false);
947 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
948 DanglingDebugInfoMap[V] = DanglingDebugInfo();
952 /// getCopyFromRegs - If there was virtual register allocated for the value V
953 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
954 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
955 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
958 if (It != FuncInfo.ValueMap.end()) {
959 unsigned InReg = It->second;
960 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
961 DAG.getDataLayout(), InReg, Ty);
962 SDValue Chain = DAG.getEntryNode();
963 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
964 resolveDanglingDebugInfo(V, Result);
970 /// getValue - Return an SDValue for the given Value.
971 SDValue SelectionDAGBuilder::getValue(const Value *V) {
972 // If we already have an SDValue for this value, use it. It's important
973 // to do this first, so that we don't create a CopyFromReg if we already
974 // have a regular SDValue.
975 SDValue &N = NodeMap[V];
976 if (N.getNode()) return N;
978 // If there's a virtual register allocated and initialized for this
980 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
981 if (copyFromReg.getNode()) {
985 // Otherwise create a new SDValue and remember it.
986 SDValue Val = getValueImpl(V);
988 resolveDanglingDebugInfo(V, Val);
992 // Return true if SDValue exists for the given Value
993 bool SelectionDAGBuilder::findValue(const Value *V) const {
994 return (NodeMap.find(V) != NodeMap.end()) ||
995 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
998 /// getNonRegisterValue - Return an SDValue for the given Value, but
999 /// don't look in FuncInfo.ValueMap for a virtual register.
1000 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1001 // If we already have an SDValue for this value, use it.
1002 SDValue &N = NodeMap[V];
1004 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1005 // Remove the debug location from the node as the node is about to be used
1006 // in a location which may differ from the original debug location. This
1007 // is relevant to Constant and ConstantFP nodes because they can appear
1008 // as constant expressions inside PHI nodes.
1009 N->setDebugLoc(DebugLoc());
1014 // Otherwise create a new SDValue and remember it.
1015 SDValue Val = getValueImpl(V);
1017 resolveDanglingDebugInfo(V, Val);
1021 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1022 /// Create an SDValue for the given value.
1023 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1024 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1026 if (const Constant *C = dyn_cast<Constant>(V)) {
1027 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1029 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1030 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1032 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1033 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1035 if (isa<ConstantPointerNull>(C)) {
1036 unsigned AS = V->getType()->getPointerAddressSpace();
1037 return DAG.getConstant(0, getCurSDLoc(),
1038 TLI.getPointerTy(DAG.getDataLayout(), AS));
1041 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1042 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1044 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1045 return DAG.getUNDEF(VT);
1047 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1048 visit(CE->getOpcode(), *CE);
1049 SDValue N1 = NodeMap[V];
1050 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1054 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1055 SmallVector<SDValue, 4> Constants;
1056 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1058 SDNode *Val = getValue(*OI).getNode();
1059 // If the operand is an empty aggregate, there are no values.
1061 // Add each leaf value from the operand to the Constants list
1062 // to form a flattened list of all the values.
1063 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1064 Constants.push_back(SDValue(Val, i));
1067 return DAG.getMergeValues(Constants, getCurSDLoc());
1070 if (const ConstantDataSequential *CDS =
1071 dyn_cast<ConstantDataSequential>(C)) {
1072 SmallVector<SDValue, 4> Ops;
1073 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1074 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1075 // Add each leaf value from the operand to the Constants list
1076 // to form a flattened list of all the values.
1077 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1078 Ops.push_back(SDValue(Val, i));
1081 if (isa<ArrayType>(CDS->getType()))
1082 return DAG.getMergeValues(Ops, getCurSDLoc());
1083 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1087 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1088 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1089 "Unknown struct or array constant!");
1091 SmallVector<EVT, 4> ValueVTs;
1092 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1093 unsigned NumElts = ValueVTs.size();
1095 return SDValue(); // empty struct
1096 SmallVector<SDValue, 4> Constants(NumElts);
1097 for (unsigned i = 0; i != NumElts; ++i) {
1098 EVT EltVT = ValueVTs[i];
1099 if (isa<UndefValue>(C))
1100 Constants[i] = DAG.getUNDEF(EltVT);
1101 else if (EltVT.isFloatingPoint())
1102 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1104 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1107 return DAG.getMergeValues(Constants, getCurSDLoc());
1110 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1111 return DAG.getBlockAddress(BA, VT);
1113 VectorType *VecTy = cast<VectorType>(V->getType());
1114 unsigned NumElements = VecTy->getNumElements();
1116 // Now that we know the number and type of the elements, get that number of
1117 // elements into the Ops array based on what kind of constant it is.
1118 SmallVector<SDValue, 16> Ops;
1119 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1120 for (unsigned i = 0; i != NumElements; ++i)
1121 Ops.push_back(getValue(CV->getOperand(i)));
1123 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1125 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1128 if (EltVT.isFloatingPoint())
1129 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1131 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1132 Ops.assign(NumElements, Op);
1135 // Create a BUILD_VECTOR node.
1136 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1139 // If this is a static alloca, generate it as the frameindex instead of
1141 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1142 DenseMap<const AllocaInst*, int>::iterator SI =
1143 FuncInfo.StaticAllocaMap.find(AI);
1144 if (SI != FuncInfo.StaticAllocaMap.end())
1145 return DAG.getFrameIndex(SI->second,
1146 TLI.getPointerTy(DAG.getDataLayout()));
1149 // If this is an instruction which fast-isel has deferred, select it now.
1150 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1151 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1152 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1154 SDValue Chain = DAG.getEntryNode();
1155 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1158 llvm_unreachable("Can't get register for value!");
1161 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1162 report_fatal_error("visitCleanupRet not yet implemented!");
1165 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1166 report_fatal_error("visitCatchEndPad not yet implemented!");
1169 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1170 report_fatal_error("visitCatchRet not yet implemented!");
1173 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1174 report_fatal_error("visitCatchPad not yet implemented!");
1177 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1178 report_fatal_error("visitTerminatePad not yet implemented!");
1181 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1182 report_fatal_error("visitCleanupPad not yet implemented!");
1185 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1187 auto &DL = DAG.getDataLayout();
1188 SDValue Chain = getControlRoot();
1189 SmallVector<ISD::OutputArg, 8> Outs;
1190 SmallVector<SDValue, 8> OutVals;
1192 if (!FuncInfo.CanLowerReturn) {
1193 unsigned DemoteReg = FuncInfo.DemoteRegister;
1194 const Function *F = I.getParent()->getParent();
1196 // Emit a store of the return value through the virtual register.
1197 // Leave Outs empty so that LowerReturn won't try to load return
1198 // registers the usual way.
1199 SmallVector<EVT, 1> PtrValueVTs;
1200 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1203 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1204 SDValue RetOp = getValue(I.getOperand(0));
1206 SmallVector<EVT, 4> ValueVTs;
1207 SmallVector<uint64_t, 4> Offsets;
1208 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1209 unsigned NumValues = ValueVTs.size();
1211 SmallVector<SDValue, 4> Chains(NumValues);
1212 for (unsigned i = 0; i != NumValues; ++i) {
1213 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1214 RetPtr.getValueType(), RetPtr,
1215 DAG.getIntPtrConstant(Offsets[i],
1218 DAG.getStore(Chain, getCurSDLoc(),
1219 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1220 // FIXME: better loc info would be nice.
1221 Add, MachinePointerInfo(), false, false, 0);
1224 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1225 MVT::Other, Chains);
1226 } else if (I.getNumOperands() != 0) {
1227 SmallVector<EVT, 4> ValueVTs;
1228 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1229 unsigned NumValues = ValueVTs.size();
1231 SDValue RetOp = getValue(I.getOperand(0));
1233 const Function *F = I.getParent()->getParent();
1235 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1236 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1238 ExtendKind = ISD::SIGN_EXTEND;
1239 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241 ExtendKind = ISD::ZERO_EXTEND;
1243 LLVMContext &Context = F->getContext();
1244 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1247 for (unsigned j = 0; j != NumValues; ++j) {
1248 EVT VT = ValueVTs[j];
1250 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1251 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1253 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1254 MVT PartVT = TLI.getRegisterType(Context, VT);
1255 SmallVector<SDValue, 4> Parts(NumParts);
1256 getCopyToParts(DAG, getCurSDLoc(),
1257 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1258 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1260 // 'inreg' on function refers to return value
1261 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1265 // Propagate extension type if any
1266 if (ExtendKind == ISD::SIGN_EXTEND)
1268 else if (ExtendKind == ISD::ZERO_EXTEND)
1271 for (unsigned i = 0; i < NumParts; ++i) {
1272 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1273 VT, /*isfixed=*/true, 0, 0));
1274 OutVals.push_back(Parts[i]);
1280 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1281 CallingConv::ID CallConv =
1282 DAG.getMachineFunction().getFunction()->getCallingConv();
1283 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1284 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1286 // Verify that the target's LowerReturn behaved as expected.
1287 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1288 "LowerReturn didn't return a valid chain!");
1290 // Update the DAG with the new chain value resulting from return lowering.
1294 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1295 /// created for it, emit nodes to copy the value into the virtual
1297 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1299 if (V->getType()->isEmptyTy())
1302 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1303 if (VMI != FuncInfo.ValueMap.end()) {
1304 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1305 CopyValueToVirtualRegister(V, VMI->second);
1309 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1310 /// the current basic block, add it to ValueMap now so that we'll get a
1312 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1313 // No need to export constants.
1314 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1316 // Already exported?
1317 if (FuncInfo.isExportedInst(V)) return;
1319 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1320 CopyValueToVirtualRegister(V, Reg);
1323 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1324 const BasicBlock *FromBB) {
1325 // The operands of the setcc have to be in this block. We don't know
1326 // how to export them from some other block.
1327 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1328 // Can export from current BB.
1329 if (VI->getParent() == FromBB)
1332 // Is already exported, noop.
1333 return FuncInfo.isExportedInst(V);
1336 // If this is an argument, we can export it if the BB is the entry block or
1337 // if it is already exported.
1338 if (isa<Argument>(V)) {
1339 if (FromBB == &FromBB->getParent()->getEntryBlock())
1342 // Otherwise, can only export this if it is already exported.
1343 return FuncInfo.isExportedInst(V);
1346 // Otherwise, constants can always be exported.
1350 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1351 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1352 const MachineBasicBlock *Dst) const {
1353 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1356 const BasicBlock *SrcBB = Src->getBasicBlock();
1357 const BasicBlock *DstBB = Dst->getBasicBlock();
1358 return BPI->getEdgeWeight(SrcBB, DstBB);
1361 void SelectionDAGBuilder::
1362 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1363 uint32_t Weight /* = 0 */) {
1365 Weight = getEdgeWeight(Src, Dst);
1366 Src->addSuccessor(Dst, Weight);
1370 static bool InBlock(const Value *V, const BasicBlock *BB) {
1371 if (const Instruction *I = dyn_cast<Instruction>(V))
1372 return I->getParent() == BB;
1376 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1377 /// This function emits a branch and is used at the leaves of an OR or an
1378 /// AND operator tree.
1381 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1382 MachineBasicBlock *TBB,
1383 MachineBasicBlock *FBB,
1384 MachineBasicBlock *CurBB,
1385 MachineBasicBlock *SwitchBB,
1388 const BasicBlock *BB = CurBB->getBasicBlock();
1390 // If the leaf of the tree is a comparison, merge the condition into
1392 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1393 // The operands of the cmp have to be in this block. We don't know
1394 // how to export them from some other block. If this is the first block
1395 // of the sequence, no exporting is needed.
1396 if (CurBB == SwitchBB ||
1397 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1398 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1399 ISD::CondCode Condition;
1400 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1401 Condition = getICmpCondCode(IC->getPredicate());
1403 const FCmpInst *FC = cast<FCmpInst>(Cond);
1404 Condition = getFCmpCondCode(FC->getPredicate());
1405 if (TM.Options.NoNaNsFPMath)
1406 Condition = getFCmpCodeWithoutNaN(Condition);
1409 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1410 TBB, FBB, CurBB, TWeight, FWeight);
1411 SwitchCases.push_back(CB);
1416 // Create a CaseBlock record representing this branch.
1417 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1418 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1419 SwitchCases.push_back(CB);
1422 /// Scale down both weights to fit into uint32_t.
1423 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1424 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1425 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1426 NewTrue = NewTrue / Scale;
1427 NewFalse = NewFalse / Scale;
1430 /// FindMergedConditions - If Cond is an expression like
1431 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1432 MachineBasicBlock *TBB,
1433 MachineBasicBlock *FBB,
1434 MachineBasicBlock *CurBB,
1435 MachineBasicBlock *SwitchBB,
1436 Instruction::BinaryOps Opc,
1439 // If this node is not part of the or/and tree, emit it as a branch.
1440 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1441 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1442 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1443 BOp->getParent() != CurBB->getBasicBlock() ||
1444 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1445 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1446 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1451 // Create TmpBB after CurBB.
1452 MachineFunction::iterator BBI = CurBB;
1453 MachineFunction &MF = DAG.getMachineFunction();
1454 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1455 CurBB->getParent()->insert(++BBI, TmpBB);
1457 if (Opc == Instruction::Or) {
1458 // Codegen X | Y as:
1467 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1468 // The requirement is that
1469 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1470 // = TrueProb for original BB.
1471 // Assuming the original weights are A and B, one choice is to set BB1's
1472 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1474 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1475 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1476 // TmpBB, but the math is more complicated.
1478 uint64_t NewTrueWeight = TWeight;
1479 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1480 ScaleWeights(NewTrueWeight, NewFalseWeight);
1481 // Emit the LHS condition.
1482 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1483 NewTrueWeight, NewFalseWeight);
1485 NewTrueWeight = TWeight;
1486 NewFalseWeight = 2 * (uint64_t)FWeight;
1487 ScaleWeights(NewTrueWeight, NewFalseWeight);
1488 // Emit the RHS condition into TmpBB.
1489 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1490 NewTrueWeight, NewFalseWeight);
1492 assert(Opc == Instruction::And && "Unknown merge op!");
1493 // Codegen X & Y as:
1501 // This requires creation of TmpBB after CurBB.
1503 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1504 // The requirement is that
1505 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1506 // = FalseProb for original BB.
1507 // Assuming the original weights are A and B, one choice is to set BB1's
1508 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1510 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1512 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1513 uint64_t NewFalseWeight = FWeight;
1514 ScaleWeights(NewTrueWeight, NewFalseWeight);
1515 // Emit the LHS condition.
1516 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1517 NewTrueWeight, NewFalseWeight);
1519 NewTrueWeight = 2 * (uint64_t)TWeight;
1520 NewFalseWeight = FWeight;
1521 ScaleWeights(NewTrueWeight, NewFalseWeight);
1522 // Emit the RHS condition into TmpBB.
1523 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1524 NewTrueWeight, NewFalseWeight);
1528 /// If the set of cases should be emitted as a series of branches, return true.
1529 /// If we should emit this as a bunch of and/or'd together conditions, return
1532 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1533 if (Cases.size() != 2) return true;
1535 // If this is two comparisons of the same values or'd or and'd together, they
1536 // will get folded into a single comparison, so don't emit two blocks.
1537 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1538 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1539 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1540 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1544 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1545 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1546 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1547 Cases[0].CC == Cases[1].CC &&
1548 isa<Constant>(Cases[0].CmpRHS) &&
1549 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1550 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1552 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1559 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1560 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1562 // Update machine-CFG edges.
1563 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1565 if (I.isUnconditional()) {
1566 // Update machine-CFG edges.
1567 BrMBB->addSuccessor(Succ0MBB);
1569 // If this is not a fall-through branch or optimizations are switched off,
1571 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1572 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1573 MVT::Other, getControlRoot(),
1574 DAG.getBasicBlock(Succ0MBB)));
1579 // If this condition is one of the special cases we handle, do special stuff
1581 const Value *CondVal = I.getCondition();
1582 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1584 // If this is a series of conditions that are or'd or and'd together, emit
1585 // this as a sequence of branches instead of setcc's with and/or operations.
1586 // As long as jumps are not expensive, this should improve performance.
1587 // For example, instead of something like:
1600 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1601 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1602 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1603 BOp->getOpcode() == Instruction::Or)) {
1604 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1605 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1606 getEdgeWeight(BrMBB, Succ1MBB));
1607 // If the compares in later blocks need to use values not currently
1608 // exported from this block, export them now. This block should always
1609 // be the first entry.
1610 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1612 // Allow some cases to be rejected.
1613 if (ShouldEmitAsBranches(SwitchCases)) {
1614 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1615 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1616 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1619 // Emit the branch for this block.
1620 visitSwitchCase(SwitchCases[0], BrMBB);
1621 SwitchCases.erase(SwitchCases.begin());
1625 // Okay, we decided not to do this, remove any inserted MBB's and clear
1627 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1628 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1630 SwitchCases.clear();
1634 // Create a CaseBlock record representing this branch.
1635 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1636 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1638 // Use visitSwitchCase to actually insert the fast branch sequence for this
1640 visitSwitchCase(CB, BrMBB);
1643 /// visitSwitchCase - Emits the necessary code to represent a single node in
1644 /// the binary search tree resulting from lowering a switch instruction.
1645 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1646 MachineBasicBlock *SwitchBB) {
1648 SDValue CondLHS = getValue(CB.CmpLHS);
1649 SDLoc dl = getCurSDLoc();
1651 // Build the setcc now.
1653 // Fold "(X == true)" to X and "(X == false)" to !X to
1654 // handle common cases produced by branch lowering.
1655 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1656 CB.CC == ISD::SETEQ)
1658 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1659 CB.CC == ISD::SETEQ) {
1660 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1661 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1663 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1665 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1667 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1668 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1670 SDValue CmpOp = getValue(CB.CmpMHS);
1671 EVT VT = CmpOp.getValueType();
1673 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1674 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1677 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1678 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1679 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1680 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1684 // Update successor info
1685 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1686 // TrueBB and FalseBB are always different unless the incoming IR is
1687 // degenerate. This only happens when running llc on weird IR.
1688 if (CB.TrueBB != CB.FalseBB)
1689 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1691 // If the lhs block is the next block, invert the condition so that we can
1692 // fall through to the lhs instead of the rhs block.
1693 if (CB.TrueBB == NextBlock(SwitchBB)) {
1694 std::swap(CB.TrueBB, CB.FalseBB);
1695 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1696 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1699 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1700 MVT::Other, getControlRoot(), Cond,
1701 DAG.getBasicBlock(CB.TrueBB));
1703 // Insert the false branch. Do this even if it's a fall through branch,
1704 // this makes it easier to do DAG optimizations which require inverting
1705 // the branch condition.
1706 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1707 DAG.getBasicBlock(CB.FalseBB));
1709 DAG.setRoot(BrCond);
1712 /// visitJumpTable - Emit JumpTable node in the current MBB
1713 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1714 // Emit the code for the jump table
1715 assert(JT.Reg != -1U && "Should lower JT Header first!");
1716 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1717 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1719 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1720 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1721 MVT::Other, Index.getValue(1),
1723 DAG.setRoot(BrJumpTable);
1726 /// visitJumpTableHeader - This function emits necessary code to produce index
1727 /// in the JumpTable from switch case.
1728 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1729 JumpTableHeader &JTH,
1730 MachineBasicBlock *SwitchBB) {
1731 SDLoc dl = getCurSDLoc();
1733 // Subtract the lowest switch case value from the value being switched on and
1734 // conditional branch to default mbb if the result is greater than the
1735 // difference between smallest and largest cases.
1736 SDValue SwitchOp = getValue(JTH.SValue);
1737 EVT VT = SwitchOp.getValueType();
1738 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1739 DAG.getConstant(JTH.First, dl, VT));
1741 // The SDNode we just created, which holds the value being switched on minus
1742 // the smallest case value, needs to be copied to a virtual register so it
1743 // can be used as an index into the jump table in a subsequent basic block.
1744 // This value may be smaller or larger than the target's pointer type, and
1745 // therefore require extension or truncating.
1746 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1747 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1749 unsigned JumpTableReg =
1750 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1751 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1752 JumpTableReg, SwitchOp);
1753 JT.Reg = JumpTableReg;
1755 // Emit the range check for the jump table, and branch to the default block
1756 // for the switch statement if the value being switched on exceeds the largest
1757 // case in the switch.
1758 SDValue CMP = DAG.getSetCC(
1759 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1760 Sub.getValueType()),
1761 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1763 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1764 MVT::Other, CopyTo, CMP,
1765 DAG.getBasicBlock(JT.Default));
1767 // Avoid emitting unnecessary branches to the next block.
1768 if (JT.MBB != NextBlock(SwitchBB))
1769 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1770 DAG.getBasicBlock(JT.MBB));
1772 DAG.setRoot(BrCond);
1775 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1776 /// tail spliced into a stack protector check success bb.
1778 /// For a high level explanation of how this fits into the stack protector
1779 /// generation see the comment on the declaration of class
1780 /// StackProtectorDescriptor.
1781 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1782 MachineBasicBlock *ParentBB) {
1784 // First create the loads to the guard/stack slot for the comparison.
1785 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1786 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1788 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1789 int FI = MFI->getStackProtectorIndex();
1791 const Value *IRGuard = SPD.getGuard();
1792 SDValue GuardPtr = getValue(IRGuard);
1793 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1795 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1798 SDLoc dl = getCurSDLoc();
1800 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1801 // guard value from the virtual register holding the value. Otherwise, emit a
1802 // volatile load to retrieve the stack guard value.
1803 unsigned GuardReg = SPD.getGuardReg();
1805 if (GuardReg && TLI.useLoadStackGuardNode())
1806 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1809 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1810 GuardPtr, MachinePointerInfo(IRGuard, 0),
1811 true, false, false, Align);
1813 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1815 MachinePointerInfo::getFixedStack(FI),
1816 true, false, false, Align);
1818 // Perform the comparison via a subtract/getsetcc.
1819 EVT VT = Guard.getValueType();
1820 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1822 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1824 Sub.getValueType()),
1825 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1827 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1828 // branch to failure MBB.
1829 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1830 MVT::Other, StackSlot.getOperand(0),
1831 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1832 // Otherwise branch to success MBB.
1833 SDValue Br = DAG.getNode(ISD::BR, dl,
1835 DAG.getBasicBlock(SPD.getSuccessMBB()));
1840 /// Codegen the failure basic block for a stack protector check.
1842 /// A failure stack protector machine basic block consists simply of a call to
1843 /// __stack_chk_fail().
1845 /// For a high level explanation of how this fits into the stack protector
1846 /// generation see the comment on the declaration of class
1847 /// StackProtectorDescriptor.
1849 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1850 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1852 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1853 nullptr, 0, false, getCurSDLoc(), false, false).second;
1857 /// visitBitTestHeader - This function emits necessary code to produce value
1858 /// suitable for "bit tests"
1859 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1860 MachineBasicBlock *SwitchBB) {
1861 SDLoc dl = getCurSDLoc();
1863 // Subtract the minimum value
1864 SDValue SwitchOp = getValue(B.SValue);
1865 EVT VT = SwitchOp.getValueType();
1866 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1867 DAG.getConstant(B.First, dl, VT));
1870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1871 SDValue RangeCmp = DAG.getSetCC(
1872 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1873 Sub.getValueType()),
1874 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1876 // Determine the type of the test operands.
1877 bool UsePtrType = false;
1878 if (!TLI.isTypeLegal(VT))
1881 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1882 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1883 // Switch table case range are encoded into series of masks.
1884 // Just use pointer type, it's guaranteed to fit.
1890 VT = TLI.getPointerTy(DAG.getDataLayout());
1891 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1894 B.RegVT = VT.getSimpleVT();
1895 B.Reg = FuncInfo.CreateReg(B.RegVT);
1896 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1898 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1900 addSuccessorWithWeight(SwitchBB, B.Default);
1901 addSuccessorWithWeight(SwitchBB, MBB);
1903 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1904 MVT::Other, CopyTo, RangeCmp,
1905 DAG.getBasicBlock(B.Default));
1907 // Avoid emitting unnecessary branches to the next block.
1908 if (MBB != NextBlock(SwitchBB))
1909 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1910 DAG.getBasicBlock(MBB));
1912 DAG.setRoot(BrRange);
1915 /// visitBitTestCase - this function produces one "bit test"
1916 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1917 MachineBasicBlock* NextMBB,
1918 uint32_t BranchWeightToNext,
1921 MachineBasicBlock *SwitchBB) {
1922 SDLoc dl = getCurSDLoc();
1924 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1926 unsigned PopCount = countPopulation(B.Mask);
1927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1928 if (PopCount == 1) {
1929 // Testing for a single bit; just compare the shift count with what it
1930 // would need to be to shift a 1 bit in that position.
1932 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1933 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1935 } else if (PopCount == BB.Range) {
1936 // There is only one zero bit in the range, test for it directly.
1938 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1939 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1942 // Make desired shift
1943 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1944 DAG.getConstant(1, dl, VT), ShiftOp);
1946 // Emit bit tests and jumps
1947 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1948 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1950 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1951 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1954 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1955 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1956 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1957 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1959 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1960 MVT::Other, getControlRoot(),
1961 Cmp, DAG.getBasicBlock(B.TargetBB));
1963 // Avoid emitting unnecessary branches to the next block.
1964 if (NextMBB != NextBlock(SwitchBB))
1965 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1966 DAG.getBasicBlock(NextMBB));
1971 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1972 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1974 // Retrieve successors.
1975 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1976 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1978 const Value *Callee(I.getCalledValue());
1979 const Function *Fn = dyn_cast<Function>(Callee);
1980 if (isa<InlineAsm>(Callee))
1982 else if (Fn && Fn->isIntrinsic()) {
1983 switch (Fn->getIntrinsicID()) {
1985 llvm_unreachable("Cannot invoke this intrinsic");
1986 case Intrinsic::donothing:
1987 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1989 case Intrinsic::experimental_patchpoint_void:
1990 case Intrinsic::experimental_patchpoint_i64:
1991 visitPatchpoint(&I, LandingPad);
1993 case Intrinsic::experimental_gc_statepoint:
1994 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1998 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2000 // If the value of the invoke is used outside of its defining block, make it
2001 // available as a virtual register.
2002 // We already took care of the exported value for the statepoint instruction
2003 // during call to the LowerStatepoint.
2004 if (!isStatepoint(I)) {
2005 CopyToExportRegsIfNeeded(&I);
2008 // Update successor info
2009 addSuccessorWithWeight(InvokeMBB, Return);
2010 addSuccessorWithWeight(InvokeMBB, LandingPad);
2012 // Drop into normal successor.
2013 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2014 MVT::Other, getControlRoot(),
2015 DAG.getBasicBlock(Return)));
2018 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2019 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2022 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2023 assert(FuncInfo.MBB->isLandingPad() &&
2024 "Call to landingpad not in landing pad!");
2026 MachineBasicBlock *MBB = FuncInfo.MBB;
2027 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2028 AddLandingPadInfo(LP, MMI, MBB);
2030 // If there aren't registers to copy the values into (e.g., during SjLj
2031 // exceptions), then don't bother to create these DAG nodes.
2032 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2033 if (TLI.getExceptionPointerRegister() == 0 &&
2034 TLI.getExceptionSelectorRegister() == 0)
2037 SmallVector<EVT, 2> ValueVTs;
2038 SDLoc dl = getCurSDLoc();
2039 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2040 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2042 // Get the two live-in registers as SDValues. The physregs have already been
2043 // copied into virtual registers.
2045 if (FuncInfo.ExceptionPointerVirtReg) {
2046 Ops[0] = DAG.getZExtOrTrunc(
2047 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2048 FuncInfo.ExceptionPointerVirtReg,
2049 TLI.getPointerTy(DAG.getDataLayout())),
2052 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2054 Ops[1] = DAG.getZExtOrTrunc(
2055 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2056 FuncInfo.ExceptionSelectorVirtReg,
2057 TLI.getPointerTy(DAG.getDataLayout())),
2061 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2062 DAG.getVTList(ValueVTs), Ops);
2066 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2068 for (const CaseCluster &CC : Clusters)
2069 assert(CC.Low == CC.High && "Input clusters must be single-case");
2072 std::sort(Clusters.begin(), Clusters.end(),
2073 [](const CaseCluster &a, const CaseCluster &b) {
2074 return a.Low->getValue().slt(b.Low->getValue());
2077 // Merge adjacent clusters with the same destination.
2078 const unsigned N = Clusters.size();
2079 unsigned DstIndex = 0;
2080 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2081 CaseCluster &CC = Clusters[SrcIndex];
2082 const ConstantInt *CaseVal = CC.Low;
2083 MachineBasicBlock *Succ = CC.MBB;
2085 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2086 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2087 // If this case has the same successor and is a neighbour, merge it into
2088 // the previous cluster.
2089 Clusters[DstIndex - 1].High = CaseVal;
2090 Clusters[DstIndex - 1].Weight += CC.Weight;
2091 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2093 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2094 sizeof(Clusters[SrcIndex]));
2097 Clusters.resize(DstIndex);
2100 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2101 MachineBasicBlock *Last) {
2103 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2104 if (JTCases[i].first.HeaderBB == First)
2105 JTCases[i].first.HeaderBB = Last;
2107 // Update BitTestCases.
2108 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2109 if (BitTestCases[i].Parent == First)
2110 BitTestCases[i].Parent = Last;
2113 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2114 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2116 // Update machine-CFG edges with unique successors.
2117 SmallSet<BasicBlock*, 32> Done;
2118 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2119 BasicBlock *BB = I.getSuccessor(i);
2120 bool Inserted = Done.insert(BB).second;
2124 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2125 addSuccessorWithWeight(IndirectBrMBB, Succ);
2128 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2129 MVT::Other, getControlRoot(),
2130 getValue(I.getAddress())));
2133 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2134 if (DAG.getTarget().Options.TrapUnreachable)
2135 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2138 void SelectionDAGBuilder::visitFSub(const User &I) {
2139 // -0.0 - X --> fneg
2140 Type *Ty = I.getType();
2141 if (isa<Constant>(I.getOperand(0)) &&
2142 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2143 SDValue Op2 = getValue(I.getOperand(1));
2144 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2145 Op2.getValueType(), Op2));
2149 visitBinary(I, ISD::FSUB);
2152 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2153 SDValue Op1 = getValue(I.getOperand(0));
2154 SDValue Op2 = getValue(I.getOperand(1));
2161 if (const OverflowingBinaryOperator *OFBinOp =
2162 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2163 nuw = OFBinOp->hasNoUnsignedWrap();
2164 nsw = OFBinOp->hasNoSignedWrap();
2166 if (const PossiblyExactOperator *ExactOp =
2167 dyn_cast<const PossiblyExactOperator>(&I))
2168 exact = ExactOp->isExact();
2169 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2170 FMF = FPOp->getFastMathFlags();
2173 Flags.setExact(exact);
2174 Flags.setNoSignedWrap(nsw);
2175 Flags.setNoUnsignedWrap(nuw);
2176 if (EnableFMFInDAG) {
2177 Flags.setAllowReciprocal(FMF.allowReciprocal());
2178 Flags.setNoInfs(FMF.noInfs());
2179 Flags.setNoNaNs(FMF.noNaNs());
2180 Flags.setNoSignedZeros(FMF.noSignedZeros());
2181 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2183 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2185 setValue(&I, BinNodeValue);
2188 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2189 SDValue Op1 = getValue(I.getOperand(0));
2190 SDValue Op2 = getValue(I.getOperand(1));
2192 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2193 Op2.getValueType(), DAG.getDataLayout());
2195 // Coerce the shift amount to the right type if we can.
2196 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2197 unsigned ShiftSize = ShiftTy.getSizeInBits();
2198 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2199 SDLoc DL = getCurSDLoc();
2201 // If the operand is smaller than the shift count type, promote it.
2202 if (ShiftSize > Op2Size)
2203 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2205 // If the operand is larger than the shift count type but the shift
2206 // count type has enough bits to represent any shift value, truncate
2207 // it now. This is a common case and it exposes the truncate to
2208 // optimization early.
2209 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2210 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2211 // Otherwise we'll need to temporarily settle for some other convenient
2212 // type. Type legalization will make adjustments once the shiftee is split.
2214 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2221 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2223 if (const OverflowingBinaryOperator *OFBinOp =
2224 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2225 nuw = OFBinOp->hasNoUnsignedWrap();
2226 nsw = OFBinOp->hasNoSignedWrap();
2228 if (const PossiblyExactOperator *ExactOp =
2229 dyn_cast<const PossiblyExactOperator>(&I))
2230 exact = ExactOp->isExact();
2233 Flags.setExact(exact);
2234 Flags.setNoSignedWrap(nsw);
2235 Flags.setNoUnsignedWrap(nuw);
2236 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2241 void SelectionDAGBuilder::visitSDiv(const User &I) {
2242 SDValue Op1 = getValue(I.getOperand(0));
2243 SDValue Op2 = getValue(I.getOperand(1));
2246 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2247 cast<PossiblyExactOperator>(&I)->isExact());
2248 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2252 void SelectionDAGBuilder::visitICmp(const User &I) {
2253 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2254 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2255 predicate = IC->getPredicate();
2256 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2257 predicate = ICmpInst::Predicate(IC->getPredicate());
2258 SDValue Op1 = getValue(I.getOperand(0));
2259 SDValue Op2 = getValue(I.getOperand(1));
2260 ISD::CondCode Opcode = getICmpCondCode(predicate);
2262 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2264 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2267 void SelectionDAGBuilder::visitFCmp(const User &I) {
2268 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2269 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2270 predicate = FC->getPredicate();
2271 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2272 predicate = FCmpInst::Predicate(FC->getPredicate());
2273 SDValue Op1 = getValue(I.getOperand(0));
2274 SDValue Op2 = getValue(I.getOperand(1));
2275 ISD::CondCode Condition = getFCmpCondCode(predicate);
2276 if (TM.Options.NoNaNsFPMath)
2277 Condition = getFCmpCodeWithoutNaN(Condition);
2278 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2280 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2283 void SelectionDAGBuilder::visitSelect(const User &I) {
2284 SmallVector<EVT, 4> ValueVTs;
2285 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2287 unsigned NumValues = ValueVTs.size();
2288 if (NumValues == 0) return;
2290 SmallVector<SDValue, 4> Values(NumValues);
2291 SDValue Cond = getValue(I.getOperand(0));
2292 SDValue LHSVal = getValue(I.getOperand(1));
2293 SDValue RHSVal = getValue(I.getOperand(2));
2294 auto BaseOps = {Cond};
2295 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2296 ISD::VSELECT : ISD::SELECT;
2298 // Min/max matching is only viable if all output VTs are the same.
2299 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2301 SelectPatternFlavor SPF = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2302 ISD::NodeType Opc = ISD::DELETED_NODE;
2304 case SPF_UMAX: Opc = ISD::UMAX; break;
2305 case SPF_UMIN: Opc = ISD::UMIN; break;
2306 case SPF_SMAX: Opc = ISD::SMAX; break;
2307 case SPF_SMIN: Opc = ISD::SMIN; break;
2311 EVT VT = ValueVTs[0];
2312 LLVMContext &Ctx = *DAG.getContext();
2313 auto &TLI = DAG.getTargetLoweringInfo();
2314 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2315 VT = TLI.getTypeToTransformTo(Ctx, VT);
2317 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2318 // If the underlying comparison instruction is used by any other instruction,
2319 // the consumed instructions won't be destroyed, so it is not profitable
2320 // to convert to a min/max.
2321 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2323 LHSVal = getValue(LHS);
2324 RHSVal = getValue(RHS);
2329 for (unsigned i = 0; i != NumValues; ++i) {
2330 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2331 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2332 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2333 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2334 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2338 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2339 DAG.getVTList(ValueVTs), Values));
2342 void SelectionDAGBuilder::visitTrunc(const User &I) {
2343 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2344 SDValue N = getValue(I.getOperand(0));
2345 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2347 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2350 void SelectionDAGBuilder::visitZExt(const User &I) {
2351 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2352 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2353 SDValue N = getValue(I.getOperand(0));
2354 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2356 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2359 void SelectionDAGBuilder::visitSExt(const User &I) {
2360 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2361 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2362 SDValue N = getValue(I.getOperand(0));
2363 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2365 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2368 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2369 // FPTrunc is never a no-op cast, no need to check
2370 SDValue N = getValue(I.getOperand(0));
2371 SDLoc dl = getCurSDLoc();
2372 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2373 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2374 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2375 DAG.getTargetConstant(
2376 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2379 void SelectionDAGBuilder::visitFPExt(const User &I) {
2380 // FPExt is never a no-op cast, no need to check
2381 SDValue N = getValue(I.getOperand(0));
2382 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2384 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2387 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2388 // FPToUI is never a no-op cast, no need to check
2389 SDValue N = getValue(I.getOperand(0));
2390 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2392 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2395 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2396 // FPToSI is never a no-op cast, no need to check
2397 SDValue N = getValue(I.getOperand(0));
2398 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2400 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2403 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2404 // UIToFP is never a no-op cast, no need to check
2405 SDValue N = getValue(I.getOperand(0));
2406 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2408 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2411 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2412 // SIToFP is never a no-op cast, no need to check
2413 SDValue N = getValue(I.getOperand(0));
2414 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2416 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2419 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2420 // What to do depends on the size of the integer and the size of the pointer.
2421 // We can either truncate, zero extend, or no-op, accordingly.
2422 SDValue N = getValue(I.getOperand(0));
2423 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2425 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2428 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2429 // What to do depends on the size of the integer and the size of the pointer.
2430 // We can either truncate, zero extend, or no-op, accordingly.
2431 SDValue N = getValue(I.getOperand(0));
2432 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2434 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2437 void SelectionDAGBuilder::visitBitCast(const User &I) {
2438 SDValue N = getValue(I.getOperand(0));
2439 SDLoc dl = getCurSDLoc();
2440 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2443 // BitCast assures us that source and destination are the same size so this is
2444 // either a BITCAST or a no-op.
2445 if (DestVT != N.getValueType())
2446 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2447 DestVT, N)); // convert types.
2448 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2449 // might fold any kind of constant expression to an integer constant and that
2450 // is not what we are looking for. Only regcognize a bitcast of a genuine
2451 // constant integer as an opaque constant.
2452 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2453 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2456 setValue(&I, N); // noop cast.
2459 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2460 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2461 const Value *SV = I.getOperand(0);
2462 SDValue N = getValue(SV);
2463 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2465 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2466 unsigned DestAS = I.getType()->getPointerAddressSpace();
2468 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2469 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2474 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2476 SDValue InVec = getValue(I.getOperand(0));
2477 SDValue InVal = getValue(I.getOperand(1));
2478 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2479 TLI.getVectorIdxTy(DAG.getDataLayout()));
2480 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2481 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2482 InVec, InVal, InIdx));
2485 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2487 SDValue InVec = getValue(I.getOperand(0));
2488 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2489 TLI.getVectorIdxTy(DAG.getDataLayout()));
2490 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2491 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2495 // Utility for visitShuffleVector - Return true if every element in Mask,
2496 // beginning from position Pos and ending in Pos+Size, falls within the
2497 // specified sequential range [L, L+Pos). or is undef.
2498 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2499 unsigned Pos, unsigned Size, int Low) {
2500 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2501 if (Mask[i] >= 0 && Mask[i] != Low)
2506 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2507 SDValue Src1 = getValue(I.getOperand(0));
2508 SDValue Src2 = getValue(I.getOperand(1));
2510 SmallVector<int, 8> Mask;
2511 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2512 unsigned MaskNumElts = Mask.size();
2514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2515 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2516 EVT SrcVT = Src1.getValueType();
2517 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2519 if (SrcNumElts == MaskNumElts) {
2520 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2525 // Normalize the shuffle vector since mask and vector length don't match.
2526 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2527 // Mask is longer than the source vectors and is a multiple of the source
2528 // vectors. We can use concatenate vector to make the mask and vectors
2530 if (SrcNumElts*2 == MaskNumElts) {
2531 // First check for Src1 in low and Src2 in high
2532 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2533 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2534 // The shuffle is concatenating two vectors together.
2535 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2539 // Then check for Src2 in low and Src1 in high
2540 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2541 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2542 // The shuffle is concatenating two vectors together.
2543 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2549 // Pad both vectors with undefs to make them the same length as the mask.
2550 unsigned NumConcat = MaskNumElts / SrcNumElts;
2551 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2552 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2553 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2555 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2556 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2560 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2561 getCurSDLoc(), VT, MOps1);
2562 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2563 getCurSDLoc(), VT, MOps2);
2565 // Readjust mask for new input vector length.
2566 SmallVector<int, 8> MappedOps;
2567 for (unsigned i = 0; i != MaskNumElts; ++i) {
2569 if (Idx >= (int)SrcNumElts)
2570 Idx -= SrcNumElts - MaskNumElts;
2571 MappedOps.push_back(Idx);
2574 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2579 if (SrcNumElts > MaskNumElts) {
2580 // Analyze the access pattern of the vector to see if we can extract
2581 // two subvectors and do the shuffle. The analysis is done by calculating
2582 // the range of elements the mask access on both vectors.
2583 int MinRange[2] = { static_cast<int>(SrcNumElts),
2584 static_cast<int>(SrcNumElts)};
2585 int MaxRange[2] = {-1, -1};
2587 for (unsigned i = 0; i != MaskNumElts; ++i) {
2593 if (Idx >= (int)SrcNumElts) {
2597 if (Idx > MaxRange[Input])
2598 MaxRange[Input] = Idx;
2599 if (Idx < MinRange[Input])
2600 MinRange[Input] = Idx;
2603 // Check if the access is smaller than the vector size and can we find
2604 // a reasonable extract index.
2605 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2607 int StartIdx[2]; // StartIdx to extract from
2608 for (unsigned Input = 0; Input < 2; ++Input) {
2609 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2610 RangeUse[Input] = 0; // Unused
2611 StartIdx[Input] = 0;
2615 // Find a good start index that is a multiple of the mask length. Then
2616 // see if the rest of the elements are in range.
2617 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2618 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2619 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2620 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2623 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2624 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2627 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2628 // Extract appropriate subvector and generate a vector shuffle
2629 for (unsigned Input = 0; Input < 2; ++Input) {
2630 SDValue &Src = Input == 0 ? Src1 : Src2;
2631 if (RangeUse[Input] == 0)
2632 Src = DAG.getUNDEF(VT);
2634 SDLoc dl = getCurSDLoc();
2636 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2637 DAG.getConstant(StartIdx[Input], dl,
2638 TLI.getVectorIdxTy(DAG.getDataLayout())));
2642 // Calculate new mask.
2643 SmallVector<int, 8> MappedOps;
2644 for (unsigned i = 0; i != MaskNumElts; ++i) {
2647 if (Idx < (int)SrcNumElts)
2650 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2652 MappedOps.push_back(Idx);
2655 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2661 // We can't use either concat vectors or extract subvectors so fall back to
2662 // replacing the shuffle with extract and build vector.
2663 // to insert and build vector.
2664 EVT EltVT = VT.getVectorElementType();
2665 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2666 SDLoc dl = getCurSDLoc();
2667 SmallVector<SDValue,8> Ops;
2668 for (unsigned i = 0; i != MaskNumElts; ++i) {
2673 Res = DAG.getUNDEF(EltVT);
2675 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2676 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2678 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2679 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2685 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2688 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2689 const Value *Op0 = I.getOperand(0);
2690 const Value *Op1 = I.getOperand(1);
2691 Type *AggTy = I.getType();
2692 Type *ValTy = Op1->getType();
2693 bool IntoUndef = isa<UndefValue>(Op0);
2694 bool FromUndef = isa<UndefValue>(Op1);
2696 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2698 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2699 SmallVector<EVT, 4> AggValueVTs;
2700 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2701 SmallVector<EVT, 4> ValValueVTs;
2702 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2704 unsigned NumAggValues = AggValueVTs.size();
2705 unsigned NumValValues = ValValueVTs.size();
2706 SmallVector<SDValue, 4> Values(NumAggValues);
2708 // Ignore an insertvalue that produces an empty object
2709 if (!NumAggValues) {
2710 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2714 SDValue Agg = getValue(Op0);
2716 // Copy the beginning value(s) from the original aggregate.
2717 for (; i != LinearIndex; ++i)
2718 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2719 SDValue(Agg.getNode(), Agg.getResNo() + i);
2720 // Copy values from the inserted value(s).
2722 SDValue Val = getValue(Op1);
2723 for (; i != LinearIndex + NumValValues; ++i)
2724 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2725 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2727 // Copy remaining value(s) from the original aggregate.
2728 for (; i != NumAggValues; ++i)
2729 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2730 SDValue(Agg.getNode(), Agg.getResNo() + i);
2732 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2733 DAG.getVTList(AggValueVTs), Values));
2736 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2737 const Value *Op0 = I.getOperand(0);
2738 Type *AggTy = Op0->getType();
2739 Type *ValTy = I.getType();
2740 bool OutOfUndef = isa<UndefValue>(Op0);
2742 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2744 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2745 SmallVector<EVT, 4> ValValueVTs;
2746 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2748 unsigned NumValValues = ValValueVTs.size();
2750 // Ignore a extractvalue that produces an empty object
2751 if (!NumValValues) {
2752 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2756 SmallVector<SDValue, 4> Values(NumValValues);
2758 SDValue Agg = getValue(Op0);
2759 // Copy out the selected value(s).
2760 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2761 Values[i - LinearIndex] =
2763 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2764 SDValue(Agg.getNode(), Agg.getResNo() + i);
2766 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2767 DAG.getVTList(ValValueVTs), Values));
2770 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2771 Value *Op0 = I.getOperand(0);
2772 // Note that the pointer operand may be a vector of pointers. Take the scalar
2773 // element which holds a pointer.
2774 Type *Ty = Op0->getType()->getScalarType();
2775 unsigned AS = Ty->getPointerAddressSpace();
2776 SDValue N = getValue(Op0);
2777 SDLoc dl = getCurSDLoc();
2779 // Normalize Vector GEP - all scalar operands should be converted to the
2781 unsigned VectorWidth = I.getType()->isVectorTy() ?
2782 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2784 if (VectorWidth && !N.getValueType().isVector()) {
2785 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2786 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2787 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2789 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2791 const Value *Idx = *OI;
2792 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2793 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2796 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2797 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2798 DAG.getConstant(Offset, dl, N.getValueType()));
2801 Ty = StTy->getElementType(Field);
2803 Ty = cast<SequentialType>(Ty)->getElementType();
2805 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2806 unsigned PtrSize = PtrTy.getSizeInBits();
2807 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2809 // If this is a scalar constant or a splat vector of constants,
2810 // handle it quickly.
2811 const auto *CI = dyn_cast<ConstantInt>(Idx);
2812 if (!CI && isa<ConstantDataVector>(Idx) &&
2813 cast<ConstantDataVector>(Idx)->getSplatValue())
2814 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2819 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2820 SDValue OffsVal = VectorWidth ?
2821 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2822 DAG.getConstant(Offs, dl, PtrTy);
2823 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2827 // N = N + Idx * ElementSize;
2828 SDValue IdxN = getValue(Idx);
2830 if (!IdxN.getValueType().isVector() && VectorWidth) {
2831 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2832 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2833 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2835 // If the index is smaller or larger than intptr_t, truncate or extend
2837 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2839 // If this is a multiply by a power of two, turn it into a shl
2840 // immediately. This is a very common case.
2841 if (ElementSize != 1) {
2842 if (ElementSize.isPowerOf2()) {
2843 unsigned Amt = ElementSize.logBase2();
2844 IdxN = DAG.getNode(ISD::SHL, dl,
2845 N.getValueType(), IdxN,
2846 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2848 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2849 IdxN = DAG.getNode(ISD::MUL, dl,
2850 N.getValueType(), IdxN, Scale);
2854 N = DAG.getNode(ISD::ADD, dl,
2855 N.getValueType(), N, IdxN);
2862 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2863 // If this is a fixed sized alloca in the entry block of the function,
2864 // allocate it statically on the stack.
2865 if (FuncInfo.StaticAllocaMap.count(&I))
2866 return; // getValue will auto-populate this.
2868 SDLoc dl = getCurSDLoc();
2869 Type *Ty = I.getAllocatedType();
2870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2871 auto &DL = DAG.getDataLayout();
2872 uint64_t TySize = DL.getTypeAllocSize(Ty);
2874 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2876 SDValue AllocSize = getValue(I.getArraySize());
2878 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2879 if (AllocSize.getValueType() != IntPtr)
2880 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2882 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2884 DAG.getConstant(TySize, dl, IntPtr));
2886 // Handle alignment. If the requested alignment is less than or equal to
2887 // the stack alignment, ignore it. If the size is greater than or equal to
2888 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2889 unsigned StackAlign =
2890 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2891 if (Align <= StackAlign)
2894 // Round the size of the allocation up to the stack alignment size
2895 // by add SA-1 to the size.
2896 AllocSize = DAG.getNode(ISD::ADD, dl,
2897 AllocSize.getValueType(), AllocSize,
2898 DAG.getIntPtrConstant(StackAlign - 1, dl));
2900 // Mask out the low bits for alignment purposes.
2901 AllocSize = DAG.getNode(ISD::AND, dl,
2902 AllocSize.getValueType(), AllocSize,
2903 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2906 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2907 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2908 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2910 DAG.setRoot(DSA.getValue(1));
2912 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2915 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2917 return visitAtomicLoad(I);
2919 const Value *SV = I.getOperand(0);
2920 SDValue Ptr = getValue(SV);
2922 Type *Ty = I.getType();
2924 bool isVolatile = I.isVolatile();
2925 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2927 // The IR notion of invariant_load only guarantees that all *non-faulting*
2928 // invariant loads result in the same value. The MI notion of invariant load
2929 // guarantees that the load can be legally moved to any location within its
2930 // containing function. The MI notion of invariant_load is stronger than the
2931 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2932 // with a guarantee that the location being loaded from is dereferenceable
2933 // throughout the function's lifetime.
2935 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2936 isDereferenceablePointer(SV, DAG.getDataLayout());
2937 unsigned Alignment = I.getAlignment();
2940 I.getAAMetadata(AAInfo);
2941 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2943 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2944 SmallVector<EVT, 4> ValueVTs;
2945 SmallVector<uint64_t, 4> Offsets;
2946 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
2947 unsigned NumValues = ValueVTs.size();
2952 bool ConstantMemory = false;
2953 if (isVolatile || NumValues > MaxParallelChains)
2954 // Serialize volatile loads with other side effects.
2956 else if (AA->pointsToConstantMemory(
2957 MemoryLocation(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2958 // Do not serialize (non-volatile) loads of constant memory with anything.
2959 Root = DAG.getEntryNode();
2960 ConstantMemory = true;
2962 // Do not serialize non-volatile loads against each other.
2963 Root = DAG.getRoot();
2966 SDLoc dl = getCurSDLoc();
2969 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2971 SmallVector<SDValue, 4> Values(NumValues);
2972 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
2973 EVT PtrVT = Ptr.getValueType();
2974 unsigned ChainI = 0;
2975 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2976 // Serializing loads here may result in excessive register pressure, and
2977 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2978 // could recover a bit by hoisting nodes upward in the chain by recognizing
2979 // they are side-effect free or do not alias. The optimizer should really
2980 // avoid this case by converting large object/array copies to llvm.memcpy
2981 // (MaxParallelChains should always remain as failsafe).
2982 if (ChainI == MaxParallelChains) {
2983 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2984 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2985 makeArrayRef(Chains.data(), ChainI));
2989 SDValue A = DAG.getNode(ISD::ADD, dl,
2991 DAG.getConstant(Offsets[i], dl, PtrVT));
2992 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2993 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2994 isNonTemporal, isInvariant, Alignment, AAInfo,
2998 Chains[ChainI] = L.getValue(1);
3001 if (!ConstantMemory) {
3002 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3003 makeArrayRef(Chains.data(), ChainI));
3007 PendingLoads.push_back(Chain);
3010 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3011 DAG.getVTList(ValueVTs), Values));
3014 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3016 return visitAtomicStore(I);
3018 const Value *SrcV = I.getOperand(0);
3019 const Value *PtrV = I.getOperand(1);
3021 SmallVector<EVT, 4> ValueVTs;
3022 SmallVector<uint64_t, 4> Offsets;
3023 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3024 SrcV->getType(), ValueVTs, &Offsets);
3025 unsigned NumValues = ValueVTs.size();
3029 // Get the lowered operands. Note that we do this after
3030 // checking if NumResults is zero, because with zero results
3031 // the operands won't have values in the map.
3032 SDValue Src = getValue(SrcV);
3033 SDValue Ptr = getValue(PtrV);
3035 SDValue Root = getRoot();
3036 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3037 EVT PtrVT = Ptr.getValueType();
3038 bool isVolatile = I.isVolatile();
3039 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3040 unsigned Alignment = I.getAlignment();
3041 SDLoc dl = getCurSDLoc();
3044 I.getAAMetadata(AAInfo);
3046 unsigned ChainI = 0;
3047 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3048 // See visitLoad comments.
3049 if (ChainI == MaxParallelChains) {
3050 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3051 makeArrayRef(Chains.data(), ChainI));
3055 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3056 DAG.getConstant(Offsets[i], dl, PtrVT));
3057 SDValue St = DAG.getStore(Root, dl,
3058 SDValue(Src.getNode(), Src.getResNo() + i),
3059 Add, MachinePointerInfo(PtrV, Offsets[i]),
3060 isVolatile, isNonTemporal, Alignment, AAInfo);
3061 Chains[ChainI] = St;
3064 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3065 makeArrayRef(Chains.data(), ChainI));
3066 DAG.setRoot(StoreNode);
3069 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3070 SDLoc sdl = getCurSDLoc();
3072 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3073 Value *PtrOperand = I.getArgOperand(1);
3074 SDValue Ptr = getValue(PtrOperand);
3075 SDValue Src0 = getValue(I.getArgOperand(0));
3076 SDValue Mask = getValue(I.getArgOperand(3));
3077 EVT VT = Src0.getValueType();
3078 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3080 Alignment = DAG.getEVTAlignment(VT);
3083 I.getAAMetadata(AAInfo);
3085 MachineMemOperand *MMO =
3086 DAG.getMachineFunction().
3087 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3088 MachineMemOperand::MOStore, VT.getStoreSize(),
3090 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3092 DAG.setRoot(StoreNode);
3093 setValue(&I, StoreNode);
3096 // Gather/scatter receive a vector of pointers.
3097 // This vector of pointers may be represented as a base pointer + vector of
3098 // indices, it depends on GEP and instruction preceeding GEP
3099 // that calculates indices
3100 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3101 SelectionDAGBuilder* SDB) {
3103 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3104 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3105 if (!Gep || Gep->getNumOperands() > 2)
3107 ShuffleVectorInst *ShuffleInst =
3108 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3109 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3110 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3111 Instruction::InsertElement)
3114 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3116 SelectionDAG& DAG = SDB->DAG;
3117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3118 // Check is the Ptr is inside current basic block
3119 // If not, look for the shuffle instruction
3120 if (SDB->findValue(Ptr))
3121 Base = SDB->getValue(Ptr);
3122 else if (SDB->findValue(ShuffleInst)) {
3123 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3124 SDLoc sdl = ShuffleNode;
3126 ISD::EXTRACT_VECTOR_ELT, sdl,
3127 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3128 DAG.getConstant(0, sdl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3129 SDB->setValue(Ptr, Base);
3134 Value *IndexVal = Gep->getOperand(1);
3135 if (SDB->findValue(IndexVal)) {
3136 Index = SDB->getValue(IndexVal);
3138 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3139 IndexVal = Sext->getOperand(0);
3140 if (SDB->findValue(IndexVal))
3141 Index = SDB->getValue(IndexVal);
3148 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3149 SDLoc sdl = getCurSDLoc();
3151 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3152 Value *Ptr = I.getArgOperand(1);
3153 SDValue Src0 = getValue(I.getArgOperand(0));
3154 SDValue Mask = getValue(I.getArgOperand(3));
3155 EVT VT = Src0.getValueType();
3156 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3158 Alignment = DAG.getEVTAlignment(VT);
3159 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3162 I.getAAMetadata(AAInfo);
3166 Value *BasePtr = Ptr;
3167 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3169 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3170 MachineMemOperand *MMO = DAG.getMachineFunction().
3171 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3172 MachineMemOperand::MOStore, VT.getStoreSize(),
3175 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3176 Index = getValue(Ptr);
3178 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3179 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3181 DAG.setRoot(Scatter);
3182 setValue(&I, Scatter);
3185 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3186 SDLoc sdl = getCurSDLoc();
3188 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3189 Value *PtrOperand = I.getArgOperand(0);
3190 SDValue Ptr = getValue(PtrOperand);
3191 SDValue Src0 = getValue(I.getArgOperand(3));
3192 SDValue Mask = getValue(I.getArgOperand(2));
3194 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3195 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3196 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3198 Alignment = DAG.getEVTAlignment(VT);
3201 I.getAAMetadata(AAInfo);
3202 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3204 SDValue InChain = DAG.getRoot();
3205 if (AA->pointsToConstantMemory(MemoryLocation(
3206 PtrOperand, AA->getTypeStoreSize(I.getType()), AAInfo))) {
3207 // Do not serialize (non-volatile) loads of constant memory with anything.
3208 InChain = DAG.getEntryNode();
3211 MachineMemOperand *MMO =
3212 DAG.getMachineFunction().
3213 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3214 MachineMemOperand::MOLoad, VT.getStoreSize(),
3215 Alignment, AAInfo, Ranges);
3217 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3219 SDValue OutChain = Load.getValue(1);
3220 DAG.setRoot(OutChain);
3224 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3225 SDLoc sdl = getCurSDLoc();
3227 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3228 Value *Ptr = I.getArgOperand(0);
3229 SDValue Src0 = getValue(I.getArgOperand(3));
3230 SDValue Mask = getValue(I.getArgOperand(2));
3232 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3233 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3234 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3236 Alignment = DAG.getEVTAlignment(VT);
3239 I.getAAMetadata(AAInfo);
3240 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3242 SDValue Root = DAG.getRoot();
3245 Value *BasePtr = Ptr;
3246 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3247 bool ConstantMemory = false;
3249 AA->pointsToConstantMemory(
3250 MemoryLocation(BasePtr, AA->getTypeStoreSize(I.getType()), AAInfo))) {
3251 // Do not serialize (non-volatile) loads of constant memory with anything.
3252 Root = DAG.getEntryNode();
3253 ConstantMemory = true;
3256 MachineMemOperand *MMO =
3257 DAG.getMachineFunction().
3258 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3259 MachineMemOperand::MOLoad, VT.getStoreSize(),
3260 Alignment, AAInfo, Ranges);
3263 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3264 Index = getValue(Ptr);
3266 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3267 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3270 SDValue OutChain = Gather.getValue(1);
3271 if (!ConstantMemory)
3272 PendingLoads.push_back(OutChain);
3273 setValue(&I, Gather);
3276 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3277 SDLoc dl = getCurSDLoc();
3278 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3279 AtomicOrdering FailureOrder = I.getFailureOrdering();
3280 SynchronizationScope Scope = I.getSynchScope();
3282 SDValue InChain = getRoot();
3284 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3285 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3286 SDValue L = DAG.getAtomicCmpSwap(
3287 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3288 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3289 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3290 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3292 SDValue OutChain = L.getValue(2);
3295 DAG.setRoot(OutChain);
3298 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3299 SDLoc dl = getCurSDLoc();
3301 switch (I.getOperation()) {
3302 default: llvm_unreachable("Unknown atomicrmw operation");
3303 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3304 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3305 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3306 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3307 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3308 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3309 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3310 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3311 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3312 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3313 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3315 AtomicOrdering Order = I.getOrdering();
3316 SynchronizationScope Scope = I.getSynchScope();
3318 SDValue InChain = getRoot();
3321 DAG.getAtomic(NT, dl,
3322 getValue(I.getValOperand()).getSimpleValueType(),
3324 getValue(I.getPointerOperand()),
3325 getValue(I.getValOperand()),
3326 I.getPointerOperand(),
3327 /* Alignment=*/ 0, Order, Scope);
3329 SDValue OutChain = L.getValue(1);
3332 DAG.setRoot(OutChain);
3335 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3336 SDLoc dl = getCurSDLoc();
3337 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3340 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3341 TLI.getPointerTy(DAG.getDataLayout()));
3342 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3343 TLI.getPointerTy(DAG.getDataLayout()));
3344 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3347 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3348 SDLoc dl = getCurSDLoc();
3349 AtomicOrdering Order = I.getOrdering();
3350 SynchronizationScope Scope = I.getSynchScope();
3352 SDValue InChain = getRoot();
3354 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3355 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3357 if (I.getAlignment() < VT.getSizeInBits() / 8)
3358 report_fatal_error("Cannot generate unaligned atomic load");
3360 MachineMemOperand *MMO =
3361 DAG.getMachineFunction().
3362 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3363 MachineMemOperand::MOVolatile |
3364 MachineMemOperand::MOLoad,
3366 I.getAlignment() ? I.getAlignment() :
3367 DAG.getEVTAlignment(VT));
3369 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3371 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3372 getValue(I.getPointerOperand()), MMO,
3375 SDValue OutChain = L.getValue(1);
3378 DAG.setRoot(OutChain);
3381 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3382 SDLoc dl = getCurSDLoc();
3384 AtomicOrdering Order = I.getOrdering();
3385 SynchronizationScope Scope = I.getSynchScope();
3387 SDValue InChain = getRoot();
3389 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3391 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3393 if (I.getAlignment() < VT.getSizeInBits() / 8)
3394 report_fatal_error("Cannot generate unaligned atomic store");
3397 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3399 getValue(I.getPointerOperand()),
3400 getValue(I.getValueOperand()),
3401 I.getPointerOperand(), I.getAlignment(),
3404 DAG.setRoot(OutChain);
3407 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3409 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3410 unsigned Intrinsic) {
3411 bool HasChain = !I.doesNotAccessMemory();
3412 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3414 // Build the operand list.
3415 SmallVector<SDValue, 8> Ops;
3416 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3418 // We don't need to serialize loads against other loads.
3419 Ops.push_back(DAG.getRoot());
3421 Ops.push_back(getRoot());
3425 // Info is set by getTgtMemInstrinsic
3426 TargetLowering::IntrinsicInfo Info;
3427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3428 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3430 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3431 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3432 Info.opc == ISD::INTRINSIC_W_CHAIN)
3433 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3434 TLI.getPointerTy(DAG.getDataLayout())));
3436 // Add all operands of the call to the operand list.
3437 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3438 SDValue Op = getValue(I.getArgOperand(i));
3442 SmallVector<EVT, 4> ValueVTs;
3443 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3446 ValueVTs.push_back(MVT::Other);
3448 SDVTList VTs = DAG.getVTList(ValueVTs);
3452 if (IsTgtIntrinsic) {
3453 // This is target intrinsic that touches memory
3454 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3455 VTs, Ops, Info.memVT,
3456 MachinePointerInfo(Info.ptrVal, Info.offset),
3457 Info.align, Info.vol,
3458 Info.readMem, Info.writeMem, Info.size);
3459 } else if (!HasChain) {
3460 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3461 } else if (!I.getType()->isVoidTy()) {
3462 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3464 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3468 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3470 PendingLoads.push_back(Chain);
3475 if (!I.getType()->isVoidTy()) {
3476 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3477 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3478 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3481 setValue(&I, Result);
3485 /// GetSignificand - Get the significand and build it into a floating-point
3486 /// number with exponent of 1:
3488 /// Op = (Op & 0x007fffff) | 0x3f800000;
3490 /// where Op is the hexadecimal representation of floating point value.
3492 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3493 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3494 DAG.getConstant(0x007fffff, dl, MVT::i32));
3495 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3496 DAG.getConstant(0x3f800000, dl, MVT::i32));
3497 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3500 /// GetExponent - Get the exponent:
3502 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3504 /// where Op is the hexadecimal representation of floating point value.
3506 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3508 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3509 DAG.getConstant(0x7f800000, dl, MVT::i32));
3510 SDValue t1 = DAG.getNode(
3511 ISD::SRL, dl, MVT::i32, t0,
3512 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3513 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3514 DAG.getConstant(127, dl, MVT::i32));
3515 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3518 /// getF32Constant - Get 32-bit floating point constant.
3520 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3521 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3525 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3526 SelectionDAG &DAG) {
3527 // IntegerPartOfX = ((int32_t)(t0);
3528 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3530 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3531 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3532 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3534 // IntegerPartOfX <<= 23;
3535 IntegerPartOfX = DAG.getNode(
3536 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3537 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3538 DAG.getDataLayout())));
3540 SDValue TwoToFractionalPartOfX;
3541 if (LimitFloatPrecision <= 6) {
3542 // For floating-point precision of 6:
3544 // TwoToFractionalPartOfX =
3546 // (0.735607626f + 0.252464424f * x) * x;
3548 // error 0.0144103317, which is 6 bits
3549 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3550 getF32Constant(DAG, 0x3e814304, dl));
3551 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3552 getF32Constant(DAG, 0x3f3c50c8, dl));
3553 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3554 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3555 getF32Constant(DAG, 0x3f7f5e7e, dl));
3556 } else if (LimitFloatPrecision <= 12) {
3557 // For floating-point precision of 12:
3559 // TwoToFractionalPartOfX =
3562 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3564 // error 0.000107046256, which is 13 to 14 bits
3565 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3566 getF32Constant(DAG, 0x3da235e3, dl));
3567 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3568 getF32Constant(DAG, 0x3e65b8f3, dl));
3569 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3570 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3571 getF32Constant(DAG, 0x3f324b07, dl));
3572 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3573 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3574 getF32Constant(DAG, 0x3f7ff8fd, dl));
3575 } else { // LimitFloatPrecision <= 18
3576 // For floating-point precision of 18:
3578 // TwoToFractionalPartOfX =
3582 // (0.554906021e-1f +
3583 // (0.961591928e-2f +
3584 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3585 // error 2.47208000*10^(-7), which is better than 18 bits
3586 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3587 getF32Constant(DAG, 0x3924b03e, dl));
3588 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3589 getF32Constant(DAG, 0x3ab24b87, dl));
3590 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3591 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3592 getF32Constant(DAG, 0x3c1d8c17, dl));
3593 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3594 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3595 getF32Constant(DAG, 0x3d634a1d, dl));
3596 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3597 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3598 getF32Constant(DAG, 0x3e75fe14, dl));
3599 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3600 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3601 getF32Constant(DAG, 0x3f317234, dl));
3602 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3603 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3604 getF32Constant(DAG, 0x3f800000, dl));
3607 // Add the exponent into the result in integer domain.
3608 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3609 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3610 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3613 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3614 /// limited-precision mode.
3615 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3616 const TargetLowering &TLI) {
3617 if (Op.getValueType() == MVT::f32 &&
3618 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3620 // Put the exponent in the right bit position for later addition to the
3623 // #define LOG2OFe 1.4426950f
3624 // t0 = Op * LOG2OFe
3625 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3626 getF32Constant(DAG, 0x3fb8aa3b, dl));
3627 return getLimitedPrecisionExp2(t0, dl, DAG);
3630 // No special expansion.
3631 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3634 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3635 /// limited-precision mode.
3636 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3637 const TargetLowering &TLI) {
3638 if (Op.getValueType() == MVT::f32 &&
3639 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3640 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3642 // Scale the exponent by log(2) [0.69314718f].
3643 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3644 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3645 getF32Constant(DAG, 0x3f317218, dl));
3647 // Get the significand and build it into a floating-point number with
3649 SDValue X = GetSignificand(DAG, Op1, dl);
3651 SDValue LogOfMantissa;
3652 if (LimitFloatPrecision <= 6) {
3653 // For floating-point precision of 6:
3657 // (1.4034025f - 0.23903021f * x) * x;
3659 // error 0.0034276066, which is better than 8 bits
3660 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3661 getF32Constant(DAG, 0xbe74c456, dl));
3662 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3663 getF32Constant(DAG, 0x3fb3a2b1, dl));
3664 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3665 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3666 getF32Constant(DAG, 0x3f949a29, dl));
3667 } else if (LimitFloatPrecision <= 12) {
3668 // For floating-point precision of 12:
3674 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3676 // error 0.000061011436, which is 14 bits
3677 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3678 getF32Constant(DAG, 0xbd67b6d6, dl));
3679 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3680 getF32Constant(DAG, 0x3ee4f4b8, dl));
3681 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3682 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3683 getF32Constant(DAG, 0x3fbc278b, dl));
3684 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3685 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3686 getF32Constant(DAG, 0x40348e95, dl));
3687 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3688 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3689 getF32Constant(DAG, 0x3fdef31a, dl));
3690 } else { // LimitFloatPrecision <= 18
3691 // For floating-point precision of 18:
3699 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3701 // error 0.0000023660568, which is better than 18 bits
3702 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3703 getF32Constant(DAG, 0xbc91e5ac, dl));
3704 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3705 getF32Constant(DAG, 0x3e4350aa, dl));
3706 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3707 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3708 getF32Constant(DAG, 0x3f60d3e3, dl));
3709 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3710 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3711 getF32Constant(DAG, 0x4011cdf0, dl));
3712 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3713 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3714 getF32Constant(DAG, 0x406cfd1c, dl));
3715 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3716 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3717 getF32Constant(DAG, 0x408797cb, dl));
3718 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3719 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3720 getF32Constant(DAG, 0x4006dcab, dl));
3723 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3726 // No special expansion.
3727 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3730 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3731 /// limited-precision mode.
3732 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3733 const TargetLowering &TLI) {
3734 if (Op.getValueType() == MVT::f32 &&
3735 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3736 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3738 // Get the exponent.
3739 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3741 // Get the significand and build it into a floating-point number with
3743 SDValue X = GetSignificand(DAG, Op1, dl);
3745 // Different possible minimax approximations of significand in
3746 // floating-point for various degrees of accuracy over [1,2].
3747 SDValue Log2ofMantissa;
3748 if (LimitFloatPrecision <= 6) {
3749 // For floating-point precision of 6:
3751 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3753 // error 0.0049451742, which is more than 7 bits
3754 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3755 getF32Constant(DAG, 0xbeb08fe0, dl));
3756 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3757 getF32Constant(DAG, 0x40019463, dl));
3758 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3759 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3760 getF32Constant(DAG, 0x3fd6633d, dl));
3761 } else if (LimitFloatPrecision <= 12) {
3762 // For floating-point precision of 12:
3768 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3770 // error 0.0000876136000, which is better than 13 bits
3771 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3772 getF32Constant(DAG, 0xbda7262e, dl));
3773 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3774 getF32Constant(DAG, 0x3f25280b, dl));
3775 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3776 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3777 getF32Constant(DAG, 0x4007b923, dl));
3778 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3779 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3780 getF32Constant(DAG, 0x40823e2f, dl));
3781 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3782 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3783 getF32Constant(DAG, 0x4020d29c, dl));
3784 } else { // LimitFloatPrecision <= 18
3785 // For floating-point precision of 18:
3794 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3796 // error 0.0000018516, which is better than 18 bits
3797 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3798 getF32Constant(DAG, 0xbcd2769e, dl));
3799 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3800 getF32Constant(DAG, 0x3e8ce0b9, dl));
3801 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3802 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3803 getF32Constant(DAG, 0x3fa22ae7, dl));
3804 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3805 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3806 getF32Constant(DAG, 0x40525723, dl));
3807 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3808 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3809 getF32Constant(DAG, 0x40aaf200, dl));
3810 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3811 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3812 getF32Constant(DAG, 0x40c39dad, dl));
3813 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3814 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3815 getF32Constant(DAG, 0x4042902c, dl));
3818 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3821 // No special expansion.
3822 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3825 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3826 /// limited-precision mode.
3827 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3828 const TargetLowering &TLI) {
3829 if (Op.getValueType() == MVT::f32 &&
3830 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3831 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3833 // Scale the exponent by log10(2) [0.30102999f].
3834 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3835 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3836 getF32Constant(DAG, 0x3e9a209a, dl));
3838 // Get the significand and build it into a floating-point number with
3840 SDValue X = GetSignificand(DAG, Op1, dl);
3842 SDValue Log10ofMantissa;
3843 if (LimitFloatPrecision <= 6) {
3844 // For floating-point precision of 6:
3846 // Log10ofMantissa =
3848 // (0.60948995f - 0.10380950f * x) * x;
3850 // error 0.0014886165, which is 6 bits
3851 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3852 getF32Constant(DAG, 0xbdd49a13, dl));
3853 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3854 getF32Constant(DAG, 0x3f1c0789, dl));
3855 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3856 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3857 getF32Constant(DAG, 0x3f011300, dl));
3858 } else if (LimitFloatPrecision <= 12) {
3859 // For floating-point precision of 12:
3861 // Log10ofMantissa =
3864 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3866 // error 0.00019228036, which is better than 12 bits
3867 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3868 getF32Constant(DAG, 0x3d431f31, dl));
3869 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3870 getF32Constant(DAG, 0x3ea21fb2, dl));
3871 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3872 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3873 getF32Constant(DAG, 0x3f6ae232, dl));
3874 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3875 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3876 getF32Constant(DAG, 0x3f25f7c3, dl));
3877 } else { // LimitFloatPrecision <= 18
3878 // For floating-point precision of 18:
3880 // Log10ofMantissa =
3885 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3887 // error 0.0000037995730, which is better than 18 bits
3888 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3889 getF32Constant(DAG, 0x3c5d51ce, dl));
3890 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3891 getF32Constant(DAG, 0x3e00685a, dl));
3892 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3893 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3894 getF32Constant(DAG, 0x3efb6798, dl));
3895 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3896 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3897 getF32Constant(DAG, 0x3f88d192, dl));
3898 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3899 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3900 getF32Constant(DAG, 0x3fc4316c, dl));
3901 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3902 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3903 getF32Constant(DAG, 0x3f57ce70, dl));
3906 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3909 // No special expansion.
3910 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3913 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3914 /// limited-precision mode.
3915 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3916 const TargetLowering &TLI) {
3917 if (Op.getValueType() == MVT::f32 &&
3918 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3919 return getLimitedPrecisionExp2(Op, dl, DAG);
3921 // No special expansion.
3922 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3925 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3926 /// limited-precision mode with x == 10.0f.
3927 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3928 SelectionDAG &DAG, const TargetLowering &TLI) {
3929 bool IsExp10 = false;
3930 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3931 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3932 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3934 IsExp10 = LHSC->isExactlyValue(Ten);
3939 // Put the exponent in the right bit position for later addition to the
3942 // #define LOG2OF10 3.3219281f
3943 // t0 = Op * LOG2OF10;
3944 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3945 getF32Constant(DAG, 0x40549a78, dl));
3946 return getLimitedPrecisionExp2(t0, dl, DAG);
3949 // No special expansion.
3950 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3954 /// ExpandPowI - Expand a llvm.powi intrinsic.
3955 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3956 SelectionDAG &DAG) {
3957 // If RHS is a constant, we can expand this out to a multiplication tree,
3958 // otherwise we end up lowering to a call to __powidf2 (for example). When
3959 // optimizing for size, we only want to do this if the expansion would produce
3960 // a small number of multiplies, otherwise we do the full expansion.
3961 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3962 // Get the exponent as a positive value.
3963 unsigned Val = RHSC->getSExtValue();
3964 if ((int)Val < 0) Val = -Val;
3966 // powi(x, 0) -> 1.0
3968 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3970 const Function *F = DAG.getMachineFunction().getFunction();
3971 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3972 // If optimizing for size, don't insert too many multiplies. This
3973 // inserts up to 5 multiplies.
3974 countPopulation(Val) + Log2_32(Val) < 7) {
3975 // We use the simple binary decomposition method to generate the multiply
3976 // sequence. There are more optimal ways to do this (for example,
3977 // powi(x,15) generates one more multiply than it should), but this has
3978 // the benefit of being both really simple and much better than a libcall.
3979 SDValue Res; // Logically starts equal to 1.0
3980 SDValue CurSquare = LHS;
3984 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3986 Res = CurSquare; // 1.0*CurSquare.
3989 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3990 CurSquare, CurSquare);
3994 // If the original was negative, invert the result, producing 1/(x*x*x).
3995 if (RHSC->getSExtValue() < 0)
3996 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3997 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4002 // Otherwise, expand to a libcall.
4003 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4006 // getTruncatedArgReg - Find underlying register used for an truncated
4008 static unsigned getTruncatedArgReg(const SDValue &N) {
4009 if (N.getOpcode() != ISD::TRUNCATE)
4012 const SDValue &Ext = N.getOperand(0);
4013 if (Ext.getOpcode() == ISD::AssertZext ||
4014 Ext.getOpcode() == ISD::AssertSext) {
4015 const SDValue &CFR = Ext.getOperand(0);
4016 if (CFR.getOpcode() == ISD::CopyFromReg)
4017 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4018 if (CFR.getOpcode() == ISD::TRUNCATE)
4019 return getTruncatedArgReg(CFR);
4024 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4025 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4026 /// At the end of instruction selection, they will be inserted to the entry BB.
4027 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4028 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4029 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4030 const Argument *Arg = dyn_cast<Argument>(V);
4034 MachineFunction &MF = DAG.getMachineFunction();
4035 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4037 // Ignore inlined function arguments here.
4039 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4040 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4043 Optional<MachineOperand> Op;
4044 // Some arguments' frame index is recorded during argument lowering.
4045 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4046 Op = MachineOperand::CreateFI(FI);
4048 if (!Op && N.getNode()) {
4050 if (N.getOpcode() == ISD::CopyFromReg)
4051 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4053 Reg = getTruncatedArgReg(N);
4054 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4055 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4056 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4061 Op = MachineOperand::CreateReg(Reg, false);
4065 // Check if ValueMap has reg number.
4066 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4067 if (VMI != FuncInfo.ValueMap.end())
4068 Op = MachineOperand::CreateReg(VMI->second, false);
4071 if (!Op && N.getNode())
4072 // Check if frame index is available.
4073 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4074 if (FrameIndexSDNode *FINode =
4075 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4076 Op = MachineOperand::CreateFI(FINode->getIndex());
4081 assert(Variable->isValidLocationForIntrinsic(DL) &&
4082 "Expected inlined-at fields to agree");
4084 FuncInfo.ArgDbgValues.push_back(
4085 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4086 Op->getReg(), Offset, Variable, Expr));
4088 FuncInfo.ArgDbgValues.push_back(
4089 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4092 .addMetadata(Variable)
4093 .addMetadata(Expr));
4098 // VisualStudio defines setjmp as _setjmp
4099 #if defined(_MSC_VER) && defined(setjmp) && \
4100 !defined(setjmp_undefined_for_msvc)
4101 # pragma push_macro("setjmp")
4103 # define setjmp_undefined_for_msvc
4106 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4107 /// we want to emit this as a call to a named external function, return the name
4108 /// otherwise lower it and return null.
4110 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4111 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4112 SDLoc sdl = getCurSDLoc();
4113 DebugLoc dl = getCurDebugLoc();
4116 switch (Intrinsic) {
4118 // By default, turn this into a target intrinsic node.
4119 visitTargetIntrinsic(I, Intrinsic);
4121 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4122 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4123 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4124 case Intrinsic::returnaddress:
4125 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4126 TLI.getPointerTy(DAG.getDataLayout()),
4127 getValue(I.getArgOperand(0))));
4129 case Intrinsic::frameaddress:
4130 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4131 TLI.getPointerTy(DAG.getDataLayout()),
4132 getValue(I.getArgOperand(0))));
4134 case Intrinsic::read_register: {
4135 Value *Reg = I.getArgOperand(0);
4136 SDValue Chain = getRoot();
4138 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4139 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4140 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4141 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4143 DAG.setRoot(Res.getValue(1));
4146 case Intrinsic::write_register: {
4147 Value *Reg = I.getArgOperand(0);
4148 Value *RegValue = I.getArgOperand(1);
4149 SDValue Chain = getRoot();
4151 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4152 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4153 RegName, getValue(RegValue)));
4156 case Intrinsic::setjmp:
4157 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4158 case Intrinsic::longjmp:
4159 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4160 case Intrinsic::memcpy: {
4161 // FIXME: this definition of "user defined address space" is x86-specific
4162 // Assert for address < 256 since we support only user defined address
4164 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4166 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4168 "Unknown address space");
4169 SDValue Op1 = getValue(I.getArgOperand(0));
4170 SDValue Op2 = getValue(I.getArgOperand(1));
4171 SDValue Op3 = getValue(I.getArgOperand(2));
4172 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4174 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4175 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4176 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4177 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4179 MachinePointerInfo(I.getArgOperand(0)),
4180 MachinePointerInfo(I.getArgOperand(1)));
4181 updateDAGForMaybeTailCall(MC);
4184 case Intrinsic::memset: {
4185 // FIXME: this definition of "user defined address space" is x86-specific
4186 // Assert for address < 256 since we support only user defined address
4188 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4190 "Unknown address space");
4191 SDValue Op1 = getValue(I.getArgOperand(0));
4192 SDValue Op2 = getValue(I.getArgOperand(1));
4193 SDValue Op3 = getValue(I.getArgOperand(2));
4194 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4196 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4197 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4198 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4199 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4200 isTC, MachinePointerInfo(I.getArgOperand(0)));
4201 updateDAGForMaybeTailCall(MS);
4204 case Intrinsic::memmove: {
4205 // FIXME: this definition of "user defined address space" is x86-specific
4206 // Assert for address < 256 since we support only user defined address
4208 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4210 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4212 "Unknown address space");
4213 SDValue Op1 = getValue(I.getArgOperand(0));
4214 SDValue Op2 = getValue(I.getArgOperand(1));
4215 SDValue Op3 = getValue(I.getArgOperand(2));
4216 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4218 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4219 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4220 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4221 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4222 isTC, MachinePointerInfo(I.getArgOperand(0)),
4223 MachinePointerInfo(I.getArgOperand(1)));
4224 updateDAGForMaybeTailCall(MM);
4227 case Intrinsic::dbg_declare: {
4228 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4229 DILocalVariable *Variable = DI.getVariable();
4230 DIExpression *Expression = DI.getExpression();
4231 const Value *Address = DI.getAddress();
4232 assert(Variable && "Missing variable");
4234 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4238 // Check if address has undef value.
4239 if (isa<UndefValue>(Address) ||
4240 (Address->use_empty() && !isa<Argument>(Address))) {
4241 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4245 SDValue &N = NodeMap[Address];
4246 if (!N.getNode() && isa<Argument>(Address))
4247 // Check unused arguments map.
4248 N = UnusedArgNodeMap[Address];
4251 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4252 Address = BCI->getOperand(0);
4253 // Parameters are handled specially.
4254 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4256 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4258 if (isParameter && !AI) {
4259 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4261 // Byval parameter. We have a frame index at this point.
4262 SDV = DAG.getFrameIndexDbgValue(
4263 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4265 // Address is an argument, so try to emit its dbg value using
4266 // virtual register info from the FuncInfo.ValueMap.
4267 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4272 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4273 true, 0, dl, SDNodeOrder);
4275 // Can't do anything with other non-AI cases yet.
4276 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4277 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4278 DEBUG(Address->dump());
4281 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4283 // If Address is an argument then try to emit its dbg value using
4284 // virtual register info from the FuncInfo.ValueMap.
4285 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4287 // If variable is pinned by a alloca in dominating bb then
4288 // use StaticAllocaMap.
4289 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4290 if (AI->getParent() != DI.getParent()) {
4291 DenseMap<const AllocaInst*, int>::iterator SI =
4292 FuncInfo.StaticAllocaMap.find(AI);
4293 if (SI != FuncInfo.StaticAllocaMap.end()) {
4294 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4295 0, dl, SDNodeOrder);
4296 DAG.AddDbgValue(SDV, nullptr, false);
4301 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4306 case Intrinsic::dbg_value: {
4307 const DbgValueInst &DI = cast<DbgValueInst>(I);
4308 assert(DI.getVariable() && "Missing variable");
4310 DILocalVariable *Variable = DI.getVariable();
4311 DIExpression *Expression = DI.getExpression();
4312 uint64_t Offset = DI.getOffset();
4313 const Value *V = DI.getValue();
4318 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4319 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4321 DAG.AddDbgValue(SDV, nullptr, false);
4323 // Do not use getValue() in here; we don't want to generate code at
4324 // this point if it hasn't been done yet.
4325 SDValue N = NodeMap[V];
4326 if (!N.getNode() && isa<Argument>(V))
4327 // Check unused arguments map.
4328 N = UnusedArgNodeMap[V];
4330 // A dbg.value for an alloca is always indirect.
4331 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4332 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4334 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4335 IsIndirect, Offset, dl, SDNodeOrder);
4336 DAG.AddDbgValue(SDV, N.getNode(), false);
4338 } else if (!V->use_empty() ) {
4339 // Do not call getValue(V) yet, as we don't want to generate code.
4340 // Remember it for later.
4341 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4342 DanglingDebugInfoMap[V] = DDI;
4344 // We may expand this to cover more cases. One case where we have no
4345 // data available is an unreferenced parameter.
4346 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4350 // Build a debug info table entry.
4351 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4352 V = BCI->getOperand(0);
4353 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4354 // Don't handle byval struct arguments or VLAs, for example.
4356 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4357 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4360 DenseMap<const AllocaInst*, int>::iterator SI =
4361 FuncInfo.StaticAllocaMap.find(AI);
4362 if (SI == FuncInfo.StaticAllocaMap.end())
4363 return nullptr; // VLAs.
4367 case Intrinsic::eh_typeid_for: {
4368 // Find the type id for the given typeinfo.
4369 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4370 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4371 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4376 case Intrinsic::eh_return_i32:
4377 case Intrinsic::eh_return_i64:
4378 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4379 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4382 getValue(I.getArgOperand(0)),
4383 getValue(I.getArgOperand(1))));
4385 case Intrinsic::eh_unwind_init:
4386 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4388 case Intrinsic::eh_dwarf_cfa: {
4389 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4390 TLI.getPointerTy(DAG.getDataLayout()));
4391 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4392 CfaArg.getValueType(),
4393 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4394 CfaArg.getValueType()),
4396 SDValue FA = DAG.getNode(
4397 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4398 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4399 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4403 case Intrinsic::eh_sjlj_callsite: {
4404 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4405 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4406 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4407 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4409 MMI.setCurrentCallSite(CI->getZExtValue());
4412 case Intrinsic::eh_sjlj_functioncontext: {
4413 // Get and store the index of the function context.
4414 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4416 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4417 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4418 MFI->setFunctionContextIndex(FI);
4421 case Intrinsic::eh_sjlj_setjmp: {
4424 Ops[1] = getValue(I.getArgOperand(0));
4425 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4426 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4427 setValue(&I, Op.getValue(0));
4428 DAG.setRoot(Op.getValue(1));
4431 case Intrinsic::eh_sjlj_longjmp: {
4432 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4433 getRoot(), getValue(I.getArgOperand(0))));
4436 case Intrinsic::eh_sjlj_setup_dispatch: {
4437 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4442 case Intrinsic::masked_gather:
4443 visitMaskedGather(I);
4445 case Intrinsic::masked_load:
4448 case Intrinsic::masked_scatter:
4449 visitMaskedScatter(I);
4451 case Intrinsic::masked_store:
4452 visitMaskedStore(I);
4454 case Intrinsic::x86_mmx_pslli_w:
4455 case Intrinsic::x86_mmx_pslli_d:
4456 case Intrinsic::x86_mmx_pslli_q:
4457 case Intrinsic::x86_mmx_psrli_w:
4458 case Intrinsic::x86_mmx_psrli_d:
4459 case Intrinsic::x86_mmx_psrli_q:
4460 case Intrinsic::x86_mmx_psrai_w:
4461 case Intrinsic::x86_mmx_psrai_d: {
4462 SDValue ShAmt = getValue(I.getArgOperand(1));
4463 if (isa<ConstantSDNode>(ShAmt)) {
4464 visitTargetIntrinsic(I, Intrinsic);
4467 unsigned NewIntrinsic = 0;
4468 EVT ShAmtVT = MVT::v2i32;
4469 switch (Intrinsic) {
4470 case Intrinsic::x86_mmx_pslli_w:
4471 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4473 case Intrinsic::x86_mmx_pslli_d:
4474 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4476 case Intrinsic::x86_mmx_pslli_q:
4477 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4479 case Intrinsic::x86_mmx_psrli_w:
4480 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4482 case Intrinsic::x86_mmx_psrli_d:
4483 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4485 case Intrinsic::x86_mmx_psrli_q:
4486 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4488 case Intrinsic::x86_mmx_psrai_w:
4489 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4491 case Intrinsic::x86_mmx_psrai_d:
4492 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4494 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4497 // The vector shift intrinsics with scalars uses 32b shift amounts but
4498 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4500 // We must do this early because v2i32 is not a legal type.
4503 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4504 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4505 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4506 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4507 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4508 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4509 getValue(I.getArgOperand(0)), ShAmt);
4513 case Intrinsic::convertff:
4514 case Intrinsic::convertfsi:
4515 case Intrinsic::convertfui:
4516 case Intrinsic::convertsif:
4517 case Intrinsic::convertuif:
4518 case Intrinsic::convertss:
4519 case Intrinsic::convertsu:
4520 case Intrinsic::convertus:
4521 case Intrinsic::convertuu: {
4522 ISD::CvtCode Code = ISD::CVT_INVALID;
4523 switch (Intrinsic) {
4524 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4525 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4526 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4527 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4528 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4529 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4530 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4531 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4532 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4533 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4535 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4536 const Value *Op1 = I.getArgOperand(0);
4537 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4538 DAG.getValueType(DestVT),
4539 DAG.getValueType(getValue(Op1).getValueType()),
4540 getValue(I.getArgOperand(1)),
4541 getValue(I.getArgOperand(2)),
4546 case Intrinsic::powi:
4547 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4548 getValue(I.getArgOperand(1)), DAG));
4550 case Intrinsic::log:
4551 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4553 case Intrinsic::log2:
4554 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4556 case Intrinsic::log10:
4557 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4559 case Intrinsic::exp:
4560 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4562 case Intrinsic::exp2:
4563 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4565 case Intrinsic::pow:
4566 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4567 getValue(I.getArgOperand(1)), DAG, TLI));
4569 case Intrinsic::sqrt:
4570 case Intrinsic::fabs:
4571 case Intrinsic::sin:
4572 case Intrinsic::cos:
4573 case Intrinsic::floor:
4574 case Intrinsic::ceil:
4575 case Intrinsic::trunc:
4576 case Intrinsic::rint:
4577 case Intrinsic::nearbyint:
4578 case Intrinsic::round: {
4580 switch (Intrinsic) {
4581 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4582 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4583 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4584 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4585 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4586 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4587 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4588 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4589 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4590 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4591 case Intrinsic::round: Opcode = ISD::FROUND; break;
4594 setValue(&I, DAG.getNode(Opcode, sdl,
4595 getValue(I.getArgOperand(0)).getValueType(),
4596 getValue(I.getArgOperand(0))));
4599 case Intrinsic::minnum:
4600 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4601 getValue(I.getArgOperand(0)).getValueType(),
4602 getValue(I.getArgOperand(0)),
4603 getValue(I.getArgOperand(1))));
4605 case Intrinsic::maxnum:
4606 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4607 getValue(I.getArgOperand(0)).getValueType(),
4608 getValue(I.getArgOperand(0)),
4609 getValue(I.getArgOperand(1))));
4611 case Intrinsic::copysign:
4612 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4613 getValue(I.getArgOperand(0)).getValueType(),
4614 getValue(I.getArgOperand(0)),
4615 getValue(I.getArgOperand(1))));
4617 case Intrinsic::fma:
4618 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4619 getValue(I.getArgOperand(0)).getValueType(),
4620 getValue(I.getArgOperand(0)),
4621 getValue(I.getArgOperand(1)),
4622 getValue(I.getArgOperand(2))));
4624 case Intrinsic::fmuladd: {
4625 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4626 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4627 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4628 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4629 getValue(I.getArgOperand(0)).getValueType(),
4630 getValue(I.getArgOperand(0)),
4631 getValue(I.getArgOperand(1)),
4632 getValue(I.getArgOperand(2))));
4634 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4635 getValue(I.getArgOperand(0)).getValueType(),
4636 getValue(I.getArgOperand(0)),
4637 getValue(I.getArgOperand(1)));
4638 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4639 getValue(I.getArgOperand(0)).getValueType(),
4641 getValue(I.getArgOperand(2)));
4646 case Intrinsic::convert_to_fp16:
4647 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4648 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4649 getValue(I.getArgOperand(0)),
4650 DAG.getTargetConstant(0, sdl,
4653 case Intrinsic::convert_from_fp16:
4654 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4655 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4656 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4657 getValue(I.getArgOperand(0)))));
4659 case Intrinsic::pcmarker: {
4660 SDValue Tmp = getValue(I.getArgOperand(0));
4661 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4664 case Intrinsic::readcyclecounter: {
4665 SDValue Op = getRoot();
4666 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4667 DAG.getVTList(MVT::i64, MVT::Other), Op);
4669 DAG.setRoot(Res.getValue(1));
4672 case Intrinsic::bswap:
4673 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4674 getValue(I.getArgOperand(0)).getValueType(),
4675 getValue(I.getArgOperand(0))));
4677 case Intrinsic::uabsdiff:
4678 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4679 getValue(I.getArgOperand(0)).getValueType(),
4680 getValue(I.getArgOperand(0)),
4681 getValue(I.getArgOperand(1))));
4683 case Intrinsic::sabsdiff:
4684 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4685 getValue(I.getArgOperand(0)).getValueType(),
4686 getValue(I.getArgOperand(0)),
4687 getValue(I.getArgOperand(1))));
4689 case Intrinsic::cttz: {
4690 SDValue Arg = getValue(I.getArgOperand(0));
4691 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4692 EVT Ty = Arg.getValueType();
4693 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4697 case Intrinsic::ctlz: {
4698 SDValue Arg = getValue(I.getArgOperand(0));
4699 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4700 EVT Ty = Arg.getValueType();
4701 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4705 case Intrinsic::ctpop: {
4706 SDValue Arg = getValue(I.getArgOperand(0));
4707 EVT Ty = Arg.getValueType();
4708 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4711 case Intrinsic::stacksave: {
4712 SDValue Op = getRoot();
4714 ISD::STACKSAVE, sdl,
4715 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4717 DAG.setRoot(Res.getValue(1));
4720 case Intrinsic::stackrestore: {
4721 Res = getValue(I.getArgOperand(0));
4722 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4725 case Intrinsic::stackprotector: {
4726 // Emit code into the DAG to store the stack guard onto the stack.
4727 MachineFunction &MF = DAG.getMachineFunction();
4728 MachineFrameInfo *MFI = MF.getFrameInfo();
4729 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4730 SDValue Src, Chain = getRoot();
4731 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4732 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4734 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4735 // global variable __stack_chk_guard.
4737 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4738 if (BC->getOpcode() == Instruction::BitCast)
4739 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4741 if (GV && TLI.useLoadStackGuardNode()) {
4742 // Emit a LOAD_STACK_GUARD node.
4743 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4745 MachinePointerInfo MPInfo(GV);
4746 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4747 unsigned Flags = MachineMemOperand::MOLoad |
4748 MachineMemOperand::MOInvariant;
4749 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4750 PtrTy.getSizeInBits() / 8,
4751 DAG.getEVTAlignment(PtrTy));
4752 Node->setMemRefs(MemRefs, MemRefs + 1);
4754 // Copy the guard value to a virtual register so that it can be
4755 // retrieved in the epilogue.
4756 Src = SDValue(Node, 0);
4757 const TargetRegisterClass *RC =
4758 TLI.getRegClassFor(Src.getSimpleValueType());
4759 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4761 SPDescriptor.setGuardReg(Reg);
4762 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4764 Src = getValue(I.getArgOperand(0)); // The guard's value.
4767 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4769 int FI = FuncInfo.StaticAllocaMap[Slot];
4770 MFI->setStackProtectorIndex(FI);
4772 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4774 // Store the stack protector onto the stack.
4775 Res = DAG.getStore(Chain, sdl, Src, FIN,
4776 MachinePointerInfo::getFixedStack(FI),
4782 case Intrinsic::objectsize: {
4783 // If we don't know by now, we're never going to know.
4784 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4786 assert(CI && "Non-constant type in __builtin_object_size?");
4788 SDValue Arg = getValue(I.getCalledValue());
4789 EVT Ty = Arg.getValueType();
4792 Res = DAG.getConstant(-1ULL, sdl, Ty);
4794 Res = DAG.getConstant(0, sdl, Ty);
4799 case Intrinsic::annotation:
4800 case Intrinsic::ptr_annotation:
4801 // Drop the intrinsic, but forward the value
4802 setValue(&I, getValue(I.getOperand(0)));
4804 case Intrinsic::assume:
4805 case Intrinsic::var_annotation:
4806 // Discard annotate attributes and assumptions
4809 case Intrinsic::init_trampoline: {
4810 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4814 Ops[1] = getValue(I.getArgOperand(0));
4815 Ops[2] = getValue(I.getArgOperand(1));
4816 Ops[3] = getValue(I.getArgOperand(2));
4817 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4818 Ops[5] = DAG.getSrcValue(F);
4820 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4825 case Intrinsic::adjust_trampoline: {
4826 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4827 TLI.getPointerTy(DAG.getDataLayout()),
4828 getValue(I.getArgOperand(0))));
4831 case Intrinsic::gcroot:
4833 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4834 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4836 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4837 GFI->addStackRoot(FI->getIndex(), TypeMap);
4840 case Intrinsic::gcread:
4841 case Intrinsic::gcwrite:
4842 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4843 case Intrinsic::flt_rounds:
4844 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4847 case Intrinsic::expect: {
4848 // Just replace __builtin_expect(exp, c) with EXP.
4849 setValue(&I, getValue(I.getArgOperand(0)));
4853 case Intrinsic::debugtrap:
4854 case Intrinsic::trap: {
4855 StringRef TrapFuncName =
4857 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4858 .getValueAsString();
4859 if (TrapFuncName.empty()) {
4860 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4861 ISD::TRAP : ISD::DEBUGTRAP;
4862 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4865 TargetLowering::ArgListTy Args;
4867 TargetLowering::CallLoweringInfo CLI(DAG);
4868 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4869 CallingConv::C, I.getType(),
4870 DAG.getExternalSymbol(TrapFuncName.data(),
4871 TLI.getPointerTy(DAG.getDataLayout())),
4872 std::move(Args), 0);
4874 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4875 DAG.setRoot(Result.second);
4879 case Intrinsic::uadd_with_overflow:
4880 case Intrinsic::sadd_with_overflow:
4881 case Intrinsic::usub_with_overflow:
4882 case Intrinsic::ssub_with_overflow:
4883 case Intrinsic::umul_with_overflow:
4884 case Intrinsic::smul_with_overflow: {
4886 switch (Intrinsic) {
4887 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4888 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4889 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4890 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4891 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4892 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4893 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4895 SDValue Op1 = getValue(I.getArgOperand(0));
4896 SDValue Op2 = getValue(I.getArgOperand(1));
4898 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4899 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4902 case Intrinsic::prefetch: {
4904 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4906 Ops[1] = getValue(I.getArgOperand(0));
4907 Ops[2] = getValue(I.getArgOperand(1));
4908 Ops[3] = getValue(I.getArgOperand(2));
4909 Ops[4] = getValue(I.getArgOperand(3));
4910 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4911 DAG.getVTList(MVT::Other), Ops,
4912 EVT::getIntegerVT(*Context, 8),
4913 MachinePointerInfo(I.getArgOperand(0)),
4915 false, /* volatile */
4917 rw==1)); /* write */
4920 case Intrinsic::lifetime_start:
4921 case Intrinsic::lifetime_end: {
4922 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4923 // Stack coloring is not enabled in O0, discard region information.
4924 if (TM.getOptLevel() == CodeGenOpt::None)
4927 SmallVector<Value *, 4> Allocas;
4928 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4930 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4931 E = Allocas.end(); Object != E; ++Object) {
4932 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4934 // Could not find an Alloca.
4935 if (!LifetimeObject)
4938 // First check that the Alloca is static, otherwise it won't have a
4939 // valid frame index.
4940 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4941 if (SI == FuncInfo.StaticAllocaMap.end())
4944 int FI = SI->second;
4949 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
4950 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4952 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4957 case Intrinsic::invariant_start:
4958 // Discard region information.
4959 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
4961 case Intrinsic::invariant_end:
4962 // Discard region information.
4964 case Intrinsic::stackprotectorcheck: {
4965 // Do not actually emit anything for this basic block. Instead we initialize
4966 // the stack protector descriptor and export the guard variable so we can
4967 // access it in FinishBasicBlock.
4968 const BasicBlock *BB = I.getParent();
4969 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4970 ExportFromCurrentBlock(SPDescriptor.getGuard());
4972 // Flush our exports since we are going to process a terminator.
4973 (void)getControlRoot();
4976 case Intrinsic::clear_cache:
4977 return TLI.getClearCacheBuiltinName();
4978 case Intrinsic::eh_actions:
4979 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
4981 case Intrinsic::donothing:
4984 case Intrinsic::experimental_stackmap: {
4988 case Intrinsic::experimental_patchpoint_void:
4989 case Intrinsic::experimental_patchpoint_i64: {
4990 visitPatchpoint(&I);
4993 case Intrinsic::experimental_gc_statepoint: {
4997 case Intrinsic::experimental_gc_result_int:
4998 case Intrinsic::experimental_gc_result_float:
4999 case Intrinsic::experimental_gc_result_ptr:
5000 case Intrinsic::experimental_gc_result: {
5004 case Intrinsic::experimental_gc_relocate: {
5008 case Intrinsic::instrprof_increment:
5009 llvm_unreachable("instrprof failed to lower an increment");
5011 case Intrinsic::localescape: {
5012 MachineFunction &MF = DAG.getMachineFunction();
5013 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5015 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5016 // is the same on all targets.
5017 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5018 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5019 if (isa<ConstantPointerNull>(Arg))
5020 continue; // Skip null pointers. They represent a hole in index space.
5021 AllocaInst *Slot = cast<AllocaInst>(Arg);
5022 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5023 "can only escape static allocas");
5024 int FI = FuncInfo.StaticAllocaMap[Slot];
5025 MCSymbol *FrameAllocSym =
5026 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5027 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5028 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5029 TII->get(TargetOpcode::LOCAL_ESCAPE))
5030 .addSym(FrameAllocSym)
5037 case Intrinsic::localrecover: {
5038 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5039 MachineFunction &MF = DAG.getMachineFunction();
5040 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5042 // Get the symbol that defines the frame offset.
5043 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5044 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5045 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5046 MCSymbol *FrameAllocSym =
5047 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5048 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5050 // Create a MCSymbol for the label to avoid any target lowering
5051 // that would make this PC relative.
5052 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5054 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5056 // Add the offset to the FP.
5057 Value *FP = I.getArgOperand(1);
5058 SDValue FPVal = getValue(FP);
5059 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5064 case Intrinsic::eh_begincatch:
5065 case Intrinsic::eh_endcatch:
5066 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5067 case Intrinsic::eh_exceptioncode: {
5068 unsigned Reg = TLI.getExceptionPointerRegister();
5069 assert(Reg && "cannot get exception code on this platform");
5070 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5071 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5072 assert(FuncInfo.MBB->isLandingPad() && "eh.exceptioncode in non-lpad");
5073 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5075 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5076 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5083 std::pair<SDValue, SDValue>
5084 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5085 MachineBasicBlock *LandingPad) {
5086 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5087 MCSymbol *BeginLabel = nullptr;
5090 // Insert a label before the invoke call to mark the try range. This can be
5091 // used to detect deletion of the invoke via the MachineModuleInfo.
5092 BeginLabel = MMI.getContext().createTempSymbol();
5094 // For SjLj, keep track of which landing pads go with which invokes
5095 // so as to maintain the ordering of pads in the LSDA.
5096 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5097 if (CallSiteIndex) {
5098 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5099 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5101 // Now that the call site is handled, stop tracking it.
5102 MMI.setCurrentCallSite(0);
5105 // Both PendingLoads and PendingExports must be flushed here;
5106 // this call might not return.
5108 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5110 CLI.setChain(getRoot());
5112 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5113 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5115 assert((CLI.IsTailCall || Result.second.getNode()) &&
5116 "Non-null chain expected with non-tail call!");
5117 assert((Result.second.getNode() || !Result.first.getNode()) &&
5118 "Null value expected with tail call!");
5120 if (!Result.second.getNode()) {
5121 // As a special case, a null chain means that a tail call has been emitted
5122 // and the DAG root is already updated.
5125 // Since there's no actual continuation from this block, nothing can be
5126 // relying on us setting vregs for them.
5127 PendingExports.clear();
5129 DAG.setRoot(Result.second);
5133 // Insert a label at the end of the invoke call to mark the try range. This
5134 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5135 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5136 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5138 // Inform MachineModuleInfo of range.
5139 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5145 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5147 MachineBasicBlock *LandingPad) {
5148 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5149 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5150 Type *RetTy = FTy->getReturnType();
5152 TargetLowering::ArgListTy Args;
5153 TargetLowering::ArgListEntry Entry;
5154 Args.reserve(CS.arg_size());
5156 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5158 const Value *V = *i;
5161 if (V->getType()->isEmptyTy())
5164 SDValue ArgNode = getValue(V);
5165 Entry.Node = ArgNode; Entry.Ty = V->getType();
5167 // Skip the first return-type Attribute to get to params.
5168 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5169 Args.push_back(Entry);
5171 // If we have an explicit sret argument that is an Instruction, (i.e., it
5172 // might point to function-local memory), we can't meaningfully tail-call.
5173 if (Entry.isSRet && isa<Instruction>(V))
5177 // Check if target-independent constraints permit a tail call here.
5178 // Target-dependent constraints are checked within TLI->LowerCallTo.
5179 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5182 TargetLowering::CallLoweringInfo CLI(DAG);
5183 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5184 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5185 .setTailCall(isTailCall);
5186 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5188 if (Result.first.getNode())
5189 setValue(CS.getInstruction(), Result.first);
5192 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5193 /// value is equal or not-equal to zero.
5194 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5195 for (const User *U : V->users()) {
5196 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5197 if (IC->isEquality())
5198 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5199 if (C->isNullValue())
5201 // Unknown instruction.
5207 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5209 SelectionDAGBuilder &Builder) {
5211 // Check to see if this load can be trivially constant folded, e.g. if the
5212 // input is from a string literal.
5213 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5214 // Cast pointer to the type we really want to load.
5215 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5216 PointerType::getUnqual(LoadTy));
5218 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5219 const_cast<Constant *>(LoadInput), *Builder.DL))
5220 return Builder.getValue(LoadCst);
5223 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5224 // still constant memory, the input chain can be the entry node.
5226 bool ConstantMemory = false;
5228 // Do not serialize (non-volatile) loads of constant memory with anything.
5229 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5230 Root = Builder.DAG.getEntryNode();
5231 ConstantMemory = true;
5233 // Do not serialize non-volatile loads against each other.
5234 Root = Builder.DAG.getRoot();
5237 SDValue Ptr = Builder.getValue(PtrVal);
5238 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5239 Ptr, MachinePointerInfo(PtrVal),
5241 false /*nontemporal*/,
5242 false /*isinvariant*/, 1 /* align=1 */);
5244 if (!ConstantMemory)
5245 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5249 /// processIntegerCallValue - Record the value for an instruction that
5250 /// produces an integer result, converting the type where necessary.
5251 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5254 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5257 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5259 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5260 setValue(&I, Value);
5263 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5264 /// If so, return true and lower it, otherwise return false and it will be
5265 /// lowered like a normal call.
5266 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5267 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5268 if (I.getNumArgOperands() != 3)
5271 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5272 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5273 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5274 !I.getType()->isIntegerTy())
5277 const Value *Size = I.getArgOperand(2);
5278 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5279 if (CSize && CSize->getZExtValue() == 0) {
5280 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5282 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5286 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5287 std::pair<SDValue, SDValue> Res =
5288 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5289 getValue(LHS), getValue(RHS), getValue(Size),
5290 MachinePointerInfo(LHS),
5291 MachinePointerInfo(RHS));
5292 if (Res.first.getNode()) {
5293 processIntegerCallValue(I, Res.first, true);
5294 PendingLoads.push_back(Res.second);
5298 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5299 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5300 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5301 bool ActuallyDoIt = true;
5304 switch (CSize->getZExtValue()) {
5306 LoadVT = MVT::Other;
5308 ActuallyDoIt = false;
5312 LoadTy = Type::getInt16Ty(CSize->getContext());
5316 LoadTy = Type::getInt32Ty(CSize->getContext());
5320 LoadTy = Type::getInt64Ty(CSize->getContext());
5324 LoadVT = MVT::v4i32;
5325 LoadTy = Type::getInt32Ty(CSize->getContext());
5326 LoadTy = VectorType::get(LoadTy, 4);
5331 // This turns into unaligned loads. We only do this if the target natively
5332 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5333 // we'll only produce a small number of byte loads.
5335 // Require that we can find a legal MVT, and only do this if the target
5336 // supports unaligned loads of that type. Expanding into byte loads would
5338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5339 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5340 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5341 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5342 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5343 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5344 // TODO: Check alignment of src and dest ptrs.
5345 if (!TLI.isTypeLegal(LoadVT) ||
5346 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5347 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5348 ActuallyDoIt = false;
5352 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5353 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5355 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5357 processIntegerCallValue(I, Res, false);
5366 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5367 /// form. If so, return true and lower it, otherwise return false and it
5368 /// will be lowered like a normal call.
5369 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5370 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5371 if (I.getNumArgOperands() != 3)
5374 const Value *Src = I.getArgOperand(0);
5375 const Value *Char = I.getArgOperand(1);
5376 const Value *Length = I.getArgOperand(2);
5377 if (!Src->getType()->isPointerTy() ||
5378 !Char->getType()->isIntegerTy() ||
5379 !Length->getType()->isIntegerTy() ||
5380 !I.getType()->isPointerTy())
5383 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5384 std::pair<SDValue, SDValue> Res =
5385 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5386 getValue(Src), getValue(Char), getValue(Length),
5387 MachinePointerInfo(Src));
5388 if (Res.first.getNode()) {
5389 setValue(&I, Res.first);
5390 PendingLoads.push_back(Res.second);
5397 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5398 /// optimized form. If so, return true and lower it, otherwise return false
5399 /// and it will be lowered like a normal call.
5400 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5401 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5402 if (I.getNumArgOperands() != 2)
5405 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5406 if (!Arg0->getType()->isPointerTy() ||
5407 !Arg1->getType()->isPointerTy() ||
5408 !I.getType()->isPointerTy())
5411 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5412 std::pair<SDValue, SDValue> Res =
5413 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5414 getValue(Arg0), getValue(Arg1),
5415 MachinePointerInfo(Arg0),
5416 MachinePointerInfo(Arg1), isStpcpy);
5417 if (Res.first.getNode()) {
5418 setValue(&I, Res.first);
5419 DAG.setRoot(Res.second);
5426 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5427 /// If so, return true and lower it, otherwise return false and it will be
5428 /// lowered like a normal call.
5429 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5430 // Verify that the prototype makes sense. int strcmp(void*,void*)
5431 if (I.getNumArgOperands() != 2)
5434 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5435 if (!Arg0->getType()->isPointerTy() ||
5436 !Arg1->getType()->isPointerTy() ||
5437 !I.getType()->isIntegerTy())
5440 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5441 std::pair<SDValue, SDValue> Res =
5442 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5443 getValue(Arg0), getValue(Arg1),
5444 MachinePointerInfo(Arg0),
5445 MachinePointerInfo(Arg1));
5446 if (Res.first.getNode()) {
5447 processIntegerCallValue(I, Res.first, true);
5448 PendingLoads.push_back(Res.second);
5455 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5456 /// form. If so, return true and lower it, otherwise return false and it
5457 /// will be lowered like a normal call.
5458 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5459 // Verify that the prototype makes sense. size_t strlen(char *)
5460 if (I.getNumArgOperands() != 1)
5463 const Value *Arg0 = I.getArgOperand(0);
5464 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5467 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5468 std::pair<SDValue, SDValue> Res =
5469 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5470 getValue(Arg0), MachinePointerInfo(Arg0));
5471 if (Res.first.getNode()) {
5472 processIntegerCallValue(I, Res.first, false);
5473 PendingLoads.push_back(Res.second);
5480 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5481 /// form. If so, return true and lower it, otherwise return false and it
5482 /// will be lowered like a normal call.
5483 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5484 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5485 if (I.getNumArgOperands() != 2)
5488 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5489 if (!Arg0->getType()->isPointerTy() ||
5490 !Arg1->getType()->isIntegerTy() ||
5491 !I.getType()->isIntegerTy())
5494 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5495 std::pair<SDValue, SDValue> Res =
5496 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5497 getValue(Arg0), getValue(Arg1),
5498 MachinePointerInfo(Arg0));
5499 if (Res.first.getNode()) {
5500 processIntegerCallValue(I, Res.first, false);
5501 PendingLoads.push_back(Res.second);
5508 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5509 /// operation (as expected), translate it to an SDNode with the specified opcode
5510 /// and return true.
5511 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5513 // Sanity check that it really is a unary floating-point call.
5514 if (I.getNumArgOperands() != 1 ||
5515 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5516 I.getType() != I.getArgOperand(0)->getType() ||
5517 !I.onlyReadsMemory())
5520 SDValue Tmp = getValue(I.getArgOperand(0));
5521 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5525 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5526 /// operation (as expected), translate it to an SDNode with the specified opcode
5527 /// and return true.
5528 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5530 // Sanity check that it really is a binary floating-point call.
5531 if (I.getNumArgOperands() != 2 ||
5532 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5533 I.getType() != I.getArgOperand(0)->getType() ||
5534 I.getType() != I.getArgOperand(1)->getType() ||
5535 !I.onlyReadsMemory())
5538 SDValue Tmp0 = getValue(I.getArgOperand(0));
5539 SDValue Tmp1 = getValue(I.getArgOperand(1));
5540 EVT VT = Tmp0.getValueType();
5541 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5545 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5546 // Handle inline assembly differently.
5547 if (isa<InlineAsm>(I.getCalledValue())) {
5552 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5553 ComputeUsesVAFloatArgument(I, &MMI);
5555 const char *RenameFn = nullptr;
5556 if (Function *F = I.getCalledFunction()) {
5557 if (F->isDeclaration()) {
5558 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5559 if (unsigned IID = II->getIntrinsicID(F)) {
5560 RenameFn = visitIntrinsicCall(I, IID);
5565 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5566 RenameFn = visitIntrinsicCall(I, IID);
5572 // Check for well-known libc/libm calls. If the function is internal, it
5573 // can't be a library call.
5575 if (!F->hasLocalLinkage() && F->hasName() &&
5576 LibInfo->getLibFunc(F->getName(), Func) &&
5577 LibInfo->hasOptimizedCodeGen(Func)) {
5580 case LibFunc::copysign:
5581 case LibFunc::copysignf:
5582 case LibFunc::copysignl:
5583 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5584 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5585 I.getType() == I.getArgOperand(0)->getType() &&
5586 I.getType() == I.getArgOperand(1)->getType() &&
5587 I.onlyReadsMemory()) {
5588 SDValue LHS = getValue(I.getArgOperand(0));
5589 SDValue RHS = getValue(I.getArgOperand(1));
5590 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5591 LHS.getValueType(), LHS, RHS));
5596 case LibFunc::fabsf:
5597 case LibFunc::fabsl:
5598 if (visitUnaryFloatCall(I, ISD::FABS))
5602 case LibFunc::fminf:
5603 case LibFunc::fminl:
5604 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5608 case LibFunc::fmaxf:
5609 case LibFunc::fmaxl:
5610 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5616 if (visitUnaryFloatCall(I, ISD::FSIN))
5622 if (visitUnaryFloatCall(I, ISD::FCOS))
5626 case LibFunc::sqrtf:
5627 case LibFunc::sqrtl:
5628 case LibFunc::sqrt_finite:
5629 case LibFunc::sqrtf_finite:
5630 case LibFunc::sqrtl_finite:
5631 if (visitUnaryFloatCall(I, ISD::FSQRT))
5634 case LibFunc::floor:
5635 case LibFunc::floorf:
5636 case LibFunc::floorl:
5637 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5640 case LibFunc::nearbyint:
5641 case LibFunc::nearbyintf:
5642 case LibFunc::nearbyintl:
5643 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5647 case LibFunc::ceilf:
5648 case LibFunc::ceill:
5649 if (visitUnaryFloatCall(I, ISD::FCEIL))
5653 case LibFunc::rintf:
5654 case LibFunc::rintl:
5655 if (visitUnaryFloatCall(I, ISD::FRINT))
5658 case LibFunc::round:
5659 case LibFunc::roundf:
5660 case LibFunc::roundl:
5661 if (visitUnaryFloatCall(I, ISD::FROUND))
5664 case LibFunc::trunc:
5665 case LibFunc::truncf:
5666 case LibFunc::truncl:
5667 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5671 case LibFunc::log2f:
5672 case LibFunc::log2l:
5673 if (visitUnaryFloatCall(I, ISD::FLOG2))
5677 case LibFunc::exp2f:
5678 case LibFunc::exp2l:
5679 if (visitUnaryFloatCall(I, ISD::FEXP2))
5682 case LibFunc::memcmp:
5683 if (visitMemCmpCall(I))
5686 case LibFunc::memchr:
5687 if (visitMemChrCall(I))
5690 case LibFunc::strcpy:
5691 if (visitStrCpyCall(I, false))
5694 case LibFunc::stpcpy:
5695 if (visitStrCpyCall(I, true))
5698 case LibFunc::strcmp:
5699 if (visitStrCmpCall(I))
5702 case LibFunc::strlen:
5703 if (visitStrLenCall(I))
5706 case LibFunc::strnlen:
5707 if (visitStrNLenCall(I))
5716 Callee = getValue(I.getCalledValue());
5718 Callee = DAG.getExternalSymbol(
5720 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5722 // Check if we can potentially perform a tail call. More detailed checking is
5723 // be done within LowerCallTo, after more information about the call is known.
5724 LowerCallTo(&I, Callee, I.isTailCall());
5729 /// AsmOperandInfo - This contains information for each constraint that we are
5731 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5733 /// CallOperand - If this is the result output operand or a clobber
5734 /// this is null, otherwise it is the incoming operand to the CallInst.
5735 /// This gets modified as the asm is processed.
5736 SDValue CallOperand;
5738 /// AssignedRegs - If this is a register or register class operand, this
5739 /// contains the set of register corresponding to the operand.
5740 RegsForValue AssignedRegs;
5742 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5743 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5746 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5747 /// corresponds to. If there is no Value* for this operand, it returns
5749 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5750 const DataLayout &DL) const {
5751 if (!CallOperandVal) return MVT::Other;
5753 if (isa<BasicBlock>(CallOperandVal))
5754 return TLI.getPointerTy(DL);
5756 llvm::Type *OpTy = CallOperandVal->getType();
5758 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5759 // If this is an indirect operand, the operand is a pointer to the
5762 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5764 report_fatal_error("Indirect operand for inline asm not a pointer!");
5765 OpTy = PtrTy->getElementType();
5768 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5769 if (StructType *STy = dyn_cast<StructType>(OpTy))
5770 if (STy->getNumElements() == 1)
5771 OpTy = STy->getElementType(0);
5773 // If OpTy is not a single value, it may be a struct/union that we
5774 // can tile with integers.
5775 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5776 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5785 OpTy = IntegerType::get(Context, BitSize);
5790 return TLI.getValueType(DL, OpTy, true);
5794 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5796 } // end anonymous namespace
5798 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5799 /// specified operand. We prefer to assign virtual registers, to allow the
5800 /// register allocator to handle the assignment process. However, if the asm
5801 /// uses features that we can't model on machineinstrs, we have SDISel do the
5802 /// allocation. This produces generally horrible, but correct, code.
5804 /// OpInfo describes the operand.
5806 static void GetRegistersForValue(SelectionDAG &DAG,
5807 const TargetLowering &TLI,
5809 SDISelAsmOperandInfo &OpInfo) {
5810 LLVMContext &Context = *DAG.getContext();
5812 MachineFunction &MF = DAG.getMachineFunction();
5813 SmallVector<unsigned, 4> Regs;
5815 // If this is a constraint for a single physreg, or a constraint for a
5816 // register class, find it.
5817 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5818 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5819 OpInfo.ConstraintCode,
5820 OpInfo.ConstraintVT);
5822 unsigned NumRegs = 1;
5823 if (OpInfo.ConstraintVT != MVT::Other) {
5824 // If this is a FP input in an integer register (or visa versa) insert a bit
5825 // cast of the input value. More generally, handle any case where the input
5826 // value disagrees with the register class we plan to stick this in.
5827 if (OpInfo.Type == InlineAsm::isInput &&
5828 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5829 // Try to convert to the first EVT that the reg class contains. If the
5830 // types are identical size, use a bitcast to convert (e.g. two differing
5832 MVT RegVT = *PhysReg.second->vt_begin();
5833 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5834 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5835 RegVT, OpInfo.CallOperand);
5836 OpInfo.ConstraintVT = RegVT;
5837 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5838 // If the input is a FP value and we want it in FP registers, do a
5839 // bitcast to the corresponding integer type. This turns an f64 value
5840 // into i64, which can be passed with two i32 values on a 32-bit
5842 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5843 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5844 RegVT, OpInfo.CallOperand);
5845 OpInfo.ConstraintVT = RegVT;
5849 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5853 EVT ValueVT = OpInfo.ConstraintVT;
5855 // If this is a constraint for a specific physical register, like {r17},
5857 if (unsigned AssignedReg = PhysReg.first) {
5858 const TargetRegisterClass *RC = PhysReg.second;
5859 if (OpInfo.ConstraintVT == MVT::Other)
5860 ValueVT = *RC->vt_begin();
5862 // Get the actual register value type. This is important, because the user
5863 // may have asked for (e.g.) the AX register in i32 type. We need to
5864 // remember that AX is actually i16 to get the right extension.
5865 RegVT = *RC->vt_begin();
5867 // This is a explicit reference to a physical register.
5868 Regs.push_back(AssignedReg);
5870 // If this is an expanded reference, add the rest of the regs to Regs.
5872 TargetRegisterClass::iterator I = RC->begin();
5873 for (; *I != AssignedReg; ++I)
5874 assert(I != RC->end() && "Didn't find reg!");
5876 // Already added the first reg.
5878 for (; NumRegs; --NumRegs, ++I) {
5879 assert(I != RC->end() && "Ran out of registers to allocate!");
5884 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5888 // Otherwise, if this was a reference to an LLVM register class, create vregs
5889 // for this reference.
5890 if (const TargetRegisterClass *RC = PhysReg.second) {
5891 RegVT = *RC->vt_begin();
5892 if (OpInfo.ConstraintVT == MVT::Other)
5895 // Create the appropriate number of virtual registers.
5896 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5897 for (; NumRegs; --NumRegs)
5898 Regs.push_back(RegInfo.createVirtualRegister(RC));
5900 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5904 // Otherwise, we couldn't allocate enough registers for this.
5907 /// visitInlineAsm - Handle a call to an InlineAsm object.
5909 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5910 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5912 /// ConstraintOperands - Information about all of the constraints.
5913 SDISelAsmOperandInfoVector ConstraintOperands;
5915 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5916 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5917 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5919 bool hasMemory = false;
5921 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5922 unsigned ResNo = 0; // ResNo - The result number of the next output.
5923 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5924 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5925 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5927 MVT OpVT = MVT::Other;
5929 // Compute the value type for each operand.
5930 switch (OpInfo.Type) {
5931 case InlineAsm::isOutput:
5932 // Indirect outputs just consume an argument.
5933 if (OpInfo.isIndirect) {
5934 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5938 // The return value of the call is this value. As such, there is no
5939 // corresponding argument.
5940 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5941 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5942 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
5943 STy->getElementType(ResNo));
5945 assert(ResNo == 0 && "Asm only has one result!");
5946 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
5950 case InlineAsm::isInput:
5951 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5953 case InlineAsm::isClobber:
5958 // If this is an input or an indirect output, process the call argument.
5959 // BasicBlocks are labels, currently appearing only in asm's.
5960 if (OpInfo.CallOperandVal) {
5961 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5962 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5964 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5967 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
5968 DAG.getDataLayout()).getSimpleVT();
5971 OpInfo.ConstraintVT = OpVT;
5973 // Indirect operand accesses access memory.
5974 if (OpInfo.isIndirect)
5977 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5978 TargetLowering::ConstraintType
5979 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5980 if (CType == TargetLowering::C_Memory) {
5988 SDValue Chain, Flag;
5990 // We won't need to flush pending loads if this asm doesn't touch
5991 // memory and is nonvolatile.
5992 if (hasMemory || IA->hasSideEffects())
5995 Chain = DAG.getRoot();
5997 // Second pass over the constraints: compute which constraint option to use
5998 // and assign registers to constraints that want a specific physreg.
5999 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6000 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6002 // If this is an output operand with a matching input operand, look up the
6003 // matching input. If their types mismatch, e.g. one is an integer, the
6004 // other is floating point, or their sizes are different, flag it as an
6006 if (OpInfo.hasMatchingInput()) {
6007 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6009 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6010 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6011 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6012 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6013 OpInfo.ConstraintVT);
6014 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6015 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6016 Input.ConstraintVT);
6017 if ((OpInfo.ConstraintVT.isInteger() !=
6018 Input.ConstraintVT.isInteger()) ||
6019 (MatchRC.second != InputRC.second)) {
6020 report_fatal_error("Unsupported asm: input constraint"
6021 " with a matching output constraint of"
6022 " incompatible type!");
6024 Input.ConstraintVT = OpInfo.ConstraintVT;
6028 // Compute the constraint code and ConstraintType to use.
6029 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6031 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6032 OpInfo.Type == InlineAsm::isClobber)
6035 // If this is a memory input, and if the operand is not indirect, do what we
6036 // need to to provide an address for the memory input.
6037 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6038 !OpInfo.isIndirect) {
6039 assert((OpInfo.isMultipleAlternative ||
6040 (OpInfo.Type == InlineAsm::isInput)) &&
6041 "Can only indirectify direct input operands!");
6043 // Memory operands really want the address of the value. If we don't have
6044 // an indirect input, put it in the constpool if we can, otherwise spill
6045 // it to a stack slot.
6046 // TODO: This isn't quite right. We need to handle these according to
6047 // the addressing mode that the constraint wants. Also, this may take
6048 // an additional register for the computation and we don't want that
6051 // If the operand is a float, integer, or vector constant, spill to a
6052 // constant pool entry to get its address.
6053 const Value *OpVal = OpInfo.CallOperandVal;
6054 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6055 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6056 OpInfo.CallOperand = DAG.getConstantPool(
6057 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6059 // Otherwise, create a stack slot and emit a store to it before the
6061 Type *Ty = OpVal->getType();
6062 auto &DL = DAG.getDataLayout();
6063 uint64_t TySize = DL.getTypeAllocSize(Ty);
6064 unsigned Align = DL.getPrefTypeAlignment(Ty);
6065 MachineFunction &MF = DAG.getMachineFunction();
6066 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6068 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6069 Chain = DAG.getStore(Chain, getCurSDLoc(),
6070 OpInfo.CallOperand, StackSlot,
6071 MachinePointerInfo::getFixedStack(SSFI),
6073 OpInfo.CallOperand = StackSlot;
6076 // There is no longer a Value* corresponding to this operand.
6077 OpInfo.CallOperandVal = nullptr;
6079 // It is now an indirect operand.
6080 OpInfo.isIndirect = true;
6083 // If this constraint is for a specific register, allocate it before
6085 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6086 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6089 // Second pass - Loop over all of the operands, assigning virtual or physregs
6090 // to register class operands.
6091 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6092 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6094 // C_Register operands have already been allocated, Other/Memory don't need
6096 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6097 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6100 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6101 std::vector<SDValue> AsmNodeOperands;
6102 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6103 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6104 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6106 // If we have a !srcloc metadata node associated with it, we want to attach
6107 // this to the ultimately generated inline asm machineinstr. To do this, we
6108 // pass in the third operand as this (potentially null) inline asm MDNode.
6109 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6110 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6112 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6113 // bits as operand 3.
6114 unsigned ExtraInfo = 0;
6115 if (IA->hasSideEffects())
6116 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6117 if (IA->isAlignStack())
6118 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6119 // Set the asm dialect.
6120 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6122 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6123 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6124 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6126 // Compute the constraint code and ConstraintType to use.
6127 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6129 // Ideally, we would only check against memory constraints. However, the
6130 // meaning of an other constraint can be target-specific and we can't easily
6131 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6132 // for other constriants as well.
6133 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6134 OpInfo.ConstraintType == TargetLowering::C_Other) {
6135 if (OpInfo.Type == InlineAsm::isInput)
6136 ExtraInfo |= InlineAsm::Extra_MayLoad;
6137 else if (OpInfo.Type == InlineAsm::isOutput)
6138 ExtraInfo |= InlineAsm::Extra_MayStore;
6139 else if (OpInfo.Type == InlineAsm::isClobber)
6140 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6144 AsmNodeOperands.push_back(DAG.getTargetConstant(
6145 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6147 // Loop over all of the inputs, copying the operand values into the
6148 // appropriate registers and processing the output regs.
6149 RegsForValue RetValRegs;
6151 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6152 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6154 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6155 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6157 switch (OpInfo.Type) {
6158 case InlineAsm::isOutput: {
6159 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6160 OpInfo.ConstraintType != TargetLowering::C_Register) {
6161 // Memory output, or 'other' output (e.g. 'X' constraint).
6162 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6164 unsigned ConstraintID =
6165 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6166 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6167 "Failed to convert memory constraint code to constraint id.");
6169 // Add information to the INLINEASM node to know about this output.
6170 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6171 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6172 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6174 AsmNodeOperands.push_back(OpInfo.CallOperand);
6178 // Otherwise, this is a register or register class output.
6180 // Copy the output from the appropriate register. Find a register that
6182 if (OpInfo.AssignedRegs.Regs.empty()) {
6183 LLVMContext &Ctx = *DAG.getContext();
6184 Ctx.emitError(CS.getInstruction(),
6185 "couldn't allocate output register for constraint '" +
6186 Twine(OpInfo.ConstraintCode) + "'");
6190 // If this is an indirect operand, store through the pointer after the
6192 if (OpInfo.isIndirect) {
6193 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6194 OpInfo.CallOperandVal));
6196 // This is the result value of the call.
6197 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6198 // Concatenate this output onto the outputs list.
6199 RetValRegs.append(OpInfo.AssignedRegs);
6202 // Add information to the INLINEASM node to know that this register is
6205 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6206 ? InlineAsm::Kind_RegDefEarlyClobber
6207 : InlineAsm::Kind_RegDef,
6208 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6211 case InlineAsm::isInput: {
6212 SDValue InOperandVal = OpInfo.CallOperand;
6214 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6215 // If this is required to match an output register we have already set,
6216 // just use its register.
6217 unsigned OperandNo = OpInfo.getMatchedOperand();
6219 // Scan until we find the definition we already emitted of this operand.
6220 // When we find it, create a RegsForValue operand.
6221 unsigned CurOp = InlineAsm::Op_FirstOperand;
6222 for (; OperandNo; --OperandNo) {
6223 // Advance to the next operand.
6225 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6226 assert((InlineAsm::isRegDefKind(OpFlag) ||
6227 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6228 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6229 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6233 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6234 if (InlineAsm::isRegDefKind(OpFlag) ||
6235 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6236 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6237 if (OpInfo.isIndirect) {
6238 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6239 LLVMContext &Ctx = *DAG.getContext();
6240 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6241 " don't know how to handle tied "
6242 "indirect register inputs");
6246 RegsForValue MatchedRegs;
6247 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6248 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6249 MatchedRegs.RegVTs.push_back(RegVT);
6250 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6251 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6253 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6254 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6256 LLVMContext &Ctx = *DAG.getContext();
6257 Ctx.emitError(CS.getInstruction(),
6258 "inline asm error: This value"
6259 " type register class is not natively supported!");
6263 SDLoc dl = getCurSDLoc();
6264 // Use the produced MatchedRegs object to
6265 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6266 Chain, &Flag, CS.getInstruction());
6267 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6268 true, OpInfo.getMatchedOperand(), dl,
6269 DAG, AsmNodeOperands);
6273 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6274 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6275 "Unexpected number of operands");
6276 // Add information to the INLINEASM node to know about this input.
6277 // See InlineAsm.h isUseOperandTiedToDef.
6278 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6279 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6280 OpInfo.getMatchedOperand());
6281 AsmNodeOperands.push_back(DAG.getTargetConstant(
6282 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6283 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6287 // Treat indirect 'X' constraint as memory.
6288 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6290 OpInfo.ConstraintType = TargetLowering::C_Memory;
6292 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6293 std::vector<SDValue> Ops;
6294 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6297 LLVMContext &Ctx = *DAG.getContext();
6298 Ctx.emitError(CS.getInstruction(),
6299 "invalid operand for inline asm constraint '" +
6300 Twine(OpInfo.ConstraintCode) + "'");
6304 // Add information to the INLINEASM node to know about this input.
6305 unsigned ResOpType =
6306 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6307 AsmNodeOperands.push_back(DAG.getTargetConstant(
6308 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6309 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6313 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6314 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6315 assert(InOperandVal.getValueType() ==
6316 TLI.getPointerTy(DAG.getDataLayout()) &&
6317 "Memory operands expect pointer values");
6319 unsigned ConstraintID =
6320 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6321 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6322 "Failed to convert memory constraint code to constraint id.");
6324 // Add information to the INLINEASM node to know about this input.
6325 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6326 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6327 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6330 AsmNodeOperands.push_back(InOperandVal);
6334 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6335 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6336 "Unknown constraint type!");
6338 // TODO: Support this.
6339 if (OpInfo.isIndirect) {
6340 LLVMContext &Ctx = *DAG.getContext();
6341 Ctx.emitError(CS.getInstruction(),
6342 "Don't know how to handle indirect register inputs yet "
6343 "for constraint '" +
6344 Twine(OpInfo.ConstraintCode) + "'");
6348 // Copy the input into the appropriate registers.
6349 if (OpInfo.AssignedRegs.Regs.empty()) {
6350 LLVMContext &Ctx = *DAG.getContext();
6351 Ctx.emitError(CS.getInstruction(),
6352 "couldn't allocate input reg for constraint '" +
6353 Twine(OpInfo.ConstraintCode) + "'");
6357 SDLoc dl = getCurSDLoc();
6359 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6360 Chain, &Flag, CS.getInstruction());
6362 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6363 dl, DAG, AsmNodeOperands);
6366 case InlineAsm::isClobber: {
6367 // Add the clobbered value to the operand list, so that the register
6368 // allocator is aware that the physreg got clobbered.
6369 if (!OpInfo.AssignedRegs.Regs.empty())
6370 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6371 false, 0, getCurSDLoc(), DAG,
6378 // Finish up input operands. Set the input chain and add the flag last.
6379 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6380 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6382 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6383 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6384 Flag = Chain.getValue(1);
6386 // If this asm returns a register value, copy the result from that register
6387 // and set it as the value of the call.
6388 if (!RetValRegs.Regs.empty()) {
6389 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6390 Chain, &Flag, CS.getInstruction());
6392 // FIXME: Why don't we do this for inline asms with MRVs?
6393 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6394 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6396 // If any of the results of the inline asm is a vector, it may have the
6397 // wrong width/num elts. This can happen for register classes that can
6398 // contain multiple different value types. The preg or vreg allocated may
6399 // not have the same VT as was expected. Convert it to the right type
6400 // with bit_convert.
6401 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6402 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6405 } else if (ResultType != Val.getValueType() &&
6406 ResultType.isInteger() && Val.getValueType().isInteger()) {
6407 // If a result value was tied to an input value, the computed result may
6408 // have a wider width than the expected result. Extract the relevant
6410 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6413 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6416 setValue(CS.getInstruction(), Val);
6417 // Don't need to use this as a chain in this case.
6418 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6422 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6424 // Process indirect outputs, first output all of the flagged copies out of
6426 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6427 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6428 const Value *Ptr = IndirectStoresToEmit[i].second;
6429 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6431 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6434 // Emit the non-flagged stores from the physregs.
6435 SmallVector<SDValue, 8> OutChains;
6436 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6437 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6438 StoresToEmit[i].first,
6439 getValue(StoresToEmit[i].second),
6440 MachinePointerInfo(StoresToEmit[i].second),
6442 OutChains.push_back(Val);
6445 if (!OutChains.empty())
6446 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6451 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6452 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6453 MVT::Other, getRoot(),
6454 getValue(I.getArgOperand(0)),
6455 DAG.getSrcValue(I.getArgOperand(0))));
6458 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6459 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6460 const DataLayout &DL = DAG.getDataLayout();
6461 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6462 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6463 DAG.getSrcValue(I.getOperand(0)),
6464 DL.getABITypeAlignment(I.getType()));
6466 DAG.setRoot(V.getValue(1));
6469 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6470 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6471 MVT::Other, getRoot(),
6472 getValue(I.getArgOperand(0)),
6473 DAG.getSrcValue(I.getArgOperand(0))));
6476 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6477 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6478 MVT::Other, getRoot(),
6479 getValue(I.getArgOperand(0)),
6480 getValue(I.getArgOperand(1)),
6481 DAG.getSrcValue(I.getArgOperand(0)),
6482 DAG.getSrcValue(I.getArgOperand(1))));
6485 /// \brief Lower an argument list according to the target calling convention.
6487 /// \return A tuple of <return-value, token-chain>
6489 /// This is a helper for lowering intrinsics that follow a target calling
6490 /// convention or require stack pointer adjustment. Only a subset of the
6491 /// intrinsic's operands need to participate in the calling convention.
6492 std::pair<SDValue, SDValue>
6493 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6494 unsigned NumArgs, SDValue Callee,
6496 MachineBasicBlock *LandingPad,
6497 bool IsPatchPoint) {
6498 TargetLowering::ArgListTy Args;
6499 Args.reserve(NumArgs);
6501 // Populate the argument list.
6502 // Attributes for args start at offset 1, after the return attribute.
6503 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6504 ArgI != ArgE; ++ArgI) {
6505 const Value *V = CS->getOperand(ArgI);
6507 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6509 TargetLowering::ArgListEntry Entry;
6510 Entry.Node = getValue(V);
6511 Entry.Ty = V->getType();
6512 Entry.setAttributes(&CS, AttrI);
6513 Args.push_back(Entry);
6516 TargetLowering::CallLoweringInfo CLI(DAG);
6517 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6518 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6519 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6521 return lowerInvokable(CLI, LandingPad);
6524 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6525 /// or patchpoint target node's operand list.
6527 /// Constants are converted to TargetConstants purely as an optimization to
6528 /// avoid constant materialization and register allocation.
6530 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6531 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6532 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6533 /// address materialization and register allocation, but may also be required
6534 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6535 /// alloca in the entry block, then the runtime may assume that the alloca's
6536 /// StackMap location can be read immediately after compilation and that the
6537 /// location is valid at any point during execution (this is similar to the
6538 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6539 /// only available in a register, then the runtime would need to trap when
6540 /// execution reaches the StackMap in order to read the alloca's location.
6541 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6542 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6543 SelectionDAGBuilder &Builder) {
6544 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6545 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6548 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6550 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6551 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6552 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6553 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6554 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6556 Ops.push_back(OpVal);
6560 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6561 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6562 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6563 // [live variables...])
6565 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6567 SDValue Chain, InFlag, Callee, NullPtr;
6568 SmallVector<SDValue, 32> Ops;
6570 SDLoc DL = getCurSDLoc();
6571 Callee = getValue(CI.getCalledValue());
6572 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6574 // The stackmap intrinsic only records the live variables (the arguemnts
6575 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6576 // intrinsic, this won't be lowered to a function call. This means we don't
6577 // have to worry about calling conventions and target specific lowering code.
6578 // Instead we perform the call lowering right here.
6580 // chain, flag = CALLSEQ_START(chain, 0)
6581 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6582 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6584 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6585 InFlag = Chain.getValue(1);
6587 // Add the <id> and <numBytes> constants.
6588 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6589 Ops.push_back(DAG.getTargetConstant(
6590 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6591 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6592 Ops.push_back(DAG.getTargetConstant(
6593 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6596 // Push live variables for the stack map.
6597 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6599 // We are not pushing any register mask info here on the operands list,
6600 // because the stackmap doesn't clobber anything.
6602 // Push the chain and the glue flag.
6603 Ops.push_back(Chain);
6604 Ops.push_back(InFlag);
6606 // Create the STACKMAP node.
6607 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6608 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6609 Chain = SDValue(SM, 0);
6610 InFlag = Chain.getValue(1);
6612 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6614 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6616 // Set the root to the target-lowered call chain.
6619 // Inform the Frame Information that we have a stackmap in this function.
6620 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6623 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6624 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6625 MachineBasicBlock *LandingPad) {
6626 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6631 // [live variables...])
6633 CallingConv::ID CC = CS.getCallingConv();
6634 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6635 bool HasDef = !CS->getType()->isVoidTy();
6636 SDLoc dl = getCurSDLoc();
6637 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6639 // Handle immediate and symbolic callees.
6640 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6641 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6643 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6644 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6645 SDLoc(SymbolicCallee),
6646 SymbolicCallee->getValueType(0));
6648 // Get the real number of arguments participating in the call <numArgs>
6649 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6650 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6652 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6653 // Intrinsics include all meta-operands up to but not including CC.
6654 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6655 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6656 "Not enough arguments provided to the patchpoint intrinsic");
6658 // For AnyRegCC the arguments are lowered later on manually.
6659 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6661 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6662 std::pair<SDValue, SDValue> Result =
6663 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6666 SDNode *CallEnd = Result.second.getNode();
6667 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6668 CallEnd = CallEnd->getOperand(0).getNode();
6670 /// Get a call instruction from the call sequence chain.
6671 /// Tail calls are not allowed.
6672 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6673 "Expected a callseq node.");
6674 SDNode *Call = CallEnd->getOperand(0).getNode();
6675 bool HasGlue = Call->getGluedNode();
6677 // Replace the target specific call node with the patchable intrinsic.
6678 SmallVector<SDValue, 8> Ops;
6680 // Add the <id> and <numBytes> constants.
6681 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6682 Ops.push_back(DAG.getTargetConstant(
6683 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6684 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6685 Ops.push_back(DAG.getTargetConstant(
6686 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6690 Ops.push_back(Callee);
6692 // Adjust <numArgs> to account for any arguments that have been passed on the
6694 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6695 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6696 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6697 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6699 // Add the calling convention
6700 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6702 // Add the arguments we omitted previously. The register allocator should
6703 // place these in any free register.
6705 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6706 Ops.push_back(getValue(CS.getArgument(i)));
6708 // Push the arguments from the call instruction up to the register mask.
6709 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6710 Ops.append(Call->op_begin() + 2, e);
6712 // Push live variables for the stack map.
6713 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6715 // Push the register mask info.
6717 Ops.push_back(*(Call->op_end()-2));
6719 Ops.push_back(*(Call->op_end()-1));
6721 // Push the chain (this is originally the first operand of the call, but
6722 // becomes now the last or second to last operand).
6723 Ops.push_back(*(Call->op_begin()));
6725 // Push the glue flag (last operand).
6727 Ops.push_back(*(Call->op_end()-1));
6730 if (IsAnyRegCC && HasDef) {
6731 // Create the return types based on the intrinsic definition
6732 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6733 SmallVector<EVT, 3> ValueVTs;
6734 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6735 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6737 // There is always a chain and a glue type at the end
6738 ValueVTs.push_back(MVT::Other);
6739 ValueVTs.push_back(MVT::Glue);
6740 NodeTys = DAG.getVTList(ValueVTs);
6742 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6744 // Replace the target specific call node with a PATCHPOINT node.
6745 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6748 // Update the NodeMap.
6751 setValue(CS.getInstruction(), SDValue(MN, 0));
6753 setValue(CS.getInstruction(), Result.first);
6756 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6757 // call sequence. Furthermore the location of the chain and glue can change
6758 // when the AnyReg calling convention is used and the intrinsic returns a
6760 if (IsAnyRegCC && HasDef) {
6761 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6762 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6763 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6765 DAG.ReplaceAllUsesWith(Call, MN);
6766 DAG.DeleteNode(Call);
6768 // Inform the Frame Information that we have a patchpoint in this function.
6769 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6772 /// Returns an AttributeSet representing the attributes applied to the return
6773 /// value of the given call.
6774 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6775 SmallVector<Attribute::AttrKind, 2> Attrs;
6777 Attrs.push_back(Attribute::SExt);
6779 Attrs.push_back(Attribute::ZExt);
6781 Attrs.push_back(Attribute::InReg);
6783 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6787 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6788 /// implementation, which just calls LowerCall.
6789 /// FIXME: When all targets are
6790 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6791 std::pair<SDValue, SDValue>
6792 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6793 // Handle the incoming return values from the call.
6795 Type *OrigRetTy = CLI.RetTy;
6796 SmallVector<EVT, 4> RetTys;
6797 SmallVector<uint64_t, 4> Offsets;
6798 auto &DL = CLI.DAG.getDataLayout();
6799 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6801 SmallVector<ISD::OutputArg, 4> Outs;
6802 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6804 bool CanLowerReturn =
6805 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6806 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6808 SDValue DemoteStackSlot;
6809 int DemoteStackIdx = -100;
6810 if (!CanLowerReturn) {
6811 // FIXME: equivalent assert?
6812 // assert(!CS.hasInAllocaArgument() &&
6813 // "sret demotion is incompatible with inalloca");
6814 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6815 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6816 MachineFunction &MF = CLI.DAG.getMachineFunction();
6817 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6818 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6820 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6822 Entry.Node = DemoteStackSlot;
6823 Entry.Ty = StackSlotPtrType;
6824 Entry.isSExt = false;
6825 Entry.isZExt = false;
6826 Entry.isInReg = false;
6827 Entry.isSRet = true;
6828 Entry.isNest = false;
6829 Entry.isByVal = false;
6830 Entry.isReturned = false;
6831 Entry.Alignment = Align;
6832 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6833 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6835 // sret demotion isn't compatible with tail-calls, since the sret argument
6836 // points into the callers stack frame.
6837 CLI.IsTailCall = false;
6839 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6841 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6842 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6843 for (unsigned i = 0; i != NumRegs; ++i) {
6844 ISD::InputArg MyFlags;
6845 MyFlags.VT = RegisterVT;
6847 MyFlags.Used = CLI.IsReturnValueUsed;
6849 MyFlags.Flags.setSExt();
6851 MyFlags.Flags.setZExt();
6853 MyFlags.Flags.setInReg();
6854 CLI.Ins.push_back(MyFlags);
6859 // Handle all of the outgoing arguments.
6861 CLI.OutVals.clear();
6862 ArgListTy &Args = CLI.getArgs();
6863 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6864 SmallVector<EVT, 4> ValueVTs;
6865 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6866 Type *FinalType = Args[i].Ty;
6867 if (Args[i].isByVal)
6868 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6869 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6870 FinalType, CLI.CallConv, CLI.IsVarArg);
6871 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6873 EVT VT = ValueVTs[Value];
6874 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6875 SDValue Op = SDValue(Args[i].Node.getNode(),
6876 Args[i].Node.getResNo() + Value);
6877 ISD::ArgFlagsTy Flags;
6878 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6884 if (Args[i].isInReg)
6888 if (Args[i].isByVal)
6890 if (Args[i].isInAlloca) {
6891 Flags.setInAlloca();
6892 // Set the byval flag for CCAssignFn callbacks that don't know about
6893 // inalloca. This way we can know how many bytes we should've allocated
6894 // and how many bytes a callee cleanup function will pop. If we port
6895 // inalloca to more targets, we'll have to add custom inalloca handling
6896 // in the various CC lowering callbacks.
6899 if (Args[i].isByVal || Args[i].isInAlloca) {
6900 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6901 Type *ElementTy = Ty->getElementType();
6902 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6903 // For ByVal, alignment should come from FE. BE will guess if this
6904 // info is not there but there are cases it cannot get right.
6905 unsigned FrameAlign;
6906 if (Args[i].Alignment)
6907 FrameAlign = Args[i].Alignment;
6909 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6910 Flags.setByValAlign(FrameAlign);
6915 Flags.setInConsecutiveRegs();
6916 Flags.setOrigAlign(OriginalAlignment);
6918 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6919 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6920 SmallVector<SDValue, 4> Parts(NumParts);
6921 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6924 ExtendKind = ISD::SIGN_EXTEND;
6925 else if (Args[i].isZExt)
6926 ExtendKind = ISD::ZERO_EXTEND;
6928 // Conservatively only handle 'returned' on non-vectors for now
6929 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6930 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6931 "unexpected use of 'returned'");
6932 // Before passing 'returned' to the target lowering code, ensure that
6933 // either the register MVT and the actual EVT are the same size or that
6934 // the return value and argument are extended in the same way; in these
6935 // cases it's safe to pass the argument register value unchanged as the
6936 // return register value (although it's at the target's option whether
6938 // TODO: allow code generation to take advantage of partially preserved
6939 // registers rather than clobbering the entire register when the
6940 // parameter extension method is not compatible with the return
6942 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6943 (ExtendKind != ISD::ANY_EXTEND &&
6944 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6945 Flags.setReturned();
6948 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6949 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6951 for (unsigned j = 0; j != NumParts; ++j) {
6952 // if it isn't first piece, alignment must be 1
6953 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6954 i < CLI.NumFixedArgs,
6955 i, j*Parts[j].getValueType().getStoreSize());
6956 if (NumParts > 1 && j == 0)
6957 MyFlags.Flags.setSplit();
6959 MyFlags.Flags.setOrigAlign(1);
6961 CLI.Outs.push_back(MyFlags);
6962 CLI.OutVals.push_back(Parts[j]);
6965 if (NeedsRegBlock && Value == NumValues - 1)
6966 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6970 SmallVector<SDValue, 4> InVals;
6971 CLI.Chain = LowerCall(CLI, InVals);
6973 // Verify that the target's LowerCall behaved as expected.
6974 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6975 "LowerCall didn't return a valid chain!");
6976 assert((!CLI.IsTailCall || InVals.empty()) &&
6977 "LowerCall emitted a return value for a tail call!");
6978 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6979 "LowerCall didn't emit the correct number of values!");
6981 // For a tail call, the return value is merely live-out and there aren't
6982 // any nodes in the DAG representing it. Return a special value to
6983 // indicate that a tail call has been emitted and no more Instructions
6984 // should be processed in the current block.
6985 if (CLI.IsTailCall) {
6986 CLI.DAG.setRoot(CLI.Chain);
6987 return std::make_pair(SDValue(), SDValue());
6990 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6991 assert(InVals[i].getNode() &&
6992 "LowerCall emitted a null value!");
6993 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6994 "LowerCall emitted a value with the wrong type!");
6997 SmallVector<SDValue, 4> ReturnValues;
6998 if (!CanLowerReturn) {
6999 // The instruction result is the result of loading from the
7000 // hidden sret parameter.
7001 SmallVector<EVT, 1> PVTs;
7002 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7004 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7005 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7006 EVT PtrVT = PVTs[0];
7008 unsigned NumValues = RetTys.size();
7009 ReturnValues.resize(NumValues);
7010 SmallVector<SDValue, 4> Chains(NumValues);
7012 for (unsigned i = 0; i < NumValues; ++i) {
7013 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7014 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7016 SDValue L = CLI.DAG.getLoad(
7017 RetTys[i], CLI.DL, CLI.Chain, Add,
7018 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7020 ReturnValues[i] = L;
7021 Chains[i] = L.getValue(1);
7024 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7026 // Collect the legal value parts into potentially illegal values
7027 // that correspond to the original function's return values.
7028 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7030 AssertOp = ISD::AssertSext;
7031 else if (CLI.RetZExt)
7032 AssertOp = ISD::AssertZext;
7033 unsigned CurReg = 0;
7034 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7036 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7037 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7039 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7040 NumRegs, RegisterVT, VT, nullptr,
7045 // For a function returning void, there is no return value. We can't create
7046 // such a node, so we just return a null return value in that case. In
7047 // that case, nothing will actually look at the value.
7048 if (ReturnValues.empty())
7049 return std::make_pair(SDValue(), CLI.Chain);
7052 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7053 CLI.DAG.getVTList(RetTys), ReturnValues);
7054 return std::make_pair(Res, CLI.Chain);
7057 void TargetLowering::LowerOperationWrapper(SDNode *N,
7058 SmallVectorImpl<SDValue> &Results,
7059 SelectionDAG &DAG) const {
7060 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7062 Results.push_back(Res);
7065 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7066 llvm_unreachable("LowerOperation not implemented for this target!");
7070 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7071 SDValue Op = getNonRegisterValue(V);
7072 assert((Op.getOpcode() != ISD::CopyFromReg ||
7073 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7074 "Copy from a reg to the same reg!");
7075 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7078 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7080 SDValue Chain = DAG.getEntryNode();
7082 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7083 FuncInfo.PreferredExtendType.end())
7085 : FuncInfo.PreferredExtendType[V];
7086 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7087 PendingExports.push_back(Chain);
7090 #include "llvm/CodeGen/SelectionDAGISel.h"
7092 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7093 /// entry block, return true. This includes arguments used by switches, since
7094 /// the switch may expand into multiple basic blocks.
7095 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7096 // With FastISel active, we may be splitting blocks, so force creation
7097 // of virtual registers for all non-dead arguments.
7099 return A->use_empty();
7101 const BasicBlock *Entry = A->getParent()->begin();
7102 for (const User *U : A->users())
7103 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7104 return false; // Use not in entry block.
7109 void SelectionDAGISel::LowerArguments(const Function &F) {
7110 SelectionDAG &DAG = SDB->DAG;
7111 SDLoc dl = SDB->getCurSDLoc();
7112 const DataLayout &DL = DAG.getDataLayout();
7113 SmallVector<ISD::InputArg, 16> Ins;
7115 if (!FuncInfo->CanLowerReturn) {
7116 // Put in an sret pointer parameter before all the other parameters.
7117 SmallVector<EVT, 1> ValueVTs;
7118 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7119 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7121 // NOTE: Assuming that a pointer will never break down to more than one VT
7123 ISD::ArgFlagsTy Flags;
7125 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7126 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7127 ISD::InputArg::NoArgIndex, 0);
7128 Ins.push_back(RetArg);
7131 // Set up the incoming argument description vector.
7133 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7134 I != E; ++I, ++Idx) {
7135 SmallVector<EVT, 4> ValueVTs;
7136 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7137 bool isArgValueUsed = !I->use_empty();
7138 unsigned PartBase = 0;
7139 Type *FinalType = I->getType();
7140 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7141 FinalType = cast<PointerType>(FinalType)->getElementType();
7142 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7143 FinalType, F.getCallingConv(), F.isVarArg());
7144 for (unsigned Value = 0, NumValues = ValueVTs.size();
7145 Value != NumValues; ++Value) {
7146 EVT VT = ValueVTs[Value];
7147 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7148 ISD::ArgFlagsTy Flags;
7149 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7151 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7153 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7155 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7157 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7159 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7161 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7162 Flags.setInAlloca();
7163 // Set the byval flag for CCAssignFn callbacks that don't know about
7164 // inalloca. This way we can know how many bytes we should've allocated
7165 // and how many bytes a callee cleanup function will pop. If we port
7166 // inalloca to more targets, we'll have to add custom inalloca handling
7167 // in the various CC lowering callbacks.
7170 if (Flags.isByVal() || Flags.isInAlloca()) {
7171 PointerType *Ty = cast<PointerType>(I->getType());
7172 Type *ElementTy = Ty->getElementType();
7173 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7174 // For ByVal, alignment should be passed from FE. BE will guess if
7175 // this info is not there but there are cases it cannot get right.
7176 unsigned FrameAlign;
7177 if (F.getParamAlignment(Idx))
7178 FrameAlign = F.getParamAlignment(Idx);
7180 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7181 Flags.setByValAlign(FrameAlign);
7183 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7186 Flags.setInConsecutiveRegs();
7187 Flags.setOrigAlign(OriginalAlignment);
7189 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7190 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7191 for (unsigned i = 0; i != NumRegs; ++i) {
7192 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7193 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7194 if (NumRegs > 1 && i == 0)
7195 MyFlags.Flags.setSplit();
7196 // if it isn't first piece, alignment must be 1
7198 MyFlags.Flags.setOrigAlign(1);
7199 Ins.push_back(MyFlags);
7201 if (NeedsRegBlock && Value == NumValues - 1)
7202 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7203 PartBase += VT.getStoreSize();
7207 // Call the target to set up the argument values.
7208 SmallVector<SDValue, 8> InVals;
7209 SDValue NewRoot = TLI->LowerFormalArguments(
7210 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7212 // Verify that the target's LowerFormalArguments behaved as expected.
7213 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7214 "LowerFormalArguments didn't return a valid chain!");
7215 assert(InVals.size() == Ins.size() &&
7216 "LowerFormalArguments didn't emit the correct number of values!");
7218 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7219 assert(InVals[i].getNode() &&
7220 "LowerFormalArguments emitted a null value!");
7221 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7222 "LowerFormalArguments emitted a value with the wrong type!");
7226 // Update the DAG with the new chain value resulting from argument lowering.
7227 DAG.setRoot(NewRoot);
7229 // Set up the argument values.
7232 if (!FuncInfo->CanLowerReturn) {
7233 // Create a virtual register for the sret pointer, and put in a copy
7234 // from the sret argument into it.
7235 SmallVector<EVT, 1> ValueVTs;
7236 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7237 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7238 MVT VT = ValueVTs[0].getSimpleVT();
7239 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7240 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7241 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7242 RegVT, VT, nullptr, AssertOp);
7244 MachineFunction& MF = SDB->DAG.getMachineFunction();
7245 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7246 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7247 FuncInfo->DemoteRegister = SRetReg;
7249 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7250 DAG.setRoot(NewRoot);
7252 // i indexes lowered arguments. Bump it past the hidden sret argument.
7253 // Idx indexes LLVM arguments. Don't touch it.
7257 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7259 SmallVector<SDValue, 4> ArgValues;
7260 SmallVector<EVT, 4> ValueVTs;
7261 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7262 unsigned NumValues = ValueVTs.size();
7264 // If this argument is unused then remember its value. It is used to generate
7265 // debugging information.
7266 if (I->use_empty() && NumValues) {
7267 SDB->setUnusedArgValue(I, InVals[i]);
7269 // Also remember any frame index for use in FastISel.
7270 if (FrameIndexSDNode *FI =
7271 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7272 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7275 for (unsigned Val = 0; Val != NumValues; ++Val) {
7276 EVT VT = ValueVTs[Val];
7277 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7278 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7280 if (!I->use_empty()) {
7281 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7282 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7283 AssertOp = ISD::AssertSext;
7284 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7285 AssertOp = ISD::AssertZext;
7287 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7288 NumParts, PartVT, VT,
7289 nullptr, AssertOp));
7295 // We don't need to do anything else for unused arguments.
7296 if (ArgValues.empty())
7299 // Note down frame index.
7300 if (FrameIndexSDNode *FI =
7301 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7302 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7304 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7305 SDB->getCurSDLoc());
7307 SDB->setValue(I, Res);
7308 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7309 if (LoadSDNode *LNode =
7310 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7311 if (FrameIndexSDNode *FI =
7312 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7313 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7316 // If this argument is live outside of the entry block, insert a copy from
7317 // wherever we got it to the vreg that other BB's will reference it as.
7318 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7319 // If we can, though, try to skip creating an unnecessary vreg.
7320 // FIXME: This isn't very clean... it would be nice to make this more
7321 // general. It's also subtly incompatible with the hacks FastISel
7323 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7324 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7325 FuncInfo->ValueMap[I] = Reg;
7329 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7330 FuncInfo->InitializeRegForValue(I);
7331 SDB->CopyToExportRegsIfNeeded(I);
7335 assert(i == InVals.size() && "Argument register count mismatch!");
7337 // Finally, if the target has anything special to do, allow it to do so.
7338 EmitFunctionEntryCode();
7341 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7342 /// ensure constants are generated when needed. Remember the virtual registers
7343 /// that need to be added to the Machine PHI nodes as input. We cannot just
7344 /// directly add them, because expansion might result in multiple MBB's for one
7345 /// BB. As such, the start of the BB might correspond to a different MBB than
7349 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7350 const TerminatorInst *TI = LLVMBB->getTerminator();
7352 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7354 // Check PHI nodes in successors that expect a value to be available from this
7356 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7357 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7358 if (!isa<PHINode>(SuccBB->begin())) continue;
7359 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7361 // If this terminator has multiple identical successors (common for
7362 // switches), only handle each succ once.
7363 if (!SuccsHandled.insert(SuccMBB).second)
7366 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7368 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7369 // nodes and Machine PHI nodes, but the incoming operands have not been
7371 for (BasicBlock::const_iterator I = SuccBB->begin();
7372 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7373 // Ignore dead phi's.
7374 if (PN->use_empty()) continue;
7377 if (PN->getType()->isEmptyTy())
7381 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7383 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7384 unsigned &RegOut = ConstantsOut[C];
7386 RegOut = FuncInfo.CreateRegs(C->getType());
7387 CopyValueToVirtualRegister(C, RegOut);
7391 DenseMap<const Value *, unsigned>::iterator I =
7392 FuncInfo.ValueMap.find(PHIOp);
7393 if (I != FuncInfo.ValueMap.end())
7396 assert(isa<AllocaInst>(PHIOp) &&
7397 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7398 "Didn't codegen value into a register!??");
7399 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7400 CopyValueToVirtualRegister(PHIOp, Reg);
7404 // Remember that this register needs to added to the machine PHI node as
7405 // the input for this MBB.
7406 SmallVector<EVT, 4> ValueVTs;
7407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7408 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7409 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7410 EVT VT = ValueVTs[vti];
7411 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7412 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7413 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7414 Reg += NumRegisters;
7419 ConstantsOut.clear();
7422 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7425 SelectionDAGBuilder::StackProtectorDescriptor::
7426 AddSuccessorMBB(const BasicBlock *BB,
7427 MachineBasicBlock *ParentMBB,
7429 MachineBasicBlock *SuccMBB) {
7430 // If SuccBB has not been created yet, create it.
7432 MachineFunction *MF = ParentMBB->getParent();
7433 MachineFunction::iterator BBI = ParentMBB;
7434 SuccMBB = MF->CreateMachineBasicBlock(BB);
7435 MF->insert(++BBI, SuccMBB);
7437 // Add it as a successor of ParentMBB.
7438 ParentMBB->addSuccessor(
7439 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7443 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7444 MachineFunction::iterator I = MBB;
7445 if (++I == FuncInfo.MF->end())
7450 /// During lowering new call nodes can be created (such as memset, etc.).
7451 /// Those will become new roots of the current DAG, but complications arise
7452 /// when they are tail calls. In such cases, the call lowering will update
7453 /// the root, but the builder still needs to know that a tail call has been
7454 /// lowered in order to avoid generating an additional return.
7455 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7456 // If the node is null, we do have a tail call.
7457 if (MaybeTC.getNode() != nullptr)
7458 DAG.setRoot(MaybeTC);
7463 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7464 unsigned *TotalCases, unsigned First,
7466 assert(Last >= First);
7467 assert(TotalCases[Last] >= TotalCases[First]);
7469 APInt LowCase = Clusters[First].Low->getValue();
7470 APInt HighCase = Clusters[Last].High->getValue();
7471 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7473 // FIXME: A range of consecutive cases has 100% density, but only requires one
7474 // comparison to lower. We should discriminate against such consecutive ranges
7477 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7478 uint64_t Range = Diff + 1;
7481 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7483 assert(NumCases < UINT64_MAX / 100);
7484 assert(Range >= NumCases);
7486 return NumCases * 100 >= Range * MinJumpTableDensity;
7489 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7490 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7491 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7494 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7495 unsigned First, unsigned Last,
7496 const SwitchInst *SI,
7497 MachineBasicBlock *DefaultMBB,
7498 CaseCluster &JTCluster) {
7499 assert(First <= Last);
7501 uint32_t Weight = 0;
7502 unsigned NumCmps = 0;
7503 std::vector<MachineBasicBlock*> Table;
7504 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7505 for (unsigned I = First; I <= Last; ++I) {
7506 assert(Clusters[I].Kind == CC_Range);
7507 Weight += Clusters[I].Weight;
7508 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7509 APInt Low = Clusters[I].Low->getValue();
7510 APInt High = Clusters[I].High->getValue();
7511 NumCmps += (Low == High) ? 1 : 2;
7513 // Fill the gap between this and the previous cluster.
7514 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7515 assert(PreviousHigh.slt(Low));
7516 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7517 for (uint64_t J = 0; J < Gap; J++)
7518 Table.push_back(DefaultMBB);
7520 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7521 for (uint64_t J = 0; J < ClusterSize; ++J)
7522 Table.push_back(Clusters[I].MBB);
7523 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7526 unsigned NumDests = JTWeights.size();
7527 if (isSuitableForBitTests(NumDests, NumCmps,
7528 Clusters[First].Low->getValue(),
7529 Clusters[Last].High->getValue())) {
7530 // Clusters[First..Last] should be lowered as bit tests instead.
7534 // Create the MBB that will load from and jump through the table.
7535 // Note: We create it here, but it's not inserted into the function yet.
7536 MachineFunction *CurMF = FuncInfo.MF;
7537 MachineBasicBlock *JumpTableMBB =
7538 CurMF->CreateMachineBasicBlock(SI->getParent());
7540 // Add successors. Note: use table order for determinism.
7541 SmallPtrSet<MachineBasicBlock *, 8> Done;
7542 for (MachineBasicBlock *Succ : Table) {
7543 if (Done.count(Succ))
7545 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7549 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7550 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7551 ->createJumpTableIndex(Table);
7553 // Set up the jump table info.
7554 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7555 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7556 Clusters[Last].High->getValue(), SI->getCondition(),
7558 JTCases.emplace_back(std::move(JTH), std::move(JT));
7560 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7561 JTCases.size() - 1, Weight);
7565 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7566 const SwitchInst *SI,
7567 MachineBasicBlock *DefaultMBB) {
7569 // Clusters must be non-empty, sorted, and only contain Range clusters.
7570 assert(!Clusters.empty());
7571 for (CaseCluster &C : Clusters)
7572 assert(C.Kind == CC_Range);
7573 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7574 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7577 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7578 if (!areJTsAllowed(TLI))
7581 const int64_t N = Clusters.size();
7582 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7584 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7585 SmallVector<unsigned, 8> TotalCases(N);
7587 for (unsigned i = 0; i < N; ++i) {
7588 APInt Hi = Clusters[i].High->getValue();
7589 APInt Lo = Clusters[i].Low->getValue();
7590 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7592 TotalCases[i] += TotalCases[i - 1];
7595 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7596 // Cheap case: the whole range might be suitable for jump table.
7597 CaseCluster JTCluster;
7598 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7599 Clusters[0] = JTCluster;
7605 // The algorithm below is not suitable for -O0.
7606 if (TM.getOptLevel() == CodeGenOpt::None)
7609 // Split Clusters into minimum number of dense partitions. The algorithm uses
7610 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7611 // for the Case Statement'" (1994), but builds the MinPartitions array in
7612 // reverse order to make it easier to reconstruct the partitions in ascending
7613 // order. In the choice between two optimal partitionings, it picks the one
7614 // which yields more jump tables.
7616 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7617 SmallVector<unsigned, 8> MinPartitions(N);
7618 // LastElement[i] is the last element of the partition starting at i.
7619 SmallVector<unsigned, 8> LastElement(N);
7620 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7621 SmallVector<unsigned, 8> NumTables(N);
7623 // Base case: There is only one way to partition Clusters[N-1].
7624 MinPartitions[N - 1] = 1;
7625 LastElement[N - 1] = N - 1;
7626 assert(MinJumpTableSize > 1);
7627 NumTables[N - 1] = 0;
7629 // Note: loop indexes are signed to avoid underflow.
7630 for (int64_t i = N - 2; i >= 0; i--) {
7631 // Find optimal partitioning of Clusters[i..N-1].
7632 // Baseline: Put Clusters[i] into a partition on its own.
7633 MinPartitions[i] = MinPartitions[i + 1] + 1;
7635 NumTables[i] = NumTables[i + 1];
7637 // Search for a solution that results in fewer partitions.
7638 for (int64_t j = N - 1; j > i; j--) {
7639 // Try building a partition from Clusters[i..j].
7640 if (isDense(Clusters, &TotalCases[0], i, j)) {
7641 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7642 bool IsTable = j - i + 1 >= MinJumpTableSize;
7643 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7645 // If this j leads to fewer partitions, or same number of partitions
7646 // with more lookup tables, it is a better partitioning.
7647 if (NumPartitions < MinPartitions[i] ||
7648 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7649 MinPartitions[i] = NumPartitions;
7651 NumTables[i] = Tables;
7657 // Iterate over the partitions, replacing some with jump tables in-place.
7658 unsigned DstIndex = 0;
7659 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7660 Last = LastElement[First];
7661 assert(Last >= First);
7662 assert(DstIndex <= First);
7663 unsigned NumClusters = Last - First + 1;
7665 CaseCluster JTCluster;
7666 if (NumClusters >= MinJumpTableSize &&
7667 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7668 Clusters[DstIndex++] = JTCluster;
7670 for (unsigned I = First; I <= Last; ++I)
7671 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7674 Clusters.resize(DstIndex);
7677 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7678 // FIXME: Using the pointer type doesn't seem ideal.
7679 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7680 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7684 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7687 const APInt &High) {
7688 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7689 // range of cases both require only one branch to lower. Just looking at the
7690 // number of clusters and destinations should be enough to decide whether to
7693 // To lower a range with bit tests, the range must fit the bitwidth of a
7695 if (!rangeFitsInWord(Low, High))
7698 // Decide whether it's profitable to lower this range with bit tests. Each
7699 // destination requires a bit test and branch, and there is an overall range
7700 // check branch. For a small number of clusters, separate comparisons might be
7701 // cheaper, and for many destinations, splitting the range might be better.
7702 return (NumDests == 1 && NumCmps >= 3) ||
7703 (NumDests == 2 && NumCmps >= 5) ||
7704 (NumDests == 3 && NumCmps >= 6);
7707 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7708 unsigned First, unsigned Last,
7709 const SwitchInst *SI,
7710 CaseCluster &BTCluster) {
7711 assert(First <= Last);
7715 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7716 unsigned NumCmps = 0;
7717 for (int64_t I = First; I <= Last; ++I) {
7718 assert(Clusters[I].Kind == CC_Range);
7719 Dests.set(Clusters[I].MBB->getNumber());
7720 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7722 unsigned NumDests = Dests.count();
7724 APInt Low = Clusters[First].Low->getValue();
7725 APInt High = Clusters[Last].High->getValue();
7726 assert(Low.slt(High));
7728 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7734 const int BitWidth = DAG.getTargetLoweringInfo()
7735 .getPointerTy(DAG.getDataLayout())
7737 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7739 if (Low.isNonNegative() && High.slt(BitWidth)) {
7740 // Optimize the case where all the case values fit in a
7741 // word without having to subtract minValue. In this case,
7742 // we can optimize away the subtraction.
7743 LowBound = APInt::getNullValue(Low.getBitWidth());
7747 CmpRange = High - Low;
7751 uint32_t TotalWeight = 0;
7752 for (unsigned i = First; i <= Last; ++i) {
7753 // Find the CaseBits for this destination.
7755 for (j = 0; j < CBV.size(); ++j)
7756 if (CBV[j].BB == Clusters[i].MBB)
7758 if (j == CBV.size())
7759 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7760 CaseBits *CB = &CBV[j];
7762 // Update Mask, Bits and ExtraWeight.
7763 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7764 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7765 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7766 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7767 CB->Bits += Hi - Lo + 1;
7768 CB->ExtraWeight += Clusters[i].Weight;
7769 TotalWeight += Clusters[i].Weight;
7770 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7774 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7775 // Sort by weight first, number of bits second.
7776 if (a.ExtraWeight != b.ExtraWeight)
7777 return a.ExtraWeight > b.ExtraWeight;
7778 return a.Bits > b.Bits;
7781 for (auto &CB : CBV) {
7782 MachineBasicBlock *BitTestBB =
7783 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7784 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7786 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7787 SI->getCondition(), -1U, MVT::Other, false, nullptr,
7788 nullptr, std::move(BTI));
7790 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7791 BitTestCases.size() - 1, TotalWeight);
7795 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7796 const SwitchInst *SI) {
7797 // Partition Clusters into as few subsets as possible, where each subset has a
7798 // range that fits in a machine word and has <= 3 unique destinations.
7801 // Clusters must be sorted and contain Range or JumpTable clusters.
7802 assert(!Clusters.empty());
7803 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7804 for (const CaseCluster &C : Clusters)
7805 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7806 for (unsigned i = 1; i < Clusters.size(); ++i)
7807 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7810 // The algorithm below is not suitable for -O0.
7811 if (TM.getOptLevel() == CodeGenOpt::None)
7814 // If target does not have legal shift left, do not emit bit tests at all.
7815 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7816 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7817 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7820 int BitWidth = PTy.getSizeInBits();
7821 const int64_t N = Clusters.size();
7823 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7824 SmallVector<unsigned, 8> MinPartitions(N);
7825 // LastElement[i] is the last element of the partition starting at i.
7826 SmallVector<unsigned, 8> LastElement(N);
7828 // FIXME: This might not be the best algorithm for finding bit test clusters.
7830 // Base case: There is only one way to partition Clusters[N-1].
7831 MinPartitions[N - 1] = 1;
7832 LastElement[N - 1] = N - 1;
7834 // Note: loop indexes are signed to avoid underflow.
7835 for (int64_t i = N - 2; i >= 0; --i) {
7836 // Find optimal partitioning of Clusters[i..N-1].
7837 // Baseline: Put Clusters[i] into a partition on its own.
7838 MinPartitions[i] = MinPartitions[i + 1] + 1;
7841 // Search for a solution that results in fewer partitions.
7842 // Note: the search is limited by BitWidth, reducing time complexity.
7843 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7844 // Try building a partition from Clusters[i..j].
7847 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7848 Clusters[j].High->getValue()))
7851 // Check nbr of destinations and cluster types.
7852 // FIXME: This works, but doesn't seem very efficient.
7853 bool RangesOnly = true;
7854 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7855 for (int64_t k = i; k <= j; k++) {
7856 if (Clusters[k].Kind != CC_Range) {
7860 Dests.set(Clusters[k].MBB->getNumber());
7862 if (!RangesOnly || Dests.count() > 3)
7865 // Check if it's a better partition.
7866 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7867 if (NumPartitions < MinPartitions[i]) {
7868 // Found a better partition.
7869 MinPartitions[i] = NumPartitions;
7875 // Iterate over the partitions, replacing with bit-test clusters in-place.
7876 unsigned DstIndex = 0;
7877 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7878 Last = LastElement[First];
7879 assert(First <= Last);
7880 assert(DstIndex <= First);
7882 CaseCluster BitTestCluster;
7883 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7884 Clusters[DstIndex++] = BitTestCluster;
7886 size_t NumClusters = Last - First + 1;
7887 std::memmove(&Clusters[DstIndex], &Clusters[First],
7888 sizeof(Clusters[0]) * NumClusters);
7889 DstIndex += NumClusters;
7892 Clusters.resize(DstIndex);
7895 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7896 MachineBasicBlock *SwitchMBB,
7897 MachineBasicBlock *DefaultMBB) {
7898 MachineFunction *CurMF = FuncInfo.MF;
7899 MachineBasicBlock *NextMBB = nullptr;
7900 MachineFunction::iterator BBI = W.MBB;
7901 if (++BBI != FuncInfo.MF->end())
7904 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7906 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7908 if (Size == 2 && W.MBB == SwitchMBB) {
7909 // If any two of the cases has the same destination, and if one value
7910 // is the same as the other, but has one bit unset that the other has set,
7911 // use bit manipulation to do two compares at once. For example:
7912 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7913 // TODO: This could be extended to merge any 2 cases in switches with 3
7915 // TODO: Handle cases where W.CaseBB != SwitchBB.
7916 CaseCluster &Small = *W.FirstCluster;
7917 CaseCluster &Big = *W.LastCluster;
7919 if (Small.Low == Small.High && Big.Low == Big.High &&
7920 Small.MBB == Big.MBB) {
7921 const APInt &SmallValue = Small.Low->getValue();
7922 const APInt &BigValue = Big.Low->getValue();
7924 // Check that there is only one bit different.
7925 APInt CommonBit = BigValue ^ SmallValue;
7926 if (CommonBit.isPowerOf2()) {
7927 SDValue CondLHS = getValue(Cond);
7928 EVT VT = CondLHS.getValueType();
7929 SDLoc DL = getCurSDLoc();
7931 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7932 DAG.getConstant(CommonBit, DL, VT));
7933 SDValue Cond = DAG.getSetCC(
7934 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7937 // Update successor info.
7938 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7939 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7940 addSuccessorWithWeight(
7941 SwitchMBB, DefaultMBB,
7942 // The default destination is the first successor in IR.
7943 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7946 // Insert the true branch.
7948 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7949 DAG.getBasicBlock(Small.MBB));
7950 // Insert the false branch.
7951 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7952 DAG.getBasicBlock(DefaultMBB));
7954 DAG.setRoot(BrCond);
7960 if (TM.getOptLevel() != CodeGenOpt::None) {
7961 // Order cases by weight so the most likely case will be checked first.
7962 std::sort(W.FirstCluster, W.LastCluster + 1,
7963 [](const CaseCluster &a, const CaseCluster &b) {
7964 return a.Weight > b.Weight;
7967 // Rearrange the case blocks so that the last one falls through if possible
7968 // without without changing the order of weights.
7969 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7971 if (I->Weight > W.LastCluster->Weight)
7973 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7974 std::swap(*I, *W.LastCluster);
7980 // Compute total weight.
7981 uint32_t UnhandledWeights = 0;
7982 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7983 UnhandledWeights += I->Weight;
7984 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7987 MachineBasicBlock *CurMBB = W.MBB;
7988 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7989 MachineBasicBlock *Fallthrough;
7990 if (I == W.LastCluster) {
7991 // For the last cluster, fall through to the default destination.
7992 Fallthrough = DefaultMBB;
7994 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7995 CurMF->insert(BBI, Fallthrough);
7996 // Put Cond in a virtual register to make it available from the new blocks.
7997 ExportFromCurrentBlock(Cond);
8001 case CC_JumpTable: {
8002 // FIXME: Optimize away range check based on pivot comparisons.
8003 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8004 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8006 // The jump block hasn't been inserted yet; insert it here.
8007 MachineBasicBlock *JumpMBB = JT->MBB;
8008 CurMF->insert(BBI, JumpMBB);
8009 addSuccessorWithWeight(CurMBB, Fallthrough);
8010 addSuccessorWithWeight(CurMBB, JumpMBB);
8012 // The jump table header will be inserted in our current block, do the
8013 // range check, and fall through to our fallthrough block.
8014 JTH->HeaderBB = CurMBB;
8015 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8017 // If we're in the right place, emit the jump table header right now.
8018 if (CurMBB == SwitchMBB) {
8019 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8020 JTH->Emitted = true;
8025 // FIXME: Optimize away range check based on pivot comparisons.
8026 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8028 // The bit test blocks haven't been inserted yet; insert them here.
8029 for (BitTestCase &BTC : BTB->Cases)
8030 CurMF->insert(BBI, BTC.ThisBB);
8032 // Fill in fields of the BitTestBlock.
8033 BTB->Parent = CurMBB;
8034 BTB->Default = Fallthrough;
8036 // If we're in the right place, emit the bit test header header right now.
8037 if (CurMBB ==SwitchMBB) {
8038 visitBitTestHeader(*BTB, SwitchMBB);
8039 BTB->Emitted = true;
8044 const Value *RHS, *LHS, *MHS;
8046 if (I->Low == I->High) {
8047 // Check Cond == I->Low.
8053 // Check I->Low <= Cond <= I->High.
8060 // The false weight is the sum of all unhandled cases.
8061 UnhandledWeights -= I->Weight;
8062 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8065 if (CurMBB == SwitchMBB)
8066 visitSwitchCase(CB, SwitchMBB);
8068 SwitchCases.push_back(CB);
8073 CurMBB = Fallthrough;
8077 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8078 CaseClusterIt First,
8079 CaseClusterIt Last) {
8080 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8081 if (X.Weight != CC.Weight)
8082 return X.Weight > CC.Weight;
8084 // Ties are broken by comparing the case value.
8085 return X.Low->getValue().slt(CC.Low->getValue());
8089 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8090 const SwitchWorkListItem &W,
8092 MachineBasicBlock *SwitchMBB) {
8093 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8094 "Clusters not sorted?");
8096 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8098 // Balance the tree based on branch weights to create a near-optimal (in terms
8099 // of search time given key frequency) binary search tree. See e.g. Kurt
8100 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8101 CaseClusterIt LastLeft = W.FirstCluster;
8102 CaseClusterIt FirstRight = W.LastCluster;
8103 uint32_t LeftWeight = LastLeft->Weight;
8104 uint32_t RightWeight = FirstRight->Weight;
8106 // Move LastLeft and FirstRight towards each other from opposite directions to
8107 // find a partitioning of the clusters which balances the weight on both
8108 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8109 // taken to ensure 0-weight nodes are distributed evenly.
8111 while (LastLeft + 1 < FirstRight) {
8112 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8113 LeftWeight += (++LastLeft)->Weight;
8115 RightWeight += (--FirstRight)->Weight;
8120 // Our binary search tree differs from a typical BST in that ours can have up
8121 // to three values in each leaf. The pivot selection above doesn't take that
8122 // into account, which means the tree might require more nodes and be less
8123 // efficient. We compensate for this here.
8125 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8126 unsigned NumRight = W.LastCluster - FirstRight + 1;
8128 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8129 // If one side has less than 3 clusters, and the other has more than 3,
8130 // consider taking a cluster from the other side.
8132 if (NumLeft < NumRight) {
8133 // Consider moving the first cluster on the right to the left side.
8134 CaseCluster &CC = *FirstRight;
8135 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8136 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8137 if (LeftSideRank <= RightSideRank) {
8138 // Moving the cluster to the left does not demote it.
8144 assert(NumRight < NumLeft);
8145 // Consider moving the last element on the left to the right side.
8146 CaseCluster &CC = *LastLeft;
8147 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8148 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8149 if (RightSideRank <= LeftSideRank) {
8150 // Moving the cluster to the right does not demot it.
8160 assert(LastLeft + 1 == FirstRight);
8161 assert(LastLeft >= W.FirstCluster);
8162 assert(FirstRight <= W.LastCluster);
8164 // Use the first element on the right as pivot since we will make less-than
8165 // comparisons against it.
8166 CaseClusterIt PivotCluster = FirstRight;
8167 assert(PivotCluster > W.FirstCluster);
8168 assert(PivotCluster <= W.LastCluster);
8170 CaseClusterIt FirstLeft = W.FirstCluster;
8171 CaseClusterIt LastRight = W.LastCluster;
8173 const ConstantInt *Pivot = PivotCluster->Low;
8175 // New blocks will be inserted immediately after the current one.
8176 MachineFunction::iterator BBI = W.MBB;
8179 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8180 // we can branch to its destination directly if it's squeezed exactly in
8181 // between the known lower bound and Pivot - 1.
8182 MachineBasicBlock *LeftMBB;
8183 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8184 FirstLeft->Low == W.GE &&
8185 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8186 LeftMBB = FirstLeft->MBB;
8188 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8189 FuncInfo.MF->insert(BBI, LeftMBB);
8190 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8191 // Put Cond in a virtual register to make it available from the new blocks.
8192 ExportFromCurrentBlock(Cond);
8195 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8196 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8197 // directly if RHS.High equals the current upper bound.
8198 MachineBasicBlock *RightMBB;
8199 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8200 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8201 RightMBB = FirstRight->MBB;
8203 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8204 FuncInfo.MF->insert(BBI, RightMBB);
8205 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8206 // Put Cond in a virtual register to make it available from the new blocks.
8207 ExportFromCurrentBlock(Cond);
8210 // Create the CaseBlock record that will be used to lower the branch.
8211 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8212 LeftWeight, RightWeight);
8214 if (W.MBB == SwitchMBB)
8215 visitSwitchCase(CB, SwitchMBB);
8217 SwitchCases.push_back(CB);
8220 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8221 // Extract cases from the switch.
8222 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8223 CaseClusterVector Clusters;
8224 Clusters.reserve(SI.getNumCases());
8225 for (auto I : SI.cases()) {
8226 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8227 const ConstantInt *CaseVal = I.getCaseValue();
8229 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8230 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8233 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8235 // Cluster adjacent cases with the same destination. We do this at all
8236 // optimization levels because it's cheap to do and will make codegen faster
8237 // if there are many clusters.
8238 sortAndRangeify(Clusters);
8240 if (TM.getOptLevel() != CodeGenOpt::None) {
8241 // Replace an unreachable default with the most popular destination.
8242 // FIXME: Exploit unreachable default more aggressively.
8243 bool UnreachableDefault =
8244 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8245 if (UnreachableDefault && !Clusters.empty()) {
8246 DenseMap<const BasicBlock *, unsigned> Popularity;
8247 unsigned MaxPop = 0;
8248 const BasicBlock *MaxBB = nullptr;
8249 for (auto I : SI.cases()) {
8250 const BasicBlock *BB = I.getCaseSuccessor();
8251 if (++Popularity[BB] > MaxPop) {
8252 MaxPop = Popularity[BB];
8257 assert(MaxPop > 0 && MaxBB);
8258 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8260 // Remove cases that were pointing to the destination that is now the
8262 CaseClusterVector New;
8263 New.reserve(Clusters.size());
8264 for (CaseCluster &CC : Clusters) {
8265 if (CC.MBB != DefaultMBB)
8268 Clusters = std::move(New);
8272 // If there is only the default destination, jump there directly.
8273 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8274 if (Clusters.empty()) {
8275 SwitchMBB->addSuccessor(DefaultMBB);
8276 if (DefaultMBB != NextBlock(SwitchMBB)) {
8277 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8278 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8283 findJumpTables(Clusters, &SI, DefaultMBB);
8284 findBitTestClusters(Clusters, &SI);
8287 dbgs() << "Case clusters: ";
8288 for (const CaseCluster &C : Clusters) {
8289 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8290 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8292 C.Low->getValue().print(dbgs(), true);
8293 if (C.Low != C.High) {
8295 C.High->getValue().print(dbgs(), true);
8302 assert(!Clusters.empty());
8303 SwitchWorkList WorkList;
8304 CaseClusterIt First = Clusters.begin();
8305 CaseClusterIt Last = Clusters.end() - 1;
8306 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8308 while (!WorkList.empty()) {
8309 SwitchWorkListItem W = WorkList.back();
8310 WorkList.pop_back();
8311 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8313 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8314 // For optimized builds, lower large range as a balanced binary tree.
8315 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8319 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);