1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
70 #define DEBUG_TYPE "isel"
72 /// LimitFloatPrecision - Generate low-precision inline sequences for
73 /// some float libcalls (6, 8 or 12 bits).
74 static unsigned LimitFloatPrecision;
76 static cl::opt<unsigned, true>
77 LimitFPPrecision("limit-float-precision",
78 cl::desc("Generate low-precision inline sequences "
79 "for some float libcalls"),
80 cl::location(LimitFloatPrecision),
84 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
85 cl::desc("Enable fast-math-flags for DAG nodes"));
87 // Limit the width of DAG chains. This is important in general to prevent
88 // DAG-based analysis from blowing up. For example, alias analysis and
89 // load clustering may not complete in reasonable time. It is difficult to
90 // recognize and avoid this situation within each individual analysis, and
91 // future analyses are likely to have the same behavior. Limiting DAG width is
92 // the safe approach and will be especially important with global DAGs.
94 // MaxParallelChains default is arbitrarily high to avoid affecting
95 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
96 // sequence over this should have been converted to llvm.memcpy by the
97 // frontend. It easy to induce this behavior with .ll code such as:
98 // %buffer = alloca [4096 x i8]
99 // %data = load [4096 x i8]* %argPtr
100 // store [4096 x i8] %data, [4096 x i8]* %buffer
101 static const unsigned MaxParallelChains = 64;
103 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts, unsigned NumParts,
105 MVT PartVT, EVT ValueVT, const Value *V);
107 /// getCopyFromParts - Create a value that contains the specified legal parts
108 /// combined into the value they represent. If the parts combine to a type
109 /// larger then ValueVT then AssertOp can be used to specify whether the extra
110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
111 /// (ISD::AssertSext).
112 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
113 const SDValue *Parts,
114 unsigned NumParts, MVT PartVT, EVT ValueVT,
116 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
117 if (ValueVT.isVector())
118 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
121 assert(NumParts > 0 && "No parts to assemble!");
122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 SDValue Val = Parts[0];
126 // Assemble the value from multiple parts.
127 if (ValueVT.isInteger()) {
128 unsigned PartBits = PartVT.getSizeInBits();
129 unsigned ValueBits = ValueVT.getSizeInBits();
131 // Assemble the power of 2 part.
132 unsigned RoundParts = NumParts & (NumParts - 1) ?
133 1 << Log2_32(NumParts) : NumParts;
134 unsigned RoundBits = PartBits * RoundParts;
135 EVT RoundVT = RoundBits == ValueBits ?
136 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
139 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
141 if (RoundParts > 2) {
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
145 RoundParts / 2, PartVT, HalfVT, V);
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
151 if (DAG.getDataLayout().isBigEndian())
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 if (RoundParts < NumParts) {
157 // Assemble the trailing non-power-of-2 part.
158 unsigned OddParts = NumParts - RoundParts;
159 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
160 Hi = getCopyFromParts(DAG, DL,
161 Parts + RoundParts, OddParts, PartVT, OddVT, V);
163 // Combine the round and odd parts.
165 if (DAG.getDataLayout().isBigEndian())
167 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
172 TLI.getPointerTy(DAG.getDataLayout())));
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
174 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
176 } else if (PartVT.isFloatingPoint()) {
177 // FP split into multiple FP parts (for ppcf128)
178 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
181 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
182 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
183 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
187 // FP split into integer parts (soft fp)
188 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
189 !PartVT.isVector() && "Unexpected split");
190 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
191 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
195 // There is now one part, held in Val. Correct it to match ValueVT.
196 EVT PartEVT = Val.getValueType();
198 if (PartEVT == ValueVT)
201 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
202 ValueVT.bitsLT(PartEVT)) {
203 // For an FP value in an integer part, we need to truncate to the right
205 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
206 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
209 if (PartEVT.isInteger() && ValueVT.isInteger()) {
210 if (ValueVT.bitsLT(PartEVT)) {
211 // For a truncate, see if we have any information to
212 // indicate whether the truncated bits will always be
213 // zero or sign-extension.
214 if (AssertOp != ISD::DELETED_NODE)
215 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
216 DAG.getValueType(ValueVT));
217 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
219 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
223 // FP_ROUND's are always exact here.
224 if (ValueVT.bitsLT(Val.getValueType()))
226 ISD::FP_ROUND, DL, ValueVT, Val,
227 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
229 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
232 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
233 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
235 llvm_unreachable("Unknown mismatch!");
238 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
239 const Twine &ErrMsg) {
240 const Instruction *I = dyn_cast_or_null<Instruction>(V);
242 return Ctx.emitError(ErrMsg);
244 const char *AsmError = ", possible invalid constraint for vector type";
245 if (const CallInst *CI = dyn_cast<CallInst>(I))
246 if (isa<InlineAsm>(CI->getCalledValue()))
247 return Ctx.emitError(I, ErrMsg + AsmError);
249 return Ctx.emitError(I, ErrMsg);
252 /// getCopyFromPartsVector - Create a value that contains the specified legal
253 /// parts combined into the value they represent. If the parts combine to a
254 /// type larger then ValueVT then AssertOp can be used to specify whether the
255 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
256 /// ValueVT (ISD::AssertSext).
257 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
258 const SDValue *Parts, unsigned NumParts,
259 MVT PartVT, EVT ValueVT, const Value *V) {
260 assert(ValueVT.isVector() && "Not a vector value");
261 assert(NumParts > 0 && "No parts to assemble!");
262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
263 SDValue Val = Parts[0];
265 // Handle a multi-element vector.
269 unsigned NumIntermediates;
271 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
272 NumIntermediates, RegisterVT);
273 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
274 NumParts = NumRegs; // Silence a compiler warning.
275 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
276 assert(RegisterVT.getSizeInBits() ==
277 Parts[0].getSimpleValueType().getSizeInBits() &&
278 "Part type sizes don't match!");
280 // Assemble the parts into intermediate operands.
281 SmallVector<SDValue, 8> Ops(NumIntermediates);
282 if (NumIntermediates == NumParts) {
283 // If the register was not expanded, truncate or copy the value,
285 for (unsigned i = 0; i != NumParts; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
287 PartVT, IntermediateVT, V);
288 } else if (NumParts > 0) {
289 // If the intermediate type was expanded, build the intermediate
290 // operands from the parts.
291 assert(NumParts % NumIntermediates == 0 &&
292 "Must expand into a divisible number of parts!");
293 unsigned Factor = NumParts / NumIntermediates;
294 for (unsigned i = 0; i != NumIntermediates; ++i)
295 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
296 PartVT, IntermediateVT, V);
299 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
300 // intermediate operands.
301 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
306 // There is now one part, held in Val. Correct it to match ValueVT.
307 EVT PartEVT = Val.getValueType();
309 if (PartEVT == ValueVT)
312 if (PartEVT.isVector()) {
313 // If the element type of the source/dest vectors are the same, but the
314 // parts vector has more elements than the value vector, then we have a
315 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
317 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
318 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
319 "Cannot narrow, it would be a lossy transformation");
321 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
322 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
325 // Vector/Vector bitcast.
326 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
327 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
329 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
330 "Cannot handle this kind of promotion");
331 // Promoted vector extract
332 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
336 // Trivial bitcast if the types are the same size and the destination
337 // vector type is legal.
338 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
339 TLI.isTypeLegal(ValueVT))
340 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
342 // Handle cases such as i8 -> <1 x i1>
343 if (ValueVT.getVectorNumElements() != 1) {
344 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
345 "non-trivial scalar-to-vector conversion");
346 return DAG.getUNDEF(ValueVT);
349 if (ValueVT.getVectorNumElements() == 1 &&
350 ValueVT.getVectorElementType() != PartEVT)
351 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
353 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
356 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
357 SDValue Val, SDValue *Parts, unsigned NumParts,
358 MVT PartVT, const Value *V);
360 /// getCopyToParts - Create a series of nodes that contain the specified value
361 /// split into legal parts. If the parts contain more bits than Val, then, for
362 /// integers, ExtendKind can be used to specify how to generate the extra bits.
363 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
364 SDValue Val, SDValue *Parts, unsigned NumParts,
365 MVT PartVT, const Value *V,
366 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
367 EVT ValueVT = Val.getValueType();
369 // Handle the vector case separately.
370 if (ValueVT.isVector())
371 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
373 unsigned PartBits = PartVT.getSizeInBits();
374 unsigned OrigNumParts = NumParts;
375 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
376 "Copying to an illegal type!");
381 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
382 EVT PartEVT = PartVT;
383 if (PartEVT == ValueVT) {
384 assert(NumParts == 1 && "No-op copy with multiple parts!");
389 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
390 // If the parts cover more bits than the value has, promote the value.
391 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
392 assert(NumParts == 1 && "Do not know what to promote to!");
393 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
395 if (ValueVT.isFloatingPoint()) {
396 // FP values need to be bitcast, then extended if they are being put
397 // into a larger container.
398 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
399 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
401 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
402 ValueVT.isInteger() &&
403 "Unknown mismatch!");
404 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
405 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
406 if (PartVT == MVT::x86mmx)
407 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 } else if (PartBits == ValueVT.getSizeInBits()) {
410 // Different types of the same size.
411 assert(NumParts == 1 && PartEVT != ValueVT);
412 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
413 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
414 // If the parts cover less bits than value has, truncate the value.
415 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
416 ValueVT.isInteger() &&
417 "Unknown mismatch!");
418 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
419 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
420 if (PartVT == MVT::x86mmx)
421 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
424 // The value may have changed - recompute ValueVT.
425 ValueVT = Val.getValueType();
426 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
427 "Failed to tile the value with PartVT!");
430 if (PartEVT != ValueVT)
431 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
432 "scalar-to-vector conversion failed");
438 // Expand the value into multiple parts.
439 if (NumParts & (NumParts - 1)) {
440 // The number of parts is not a power of 2. Split off and copy the tail.
441 assert(PartVT.isInteger() && ValueVT.isInteger() &&
442 "Do not know what to expand to!");
443 unsigned RoundParts = 1 << Log2_32(NumParts);
444 unsigned RoundBits = RoundParts * PartBits;
445 unsigned OddParts = NumParts - RoundParts;
446 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
447 DAG.getIntPtrConstant(RoundBits, DL));
448 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
450 if (DAG.getDataLayout().isBigEndian())
451 // The odd parts were reversed by getCopyToParts - unreverse them.
452 std::reverse(Parts + RoundParts, Parts + NumParts);
454 NumParts = RoundParts;
455 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
456 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
459 // The number of parts is a power of 2. Repeatedly bisect the value using
461 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
462 EVT::getIntegerVT(*DAG.getContext(),
463 ValueVT.getSizeInBits()),
466 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
467 for (unsigned i = 0; i < NumParts; i += StepSize) {
468 unsigned ThisBits = StepSize * PartBits / 2;
469 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
470 SDValue &Part0 = Parts[i];
471 SDValue &Part1 = Parts[i+StepSize/2];
473 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
474 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
475 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
476 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
478 if (ThisBits == PartBits && ThisVT != PartVT) {
479 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
480 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
485 if (DAG.getDataLayout().isBigEndian())
486 std::reverse(Parts, Parts + OrigNumParts);
490 /// getCopyToPartsVector - Create a series of nodes that contain the specified
491 /// value split into legal parts.
492 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
493 SDValue Val, SDValue *Parts, unsigned NumParts,
494 MVT PartVT, const Value *V) {
495 EVT ValueVT = Val.getValueType();
496 assert(ValueVT.isVector() && "Not a vector");
497 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
500 EVT PartEVT = PartVT;
501 if (PartEVT == ValueVT) {
503 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
504 // Bitconvert vector->vector case.
505 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
508 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
509 EVT ElementVT = PartVT.getVectorElementType();
510 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
512 SmallVector<SDValue, 16> Ops;
513 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
514 Ops.push_back(DAG.getNode(
515 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
516 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
518 for (unsigned i = ValueVT.getVectorNumElements(),
519 e = PartVT.getVectorNumElements(); i != e; ++i)
520 Ops.push_back(DAG.getUNDEF(ElementVT));
522 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
524 // FIXME: Use CONCAT for 2x -> 4x.
526 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
527 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
528 } else if (PartVT.isVector() &&
529 PartEVT.getVectorElementType().bitsGE(
530 ValueVT.getVectorElementType()) &&
531 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
533 // Promoted vector extract
534 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
536 // Vector -> scalar conversion.
537 assert(ValueVT.getVectorNumElements() == 1 &&
538 "Only trivial vector-to-scalar conversions should get here!");
540 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
541 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
543 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
550 // Handle a multi-element vector.
553 unsigned NumIntermediates;
554 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
556 NumIntermediates, RegisterVT);
557 unsigned NumElements = ValueVT.getVectorNumElements();
559 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
560 NumParts = NumRegs; // Silence a compiler warning.
561 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
563 // Split the vector into intermediate operands.
564 SmallVector<SDValue, 8> Ops(NumIntermediates);
565 for (unsigned i = 0; i != NumIntermediates; ++i) {
566 if (IntermediateVT.isVector())
568 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
569 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
570 TLI.getVectorIdxTy(DAG.getDataLayout())));
572 Ops[i] = DAG.getNode(
573 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
574 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
577 // Split the intermediate operands into legal parts.
578 if (NumParts == NumIntermediates) {
579 // If the register was not expanded, promote or copy the value,
581 for (unsigned i = 0; i != NumParts; ++i)
582 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
583 } else if (NumParts > 0) {
584 // If the intermediate type was expanded, split each the value into
586 assert(NumIntermediates != 0 && "division by zero");
587 assert(NumParts % NumIntermediates == 0 &&
588 "Must expand into a divisible number of parts!");
589 unsigned Factor = NumParts / NumIntermediates;
590 for (unsigned i = 0; i != NumIntermediates; ++i)
591 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
595 RegsForValue::RegsForValue() {}
597 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
599 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
601 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
602 const DataLayout &DL, unsigned Reg, Type *Ty) {
603 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
605 for (EVT ValueVT : ValueVTs) {
606 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
607 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
608 for (unsigned i = 0; i != NumRegs; ++i)
609 Regs.push_back(Reg + i);
610 RegVTs.push_back(RegisterVT);
615 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
616 /// this value and returns the result as a ValueVT value. This uses
617 /// Chain/Flag as the input and updates them for the output Chain/Flag.
618 /// If the Flag pointer is NULL, no flag is used.
619 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
620 FunctionLoweringInfo &FuncInfo,
622 SDValue &Chain, SDValue *Flag,
623 const Value *V) const {
624 // A Value with type {} or [0 x %t] needs no registers.
625 if (ValueVTs.empty())
628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
630 // Assemble the legal parts into the final values.
631 SmallVector<SDValue, 4> Values(ValueVTs.size());
632 SmallVector<SDValue, 8> Parts;
633 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
634 // Copy the legal parts from the registers.
635 EVT ValueVT = ValueVTs[Value];
636 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
637 MVT RegisterVT = RegVTs[Value];
639 Parts.resize(NumRegs);
640 for (unsigned i = 0; i != NumRegs; ++i) {
643 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
646 *Flag = P.getValue(2);
649 Chain = P.getValue(1);
652 // If the source register was virtual and if we know something about it,
653 // add an assert node.
654 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
655 !RegisterVT.isInteger() || RegisterVT.isVector())
658 const FunctionLoweringInfo::LiveOutInfo *LOI =
659 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
663 unsigned RegSize = RegisterVT.getSizeInBits();
664 unsigned NumSignBits = LOI->NumSignBits;
665 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
667 if (NumZeroBits == RegSize) {
668 // The current value is a zero.
669 // Explicitly express that as it would be easier for
670 // optimizations to kick in.
671 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
675 // FIXME: We capture more information than the dag can represent. For
676 // now, just use the tightest assertzext/assertsext possible.
678 EVT FromVT(MVT::Other);
679 if (NumSignBits == RegSize)
680 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
681 else if (NumZeroBits >= RegSize-1)
682 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
683 else if (NumSignBits > RegSize-8)
684 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
685 else if (NumZeroBits >= RegSize-8)
686 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
687 else if (NumSignBits > RegSize-16)
688 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
689 else if (NumZeroBits >= RegSize-16)
690 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
691 else if (NumSignBits > RegSize-32)
692 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
693 else if (NumZeroBits >= RegSize-32)
694 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
698 // Add an assertion node.
699 assert(FromVT != MVT::Other);
700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
701 RegisterVT, P, DAG.getValueType(FromVT));
704 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
705 NumRegs, RegisterVT, ValueVT, V);
710 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
713 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
714 /// specified value into the registers specified by this object. This uses
715 /// Chain/Flag as the input and updates them for the output Chain/Flag.
716 /// If the Flag pointer is NULL, no flag is used.
717 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
718 SDValue &Chain, SDValue *Flag, const Value *V,
719 ISD::NodeType PreferredExtendType) const {
720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
721 ISD::NodeType ExtendKind = PreferredExtendType;
723 // Get the list of the values's legal parts.
724 unsigned NumRegs = Regs.size();
725 SmallVector<SDValue, 8> Parts(NumRegs);
726 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
727 EVT ValueVT = ValueVTs[Value];
728 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
729 MVT RegisterVT = RegVTs[Value];
731 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
732 ExtendKind = ISD::ZERO_EXTEND;
734 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
735 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
739 // Copy the parts into the registers.
740 SmallVector<SDValue, 8> Chains(NumRegs);
741 for (unsigned i = 0; i != NumRegs; ++i) {
744 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
746 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
747 *Flag = Part.getValue(1);
750 Chains[i] = Part.getValue(0);
753 if (NumRegs == 1 || Flag)
754 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
755 // flagged to it. That is the CopyToReg nodes and the user are considered
756 // a single scheduling unit. If we create a TokenFactor and return it as
757 // chain, then the TokenFactor is both a predecessor (operand) of the
758 // user as well as a successor (the TF operands are flagged to the user).
759 // c1, f1 = CopyToReg
760 // c2, f2 = CopyToReg
761 // c3 = TokenFactor c1, c2
764 Chain = Chains[NumRegs-1];
766 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
769 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
770 /// operand list. This adds the code marker and includes the number of
771 /// values added into it.
772 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
773 unsigned MatchingIdx, SDLoc dl,
775 std::vector<SDValue> &Ops) const {
776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
780 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
781 else if (!Regs.empty() &&
782 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
783 // Put the register class of the virtual registers in the flag word. That
784 // way, later passes can recompute register class constraints for inline
785 // assembly as well as normal instructions.
786 // Don't do this for tied operands that can use the regclass information
788 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
789 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
790 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
793 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
796 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
797 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
798 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
799 MVT RegisterVT = RegVTs[Value];
800 for (unsigned i = 0; i != NumRegs; ++i) {
801 assert(Reg < Regs.size() && "Mismatch in # registers expected");
802 unsigned TheReg = Regs[Reg++];
803 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
805 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
806 // If we clobbered the stack pointer, MFI should know about it.
807 assert(DAG.getMachineFunction().getFrameInfo()->
808 hasOpaqueSPAdjustment());
814 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
815 const TargetLibraryInfo *li) {
819 DL = &DAG.getDataLayout();
820 Context = DAG.getContext();
821 LPadToCallSiteMap.clear();
824 /// clear - Clear out the current SelectionDAG and the associated
825 /// state and prepare this SelectionDAGBuilder object to be used
826 /// for a new block. This doesn't clear out information about
827 /// additional blocks that are needed to complete switch lowering
828 /// or PHI node updating; that information is cleared out as it is
830 void SelectionDAGBuilder::clear() {
832 UnusedArgNodeMap.clear();
833 PendingLoads.clear();
834 PendingExports.clear();
837 SDNodeOrder = LowestSDNodeOrder;
838 StatepointLowering.clear();
841 /// clearDanglingDebugInfo - Clear the dangling debug information
842 /// map. This function is separated from the clear so that debug
843 /// information that is dangling in a basic block can be properly
844 /// resolved in a different basic block. This allows the
845 /// SelectionDAG to resolve dangling debug information attached
847 void SelectionDAGBuilder::clearDanglingDebugInfo() {
848 DanglingDebugInfoMap.clear();
851 /// getRoot - Return the current virtual root of the Selection DAG,
852 /// flushing any PendingLoad items. This must be done before emitting
853 /// a store or any other node that may need to be ordered after any
854 /// prior load instructions.
856 SDValue SelectionDAGBuilder::getRoot() {
857 if (PendingLoads.empty())
858 return DAG.getRoot();
860 if (PendingLoads.size() == 1) {
861 SDValue Root = PendingLoads[0];
863 PendingLoads.clear();
867 // Otherwise, we have to make a token factor node.
868 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
870 PendingLoads.clear();
875 /// getControlRoot - Similar to getRoot, but instead of flushing all the
876 /// PendingLoad items, flush all the PendingExports items. It is necessary
877 /// to do this before emitting a terminator instruction.
879 SDValue SelectionDAGBuilder::getControlRoot() {
880 SDValue Root = DAG.getRoot();
882 if (PendingExports.empty())
885 // Turn all of the CopyToReg chains into one factored node.
886 if (Root.getOpcode() != ISD::EntryToken) {
887 unsigned i = 0, e = PendingExports.size();
888 for (; i != e; ++i) {
889 assert(PendingExports[i].getNode()->getNumOperands() > 1);
890 if (PendingExports[i].getNode()->getOperand(0) == Root)
891 break; // Don't add the root if we already indirectly depend on it.
895 PendingExports.push_back(Root);
898 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
900 PendingExports.clear();
905 void SelectionDAGBuilder::visit(const Instruction &I) {
906 // Set up outgoing PHI node register values before emitting the terminator.
907 if (isa<TerminatorInst>(&I))
908 HandlePHINodesInSuccessorBlocks(I.getParent());
914 visit(I.getOpcode(), I);
916 if (!isa<TerminatorInst>(&I) && !HasTailCall &&
917 !isStatepoint(&I)) // statepoints handle their exports internally
918 CopyToExportRegsIfNeeded(&I);
923 void SelectionDAGBuilder::visitPHI(const PHINode &) {
924 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
927 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
928 // Note: this doesn't use InstVisitor, because it has to work with
929 // ConstantExpr's in addition to instructions.
931 default: llvm_unreachable("Unknown instruction type encountered!");
932 // Build the switch statement using the Instruction.def file.
933 #define HANDLE_INST(NUM, OPCODE, CLASS) \
934 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
935 #include "llvm/IR/Instruction.def"
939 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
940 // generate the debug data structures now that we've seen its definition.
941 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
943 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
945 const DbgValueInst *DI = DDI.getDI();
946 DebugLoc dl = DDI.getdl();
947 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
948 DILocalVariable *Variable = DI->getVariable();
949 DIExpression *Expr = DI->getExpression();
950 assert(Variable->isValidLocationForIntrinsic(dl) &&
951 "Expected inlined-at fields to agree");
952 uint64_t Offset = DI->getOffset();
953 // A dbg.value for an alloca is always indirect.
954 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
957 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
959 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
960 IsIndirect, Offset, dl, DbgSDNodeOrder);
961 DAG.AddDbgValue(SDV, Val.getNode(), false);
964 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
965 DanglingDebugInfoMap[V] = DanglingDebugInfo();
969 /// getCopyFromRegs - If there was virtual register allocated for the value V
970 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
971 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
972 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
975 if (It != FuncInfo.ValueMap.end()) {
976 unsigned InReg = It->second;
977 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
978 DAG.getDataLayout(), InReg, Ty);
979 SDValue Chain = DAG.getEntryNode();
980 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
981 resolveDanglingDebugInfo(V, Result);
987 /// getValue - Return an SDValue for the given Value.
988 SDValue SelectionDAGBuilder::getValue(const Value *V) {
989 // If we already have an SDValue for this value, use it. It's important
990 // to do this first, so that we don't create a CopyFromReg if we already
991 // have a regular SDValue.
992 SDValue &N = NodeMap[V];
993 if (N.getNode()) return N;
995 // If there's a virtual register allocated and initialized for this
997 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
998 if (copyFromReg.getNode()) {
1002 // Otherwise create a new SDValue and remember it.
1003 SDValue Val = getValueImpl(V);
1005 resolveDanglingDebugInfo(V, Val);
1009 // Return true if SDValue exists for the given Value
1010 bool SelectionDAGBuilder::findValue(const Value *V) const {
1011 return (NodeMap.find(V) != NodeMap.end()) ||
1012 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1015 /// getNonRegisterValue - Return an SDValue for the given Value, but
1016 /// don't look in FuncInfo.ValueMap for a virtual register.
1017 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1018 // If we already have an SDValue for this value, use it.
1019 SDValue &N = NodeMap[V];
1021 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1022 // Remove the debug location from the node as the node is about to be used
1023 // in a location which may differ from the original debug location. This
1024 // is relevant to Constant and ConstantFP nodes because they can appear
1025 // as constant expressions inside PHI nodes.
1026 N->setDebugLoc(DebugLoc());
1031 // Otherwise create a new SDValue and remember it.
1032 SDValue Val = getValueImpl(V);
1034 resolveDanglingDebugInfo(V, Val);
1038 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1039 /// Create an SDValue for the given value.
1040 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1041 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1043 if (const Constant *C = dyn_cast<Constant>(V)) {
1044 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1046 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1047 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1049 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1050 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1052 if (isa<ConstantPointerNull>(C)) {
1053 unsigned AS = V->getType()->getPointerAddressSpace();
1054 return DAG.getConstant(0, getCurSDLoc(),
1055 TLI.getPointerTy(DAG.getDataLayout(), AS));
1058 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1059 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1061 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1062 return DAG.getUNDEF(VT);
1064 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1065 visit(CE->getOpcode(), *CE);
1066 SDValue N1 = NodeMap[V];
1067 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1071 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1072 SmallVector<SDValue, 4> Constants;
1073 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1075 SDNode *Val = getValue(*OI).getNode();
1076 // If the operand is an empty aggregate, there are no values.
1078 // Add each leaf value from the operand to the Constants list
1079 // to form a flattened list of all the values.
1080 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1081 Constants.push_back(SDValue(Val, i));
1084 return DAG.getMergeValues(Constants, getCurSDLoc());
1087 if (const ConstantDataSequential *CDS =
1088 dyn_cast<ConstantDataSequential>(C)) {
1089 SmallVector<SDValue, 4> Ops;
1090 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1091 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1092 // Add each leaf value from the operand to the Constants list
1093 // to form a flattened list of all the values.
1094 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1095 Ops.push_back(SDValue(Val, i));
1098 if (isa<ArrayType>(CDS->getType()))
1099 return DAG.getMergeValues(Ops, getCurSDLoc());
1100 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1104 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1105 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1106 "Unknown struct or array constant!");
1108 SmallVector<EVT, 4> ValueVTs;
1109 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1110 unsigned NumElts = ValueVTs.size();
1112 return SDValue(); // empty struct
1113 SmallVector<SDValue, 4> Constants(NumElts);
1114 for (unsigned i = 0; i != NumElts; ++i) {
1115 EVT EltVT = ValueVTs[i];
1116 if (isa<UndefValue>(C))
1117 Constants[i] = DAG.getUNDEF(EltVT);
1118 else if (EltVT.isFloatingPoint())
1119 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1121 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1124 return DAG.getMergeValues(Constants, getCurSDLoc());
1127 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1128 return DAG.getBlockAddress(BA, VT);
1130 VectorType *VecTy = cast<VectorType>(V->getType());
1131 unsigned NumElements = VecTy->getNumElements();
1133 // Now that we know the number and type of the elements, get that number of
1134 // elements into the Ops array based on what kind of constant it is.
1135 SmallVector<SDValue, 16> Ops;
1136 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1137 for (unsigned i = 0; i != NumElements; ++i)
1138 Ops.push_back(getValue(CV->getOperand(i)));
1140 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1142 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1145 if (EltVT.isFloatingPoint())
1146 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1148 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1149 Ops.assign(NumElements, Op);
1152 // Create a BUILD_VECTOR node.
1153 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1156 // If this is a static alloca, generate it as the frameindex instead of
1158 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1159 DenseMap<const AllocaInst*, int>::iterator SI =
1160 FuncInfo.StaticAllocaMap.find(AI);
1161 if (SI != FuncInfo.StaticAllocaMap.end())
1162 return DAG.getFrameIndex(SI->second,
1163 TLI.getPointerTy(DAG.getDataLayout()));
1166 // If this is an instruction which fast-isel has deferred, select it now.
1167 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1168 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1169 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1171 SDValue Chain = DAG.getEntryNode();
1172 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1175 llvm_unreachable("Can't get register for value!");
1178 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1179 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1180 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1181 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1182 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1183 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1184 if (IsMSVCCXX || IsCoreCLR)
1185 CatchPadMBB->setIsEHFuncletEntry();
1187 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1189 // Update machine-CFG edge.
1190 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1193 DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot());
1195 // If this is not a fall-through branch or optimizations are switched off,
1197 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1198 TM.getOptLevel() == CodeGenOpt::None)
1199 Chain = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
1200 DAG.getBasicBlock(NormalDestMBB));
1204 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1205 // Update machine-CFG edge.
1206 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1207 FuncInfo.MBB->addSuccessor(TargetMBB);
1209 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1210 bool IsSEH = isAsynchronousEHPersonality(Pers);
1212 // If this is not a fall-through branch or optimizations are switched off,
1214 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1215 TM.getOptLevel() == CodeGenOpt::None)
1216 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1217 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1221 // Figure out the funclet membership for the catchret's successor.
1222 // This will be used by the FuncletLayout pass to determine how to order the
1224 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1225 WinEHFuncInfo &EHInfo =
1226 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
1227 const BasicBlock *SuccessorColor = EHInfo.CatchRetSuccessorColorMap[&I];
1228 assert(SuccessorColor && "No parent funclet for catchret!");
1229 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1230 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1232 // Create the terminator node.
1233 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1234 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1235 DAG.getBasicBlock(SuccessorColorMBB));
1239 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1240 llvm_unreachable("should never codegen catchendpads");
1243 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1244 // Don't emit any special code for the cleanuppad instruction. It just marks
1245 // the start of a funclet.
1246 FuncInfo.MBB->setIsEHFuncletEntry();
1247 FuncInfo.MBB->setIsCleanupFuncletEntry();
1250 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1251 /// many places it could ultimately go. In the IR, we have a single unwind
1252 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1253 /// This function skips over imaginary basic blocks that hold catchpad,
1254 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1255 /// basic block destinations. As those destinations may not be successors of
1256 /// EHPadBB, here we also calculate the edge weight to those destinations. The
1257 /// passed-in Weight is the edge weight to EHPadBB.
1258 static void findUnwindDestinations(
1259 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, uint32_t Weight,
1260 SmallVectorImpl<std::pair<MachineBasicBlock *, uint32_t>> &UnwindDests) {
1261 EHPersonality Personality =
1262 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1263 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1264 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1267 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1268 BasicBlock *NewEHPadBB = nullptr;
1269 if (isa<LandingPadInst>(Pad)) {
1270 // Stop on landingpads. They are not funclets.
1271 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1273 } else if (isa<CleanupPadInst>(Pad)) {
1274 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1276 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1277 UnwindDests.back().first->setIsEHFuncletEntry();
1279 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1280 // Add the catchpad handler to the possible destinations.
1281 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1282 // In MSVC C++, catchblocks are funclets and need prologues.
1283 if (IsMSVCCXX || IsCoreCLR)
1284 UnwindDests.back().first->setIsEHFuncletEntry();
1285 NewEHPadBB = CPI->getUnwindDest();
1286 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad))
1287 NewEHPadBB = CEPI->getUnwindDest();
1288 else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad))
1289 NewEHPadBB = CEPI->getUnwindDest();
1293 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1294 if (BPI && NewEHPadBB) {
1295 // When BPI is available, the calculated weight cannot be zero as zero
1296 // will be turned to a default weight in MachineBlockFrequencyInfo.
1297 Weight = std::max<uint32_t>(
1298 BPI->getEdgeProbability(EHPadBB, NewEHPadBB).scale(Weight), 1);
1300 EHPadBB = NewEHPadBB;
1304 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1305 // Update successor info.
1306 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
1307 auto UnwindDest = I.getUnwindDest();
1308 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1309 uint32_t UnwindDestWeight =
1310 BPI ? BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(), UnwindDest) : 0;
1311 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestWeight, UnwindDests);
1312 for (auto &UnwindDest : UnwindDests) {
1313 UnwindDest.first->setIsEHPad();
1314 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1317 // Create the terminator node.
1319 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1323 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1324 report_fatal_error("visitCleanupEndPad not yet implemented!");
1327 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1328 report_fatal_error("visitTerminatePad not yet implemented!");
1331 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1332 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1333 auto &DL = DAG.getDataLayout();
1334 SDValue Chain = getControlRoot();
1335 SmallVector<ISD::OutputArg, 8> Outs;
1336 SmallVector<SDValue, 8> OutVals;
1338 if (!FuncInfo.CanLowerReturn) {
1339 unsigned DemoteReg = FuncInfo.DemoteRegister;
1340 const Function *F = I.getParent()->getParent();
1342 // Emit a store of the return value through the virtual register.
1343 // Leave Outs empty so that LowerReturn won't try to load return
1344 // registers the usual way.
1345 SmallVector<EVT, 1> PtrValueVTs;
1346 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1349 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1350 SDValue RetOp = getValue(I.getOperand(0));
1352 SmallVector<EVT, 4> ValueVTs;
1353 SmallVector<uint64_t, 4> Offsets;
1354 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1355 unsigned NumValues = ValueVTs.size();
1357 SmallVector<SDValue, 4> Chains(NumValues);
1358 for (unsigned i = 0; i != NumValues; ++i) {
1359 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1360 RetPtr.getValueType(), RetPtr,
1361 DAG.getIntPtrConstant(Offsets[i],
1364 DAG.getStore(Chain, getCurSDLoc(),
1365 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1366 // FIXME: better loc info would be nice.
1367 Add, MachinePointerInfo(), false, false, 0);
1370 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1371 MVT::Other, Chains);
1372 } else if (I.getNumOperands() != 0) {
1373 SmallVector<EVT, 4> ValueVTs;
1374 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1375 unsigned NumValues = ValueVTs.size();
1377 SDValue RetOp = getValue(I.getOperand(0));
1379 const Function *F = I.getParent()->getParent();
1381 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1382 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1384 ExtendKind = ISD::SIGN_EXTEND;
1385 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1387 ExtendKind = ISD::ZERO_EXTEND;
1389 LLVMContext &Context = F->getContext();
1390 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1393 for (unsigned j = 0; j != NumValues; ++j) {
1394 EVT VT = ValueVTs[j];
1396 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1397 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1399 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1400 MVT PartVT = TLI.getRegisterType(Context, VT);
1401 SmallVector<SDValue, 4> Parts(NumParts);
1402 getCopyToParts(DAG, getCurSDLoc(),
1403 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1404 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1406 // 'inreg' on function refers to return value
1407 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1411 // Propagate extension type if any
1412 if (ExtendKind == ISD::SIGN_EXTEND)
1414 else if (ExtendKind == ISD::ZERO_EXTEND)
1417 for (unsigned i = 0; i < NumParts; ++i) {
1418 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1419 VT, /*isfixed=*/true, 0, 0));
1420 OutVals.push_back(Parts[i]);
1426 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1427 CallingConv::ID CallConv =
1428 DAG.getMachineFunction().getFunction()->getCallingConv();
1429 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1430 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1432 // Verify that the target's LowerReturn behaved as expected.
1433 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1434 "LowerReturn didn't return a valid chain!");
1436 // Update the DAG with the new chain value resulting from return lowering.
1440 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1441 /// created for it, emit nodes to copy the value into the virtual
1443 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1445 if (V->getType()->isEmptyTy())
1448 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1449 if (VMI != FuncInfo.ValueMap.end()) {
1450 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1451 CopyValueToVirtualRegister(V, VMI->second);
1455 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1456 /// the current basic block, add it to ValueMap now so that we'll get a
1458 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1459 // No need to export constants.
1460 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1462 // Already exported?
1463 if (FuncInfo.isExportedInst(V)) return;
1465 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1466 CopyValueToVirtualRegister(V, Reg);
1469 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1470 const BasicBlock *FromBB) {
1471 // The operands of the setcc have to be in this block. We don't know
1472 // how to export them from some other block.
1473 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1474 // Can export from current BB.
1475 if (VI->getParent() == FromBB)
1478 // Is already exported, noop.
1479 return FuncInfo.isExportedInst(V);
1482 // If this is an argument, we can export it if the BB is the entry block or
1483 // if it is already exported.
1484 if (isa<Argument>(V)) {
1485 if (FromBB == &FromBB->getParent()->getEntryBlock())
1488 // Otherwise, can only export this if it is already exported.
1489 return FuncInfo.isExportedInst(V);
1492 // Otherwise, constants can always be exported.
1496 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1497 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1498 const MachineBasicBlock *Dst) const {
1499 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1502 const BasicBlock *SrcBB = Src->getBasicBlock();
1503 const BasicBlock *DstBB = Dst->getBasicBlock();
1504 return BPI->getEdgeWeight(SrcBB, DstBB);
1507 void SelectionDAGBuilder::
1508 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1509 uint32_t Weight /* = 0 */) {
1511 Src->addSuccessorWithoutWeight(Dst);
1514 Weight = getEdgeWeight(Src, Dst);
1515 Src->addSuccessor(Dst, Weight);
1520 static bool InBlock(const Value *V, const BasicBlock *BB) {
1521 if (const Instruction *I = dyn_cast<Instruction>(V))
1522 return I->getParent() == BB;
1526 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1527 /// This function emits a branch and is used at the leaves of an OR or an
1528 /// AND operator tree.
1531 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1532 MachineBasicBlock *TBB,
1533 MachineBasicBlock *FBB,
1534 MachineBasicBlock *CurBB,
1535 MachineBasicBlock *SwitchBB,
1538 const BasicBlock *BB = CurBB->getBasicBlock();
1540 // If the leaf of the tree is a comparison, merge the condition into
1542 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1543 // The operands of the cmp have to be in this block. We don't know
1544 // how to export them from some other block. If this is the first block
1545 // of the sequence, no exporting is needed.
1546 if (CurBB == SwitchBB ||
1547 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1548 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1549 ISD::CondCode Condition;
1550 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1551 Condition = getICmpCondCode(IC->getPredicate());
1553 const FCmpInst *FC = cast<FCmpInst>(Cond);
1554 Condition = getFCmpCondCode(FC->getPredicate());
1555 if (TM.Options.NoNaNsFPMath)
1556 Condition = getFCmpCodeWithoutNaN(Condition);
1559 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1560 TBB, FBB, CurBB, TWeight, FWeight);
1561 SwitchCases.push_back(CB);
1566 // Create a CaseBlock record representing this branch.
1567 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1568 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1569 SwitchCases.push_back(CB);
1572 /// Scale down both weights to fit into uint32_t.
1573 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1574 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1575 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1576 NewTrue = NewTrue / Scale;
1577 NewFalse = NewFalse / Scale;
1580 /// FindMergedConditions - If Cond is an expression like
1581 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1582 MachineBasicBlock *TBB,
1583 MachineBasicBlock *FBB,
1584 MachineBasicBlock *CurBB,
1585 MachineBasicBlock *SwitchBB,
1586 Instruction::BinaryOps Opc,
1589 // If this node is not part of the or/and tree, emit it as a branch.
1590 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1591 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1592 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1593 BOp->getParent() != CurBB->getBasicBlock() ||
1594 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1595 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1596 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1601 // Create TmpBB after CurBB.
1602 MachineFunction::iterator BBI(CurBB);
1603 MachineFunction &MF = DAG.getMachineFunction();
1604 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1605 CurBB->getParent()->insert(++BBI, TmpBB);
1607 if (Opc == Instruction::Or) {
1608 // Codegen X | Y as:
1617 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1618 // The requirement is that
1619 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1620 // = TrueProb for original BB.
1621 // Assuming the original weights are A and B, one choice is to set BB1's
1622 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1624 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1625 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1626 // TmpBB, but the math is more complicated.
1628 uint64_t NewTrueWeight = TWeight;
1629 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1630 ScaleWeights(NewTrueWeight, NewFalseWeight);
1631 // Emit the LHS condition.
1632 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1633 NewTrueWeight, NewFalseWeight);
1635 NewTrueWeight = TWeight;
1636 NewFalseWeight = 2 * (uint64_t)FWeight;
1637 ScaleWeights(NewTrueWeight, NewFalseWeight);
1638 // Emit the RHS condition into TmpBB.
1639 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1640 NewTrueWeight, NewFalseWeight);
1642 assert(Opc == Instruction::And && "Unknown merge op!");
1643 // Codegen X & Y as:
1651 // This requires creation of TmpBB after CurBB.
1653 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1654 // The requirement is that
1655 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1656 // = FalseProb for original BB.
1657 // Assuming the original weights are A and B, one choice is to set BB1's
1658 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1660 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1662 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1663 uint64_t NewFalseWeight = FWeight;
1664 ScaleWeights(NewTrueWeight, NewFalseWeight);
1665 // Emit the LHS condition.
1666 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1667 NewTrueWeight, NewFalseWeight);
1669 NewTrueWeight = 2 * (uint64_t)TWeight;
1670 NewFalseWeight = FWeight;
1671 ScaleWeights(NewTrueWeight, NewFalseWeight);
1672 // Emit the RHS condition into TmpBB.
1673 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1674 NewTrueWeight, NewFalseWeight);
1678 /// If the set of cases should be emitted as a series of branches, return true.
1679 /// If we should emit this as a bunch of and/or'd together conditions, return
1682 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1683 if (Cases.size() != 2) return true;
1685 // If this is two comparisons of the same values or'd or and'd together, they
1686 // will get folded into a single comparison, so don't emit two blocks.
1687 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1688 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1689 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1690 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1694 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1695 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1696 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1697 Cases[0].CC == Cases[1].CC &&
1698 isa<Constant>(Cases[0].CmpRHS) &&
1699 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1700 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1702 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1709 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1710 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1712 // Update machine-CFG edges.
1713 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1715 if (I.isUnconditional()) {
1716 // Update machine-CFG edges.
1717 BrMBB->addSuccessor(Succ0MBB);
1719 // If this is not a fall-through branch or optimizations are switched off,
1721 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1722 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1723 MVT::Other, getControlRoot(),
1724 DAG.getBasicBlock(Succ0MBB)));
1729 // If this condition is one of the special cases we handle, do special stuff
1731 const Value *CondVal = I.getCondition();
1732 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1734 // If this is a series of conditions that are or'd or and'd together, emit
1735 // this as a sequence of branches instead of setcc's with and/or operations.
1736 // As long as jumps are not expensive, this should improve performance.
1737 // For example, instead of something like:
1750 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1751 Instruction::BinaryOps Opcode = BOp->getOpcode();
1752 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1753 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1754 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1755 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1756 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1757 getEdgeWeight(BrMBB, Succ1MBB));
1758 // If the compares in later blocks need to use values not currently
1759 // exported from this block, export them now. This block should always
1760 // be the first entry.
1761 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1763 // Allow some cases to be rejected.
1764 if (ShouldEmitAsBranches(SwitchCases)) {
1765 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1766 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1767 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1770 // Emit the branch for this block.
1771 visitSwitchCase(SwitchCases[0], BrMBB);
1772 SwitchCases.erase(SwitchCases.begin());
1776 // Okay, we decided not to do this, remove any inserted MBB's and clear
1778 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1779 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1781 SwitchCases.clear();
1785 // Create a CaseBlock record representing this branch.
1786 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1787 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1789 // Use visitSwitchCase to actually insert the fast branch sequence for this
1791 visitSwitchCase(CB, BrMBB);
1794 /// visitSwitchCase - Emits the necessary code to represent a single node in
1795 /// the binary search tree resulting from lowering a switch instruction.
1796 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1797 MachineBasicBlock *SwitchBB) {
1799 SDValue CondLHS = getValue(CB.CmpLHS);
1800 SDLoc dl = getCurSDLoc();
1802 // Build the setcc now.
1804 // Fold "(X == true)" to X and "(X == false)" to !X to
1805 // handle common cases produced by branch lowering.
1806 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1807 CB.CC == ISD::SETEQ)
1809 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1810 CB.CC == ISD::SETEQ) {
1811 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1812 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1814 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1816 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1818 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1819 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1821 SDValue CmpOp = getValue(CB.CmpMHS);
1822 EVT VT = CmpOp.getValueType();
1824 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1825 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1828 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1829 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1830 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1831 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1835 // Update successor info
1836 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1837 // TrueBB and FalseBB are always different unless the incoming IR is
1838 // degenerate. This only happens when running llc on weird IR.
1839 if (CB.TrueBB != CB.FalseBB)
1840 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1842 // If the lhs block is the next block, invert the condition so that we can
1843 // fall through to the lhs instead of the rhs block.
1844 if (CB.TrueBB == NextBlock(SwitchBB)) {
1845 std::swap(CB.TrueBB, CB.FalseBB);
1846 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1847 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1850 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1851 MVT::Other, getControlRoot(), Cond,
1852 DAG.getBasicBlock(CB.TrueBB));
1854 // Insert the false branch. Do this even if it's a fall through branch,
1855 // this makes it easier to do DAG optimizations which require inverting
1856 // the branch condition.
1857 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1858 DAG.getBasicBlock(CB.FalseBB));
1860 DAG.setRoot(BrCond);
1863 /// visitJumpTable - Emit JumpTable node in the current MBB
1864 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1865 // Emit the code for the jump table
1866 assert(JT.Reg != -1U && "Should lower JT Header first!");
1867 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1868 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1870 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1871 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1872 MVT::Other, Index.getValue(1),
1874 DAG.setRoot(BrJumpTable);
1877 /// visitJumpTableHeader - This function emits necessary code to produce index
1878 /// in the JumpTable from switch case.
1879 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1880 JumpTableHeader &JTH,
1881 MachineBasicBlock *SwitchBB) {
1882 SDLoc dl = getCurSDLoc();
1884 // Subtract the lowest switch case value from the value being switched on and
1885 // conditional branch to default mbb if the result is greater than the
1886 // difference between smallest and largest cases.
1887 SDValue SwitchOp = getValue(JTH.SValue);
1888 EVT VT = SwitchOp.getValueType();
1889 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1890 DAG.getConstant(JTH.First, dl, VT));
1892 // The SDNode we just created, which holds the value being switched on minus
1893 // the smallest case value, needs to be copied to a virtual register so it
1894 // can be used as an index into the jump table in a subsequent basic block.
1895 // This value may be smaller or larger than the target's pointer type, and
1896 // therefore require extension or truncating.
1897 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1898 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1900 unsigned JumpTableReg =
1901 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1902 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1903 JumpTableReg, SwitchOp);
1904 JT.Reg = JumpTableReg;
1906 // Emit the range check for the jump table, and branch to the default block
1907 // for the switch statement if the value being switched on exceeds the largest
1908 // case in the switch.
1909 SDValue CMP = DAG.getSetCC(
1910 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1911 Sub.getValueType()),
1912 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1914 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1915 MVT::Other, CopyTo, CMP,
1916 DAG.getBasicBlock(JT.Default));
1918 // Avoid emitting unnecessary branches to the next block.
1919 if (JT.MBB != NextBlock(SwitchBB))
1920 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1921 DAG.getBasicBlock(JT.MBB));
1923 DAG.setRoot(BrCond);
1926 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1927 /// tail spliced into a stack protector check success bb.
1929 /// For a high level explanation of how this fits into the stack protector
1930 /// generation see the comment on the declaration of class
1931 /// StackProtectorDescriptor.
1932 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1933 MachineBasicBlock *ParentBB) {
1935 // First create the loads to the guard/stack slot for the comparison.
1936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1937 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1939 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1940 int FI = MFI->getStackProtectorIndex();
1942 const Value *IRGuard = SPD.getGuard();
1943 SDValue GuardPtr = getValue(IRGuard);
1944 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1946 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1949 SDLoc dl = getCurSDLoc();
1951 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1952 // guard value from the virtual register holding the value. Otherwise, emit a
1953 // volatile load to retrieve the stack guard value.
1954 unsigned GuardReg = SPD.getGuardReg();
1956 if (GuardReg && TLI.useLoadStackGuardNode())
1957 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1960 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1961 GuardPtr, MachinePointerInfo(IRGuard, 0),
1962 true, false, false, Align);
1964 SDValue StackSlot = DAG.getLoad(
1965 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1966 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1967 false, false, Align);
1969 // Perform the comparison via a subtract/getsetcc.
1970 EVT VT = Guard.getValueType();
1971 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1973 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1975 Sub.getValueType()),
1976 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1978 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1979 // branch to failure MBB.
1980 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1981 MVT::Other, StackSlot.getOperand(0),
1982 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1983 // Otherwise branch to success MBB.
1984 SDValue Br = DAG.getNode(ISD::BR, dl,
1986 DAG.getBasicBlock(SPD.getSuccessMBB()));
1991 /// Codegen the failure basic block for a stack protector check.
1993 /// A failure stack protector machine basic block consists simply of a call to
1994 /// __stack_chk_fail().
1996 /// For a high level explanation of how this fits into the stack protector
1997 /// generation see the comment on the declaration of class
1998 /// StackProtectorDescriptor.
2000 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2001 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2003 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2004 None, false, getCurSDLoc(), false, false).second;
2008 /// visitBitTestHeader - This function emits necessary code to produce value
2009 /// suitable for "bit tests"
2010 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2011 MachineBasicBlock *SwitchBB) {
2012 SDLoc dl = getCurSDLoc();
2014 // Subtract the minimum value
2015 SDValue SwitchOp = getValue(B.SValue);
2016 EVT VT = SwitchOp.getValueType();
2017 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2018 DAG.getConstant(B.First, dl, VT));
2021 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2022 SDValue RangeCmp = DAG.getSetCC(
2023 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2024 Sub.getValueType()),
2025 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2027 // Determine the type of the test operands.
2028 bool UsePtrType = false;
2029 if (!TLI.isTypeLegal(VT))
2032 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2033 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2034 // Switch table case range are encoded into series of masks.
2035 // Just use pointer type, it's guaranteed to fit.
2041 VT = TLI.getPointerTy(DAG.getDataLayout());
2042 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2045 B.RegVT = VT.getSimpleVT();
2046 B.Reg = FuncInfo.CreateReg(B.RegVT);
2047 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2049 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2051 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
2052 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
2054 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2055 MVT::Other, CopyTo, RangeCmp,
2056 DAG.getBasicBlock(B.Default));
2058 // Avoid emitting unnecessary branches to the next block.
2059 if (MBB != NextBlock(SwitchBB))
2060 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2061 DAG.getBasicBlock(MBB));
2063 DAG.setRoot(BrRange);
2066 /// visitBitTestCase - this function produces one "bit test"
2067 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2068 MachineBasicBlock* NextMBB,
2069 uint32_t BranchWeightToNext,
2072 MachineBasicBlock *SwitchBB) {
2073 SDLoc dl = getCurSDLoc();
2075 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2077 unsigned PopCount = countPopulation(B.Mask);
2078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2079 if (PopCount == 1) {
2080 // Testing for a single bit; just compare the shift count with what it
2081 // would need to be to shift a 1 bit in that position.
2083 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2084 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2086 } else if (PopCount == BB.Range) {
2087 // There is only one zero bit in the range, test for it directly.
2089 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2090 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2093 // Make desired shift
2094 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2095 DAG.getConstant(1, dl, VT), ShiftOp);
2097 // Emit bit tests and jumps
2098 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2099 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2101 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2102 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2105 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2106 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2107 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2108 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2110 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2111 MVT::Other, getControlRoot(),
2112 Cmp, DAG.getBasicBlock(B.TargetBB));
2114 // Avoid emitting unnecessary branches to the next block.
2115 if (NextMBB != NextBlock(SwitchBB))
2116 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2117 DAG.getBasicBlock(NextMBB));
2122 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2123 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2125 // Retrieve successors. Look through artificial IR level blocks like catchpads
2126 // and catchendpads for successors.
2127 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2128 const BasicBlock *EHPadBB = I.getSuccessor(1);
2130 const Value *Callee(I.getCalledValue());
2131 const Function *Fn = dyn_cast<Function>(Callee);
2132 if (isa<InlineAsm>(Callee))
2134 else if (Fn && Fn->isIntrinsic()) {
2135 switch (Fn->getIntrinsicID()) {
2137 llvm_unreachable("Cannot invoke this intrinsic");
2138 case Intrinsic::donothing:
2139 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2141 case Intrinsic::experimental_patchpoint_void:
2142 case Intrinsic::experimental_patchpoint_i64:
2143 visitPatchpoint(&I, EHPadBB);
2145 case Intrinsic::experimental_gc_statepoint:
2146 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2150 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2152 // If the value of the invoke is used outside of its defining block, make it
2153 // available as a virtual register.
2154 // We already took care of the exported value for the statepoint instruction
2155 // during call to the LowerStatepoint.
2156 if (!isStatepoint(I)) {
2157 CopyToExportRegsIfNeeded(&I);
2160 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
2161 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2162 uint32_t EHPadBBWeight =
2163 BPI ? BPI->getEdgeWeight(InvokeMBB->getBasicBlock(), EHPadBB) : 0;
2164 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBWeight, UnwindDests);
2166 // Update successor info.
2167 addSuccessorWithWeight(InvokeMBB, Return);
2168 for (auto &UnwindDest : UnwindDests) {
2169 UnwindDest.first->setIsEHPad();
2170 addSuccessorWithWeight(InvokeMBB, UnwindDest.first, UnwindDest.second);
2173 // Drop into normal successor.
2174 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2175 MVT::Other, getControlRoot(),
2176 DAG.getBasicBlock(Return)));
2179 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2180 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2183 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2184 assert(FuncInfo.MBB->isEHPad() &&
2185 "Call to landingpad not in landing pad!");
2187 MachineBasicBlock *MBB = FuncInfo.MBB;
2188 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2189 AddLandingPadInfo(LP, MMI, MBB);
2191 // If there aren't registers to copy the values into (e.g., during SjLj
2192 // exceptions), then don't bother to create these DAG nodes.
2193 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2194 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2195 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2196 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2199 SmallVector<EVT, 2> ValueVTs;
2200 SDLoc dl = getCurSDLoc();
2201 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2202 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2204 // Get the two live-in registers as SDValues. The physregs have already been
2205 // copied into virtual registers.
2207 if (FuncInfo.ExceptionPointerVirtReg) {
2208 Ops[0] = DAG.getZExtOrTrunc(
2209 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2210 FuncInfo.ExceptionPointerVirtReg,
2211 TLI.getPointerTy(DAG.getDataLayout())),
2214 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2216 Ops[1] = DAG.getZExtOrTrunc(
2217 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2218 FuncInfo.ExceptionSelectorVirtReg,
2219 TLI.getPointerTy(DAG.getDataLayout())),
2223 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2224 DAG.getVTList(ValueVTs), Ops);
2228 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2230 for (const CaseCluster &CC : Clusters)
2231 assert(CC.Low == CC.High && "Input clusters must be single-case");
2234 std::sort(Clusters.begin(), Clusters.end(),
2235 [](const CaseCluster &a, const CaseCluster &b) {
2236 return a.Low->getValue().slt(b.Low->getValue());
2239 // Merge adjacent clusters with the same destination.
2240 const unsigned N = Clusters.size();
2241 unsigned DstIndex = 0;
2242 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2243 CaseCluster &CC = Clusters[SrcIndex];
2244 const ConstantInt *CaseVal = CC.Low;
2245 MachineBasicBlock *Succ = CC.MBB;
2247 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2248 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2249 // If this case has the same successor and is a neighbour, merge it into
2250 // the previous cluster.
2251 Clusters[DstIndex - 1].High = CaseVal;
2252 Clusters[DstIndex - 1].Weight += CC.Weight;
2253 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2255 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2256 sizeof(Clusters[SrcIndex]));
2259 Clusters.resize(DstIndex);
2262 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2263 MachineBasicBlock *Last) {
2265 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2266 if (JTCases[i].first.HeaderBB == First)
2267 JTCases[i].first.HeaderBB = Last;
2269 // Update BitTestCases.
2270 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2271 if (BitTestCases[i].Parent == First)
2272 BitTestCases[i].Parent = Last;
2275 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2276 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2278 // Update machine-CFG edges with unique successors.
2279 SmallSet<BasicBlock*, 32> Done;
2280 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2281 BasicBlock *BB = I.getSuccessor(i);
2282 bool Inserted = Done.insert(BB).second;
2286 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2287 addSuccessorWithWeight(IndirectBrMBB, Succ);
2290 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2291 MVT::Other, getControlRoot(),
2292 getValue(I.getAddress())));
2295 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2296 if (DAG.getTarget().Options.TrapUnreachable)
2298 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2301 void SelectionDAGBuilder::visitFSub(const User &I) {
2302 // -0.0 - X --> fneg
2303 Type *Ty = I.getType();
2304 if (isa<Constant>(I.getOperand(0)) &&
2305 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2306 SDValue Op2 = getValue(I.getOperand(1));
2307 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2308 Op2.getValueType(), Op2));
2312 visitBinary(I, ISD::FSUB);
2315 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2316 SDValue Op1 = getValue(I.getOperand(0));
2317 SDValue Op2 = getValue(I.getOperand(1));
2324 if (const OverflowingBinaryOperator *OFBinOp =
2325 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2326 nuw = OFBinOp->hasNoUnsignedWrap();
2327 nsw = OFBinOp->hasNoSignedWrap();
2329 if (const PossiblyExactOperator *ExactOp =
2330 dyn_cast<const PossiblyExactOperator>(&I))
2331 exact = ExactOp->isExact();
2332 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2333 FMF = FPOp->getFastMathFlags();
2336 Flags.setExact(exact);
2337 Flags.setNoSignedWrap(nsw);
2338 Flags.setNoUnsignedWrap(nuw);
2339 if (EnableFMFInDAG) {
2340 Flags.setAllowReciprocal(FMF.allowReciprocal());
2341 Flags.setNoInfs(FMF.noInfs());
2342 Flags.setNoNaNs(FMF.noNaNs());
2343 Flags.setNoSignedZeros(FMF.noSignedZeros());
2344 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2346 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2348 setValue(&I, BinNodeValue);
2351 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2352 SDValue Op1 = getValue(I.getOperand(0));
2353 SDValue Op2 = getValue(I.getOperand(1));
2355 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2356 Op2.getValueType(), DAG.getDataLayout());
2358 // Coerce the shift amount to the right type if we can.
2359 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2360 unsigned ShiftSize = ShiftTy.getSizeInBits();
2361 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2362 SDLoc DL = getCurSDLoc();
2364 // If the operand is smaller than the shift count type, promote it.
2365 if (ShiftSize > Op2Size)
2366 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2368 // If the operand is larger than the shift count type but the shift
2369 // count type has enough bits to represent any shift value, truncate
2370 // it now. This is a common case and it exposes the truncate to
2371 // optimization early.
2372 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2373 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2374 // Otherwise we'll need to temporarily settle for some other convenient
2375 // type. Type legalization will make adjustments once the shiftee is split.
2377 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2384 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2386 if (const OverflowingBinaryOperator *OFBinOp =
2387 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2388 nuw = OFBinOp->hasNoUnsignedWrap();
2389 nsw = OFBinOp->hasNoSignedWrap();
2391 if (const PossiblyExactOperator *ExactOp =
2392 dyn_cast<const PossiblyExactOperator>(&I))
2393 exact = ExactOp->isExact();
2396 Flags.setExact(exact);
2397 Flags.setNoSignedWrap(nsw);
2398 Flags.setNoUnsignedWrap(nuw);
2399 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2404 void SelectionDAGBuilder::visitSDiv(const User &I) {
2405 SDValue Op1 = getValue(I.getOperand(0));
2406 SDValue Op2 = getValue(I.getOperand(1));
2409 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2410 cast<PossiblyExactOperator>(&I)->isExact());
2411 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2415 void SelectionDAGBuilder::visitICmp(const User &I) {
2416 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2417 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2418 predicate = IC->getPredicate();
2419 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2420 predicate = ICmpInst::Predicate(IC->getPredicate());
2421 SDValue Op1 = getValue(I.getOperand(0));
2422 SDValue Op2 = getValue(I.getOperand(1));
2423 ISD::CondCode Opcode = getICmpCondCode(predicate);
2425 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2427 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2430 void SelectionDAGBuilder::visitFCmp(const User &I) {
2431 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2432 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2433 predicate = FC->getPredicate();
2434 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2435 predicate = FCmpInst::Predicate(FC->getPredicate());
2436 SDValue Op1 = getValue(I.getOperand(0));
2437 SDValue Op2 = getValue(I.getOperand(1));
2438 ISD::CondCode Condition = getFCmpCondCode(predicate);
2440 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2441 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2442 // further optimization, but currently FMF is only applicable to binary nodes.
2443 if (TM.Options.NoNaNsFPMath)
2444 Condition = getFCmpCodeWithoutNaN(Condition);
2445 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2447 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2450 void SelectionDAGBuilder::visitSelect(const User &I) {
2451 SmallVector<EVT, 4> ValueVTs;
2452 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2454 unsigned NumValues = ValueVTs.size();
2455 if (NumValues == 0) return;
2457 SmallVector<SDValue, 4> Values(NumValues);
2458 SDValue Cond = getValue(I.getOperand(0));
2459 SDValue LHSVal = getValue(I.getOperand(1));
2460 SDValue RHSVal = getValue(I.getOperand(2));
2461 auto BaseOps = {Cond};
2462 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2463 ISD::VSELECT : ISD::SELECT;
2465 // Min/max matching is only viable if all output VTs are the same.
2466 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2467 EVT VT = ValueVTs[0];
2468 LLVMContext &Ctx = *DAG.getContext();
2469 auto &TLI = DAG.getTargetLoweringInfo();
2470 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2471 VT = TLI.getTypeToTransformTo(Ctx, VT);
2474 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2475 ISD::NodeType Opc = ISD::DELETED_NODE;
2476 switch (SPR.Flavor) {
2477 case SPF_UMAX: Opc = ISD::UMAX; break;
2478 case SPF_UMIN: Opc = ISD::UMIN; break;
2479 case SPF_SMAX: Opc = ISD::SMAX; break;
2480 case SPF_SMIN: Opc = ISD::SMIN; break;
2482 switch (SPR.NaNBehavior) {
2483 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2484 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2485 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2486 case SPNB_RETURNS_ANY:
2487 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2493 switch (SPR.NaNBehavior) {
2494 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2495 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2496 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2497 case SPNB_RETURNS_ANY:
2498 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2506 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2507 // If the underlying comparison instruction is used by any other instruction,
2508 // the consumed instructions won't be destroyed, so it is not profitable
2509 // to convert to a min/max.
2510 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2512 LHSVal = getValue(LHS);
2513 RHSVal = getValue(RHS);
2518 for (unsigned i = 0; i != NumValues; ++i) {
2519 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2520 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2521 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2522 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2523 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2527 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2528 DAG.getVTList(ValueVTs), Values));
2531 void SelectionDAGBuilder::visitTrunc(const User &I) {
2532 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2533 SDValue N = getValue(I.getOperand(0));
2534 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2536 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2539 void SelectionDAGBuilder::visitZExt(const User &I) {
2540 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2541 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2542 SDValue N = getValue(I.getOperand(0));
2543 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2545 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2548 void SelectionDAGBuilder::visitSExt(const User &I) {
2549 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2550 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2551 SDValue N = getValue(I.getOperand(0));
2552 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2554 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2557 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2558 // FPTrunc is never a no-op cast, no need to check
2559 SDValue N = getValue(I.getOperand(0));
2560 SDLoc dl = getCurSDLoc();
2561 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2562 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2563 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2564 DAG.getTargetConstant(
2565 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2568 void SelectionDAGBuilder::visitFPExt(const User &I) {
2569 // FPExt is never a no-op cast, no need to check
2570 SDValue N = getValue(I.getOperand(0));
2571 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2573 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2576 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2577 // FPToUI is never a no-op cast, no need to check
2578 SDValue N = getValue(I.getOperand(0));
2579 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2581 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2584 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2585 // FPToSI is never a no-op cast, no need to check
2586 SDValue N = getValue(I.getOperand(0));
2587 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2589 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2592 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2593 // UIToFP is never a no-op cast, no need to check
2594 SDValue N = getValue(I.getOperand(0));
2595 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2597 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2600 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2601 // SIToFP is never a no-op cast, no need to check
2602 SDValue N = getValue(I.getOperand(0));
2603 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2605 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2608 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2609 // What to do depends on the size of the integer and the size of the pointer.
2610 // We can either truncate, zero extend, or no-op, accordingly.
2611 SDValue N = getValue(I.getOperand(0));
2612 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2614 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2617 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2618 // What to do depends on the size of the integer and the size of the pointer.
2619 // We can either truncate, zero extend, or no-op, accordingly.
2620 SDValue N = getValue(I.getOperand(0));
2621 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2623 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2626 void SelectionDAGBuilder::visitBitCast(const User &I) {
2627 SDValue N = getValue(I.getOperand(0));
2628 SDLoc dl = getCurSDLoc();
2629 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2632 // BitCast assures us that source and destination are the same size so this is
2633 // either a BITCAST or a no-op.
2634 if (DestVT != N.getValueType())
2635 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2636 DestVT, N)); // convert types.
2637 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2638 // might fold any kind of constant expression to an integer constant and that
2639 // is not what we are looking for. Only regcognize a bitcast of a genuine
2640 // constant integer as an opaque constant.
2641 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2642 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2645 setValue(&I, N); // noop cast.
2648 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2650 const Value *SV = I.getOperand(0);
2651 SDValue N = getValue(SV);
2652 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2654 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2655 unsigned DestAS = I.getType()->getPointerAddressSpace();
2657 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2658 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2663 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2665 SDValue InVec = getValue(I.getOperand(0));
2666 SDValue InVal = getValue(I.getOperand(1));
2667 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2668 TLI.getVectorIdxTy(DAG.getDataLayout()));
2669 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2670 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2671 InVec, InVal, InIdx));
2674 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2676 SDValue InVec = getValue(I.getOperand(0));
2677 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2678 TLI.getVectorIdxTy(DAG.getDataLayout()));
2679 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2680 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2684 // Utility for visitShuffleVector - Return true if every element in Mask,
2685 // beginning from position Pos and ending in Pos+Size, falls within the
2686 // specified sequential range [L, L+Pos). or is undef.
2687 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2688 unsigned Pos, unsigned Size, int Low) {
2689 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2690 if (Mask[i] >= 0 && Mask[i] != Low)
2695 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2696 SDValue Src1 = getValue(I.getOperand(0));
2697 SDValue Src2 = getValue(I.getOperand(1));
2699 SmallVector<int, 8> Mask;
2700 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2701 unsigned MaskNumElts = Mask.size();
2703 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2704 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2705 EVT SrcVT = Src1.getValueType();
2706 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2708 if (SrcNumElts == MaskNumElts) {
2709 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2714 // Normalize the shuffle vector since mask and vector length don't match.
2715 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2716 // Mask is longer than the source vectors and is a multiple of the source
2717 // vectors. We can use concatenate vector to make the mask and vectors
2719 if (SrcNumElts*2 == MaskNumElts) {
2720 // First check for Src1 in low and Src2 in high
2721 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2722 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2723 // The shuffle is concatenating two vectors together.
2724 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2728 // Then check for Src2 in low and Src1 in high
2729 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2730 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2731 // The shuffle is concatenating two vectors together.
2732 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2738 // Pad both vectors with undefs to make them the same length as the mask.
2739 unsigned NumConcat = MaskNumElts / SrcNumElts;
2740 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2741 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2742 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2744 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2745 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2749 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2750 getCurSDLoc(), VT, MOps1);
2751 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2752 getCurSDLoc(), VT, MOps2);
2754 // Readjust mask for new input vector length.
2755 SmallVector<int, 8> MappedOps;
2756 for (unsigned i = 0; i != MaskNumElts; ++i) {
2758 if (Idx >= (int)SrcNumElts)
2759 Idx -= SrcNumElts - MaskNumElts;
2760 MappedOps.push_back(Idx);
2763 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2768 if (SrcNumElts > MaskNumElts) {
2769 // Analyze the access pattern of the vector to see if we can extract
2770 // two subvectors and do the shuffle. The analysis is done by calculating
2771 // the range of elements the mask access on both vectors.
2772 int MinRange[2] = { static_cast<int>(SrcNumElts),
2773 static_cast<int>(SrcNumElts)};
2774 int MaxRange[2] = {-1, -1};
2776 for (unsigned i = 0; i != MaskNumElts; ++i) {
2782 if (Idx >= (int)SrcNumElts) {
2786 if (Idx > MaxRange[Input])
2787 MaxRange[Input] = Idx;
2788 if (Idx < MinRange[Input])
2789 MinRange[Input] = Idx;
2792 // Check if the access is smaller than the vector size and can we find
2793 // a reasonable extract index.
2794 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2796 int StartIdx[2]; // StartIdx to extract from
2797 for (unsigned Input = 0; Input < 2; ++Input) {
2798 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2799 RangeUse[Input] = 0; // Unused
2800 StartIdx[Input] = 0;
2804 // Find a good start index that is a multiple of the mask length. Then
2805 // see if the rest of the elements are in range.
2806 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2807 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2808 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2809 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2812 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2813 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2816 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2817 // Extract appropriate subvector and generate a vector shuffle
2818 for (unsigned Input = 0; Input < 2; ++Input) {
2819 SDValue &Src = Input == 0 ? Src1 : Src2;
2820 if (RangeUse[Input] == 0)
2821 Src = DAG.getUNDEF(VT);
2823 SDLoc dl = getCurSDLoc();
2825 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2826 DAG.getConstant(StartIdx[Input], dl,
2827 TLI.getVectorIdxTy(DAG.getDataLayout())));
2831 // Calculate new mask.
2832 SmallVector<int, 8> MappedOps;
2833 for (unsigned i = 0; i != MaskNumElts; ++i) {
2836 if (Idx < (int)SrcNumElts)
2839 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2841 MappedOps.push_back(Idx);
2844 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2850 // We can't use either concat vectors or extract subvectors so fall back to
2851 // replacing the shuffle with extract and build vector.
2852 // to insert and build vector.
2853 EVT EltVT = VT.getVectorElementType();
2854 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2855 SDLoc dl = getCurSDLoc();
2856 SmallVector<SDValue,8> Ops;
2857 for (unsigned i = 0; i != MaskNumElts; ++i) {
2862 Res = DAG.getUNDEF(EltVT);
2864 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2865 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2867 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2868 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2874 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2877 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2878 const Value *Op0 = I.getOperand(0);
2879 const Value *Op1 = I.getOperand(1);
2880 Type *AggTy = I.getType();
2881 Type *ValTy = Op1->getType();
2882 bool IntoUndef = isa<UndefValue>(Op0);
2883 bool FromUndef = isa<UndefValue>(Op1);
2885 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2888 SmallVector<EVT, 4> AggValueVTs;
2889 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2890 SmallVector<EVT, 4> ValValueVTs;
2891 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2893 unsigned NumAggValues = AggValueVTs.size();
2894 unsigned NumValValues = ValValueVTs.size();
2895 SmallVector<SDValue, 4> Values(NumAggValues);
2897 // Ignore an insertvalue that produces an empty object
2898 if (!NumAggValues) {
2899 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2903 SDValue Agg = getValue(Op0);
2905 // Copy the beginning value(s) from the original aggregate.
2906 for (; i != LinearIndex; ++i)
2907 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2908 SDValue(Agg.getNode(), Agg.getResNo() + i);
2909 // Copy values from the inserted value(s).
2911 SDValue Val = getValue(Op1);
2912 for (; i != LinearIndex + NumValValues; ++i)
2913 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2914 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2916 // Copy remaining value(s) from the original aggregate.
2917 for (; i != NumAggValues; ++i)
2918 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2919 SDValue(Agg.getNode(), Agg.getResNo() + i);
2921 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2922 DAG.getVTList(AggValueVTs), Values));
2925 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2926 const Value *Op0 = I.getOperand(0);
2927 Type *AggTy = Op0->getType();
2928 Type *ValTy = I.getType();
2929 bool OutOfUndef = isa<UndefValue>(Op0);
2931 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2933 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2934 SmallVector<EVT, 4> ValValueVTs;
2935 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2937 unsigned NumValValues = ValValueVTs.size();
2939 // Ignore a extractvalue that produces an empty object
2940 if (!NumValValues) {
2941 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2945 SmallVector<SDValue, 4> Values(NumValValues);
2947 SDValue Agg = getValue(Op0);
2948 // Copy out the selected value(s).
2949 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2950 Values[i - LinearIndex] =
2952 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2953 SDValue(Agg.getNode(), Agg.getResNo() + i);
2955 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2956 DAG.getVTList(ValValueVTs), Values));
2959 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2960 Value *Op0 = I.getOperand(0);
2961 // Note that the pointer operand may be a vector of pointers. Take the scalar
2962 // element which holds a pointer.
2963 Type *Ty = Op0->getType()->getScalarType();
2964 unsigned AS = Ty->getPointerAddressSpace();
2965 SDValue N = getValue(Op0);
2966 SDLoc dl = getCurSDLoc();
2968 // Normalize Vector GEP - all scalar operands should be converted to the
2970 unsigned VectorWidth = I.getType()->isVectorTy() ?
2971 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2973 if (VectorWidth && !N.getValueType().isVector()) {
2974 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2975 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2976 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2978 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2980 const Value *Idx = *OI;
2981 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2982 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2985 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2986 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2987 DAG.getConstant(Offset, dl, N.getValueType()));
2990 Ty = StTy->getElementType(Field);
2992 Ty = cast<SequentialType>(Ty)->getElementType();
2994 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2995 unsigned PtrSize = PtrTy.getSizeInBits();
2996 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2998 // If this is a scalar constant or a splat vector of constants,
2999 // handle it quickly.
3000 const auto *CI = dyn_cast<ConstantInt>(Idx);
3001 if (!CI && isa<ConstantDataVector>(Idx) &&
3002 cast<ConstantDataVector>(Idx)->getSplatValue())
3003 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3008 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3009 SDValue OffsVal = VectorWidth ?
3010 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
3011 DAG.getConstant(Offs, dl, PtrTy);
3012 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
3016 // N = N + Idx * ElementSize;
3017 SDValue IdxN = getValue(Idx);
3019 if (!IdxN.getValueType().isVector() && VectorWidth) {
3020 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3021 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
3022 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3024 // If the index is smaller or larger than intptr_t, truncate or extend
3026 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3028 // If this is a multiply by a power of two, turn it into a shl
3029 // immediately. This is a very common case.
3030 if (ElementSize != 1) {
3031 if (ElementSize.isPowerOf2()) {
3032 unsigned Amt = ElementSize.logBase2();
3033 IdxN = DAG.getNode(ISD::SHL, dl,
3034 N.getValueType(), IdxN,
3035 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3037 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3038 IdxN = DAG.getNode(ISD::MUL, dl,
3039 N.getValueType(), IdxN, Scale);
3043 N = DAG.getNode(ISD::ADD, dl,
3044 N.getValueType(), N, IdxN);
3051 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3052 // If this is a fixed sized alloca in the entry block of the function,
3053 // allocate it statically on the stack.
3054 if (FuncInfo.StaticAllocaMap.count(&I))
3055 return; // getValue will auto-populate this.
3057 SDLoc dl = getCurSDLoc();
3058 Type *Ty = I.getAllocatedType();
3059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3060 auto &DL = DAG.getDataLayout();
3061 uint64_t TySize = DL.getTypeAllocSize(Ty);
3063 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3065 SDValue AllocSize = getValue(I.getArraySize());
3067 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3068 if (AllocSize.getValueType() != IntPtr)
3069 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3071 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3073 DAG.getConstant(TySize, dl, IntPtr));
3075 // Handle alignment. If the requested alignment is less than or equal to
3076 // the stack alignment, ignore it. If the size is greater than or equal to
3077 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3078 unsigned StackAlign =
3079 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3080 if (Align <= StackAlign)
3083 // Round the size of the allocation up to the stack alignment size
3084 // by add SA-1 to the size.
3085 AllocSize = DAG.getNode(ISD::ADD, dl,
3086 AllocSize.getValueType(), AllocSize,
3087 DAG.getIntPtrConstant(StackAlign - 1, dl));
3089 // Mask out the low bits for alignment purposes.
3090 AllocSize = DAG.getNode(ISD::AND, dl,
3091 AllocSize.getValueType(), AllocSize,
3092 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3095 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3096 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3097 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3099 DAG.setRoot(DSA.getValue(1));
3101 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3104 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3106 return visitAtomicLoad(I);
3108 const Value *SV = I.getOperand(0);
3109 SDValue Ptr = getValue(SV);
3111 Type *Ty = I.getType();
3113 bool isVolatile = I.isVolatile();
3114 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3116 // The IR notion of invariant_load only guarantees that all *non-faulting*
3117 // invariant loads result in the same value. The MI notion of invariant load
3118 // guarantees that the load can be legally moved to any location within its
3119 // containing function. The MI notion of invariant_load is stronger than the
3120 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3121 // with a guarantee that the location being loaded from is dereferenceable
3122 // throughout the function's lifetime.
3124 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3125 isDereferenceablePointer(SV, DAG.getDataLayout());
3126 unsigned Alignment = I.getAlignment();
3129 I.getAAMetadata(AAInfo);
3130 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3132 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3133 SmallVector<EVT, 4> ValueVTs;
3134 SmallVector<uint64_t, 4> Offsets;
3135 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3136 unsigned NumValues = ValueVTs.size();
3141 bool ConstantMemory = false;
3142 if (isVolatile || NumValues > MaxParallelChains)
3143 // Serialize volatile loads with other side effects.
3145 else if (AA->pointsToConstantMemory(MemoryLocation(
3146 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3147 // Do not serialize (non-volatile) loads of constant memory with anything.
3148 Root = DAG.getEntryNode();
3149 ConstantMemory = true;
3151 // Do not serialize non-volatile loads against each other.
3152 Root = DAG.getRoot();
3155 SDLoc dl = getCurSDLoc();
3158 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3160 SmallVector<SDValue, 4> Values(NumValues);
3161 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3162 EVT PtrVT = Ptr.getValueType();
3163 unsigned ChainI = 0;
3164 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3165 // Serializing loads here may result in excessive register pressure, and
3166 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3167 // could recover a bit by hoisting nodes upward in the chain by recognizing
3168 // they are side-effect free or do not alias. The optimizer should really
3169 // avoid this case by converting large object/array copies to llvm.memcpy
3170 // (MaxParallelChains should always remain as failsafe).
3171 if (ChainI == MaxParallelChains) {
3172 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3173 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3174 makeArrayRef(Chains.data(), ChainI));
3178 SDValue A = DAG.getNode(ISD::ADD, dl,
3180 DAG.getConstant(Offsets[i], dl, PtrVT));
3181 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3182 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3183 isNonTemporal, isInvariant, Alignment, AAInfo,
3187 Chains[ChainI] = L.getValue(1);
3190 if (!ConstantMemory) {
3191 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3192 makeArrayRef(Chains.data(), ChainI));
3196 PendingLoads.push_back(Chain);
3199 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3200 DAG.getVTList(ValueVTs), Values));
3203 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3205 return visitAtomicStore(I);
3207 const Value *SrcV = I.getOperand(0);
3208 const Value *PtrV = I.getOperand(1);
3210 SmallVector<EVT, 4> ValueVTs;
3211 SmallVector<uint64_t, 4> Offsets;
3212 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3213 SrcV->getType(), ValueVTs, &Offsets);
3214 unsigned NumValues = ValueVTs.size();
3218 // Get the lowered operands. Note that we do this after
3219 // checking if NumResults is zero, because with zero results
3220 // the operands won't have values in the map.
3221 SDValue Src = getValue(SrcV);
3222 SDValue Ptr = getValue(PtrV);
3224 SDValue Root = getRoot();
3225 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3226 EVT PtrVT = Ptr.getValueType();
3227 bool isVolatile = I.isVolatile();
3228 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3229 unsigned Alignment = I.getAlignment();
3230 SDLoc dl = getCurSDLoc();
3233 I.getAAMetadata(AAInfo);
3235 unsigned ChainI = 0;
3236 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3237 // See visitLoad comments.
3238 if (ChainI == MaxParallelChains) {
3239 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3240 makeArrayRef(Chains.data(), ChainI));
3244 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3245 DAG.getConstant(Offsets[i], dl, PtrVT));
3246 SDValue St = DAG.getStore(Root, dl,
3247 SDValue(Src.getNode(), Src.getResNo() + i),
3248 Add, MachinePointerInfo(PtrV, Offsets[i]),
3249 isVolatile, isNonTemporal, Alignment, AAInfo);
3250 Chains[ChainI] = St;
3253 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3254 makeArrayRef(Chains.data(), ChainI));
3255 DAG.setRoot(StoreNode);
3258 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3259 SDLoc sdl = getCurSDLoc();
3261 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3262 Value *PtrOperand = I.getArgOperand(1);
3263 SDValue Ptr = getValue(PtrOperand);
3264 SDValue Src0 = getValue(I.getArgOperand(0));
3265 SDValue Mask = getValue(I.getArgOperand(3));
3266 EVT VT = Src0.getValueType();
3267 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3269 Alignment = DAG.getEVTAlignment(VT);
3272 I.getAAMetadata(AAInfo);
3274 MachineMemOperand *MMO =
3275 DAG.getMachineFunction().
3276 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3277 MachineMemOperand::MOStore, VT.getStoreSize(),
3279 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3281 DAG.setRoot(StoreNode);
3282 setValue(&I, StoreNode);
3285 // Get a uniform base for the Gather/Scatter intrinsic.
3286 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3287 // We try to represent it as a base pointer + vector of indices.
3288 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3289 // The first operand of the GEP may be a single pointer or a vector of pointers
3291 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3293 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3294 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3296 // When the first GEP operand is a single pointer - it is the uniform base we
3297 // are looking for. If first operand of the GEP is a splat vector - we
3298 // extract the spalt value and use it as a uniform base.
3299 // In all other cases the function returns 'false'.
3301 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3302 SelectionDAGBuilder* SDB) {
3304 SelectionDAG& DAG = SDB->DAG;
3305 LLVMContext &Context = *DAG.getContext();
3307 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3308 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3309 if (!GEP || GEP->getNumOperands() > 2)
3312 Value *GEPPtr = GEP->getPointerOperand();
3313 if (!GEPPtr->getType()->isVectorTy())
3315 else if (!(Ptr = getSplatValue(GEPPtr)))
3318 Value *IndexVal = GEP->getOperand(1);
3320 // The operands of the GEP may be defined in another basic block.
3321 // In this case we'll not find nodes for the operands.
3322 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3325 Base = SDB->getValue(Ptr);
3326 Index = SDB->getValue(IndexVal);
3328 // Suppress sign extension.
3329 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3330 if (SDB->findValue(Sext->getOperand(0))) {
3331 IndexVal = Sext->getOperand(0);
3332 Index = SDB->getValue(IndexVal);
3335 if (!Index.getValueType().isVector()) {
3336 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3337 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3338 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3339 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3344 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3345 SDLoc sdl = getCurSDLoc();
3347 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3348 Value *Ptr = I.getArgOperand(1);
3349 SDValue Src0 = getValue(I.getArgOperand(0));
3350 SDValue Mask = getValue(I.getArgOperand(3));
3351 EVT VT = Src0.getValueType();
3352 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3354 Alignment = DAG.getEVTAlignment(VT);
3355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3358 I.getAAMetadata(AAInfo);
3362 Value *BasePtr = Ptr;
3363 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3365 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3366 MachineMemOperand *MMO = DAG.getMachineFunction().
3367 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3368 MachineMemOperand::MOStore, VT.getStoreSize(),
3371 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3372 Index = getValue(Ptr);
3374 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3375 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3377 DAG.setRoot(Scatter);
3378 setValue(&I, Scatter);
3381 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3382 SDLoc sdl = getCurSDLoc();
3384 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3385 Value *PtrOperand = I.getArgOperand(0);
3386 SDValue Ptr = getValue(PtrOperand);
3387 SDValue Src0 = getValue(I.getArgOperand(3));
3388 SDValue Mask = getValue(I.getArgOperand(2));
3390 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3391 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3392 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3394 Alignment = DAG.getEVTAlignment(VT);
3397 I.getAAMetadata(AAInfo);
3398 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3400 SDValue InChain = DAG.getRoot();
3401 if (AA->pointsToConstantMemory(MemoryLocation(
3402 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3404 // Do not serialize (non-volatile) loads of constant memory with anything.
3405 InChain = DAG.getEntryNode();
3408 MachineMemOperand *MMO =
3409 DAG.getMachineFunction().
3410 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3411 MachineMemOperand::MOLoad, VT.getStoreSize(),
3412 Alignment, AAInfo, Ranges);
3414 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3416 SDValue OutChain = Load.getValue(1);
3417 DAG.setRoot(OutChain);
3421 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3422 SDLoc sdl = getCurSDLoc();
3424 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3425 Value *Ptr = I.getArgOperand(0);
3426 SDValue Src0 = getValue(I.getArgOperand(3));
3427 SDValue Mask = getValue(I.getArgOperand(2));
3429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3430 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3431 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3433 Alignment = DAG.getEVTAlignment(VT);
3436 I.getAAMetadata(AAInfo);
3437 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3439 SDValue Root = DAG.getRoot();
3442 Value *BasePtr = Ptr;
3443 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3444 bool ConstantMemory = false;
3446 AA->pointsToConstantMemory(MemoryLocation(
3447 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3449 // Do not serialize (non-volatile) loads of constant memory with anything.
3450 Root = DAG.getEntryNode();
3451 ConstantMemory = true;
3454 MachineMemOperand *MMO =
3455 DAG.getMachineFunction().
3456 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3457 MachineMemOperand::MOLoad, VT.getStoreSize(),
3458 Alignment, AAInfo, Ranges);
3461 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3462 Index = getValue(Ptr);
3464 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3465 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3468 SDValue OutChain = Gather.getValue(1);
3469 if (!ConstantMemory)
3470 PendingLoads.push_back(OutChain);
3471 setValue(&I, Gather);
3474 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3475 SDLoc dl = getCurSDLoc();
3476 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3477 AtomicOrdering FailureOrder = I.getFailureOrdering();
3478 SynchronizationScope Scope = I.getSynchScope();
3480 SDValue InChain = getRoot();
3482 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3483 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3484 SDValue L = DAG.getAtomicCmpSwap(
3485 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3486 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3487 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3488 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3490 SDValue OutChain = L.getValue(2);
3493 DAG.setRoot(OutChain);
3496 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3497 SDLoc dl = getCurSDLoc();
3499 switch (I.getOperation()) {
3500 default: llvm_unreachable("Unknown atomicrmw operation");
3501 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3502 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3503 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3504 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3505 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3506 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3507 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3508 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3509 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3510 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3511 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3513 AtomicOrdering Order = I.getOrdering();
3514 SynchronizationScope Scope = I.getSynchScope();
3516 SDValue InChain = getRoot();
3519 DAG.getAtomic(NT, dl,
3520 getValue(I.getValOperand()).getSimpleValueType(),
3522 getValue(I.getPointerOperand()),
3523 getValue(I.getValOperand()),
3524 I.getPointerOperand(),
3525 /* Alignment=*/ 0, Order, Scope);
3527 SDValue OutChain = L.getValue(1);
3530 DAG.setRoot(OutChain);
3533 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3534 SDLoc dl = getCurSDLoc();
3535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3538 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3539 TLI.getPointerTy(DAG.getDataLayout()));
3540 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3541 TLI.getPointerTy(DAG.getDataLayout()));
3542 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3545 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3546 SDLoc dl = getCurSDLoc();
3547 AtomicOrdering Order = I.getOrdering();
3548 SynchronizationScope Scope = I.getSynchScope();
3550 SDValue InChain = getRoot();
3552 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3553 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3555 if (I.getAlignment() < VT.getSizeInBits() / 8)
3556 report_fatal_error("Cannot generate unaligned atomic load");
3558 MachineMemOperand *MMO =
3559 DAG.getMachineFunction().
3560 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3561 MachineMemOperand::MOVolatile |
3562 MachineMemOperand::MOLoad,
3564 I.getAlignment() ? I.getAlignment() :
3565 DAG.getEVTAlignment(VT));
3567 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3569 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3570 getValue(I.getPointerOperand()), MMO,
3573 SDValue OutChain = L.getValue(1);
3576 DAG.setRoot(OutChain);
3579 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3580 SDLoc dl = getCurSDLoc();
3582 AtomicOrdering Order = I.getOrdering();
3583 SynchronizationScope Scope = I.getSynchScope();
3585 SDValue InChain = getRoot();
3587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3589 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3591 if (I.getAlignment() < VT.getSizeInBits() / 8)
3592 report_fatal_error("Cannot generate unaligned atomic store");
3595 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3597 getValue(I.getPointerOperand()),
3598 getValue(I.getValueOperand()),
3599 I.getPointerOperand(), I.getAlignment(),
3602 DAG.setRoot(OutChain);
3605 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3607 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3608 unsigned Intrinsic) {
3609 bool HasChain = !I.doesNotAccessMemory();
3610 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3612 // Build the operand list.
3613 SmallVector<SDValue, 8> Ops;
3614 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3616 // We don't need to serialize loads against other loads.
3617 Ops.push_back(DAG.getRoot());
3619 Ops.push_back(getRoot());
3623 // Info is set by getTgtMemInstrinsic
3624 TargetLowering::IntrinsicInfo Info;
3625 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3626 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3628 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3629 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3630 Info.opc == ISD::INTRINSIC_W_CHAIN)
3631 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3632 TLI.getPointerTy(DAG.getDataLayout())));
3634 // Add all operands of the call to the operand list.
3635 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3636 SDValue Op = getValue(I.getArgOperand(i));
3640 SmallVector<EVT, 4> ValueVTs;
3641 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3644 ValueVTs.push_back(MVT::Other);
3646 SDVTList VTs = DAG.getVTList(ValueVTs);
3650 if (IsTgtIntrinsic) {
3651 // This is target intrinsic that touches memory
3652 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3653 VTs, Ops, Info.memVT,
3654 MachinePointerInfo(Info.ptrVal, Info.offset),
3655 Info.align, Info.vol,
3656 Info.readMem, Info.writeMem, Info.size);
3657 } else if (!HasChain) {
3658 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3659 } else if (!I.getType()->isVoidTy()) {
3660 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3662 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3666 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3668 PendingLoads.push_back(Chain);
3673 if (!I.getType()->isVoidTy()) {
3674 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3675 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3676 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3679 setValue(&I, Result);
3683 /// GetSignificand - Get the significand and build it into a floating-point
3684 /// number with exponent of 1:
3686 /// Op = (Op & 0x007fffff) | 0x3f800000;
3688 /// where Op is the hexadecimal representation of floating point value.
3690 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3691 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3692 DAG.getConstant(0x007fffff, dl, MVT::i32));
3693 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3694 DAG.getConstant(0x3f800000, dl, MVT::i32));
3695 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3698 /// GetExponent - Get the exponent:
3700 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3702 /// where Op is the hexadecimal representation of floating point value.
3704 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3706 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3707 DAG.getConstant(0x7f800000, dl, MVT::i32));
3708 SDValue t1 = DAG.getNode(
3709 ISD::SRL, dl, MVT::i32, t0,
3710 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3711 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3712 DAG.getConstant(127, dl, MVT::i32));
3713 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3716 /// getF32Constant - Get 32-bit floating point constant.
3718 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3719 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3723 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3724 SelectionDAG &DAG) {
3725 // TODO: What fast-math-flags should be set on the floating-point nodes?
3727 // IntegerPartOfX = ((int32_t)(t0);
3728 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3730 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3731 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3732 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3734 // IntegerPartOfX <<= 23;
3735 IntegerPartOfX = DAG.getNode(
3736 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3737 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3738 DAG.getDataLayout())));
3740 SDValue TwoToFractionalPartOfX;
3741 if (LimitFloatPrecision <= 6) {
3742 // For floating-point precision of 6:
3744 // TwoToFractionalPartOfX =
3746 // (0.735607626f + 0.252464424f * x) * x;
3748 // error 0.0144103317, which is 6 bits
3749 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3750 getF32Constant(DAG, 0x3e814304, dl));
3751 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3752 getF32Constant(DAG, 0x3f3c50c8, dl));
3753 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3754 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3755 getF32Constant(DAG, 0x3f7f5e7e, dl));
3756 } else if (LimitFloatPrecision <= 12) {
3757 // For floating-point precision of 12:
3759 // TwoToFractionalPartOfX =
3762 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3764 // error 0.000107046256, which is 13 to 14 bits
3765 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3766 getF32Constant(DAG, 0x3da235e3, dl));
3767 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3768 getF32Constant(DAG, 0x3e65b8f3, dl));
3769 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3770 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3771 getF32Constant(DAG, 0x3f324b07, dl));
3772 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3773 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3774 getF32Constant(DAG, 0x3f7ff8fd, dl));
3775 } else { // LimitFloatPrecision <= 18
3776 // For floating-point precision of 18:
3778 // TwoToFractionalPartOfX =
3782 // (0.554906021e-1f +
3783 // (0.961591928e-2f +
3784 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3785 // error 2.47208000*10^(-7), which is better than 18 bits
3786 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3787 getF32Constant(DAG, 0x3924b03e, dl));
3788 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3789 getF32Constant(DAG, 0x3ab24b87, dl));
3790 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3791 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3792 getF32Constant(DAG, 0x3c1d8c17, dl));
3793 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3794 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3795 getF32Constant(DAG, 0x3d634a1d, dl));
3796 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3797 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3798 getF32Constant(DAG, 0x3e75fe14, dl));
3799 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3800 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3801 getF32Constant(DAG, 0x3f317234, dl));
3802 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3803 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3804 getF32Constant(DAG, 0x3f800000, dl));
3807 // Add the exponent into the result in integer domain.
3808 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3809 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3810 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3813 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3814 /// limited-precision mode.
3815 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3816 const TargetLowering &TLI) {
3817 if (Op.getValueType() == MVT::f32 &&
3818 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3820 // Put the exponent in the right bit position for later addition to the
3823 // #define LOG2OFe 1.4426950f
3824 // t0 = Op * LOG2OFe
3826 // TODO: What fast-math-flags should be set here?
3827 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3828 getF32Constant(DAG, 0x3fb8aa3b, dl));
3829 return getLimitedPrecisionExp2(t0, dl, DAG);
3832 // No special expansion.
3833 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3836 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3837 /// limited-precision mode.
3838 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3839 const TargetLowering &TLI) {
3841 // TODO: What fast-math-flags should be set on the floating-point nodes?
3843 if (Op.getValueType() == MVT::f32 &&
3844 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3845 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3847 // Scale the exponent by log(2) [0.69314718f].
3848 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3849 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3850 getF32Constant(DAG, 0x3f317218, dl));
3852 // Get the significand and build it into a floating-point number with
3854 SDValue X = GetSignificand(DAG, Op1, dl);
3856 SDValue LogOfMantissa;
3857 if (LimitFloatPrecision <= 6) {
3858 // For floating-point precision of 6:
3862 // (1.4034025f - 0.23903021f * x) * x;
3864 // error 0.0034276066, which is better than 8 bits
3865 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3866 getF32Constant(DAG, 0xbe74c456, dl));
3867 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3868 getF32Constant(DAG, 0x3fb3a2b1, dl));
3869 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3870 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3871 getF32Constant(DAG, 0x3f949a29, dl));
3872 } else if (LimitFloatPrecision <= 12) {
3873 // For floating-point precision of 12:
3879 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3881 // error 0.000061011436, which is 14 bits
3882 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3883 getF32Constant(DAG, 0xbd67b6d6, dl));
3884 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3885 getF32Constant(DAG, 0x3ee4f4b8, dl));
3886 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3887 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3888 getF32Constant(DAG, 0x3fbc278b, dl));
3889 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3890 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3891 getF32Constant(DAG, 0x40348e95, dl));
3892 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3893 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3894 getF32Constant(DAG, 0x3fdef31a, dl));
3895 } else { // LimitFloatPrecision <= 18
3896 // For floating-point precision of 18:
3904 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3906 // error 0.0000023660568, which is better than 18 bits
3907 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3908 getF32Constant(DAG, 0xbc91e5ac, dl));
3909 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3910 getF32Constant(DAG, 0x3e4350aa, dl));
3911 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3912 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3913 getF32Constant(DAG, 0x3f60d3e3, dl));
3914 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3915 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3916 getF32Constant(DAG, 0x4011cdf0, dl));
3917 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3918 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3919 getF32Constant(DAG, 0x406cfd1c, dl));
3920 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3921 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3922 getF32Constant(DAG, 0x408797cb, dl));
3923 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3924 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3925 getF32Constant(DAG, 0x4006dcab, dl));
3928 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3931 // No special expansion.
3932 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3935 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3936 /// limited-precision mode.
3937 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3938 const TargetLowering &TLI) {
3940 // TODO: What fast-math-flags should be set on the floating-point nodes?
3942 if (Op.getValueType() == MVT::f32 &&
3943 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3944 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3946 // Get the exponent.
3947 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3949 // Get the significand and build it into a floating-point number with
3951 SDValue X = GetSignificand(DAG, Op1, dl);
3953 // Different possible minimax approximations of significand in
3954 // floating-point for various degrees of accuracy over [1,2].
3955 SDValue Log2ofMantissa;
3956 if (LimitFloatPrecision <= 6) {
3957 // For floating-point precision of 6:
3959 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3961 // error 0.0049451742, which is more than 7 bits
3962 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3963 getF32Constant(DAG, 0xbeb08fe0, dl));
3964 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3965 getF32Constant(DAG, 0x40019463, dl));
3966 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3967 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3968 getF32Constant(DAG, 0x3fd6633d, dl));
3969 } else if (LimitFloatPrecision <= 12) {
3970 // For floating-point precision of 12:
3976 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3978 // error 0.0000876136000, which is better than 13 bits
3979 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3980 getF32Constant(DAG, 0xbda7262e, dl));
3981 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3982 getF32Constant(DAG, 0x3f25280b, dl));
3983 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3984 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3985 getF32Constant(DAG, 0x4007b923, dl));
3986 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3987 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3988 getF32Constant(DAG, 0x40823e2f, dl));
3989 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3990 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3991 getF32Constant(DAG, 0x4020d29c, dl));
3992 } else { // LimitFloatPrecision <= 18
3993 // For floating-point precision of 18:
4002 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4004 // error 0.0000018516, which is better than 18 bits
4005 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4006 getF32Constant(DAG, 0xbcd2769e, dl));
4007 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4008 getF32Constant(DAG, 0x3e8ce0b9, dl));
4009 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4010 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4011 getF32Constant(DAG, 0x3fa22ae7, dl));
4012 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4013 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4014 getF32Constant(DAG, 0x40525723, dl));
4015 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4016 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4017 getF32Constant(DAG, 0x40aaf200, dl));
4018 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4019 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4020 getF32Constant(DAG, 0x40c39dad, dl));
4021 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4022 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4023 getF32Constant(DAG, 0x4042902c, dl));
4026 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4029 // No special expansion.
4030 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4033 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4034 /// limited-precision mode.
4035 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4036 const TargetLowering &TLI) {
4038 // TODO: What fast-math-flags should be set on the floating-point nodes?
4040 if (Op.getValueType() == MVT::f32 &&
4041 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4042 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4044 // Scale the exponent by log10(2) [0.30102999f].
4045 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4046 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4047 getF32Constant(DAG, 0x3e9a209a, dl));
4049 // Get the significand and build it into a floating-point number with
4051 SDValue X = GetSignificand(DAG, Op1, dl);
4053 SDValue Log10ofMantissa;
4054 if (LimitFloatPrecision <= 6) {
4055 // For floating-point precision of 6:
4057 // Log10ofMantissa =
4059 // (0.60948995f - 0.10380950f * x) * x;
4061 // error 0.0014886165, which is 6 bits
4062 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4063 getF32Constant(DAG, 0xbdd49a13, dl));
4064 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4065 getF32Constant(DAG, 0x3f1c0789, dl));
4066 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4067 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4068 getF32Constant(DAG, 0x3f011300, dl));
4069 } else if (LimitFloatPrecision <= 12) {
4070 // For floating-point precision of 12:
4072 // Log10ofMantissa =
4075 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4077 // error 0.00019228036, which is better than 12 bits
4078 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4079 getF32Constant(DAG, 0x3d431f31, dl));
4080 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4081 getF32Constant(DAG, 0x3ea21fb2, dl));
4082 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4083 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4084 getF32Constant(DAG, 0x3f6ae232, dl));
4085 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4086 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4087 getF32Constant(DAG, 0x3f25f7c3, dl));
4088 } else { // LimitFloatPrecision <= 18
4089 // For floating-point precision of 18:
4091 // Log10ofMantissa =
4096 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4098 // error 0.0000037995730, which is better than 18 bits
4099 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4100 getF32Constant(DAG, 0x3c5d51ce, dl));
4101 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4102 getF32Constant(DAG, 0x3e00685a, dl));
4103 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4104 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4105 getF32Constant(DAG, 0x3efb6798, dl));
4106 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4107 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4108 getF32Constant(DAG, 0x3f88d192, dl));
4109 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4110 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4111 getF32Constant(DAG, 0x3fc4316c, dl));
4112 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4113 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4114 getF32Constant(DAG, 0x3f57ce70, dl));
4117 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4120 // No special expansion.
4121 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4124 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4125 /// limited-precision mode.
4126 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4127 const TargetLowering &TLI) {
4128 if (Op.getValueType() == MVT::f32 &&
4129 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4130 return getLimitedPrecisionExp2(Op, dl, DAG);
4132 // No special expansion.
4133 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4136 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4137 /// limited-precision mode with x == 10.0f.
4138 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4139 SelectionDAG &DAG, const TargetLowering &TLI) {
4140 bool IsExp10 = false;
4141 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4142 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4143 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4145 IsExp10 = LHSC->isExactlyValue(Ten);
4149 // TODO: What fast-math-flags should be set on the FMUL node?
4151 // Put the exponent in the right bit position for later addition to the
4154 // #define LOG2OF10 3.3219281f
4155 // t0 = Op * LOG2OF10;
4156 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4157 getF32Constant(DAG, 0x40549a78, dl));
4158 return getLimitedPrecisionExp2(t0, dl, DAG);
4161 // No special expansion.
4162 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4166 /// ExpandPowI - Expand a llvm.powi intrinsic.
4167 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4168 SelectionDAG &DAG) {
4169 // If RHS is a constant, we can expand this out to a multiplication tree,
4170 // otherwise we end up lowering to a call to __powidf2 (for example). When
4171 // optimizing for size, we only want to do this if the expansion would produce
4172 // a small number of multiplies, otherwise we do the full expansion.
4173 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4174 // Get the exponent as a positive value.
4175 unsigned Val = RHSC->getSExtValue();
4176 if ((int)Val < 0) Val = -Val;
4178 // powi(x, 0) -> 1.0
4180 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4182 const Function *F = DAG.getMachineFunction().getFunction();
4183 if (!F->optForSize() ||
4184 // If optimizing for size, don't insert too many multiplies.
4185 // This inserts up to 5 multiplies.
4186 countPopulation(Val) + Log2_32(Val) < 7) {
4187 // We use the simple binary decomposition method to generate the multiply
4188 // sequence. There are more optimal ways to do this (for example,
4189 // powi(x,15) generates one more multiply than it should), but this has
4190 // the benefit of being both really simple and much better than a libcall.
4191 SDValue Res; // Logically starts equal to 1.0
4192 SDValue CurSquare = LHS;
4193 // TODO: Intrinsics should have fast-math-flags that propagate to these
4198 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4200 Res = CurSquare; // 1.0*CurSquare.
4203 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4204 CurSquare, CurSquare);
4208 // If the original was negative, invert the result, producing 1/(x*x*x).
4209 if (RHSC->getSExtValue() < 0)
4210 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4211 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4216 // Otherwise, expand to a libcall.
4217 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4220 // getUnderlyingArgReg - Find underlying register used for a truncated or
4221 // bitcasted argument.
4222 static unsigned getUnderlyingArgReg(const SDValue &N) {
4223 switch (N.getOpcode()) {
4224 case ISD::CopyFromReg:
4225 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4227 case ISD::AssertZext:
4228 case ISD::AssertSext:
4230 return getUnderlyingArgReg(N.getOperand(0));
4236 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4237 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4238 /// At the end of instruction selection, they will be inserted to the entry BB.
4239 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4240 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4241 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4242 const Argument *Arg = dyn_cast<Argument>(V);
4246 MachineFunction &MF = DAG.getMachineFunction();
4247 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4249 // Ignore inlined function arguments here.
4251 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4252 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4255 Optional<MachineOperand> Op;
4256 // Some arguments' frame index is recorded during argument lowering.
4257 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4258 Op = MachineOperand::CreateFI(FI);
4260 if (!Op && N.getNode()) {
4261 unsigned Reg = getUnderlyingArgReg(N);
4262 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4263 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4264 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4269 Op = MachineOperand::CreateReg(Reg, false);
4273 // Check if ValueMap has reg number.
4274 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4275 if (VMI != FuncInfo.ValueMap.end())
4276 Op = MachineOperand::CreateReg(VMI->second, false);
4279 if (!Op && N.getNode())
4280 // Check if frame index is available.
4281 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4282 if (FrameIndexSDNode *FINode =
4283 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4284 Op = MachineOperand::CreateFI(FINode->getIndex());
4289 assert(Variable->isValidLocationForIntrinsic(DL) &&
4290 "Expected inlined-at fields to agree");
4292 FuncInfo.ArgDbgValues.push_back(
4293 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4294 Op->getReg(), Offset, Variable, Expr));
4296 FuncInfo.ArgDbgValues.push_back(
4297 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4300 .addMetadata(Variable)
4301 .addMetadata(Expr));
4306 // VisualStudio defines setjmp as _setjmp
4307 #if defined(_MSC_VER) && defined(setjmp) && \
4308 !defined(setjmp_undefined_for_msvc)
4309 # pragma push_macro("setjmp")
4311 # define setjmp_undefined_for_msvc
4314 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4315 /// we want to emit this as a call to a named external function, return the name
4316 /// otherwise lower it and return null.
4318 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4319 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4320 SDLoc sdl = getCurSDLoc();
4321 DebugLoc dl = getCurDebugLoc();
4324 switch (Intrinsic) {
4326 // By default, turn this into a target intrinsic node.
4327 visitTargetIntrinsic(I, Intrinsic);
4329 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4330 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4331 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4332 case Intrinsic::returnaddress:
4333 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4334 TLI.getPointerTy(DAG.getDataLayout()),
4335 getValue(I.getArgOperand(0))));
4337 case Intrinsic::frameaddress:
4338 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4339 TLI.getPointerTy(DAG.getDataLayout()),
4340 getValue(I.getArgOperand(0))));
4342 case Intrinsic::read_register: {
4343 Value *Reg = I.getArgOperand(0);
4344 SDValue Chain = getRoot();
4346 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4347 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4348 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4349 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4351 DAG.setRoot(Res.getValue(1));
4354 case Intrinsic::write_register: {
4355 Value *Reg = I.getArgOperand(0);
4356 Value *RegValue = I.getArgOperand(1);
4357 SDValue Chain = getRoot();
4359 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4360 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4361 RegName, getValue(RegValue)));
4364 case Intrinsic::setjmp:
4365 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4366 case Intrinsic::longjmp:
4367 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4368 case Intrinsic::memcpy: {
4369 // FIXME: this definition of "user defined address space" is x86-specific
4370 // Assert for address < 256 since we support only user defined address
4372 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4374 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4376 "Unknown address space");
4377 SDValue Op1 = getValue(I.getArgOperand(0));
4378 SDValue Op2 = getValue(I.getArgOperand(1));
4379 SDValue Op3 = getValue(I.getArgOperand(2));
4380 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4382 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4383 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4384 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4385 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4387 MachinePointerInfo(I.getArgOperand(0)),
4388 MachinePointerInfo(I.getArgOperand(1)));
4389 updateDAGForMaybeTailCall(MC);
4392 case Intrinsic::memset: {
4393 // FIXME: this definition of "user defined address space" is x86-specific
4394 // Assert for address < 256 since we support only user defined address
4396 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4398 "Unknown address space");
4399 SDValue Op1 = getValue(I.getArgOperand(0));
4400 SDValue Op2 = getValue(I.getArgOperand(1));
4401 SDValue Op3 = getValue(I.getArgOperand(2));
4402 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4404 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4405 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4406 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4407 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4408 isTC, MachinePointerInfo(I.getArgOperand(0)));
4409 updateDAGForMaybeTailCall(MS);
4412 case Intrinsic::memmove: {
4413 // FIXME: this definition of "user defined address space" is x86-specific
4414 // Assert for address < 256 since we support only user defined address
4416 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4418 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4420 "Unknown address space");
4421 SDValue Op1 = getValue(I.getArgOperand(0));
4422 SDValue Op2 = getValue(I.getArgOperand(1));
4423 SDValue Op3 = getValue(I.getArgOperand(2));
4424 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4426 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4427 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4428 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4429 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4430 isTC, MachinePointerInfo(I.getArgOperand(0)),
4431 MachinePointerInfo(I.getArgOperand(1)));
4432 updateDAGForMaybeTailCall(MM);
4435 case Intrinsic::dbg_declare: {
4436 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4437 DILocalVariable *Variable = DI.getVariable();
4438 DIExpression *Expression = DI.getExpression();
4439 const Value *Address = DI.getAddress();
4440 assert(Variable && "Missing variable");
4442 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4446 // Check if address has undef value.
4447 if (isa<UndefValue>(Address) ||
4448 (Address->use_empty() && !isa<Argument>(Address))) {
4449 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4453 SDValue &N = NodeMap[Address];
4454 if (!N.getNode() && isa<Argument>(Address))
4455 // Check unused arguments map.
4456 N = UnusedArgNodeMap[Address];
4459 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4460 Address = BCI->getOperand(0);
4461 // Parameters are handled specially.
4462 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4464 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4466 if (isParameter && !AI) {
4467 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4469 // Byval parameter. We have a frame index at this point.
4470 SDV = DAG.getFrameIndexDbgValue(
4471 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4473 // Address is an argument, so try to emit its dbg value using
4474 // virtual register info from the FuncInfo.ValueMap.
4475 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4480 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4481 true, 0, dl, SDNodeOrder);
4483 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4485 // If Address is an argument then try to emit its dbg value using
4486 // virtual register info from the FuncInfo.ValueMap.
4487 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4489 // If variable is pinned by a alloca in dominating bb then
4490 // use StaticAllocaMap.
4491 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4492 if (AI->getParent() != DI.getParent()) {
4493 DenseMap<const AllocaInst*, int>::iterator SI =
4494 FuncInfo.StaticAllocaMap.find(AI);
4495 if (SI != FuncInfo.StaticAllocaMap.end()) {
4496 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4497 0, dl, SDNodeOrder);
4498 DAG.AddDbgValue(SDV, nullptr, false);
4503 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4508 case Intrinsic::dbg_value: {
4509 const DbgValueInst &DI = cast<DbgValueInst>(I);
4510 assert(DI.getVariable() && "Missing variable");
4512 DILocalVariable *Variable = DI.getVariable();
4513 DIExpression *Expression = DI.getExpression();
4514 uint64_t Offset = DI.getOffset();
4515 const Value *V = DI.getValue();
4520 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4521 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4523 DAG.AddDbgValue(SDV, nullptr, false);
4525 // Do not use getValue() in here; we don't want to generate code at
4526 // this point if it hasn't been done yet.
4527 SDValue N = NodeMap[V];
4528 if (!N.getNode() && isa<Argument>(V))
4529 // Check unused arguments map.
4530 N = UnusedArgNodeMap[V];
4532 // A dbg.value for an alloca is always indirect.
4533 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4534 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4536 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4537 IsIndirect, Offset, dl, SDNodeOrder);
4538 DAG.AddDbgValue(SDV, N.getNode(), false);
4540 } else if (!V->use_empty() ) {
4541 // Do not call getValue(V) yet, as we don't want to generate code.
4542 // Remember it for later.
4543 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4544 DanglingDebugInfoMap[V] = DDI;
4546 // We may expand this to cover more cases. One case where we have no
4547 // data available is an unreferenced parameter.
4548 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4552 // Build a debug info table entry.
4553 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4554 V = BCI->getOperand(0);
4555 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4556 // Don't handle byval struct arguments or VLAs, for example.
4558 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4559 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4562 DenseMap<const AllocaInst*, int>::iterator SI =
4563 FuncInfo.StaticAllocaMap.find(AI);
4564 if (SI == FuncInfo.StaticAllocaMap.end())
4565 return nullptr; // VLAs.
4569 case Intrinsic::eh_typeid_for: {
4570 // Find the type id for the given typeinfo.
4571 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4572 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4573 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4578 case Intrinsic::eh_return_i32:
4579 case Intrinsic::eh_return_i64:
4580 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4581 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4584 getValue(I.getArgOperand(0)),
4585 getValue(I.getArgOperand(1))));
4587 case Intrinsic::eh_unwind_init:
4588 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4590 case Intrinsic::eh_dwarf_cfa: {
4591 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4592 TLI.getPointerTy(DAG.getDataLayout()));
4593 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4594 CfaArg.getValueType(),
4595 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4596 CfaArg.getValueType()),
4598 SDValue FA = DAG.getNode(
4599 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4600 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4601 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4605 case Intrinsic::eh_sjlj_callsite: {
4606 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4607 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4608 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4609 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4611 MMI.setCurrentCallSite(CI->getZExtValue());
4614 case Intrinsic::eh_sjlj_functioncontext: {
4615 // Get and store the index of the function context.
4616 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4618 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4619 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4620 MFI->setFunctionContextIndex(FI);
4623 case Intrinsic::eh_sjlj_setjmp: {
4626 Ops[1] = getValue(I.getArgOperand(0));
4627 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4628 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4629 setValue(&I, Op.getValue(0));
4630 DAG.setRoot(Op.getValue(1));
4633 case Intrinsic::eh_sjlj_longjmp: {
4634 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4635 getRoot(), getValue(I.getArgOperand(0))));
4638 case Intrinsic::eh_sjlj_setup_dispatch: {
4639 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4644 case Intrinsic::masked_gather:
4645 visitMaskedGather(I);
4647 case Intrinsic::masked_load:
4650 case Intrinsic::masked_scatter:
4651 visitMaskedScatter(I);
4653 case Intrinsic::masked_store:
4654 visitMaskedStore(I);
4656 case Intrinsic::x86_mmx_pslli_w:
4657 case Intrinsic::x86_mmx_pslli_d:
4658 case Intrinsic::x86_mmx_pslli_q:
4659 case Intrinsic::x86_mmx_psrli_w:
4660 case Intrinsic::x86_mmx_psrli_d:
4661 case Intrinsic::x86_mmx_psrli_q:
4662 case Intrinsic::x86_mmx_psrai_w:
4663 case Intrinsic::x86_mmx_psrai_d: {
4664 SDValue ShAmt = getValue(I.getArgOperand(1));
4665 if (isa<ConstantSDNode>(ShAmt)) {
4666 visitTargetIntrinsic(I, Intrinsic);
4669 unsigned NewIntrinsic = 0;
4670 EVT ShAmtVT = MVT::v2i32;
4671 switch (Intrinsic) {
4672 case Intrinsic::x86_mmx_pslli_w:
4673 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4675 case Intrinsic::x86_mmx_pslli_d:
4676 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4678 case Intrinsic::x86_mmx_pslli_q:
4679 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4681 case Intrinsic::x86_mmx_psrli_w:
4682 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4684 case Intrinsic::x86_mmx_psrli_d:
4685 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4687 case Intrinsic::x86_mmx_psrli_q:
4688 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4690 case Intrinsic::x86_mmx_psrai_w:
4691 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4693 case Intrinsic::x86_mmx_psrai_d:
4694 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4696 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4699 // The vector shift intrinsics with scalars uses 32b shift amounts but
4700 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4702 // We must do this early because v2i32 is not a legal type.
4705 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4706 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4707 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4708 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4709 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4710 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4711 getValue(I.getArgOperand(0)), ShAmt);
4715 case Intrinsic::convertff:
4716 case Intrinsic::convertfsi:
4717 case Intrinsic::convertfui:
4718 case Intrinsic::convertsif:
4719 case Intrinsic::convertuif:
4720 case Intrinsic::convertss:
4721 case Intrinsic::convertsu:
4722 case Intrinsic::convertus:
4723 case Intrinsic::convertuu: {
4724 ISD::CvtCode Code = ISD::CVT_INVALID;
4725 switch (Intrinsic) {
4726 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4727 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4728 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4729 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4730 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4731 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4732 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4733 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4734 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4735 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4737 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4738 const Value *Op1 = I.getArgOperand(0);
4739 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4740 DAG.getValueType(DestVT),
4741 DAG.getValueType(getValue(Op1).getValueType()),
4742 getValue(I.getArgOperand(1)),
4743 getValue(I.getArgOperand(2)),
4748 case Intrinsic::powi:
4749 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4750 getValue(I.getArgOperand(1)), DAG));
4752 case Intrinsic::log:
4753 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4755 case Intrinsic::log2:
4756 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4758 case Intrinsic::log10:
4759 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4761 case Intrinsic::exp:
4762 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4764 case Intrinsic::exp2:
4765 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4767 case Intrinsic::pow:
4768 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4769 getValue(I.getArgOperand(1)), DAG, TLI));
4771 case Intrinsic::sqrt:
4772 case Intrinsic::fabs:
4773 case Intrinsic::sin:
4774 case Intrinsic::cos:
4775 case Intrinsic::floor:
4776 case Intrinsic::ceil:
4777 case Intrinsic::trunc:
4778 case Intrinsic::rint:
4779 case Intrinsic::nearbyint:
4780 case Intrinsic::round: {
4782 switch (Intrinsic) {
4783 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4784 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4785 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4786 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4787 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4788 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4789 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4790 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4791 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4792 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4793 case Intrinsic::round: Opcode = ISD::FROUND; break;
4796 setValue(&I, DAG.getNode(Opcode, sdl,
4797 getValue(I.getArgOperand(0)).getValueType(),
4798 getValue(I.getArgOperand(0))));
4801 case Intrinsic::minnum:
4802 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4803 getValue(I.getArgOperand(0)).getValueType(),
4804 getValue(I.getArgOperand(0)),
4805 getValue(I.getArgOperand(1))));
4807 case Intrinsic::maxnum:
4808 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4809 getValue(I.getArgOperand(0)).getValueType(),
4810 getValue(I.getArgOperand(0)),
4811 getValue(I.getArgOperand(1))));
4813 case Intrinsic::copysign:
4814 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4815 getValue(I.getArgOperand(0)).getValueType(),
4816 getValue(I.getArgOperand(0)),
4817 getValue(I.getArgOperand(1))));
4819 case Intrinsic::fma:
4820 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4821 getValue(I.getArgOperand(0)).getValueType(),
4822 getValue(I.getArgOperand(0)),
4823 getValue(I.getArgOperand(1)),
4824 getValue(I.getArgOperand(2))));
4826 case Intrinsic::fmuladd: {
4827 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4828 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4829 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4830 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4831 getValue(I.getArgOperand(0)).getValueType(),
4832 getValue(I.getArgOperand(0)),
4833 getValue(I.getArgOperand(1)),
4834 getValue(I.getArgOperand(2))));
4836 // TODO: Intrinsic calls should have fast-math-flags.
4837 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4838 getValue(I.getArgOperand(0)).getValueType(),
4839 getValue(I.getArgOperand(0)),
4840 getValue(I.getArgOperand(1)));
4841 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4842 getValue(I.getArgOperand(0)).getValueType(),
4844 getValue(I.getArgOperand(2)));
4849 case Intrinsic::convert_to_fp16:
4850 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4851 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4852 getValue(I.getArgOperand(0)),
4853 DAG.getTargetConstant(0, sdl,
4856 case Intrinsic::convert_from_fp16:
4857 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4858 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4859 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4860 getValue(I.getArgOperand(0)))));
4862 case Intrinsic::pcmarker: {
4863 SDValue Tmp = getValue(I.getArgOperand(0));
4864 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4867 case Intrinsic::readcyclecounter: {
4868 SDValue Op = getRoot();
4869 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4870 DAG.getVTList(MVT::i64, MVT::Other), Op);
4872 DAG.setRoot(Res.getValue(1));
4875 case Intrinsic::bitreverse:
4876 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
4877 getValue(I.getArgOperand(0)).getValueType(),
4878 getValue(I.getArgOperand(0))));
4880 case Intrinsic::bswap:
4881 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4882 getValue(I.getArgOperand(0)).getValueType(),
4883 getValue(I.getArgOperand(0))));
4885 case Intrinsic::uabsdiff:
4886 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4887 getValue(I.getArgOperand(0)).getValueType(),
4888 getValue(I.getArgOperand(0)),
4889 getValue(I.getArgOperand(1))));
4891 case Intrinsic::sabsdiff:
4892 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4893 getValue(I.getArgOperand(0)).getValueType(),
4894 getValue(I.getArgOperand(0)),
4895 getValue(I.getArgOperand(1))));
4897 case Intrinsic::cttz: {
4898 SDValue Arg = getValue(I.getArgOperand(0));
4899 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4900 EVT Ty = Arg.getValueType();
4901 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4905 case Intrinsic::ctlz: {
4906 SDValue Arg = getValue(I.getArgOperand(0));
4907 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4908 EVT Ty = Arg.getValueType();
4909 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4913 case Intrinsic::ctpop: {
4914 SDValue Arg = getValue(I.getArgOperand(0));
4915 EVT Ty = Arg.getValueType();
4916 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4919 case Intrinsic::stacksave: {
4920 SDValue Op = getRoot();
4922 ISD::STACKSAVE, sdl,
4923 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4925 DAG.setRoot(Res.getValue(1));
4928 case Intrinsic::stackrestore: {
4929 Res = getValue(I.getArgOperand(0));
4930 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4933 case Intrinsic::stackprotector: {
4934 // Emit code into the DAG to store the stack guard onto the stack.
4935 MachineFunction &MF = DAG.getMachineFunction();
4936 MachineFrameInfo *MFI = MF.getFrameInfo();
4937 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4938 SDValue Src, Chain = getRoot();
4939 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4940 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4942 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4943 // global variable __stack_chk_guard.
4945 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4946 if (BC->getOpcode() == Instruction::BitCast)
4947 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4949 if (GV && TLI.useLoadStackGuardNode()) {
4950 // Emit a LOAD_STACK_GUARD node.
4951 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4953 MachinePointerInfo MPInfo(GV);
4954 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4955 unsigned Flags = MachineMemOperand::MOLoad |
4956 MachineMemOperand::MOInvariant;
4957 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4958 PtrTy.getSizeInBits() / 8,
4959 DAG.getEVTAlignment(PtrTy));
4960 Node->setMemRefs(MemRefs, MemRefs + 1);
4962 // Copy the guard value to a virtual register so that it can be
4963 // retrieved in the epilogue.
4964 Src = SDValue(Node, 0);
4965 const TargetRegisterClass *RC =
4966 TLI.getRegClassFor(Src.getSimpleValueType());
4967 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4969 SPDescriptor.setGuardReg(Reg);
4970 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4972 Src = getValue(I.getArgOperand(0)); // The guard's value.
4975 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4977 int FI = FuncInfo.StaticAllocaMap[Slot];
4978 MFI->setStackProtectorIndex(FI);
4980 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4982 // Store the stack protector onto the stack.
4983 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4984 DAG.getMachineFunction(), FI),
4990 case Intrinsic::objectsize: {
4991 // If we don't know by now, we're never going to know.
4992 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4994 assert(CI && "Non-constant type in __builtin_object_size?");
4996 SDValue Arg = getValue(I.getCalledValue());
4997 EVT Ty = Arg.getValueType();
5000 Res = DAG.getConstant(-1ULL, sdl, Ty);
5002 Res = DAG.getConstant(0, sdl, Ty);
5007 case Intrinsic::annotation:
5008 case Intrinsic::ptr_annotation:
5009 // Drop the intrinsic, but forward the value
5010 setValue(&I, getValue(I.getOperand(0)));
5012 case Intrinsic::assume:
5013 case Intrinsic::var_annotation:
5014 // Discard annotate attributes and assumptions
5017 case Intrinsic::init_trampoline: {
5018 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5022 Ops[1] = getValue(I.getArgOperand(0));
5023 Ops[2] = getValue(I.getArgOperand(1));
5024 Ops[3] = getValue(I.getArgOperand(2));
5025 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5026 Ops[5] = DAG.getSrcValue(F);
5028 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5033 case Intrinsic::adjust_trampoline: {
5034 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5035 TLI.getPointerTy(DAG.getDataLayout()),
5036 getValue(I.getArgOperand(0))));
5039 case Intrinsic::gcroot:
5041 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5042 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5044 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5045 GFI->addStackRoot(FI->getIndex(), TypeMap);
5048 case Intrinsic::gcread:
5049 case Intrinsic::gcwrite:
5050 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5051 case Intrinsic::flt_rounds:
5052 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5055 case Intrinsic::expect: {
5056 // Just replace __builtin_expect(exp, c) with EXP.
5057 setValue(&I, getValue(I.getArgOperand(0)));
5061 case Intrinsic::debugtrap:
5062 case Intrinsic::trap: {
5063 StringRef TrapFuncName =
5065 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5066 .getValueAsString();
5067 if (TrapFuncName.empty()) {
5068 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5069 ISD::TRAP : ISD::DEBUGTRAP;
5070 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5073 TargetLowering::ArgListTy Args;
5075 TargetLowering::CallLoweringInfo CLI(DAG);
5076 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5077 CallingConv::C, I.getType(),
5078 DAG.getExternalSymbol(TrapFuncName.data(),
5079 TLI.getPointerTy(DAG.getDataLayout())),
5080 std::move(Args), 0);
5082 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5083 DAG.setRoot(Result.second);
5087 case Intrinsic::uadd_with_overflow:
5088 case Intrinsic::sadd_with_overflow:
5089 case Intrinsic::usub_with_overflow:
5090 case Intrinsic::ssub_with_overflow:
5091 case Intrinsic::umul_with_overflow:
5092 case Intrinsic::smul_with_overflow: {
5094 switch (Intrinsic) {
5095 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5096 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5097 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5098 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5099 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5100 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5101 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5103 SDValue Op1 = getValue(I.getArgOperand(0));
5104 SDValue Op2 = getValue(I.getArgOperand(1));
5106 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5107 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5110 case Intrinsic::prefetch: {
5112 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5114 Ops[1] = getValue(I.getArgOperand(0));
5115 Ops[2] = getValue(I.getArgOperand(1));
5116 Ops[3] = getValue(I.getArgOperand(2));
5117 Ops[4] = getValue(I.getArgOperand(3));
5118 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5119 DAG.getVTList(MVT::Other), Ops,
5120 EVT::getIntegerVT(*Context, 8),
5121 MachinePointerInfo(I.getArgOperand(0)),
5123 false, /* volatile */
5125 rw==1)); /* write */
5128 case Intrinsic::lifetime_start:
5129 case Intrinsic::lifetime_end: {
5130 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5131 // Stack coloring is not enabled in O0, discard region information.
5132 if (TM.getOptLevel() == CodeGenOpt::None)
5135 SmallVector<Value *, 4> Allocas;
5136 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5138 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5139 E = Allocas.end(); Object != E; ++Object) {
5140 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5142 // Could not find an Alloca.
5143 if (!LifetimeObject)
5146 // First check that the Alloca is static, otherwise it won't have a
5147 // valid frame index.
5148 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5149 if (SI == FuncInfo.StaticAllocaMap.end())
5152 int FI = SI->second;
5157 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5158 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5160 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5165 case Intrinsic::invariant_start:
5166 // Discard region information.
5167 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5169 case Intrinsic::invariant_end:
5170 // Discard region information.
5172 case Intrinsic::stackprotectorcheck: {
5173 // Do not actually emit anything for this basic block. Instead we initialize
5174 // the stack protector descriptor and export the guard variable so we can
5175 // access it in FinishBasicBlock.
5176 const BasicBlock *BB = I.getParent();
5177 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5178 ExportFromCurrentBlock(SPDescriptor.getGuard());
5180 // Flush our exports since we are going to process a terminator.
5181 (void)getControlRoot();
5184 case Intrinsic::clear_cache:
5185 return TLI.getClearCacheBuiltinName();
5186 case Intrinsic::donothing:
5189 case Intrinsic::experimental_stackmap: {
5193 case Intrinsic::experimental_patchpoint_void:
5194 case Intrinsic::experimental_patchpoint_i64: {
5195 visitPatchpoint(&I);
5198 case Intrinsic::experimental_gc_statepoint: {
5202 case Intrinsic::experimental_gc_result_int:
5203 case Intrinsic::experimental_gc_result_float:
5204 case Intrinsic::experimental_gc_result_ptr:
5205 case Intrinsic::experimental_gc_result: {
5209 case Intrinsic::experimental_gc_relocate: {
5213 case Intrinsic::instrprof_increment:
5214 llvm_unreachable("instrprof failed to lower an increment");
5216 case Intrinsic::localescape: {
5217 MachineFunction &MF = DAG.getMachineFunction();
5218 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5220 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5221 // is the same on all targets.
5222 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5223 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5224 if (isa<ConstantPointerNull>(Arg))
5225 continue; // Skip null pointers. They represent a hole in index space.
5226 AllocaInst *Slot = cast<AllocaInst>(Arg);
5227 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5228 "can only escape static allocas");
5229 int FI = FuncInfo.StaticAllocaMap[Slot];
5230 MCSymbol *FrameAllocSym =
5231 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5232 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5233 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5234 TII->get(TargetOpcode::LOCAL_ESCAPE))
5235 .addSym(FrameAllocSym)
5242 case Intrinsic::localrecover: {
5243 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5244 MachineFunction &MF = DAG.getMachineFunction();
5245 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5247 // Get the symbol that defines the frame offset.
5248 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5249 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5250 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5251 MCSymbol *FrameAllocSym =
5252 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5253 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5255 // Create a MCSymbol for the label to avoid any target lowering
5256 // that would make this PC relative.
5257 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5259 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5261 // Add the offset to the FP.
5262 Value *FP = I.getArgOperand(1);
5263 SDValue FPVal = getValue(FP);
5264 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5270 case Intrinsic::eh_exceptionpointer:
5271 case Intrinsic::eh_exceptioncode: {
5272 // Get the exception pointer vreg, copy from it, and resize it to fit.
5273 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5274 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5275 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5276 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5278 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5279 if (Intrinsic == Intrinsic::eh_exceptioncode)
5280 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5287 std::pair<SDValue, SDValue>
5288 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5289 const BasicBlock *EHPadBB) {
5290 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5291 MCSymbol *BeginLabel = nullptr;
5294 // Insert a label before the invoke call to mark the try range. This can be
5295 // used to detect deletion of the invoke via the MachineModuleInfo.
5296 BeginLabel = MMI.getContext().createTempSymbol();
5298 // For SjLj, keep track of which landing pads go with which invokes
5299 // so as to maintain the ordering of pads in the LSDA.
5300 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5301 if (CallSiteIndex) {
5302 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5303 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5305 // Now that the call site is handled, stop tracking it.
5306 MMI.setCurrentCallSite(0);
5309 // Both PendingLoads and PendingExports must be flushed here;
5310 // this call might not return.
5312 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5314 CLI.setChain(getRoot());
5316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5317 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5319 assert((CLI.IsTailCall || Result.second.getNode()) &&
5320 "Non-null chain expected with non-tail call!");
5321 assert((Result.second.getNode() || !Result.first.getNode()) &&
5322 "Null value expected with tail call!");
5324 if (!Result.second.getNode()) {
5325 // As a special case, a null chain means that a tail call has been emitted
5326 // and the DAG root is already updated.
5329 // Since there's no actual continuation from this block, nothing can be
5330 // relying on us setting vregs for them.
5331 PendingExports.clear();
5333 DAG.setRoot(Result.second);
5337 // Insert a label at the end of the invoke call to mark the try range. This
5338 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5339 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5340 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5342 // Inform MachineModuleInfo of range.
5343 if (MMI.hasEHFunclets()) {
5344 WinEHFuncInfo &EHInfo =
5345 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5346 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5348 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5355 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5357 const BasicBlock *EHPadBB) {
5358 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5359 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5360 Type *RetTy = FTy->getReturnType();
5362 TargetLowering::ArgListTy Args;
5363 TargetLowering::ArgListEntry Entry;
5364 Args.reserve(CS.arg_size());
5366 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5368 const Value *V = *i;
5371 if (V->getType()->isEmptyTy())
5374 SDValue ArgNode = getValue(V);
5375 Entry.Node = ArgNode; Entry.Ty = V->getType();
5377 // Skip the first return-type Attribute to get to params.
5378 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5379 Args.push_back(Entry);
5381 // If we have an explicit sret argument that is an Instruction, (i.e., it
5382 // might point to function-local memory), we can't meaningfully tail-call.
5383 if (Entry.isSRet && isa<Instruction>(V))
5387 // Check if target-independent constraints permit a tail call here.
5388 // Target-dependent constraints are checked within TLI->LowerCallTo.
5389 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5392 TargetLowering::CallLoweringInfo CLI(DAG);
5393 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5394 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5395 .setTailCall(isTailCall);
5396 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5398 if (Result.first.getNode())
5399 setValue(CS.getInstruction(), Result.first);
5402 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5403 /// value is equal or not-equal to zero.
5404 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5405 for (const User *U : V->users()) {
5406 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5407 if (IC->isEquality())
5408 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5409 if (C->isNullValue())
5411 // Unknown instruction.
5417 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5419 SelectionDAGBuilder &Builder) {
5421 // Check to see if this load can be trivially constant folded, e.g. if the
5422 // input is from a string literal.
5423 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5424 // Cast pointer to the type we really want to load.
5425 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5426 PointerType::getUnqual(LoadTy));
5428 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5429 const_cast<Constant *>(LoadInput), *Builder.DL))
5430 return Builder.getValue(LoadCst);
5433 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5434 // still constant memory, the input chain can be the entry node.
5436 bool ConstantMemory = false;
5438 // Do not serialize (non-volatile) loads of constant memory with anything.
5439 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5440 Root = Builder.DAG.getEntryNode();
5441 ConstantMemory = true;
5443 // Do not serialize non-volatile loads against each other.
5444 Root = Builder.DAG.getRoot();
5447 SDValue Ptr = Builder.getValue(PtrVal);
5448 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5449 Ptr, MachinePointerInfo(PtrVal),
5451 false /*nontemporal*/,
5452 false /*isinvariant*/, 1 /* align=1 */);
5454 if (!ConstantMemory)
5455 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5459 /// processIntegerCallValue - Record the value for an instruction that
5460 /// produces an integer result, converting the type where necessary.
5461 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5464 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5467 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5469 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5470 setValue(&I, Value);
5473 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5474 /// If so, return true and lower it, otherwise return false and it will be
5475 /// lowered like a normal call.
5476 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5477 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5478 if (I.getNumArgOperands() != 3)
5481 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5482 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5483 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5484 !I.getType()->isIntegerTy())
5487 const Value *Size = I.getArgOperand(2);
5488 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5489 if (CSize && CSize->getZExtValue() == 0) {
5490 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5492 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5496 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5497 std::pair<SDValue, SDValue> Res =
5498 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5499 getValue(LHS), getValue(RHS), getValue(Size),
5500 MachinePointerInfo(LHS),
5501 MachinePointerInfo(RHS));
5502 if (Res.first.getNode()) {
5503 processIntegerCallValue(I, Res.first, true);
5504 PendingLoads.push_back(Res.second);
5508 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5509 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5510 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5511 bool ActuallyDoIt = true;
5514 switch (CSize->getZExtValue()) {
5516 LoadVT = MVT::Other;
5518 ActuallyDoIt = false;
5522 LoadTy = Type::getInt16Ty(CSize->getContext());
5526 LoadTy = Type::getInt32Ty(CSize->getContext());
5530 LoadTy = Type::getInt64Ty(CSize->getContext());
5534 LoadVT = MVT::v4i32;
5535 LoadTy = Type::getInt32Ty(CSize->getContext());
5536 LoadTy = VectorType::get(LoadTy, 4);
5541 // This turns into unaligned loads. We only do this if the target natively
5542 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5543 // we'll only produce a small number of byte loads.
5545 // Require that we can find a legal MVT, and only do this if the target
5546 // supports unaligned loads of that type. Expanding into byte loads would
5548 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5549 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5550 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5551 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5552 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5553 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5554 // TODO: Check alignment of src and dest ptrs.
5555 if (!TLI.isTypeLegal(LoadVT) ||
5556 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5557 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5558 ActuallyDoIt = false;
5562 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5563 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5565 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5567 processIntegerCallValue(I, Res, false);
5576 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5577 /// form. If so, return true and lower it, otherwise return false and it
5578 /// will be lowered like a normal call.
5579 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5580 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5581 if (I.getNumArgOperands() != 3)
5584 const Value *Src = I.getArgOperand(0);
5585 const Value *Char = I.getArgOperand(1);
5586 const Value *Length = I.getArgOperand(2);
5587 if (!Src->getType()->isPointerTy() ||
5588 !Char->getType()->isIntegerTy() ||
5589 !Length->getType()->isIntegerTy() ||
5590 !I.getType()->isPointerTy())
5593 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5594 std::pair<SDValue, SDValue> Res =
5595 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5596 getValue(Src), getValue(Char), getValue(Length),
5597 MachinePointerInfo(Src));
5598 if (Res.first.getNode()) {
5599 setValue(&I, Res.first);
5600 PendingLoads.push_back(Res.second);
5607 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5608 /// optimized form. If so, return true and lower it, otherwise return false
5609 /// and it will be lowered like a normal call.
5610 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5611 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5612 if (I.getNumArgOperands() != 2)
5615 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5616 if (!Arg0->getType()->isPointerTy() ||
5617 !Arg1->getType()->isPointerTy() ||
5618 !I.getType()->isPointerTy())
5621 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5622 std::pair<SDValue, SDValue> Res =
5623 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5624 getValue(Arg0), getValue(Arg1),
5625 MachinePointerInfo(Arg0),
5626 MachinePointerInfo(Arg1), isStpcpy);
5627 if (Res.first.getNode()) {
5628 setValue(&I, Res.first);
5629 DAG.setRoot(Res.second);
5636 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5637 /// If so, return true and lower it, otherwise return false and it will be
5638 /// lowered like a normal call.
5639 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5640 // Verify that the prototype makes sense. int strcmp(void*,void*)
5641 if (I.getNumArgOperands() != 2)
5644 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5645 if (!Arg0->getType()->isPointerTy() ||
5646 !Arg1->getType()->isPointerTy() ||
5647 !I.getType()->isIntegerTy())
5650 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5651 std::pair<SDValue, SDValue> Res =
5652 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5653 getValue(Arg0), getValue(Arg1),
5654 MachinePointerInfo(Arg0),
5655 MachinePointerInfo(Arg1));
5656 if (Res.first.getNode()) {
5657 processIntegerCallValue(I, Res.first, true);
5658 PendingLoads.push_back(Res.second);
5665 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5666 /// form. If so, return true and lower it, otherwise return false and it
5667 /// will be lowered like a normal call.
5668 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5669 // Verify that the prototype makes sense. size_t strlen(char *)
5670 if (I.getNumArgOperands() != 1)
5673 const Value *Arg0 = I.getArgOperand(0);
5674 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5677 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5678 std::pair<SDValue, SDValue> Res =
5679 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5680 getValue(Arg0), MachinePointerInfo(Arg0));
5681 if (Res.first.getNode()) {
5682 processIntegerCallValue(I, Res.first, false);
5683 PendingLoads.push_back(Res.second);
5690 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5691 /// form. If so, return true and lower it, otherwise return false and it
5692 /// will be lowered like a normal call.
5693 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5694 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5695 if (I.getNumArgOperands() != 2)
5698 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5699 if (!Arg0->getType()->isPointerTy() ||
5700 !Arg1->getType()->isIntegerTy() ||
5701 !I.getType()->isIntegerTy())
5704 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5705 std::pair<SDValue, SDValue> Res =
5706 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5707 getValue(Arg0), getValue(Arg1),
5708 MachinePointerInfo(Arg0));
5709 if (Res.first.getNode()) {
5710 processIntegerCallValue(I, Res.first, false);
5711 PendingLoads.push_back(Res.second);
5718 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5719 /// operation (as expected), translate it to an SDNode with the specified opcode
5720 /// and return true.
5721 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5723 // Sanity check that it really is a unary floating-point call.
5724 if (I.getNumArgOperands() != 1 ||
5725 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5726 I.getType() != I.getArgOperand(0)->getType() ||
5727 !I.onlyReadsMemory())
5730 SDValue Tmp = getValue(I.getArgOperand(0));
5731 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5735 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5736 /// operation (as expected), translate it to an SDNode with the specified opcode
5737 /// and return true.
5738 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5740 // Sanity check that it really is a binary floating-point call.
5741 if (I.getNumArgOperands() != 2 ||
5742 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5743 I.getType() != I.getArgOperand(0)->getType() ||
5744 I.getType() != I.getArgOperand(1)->getType() ||
5745 !I.onlyReadsMemory())
5748 SDValue Tmp0 = getValue(I.getArgOperand(0));
5749 SDValue Tmp1 = getValue(I.getArgOperand(1));
5750 EVT VT = Tmp0.getValueType();
5751 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5755 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5756 // Handle inline assembly differently.
5757 if (isa<InlineAsm>(I.getCalledValue())) {
5762 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5763 ComputeUsesVAFloatArgument(I, &MMI);
5765 const char *RenameFn = nullptr;
5766 if (Function *F = I.getCalledFunction()) {
5767 if (F->isDeclaration()) {
5768 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5769 if (unsigned IID = II->getIntrinsicID(F)) {
5770 RenameFn = visitIntrinsicCall(I, IID);
5775 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5776 RenameFn = visitIntrinsicCall(I, IID);
5782 // Check for well-known libc/libm calls. If the function is internal, it
5783 // can't be a library call.
5785 if (!F->hasLocalLinkage() && F->hasName() &&
5786 LibInfo->getLibFunc(F->getName(), Func) &&
5787 LibInfo->hasOptimizedCodeGen(Func)) {
5790 case LibFunc::copysign:
5791 case LibFunc::copysignf:
5792 case LibFunc::copysignl:
5793 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5794 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5795 I.getType() == I.getArgOperand(0)->getType() &&
5796 I.getType() == I.getArgOperand(1)->getType() &&
5797 I.onlyReadsMemory()) {
5798 SDValue LHS = getValue(I.getArgOperand(0));
5799 SDValue RHS = getValue(I.getArgOperand(1));
5800 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5801 LHS.getValueType(), LHS, RHS));
5806 case LibFunc::fabsf:
5807 case LibFunc::fabsl:
5808 if (visitUnaryFloatCall(I, ISD::FABS))
5812 case LibFunc::fminf:
5813 case LibFunc::fminl:
5814 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5818 case LibFunc::fmaxf:
5819 case LibFunc::fmaxl:
5820 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5826 if (visitUnaryFloatCall(I, ISD::FSIN))
5832 if (visitUnaryFloatCall(I, ISD::FCOS))
5836 case LibFunc::sqrtf:
5837 case LibFunc::sqrtl:
5838 case LibFunc::sqrt_finite:
5839 case LibFunc::sqrtf_finite:
5840 case LibFunc::sqrtl_finite:
5841 if (visitUnaryFloatCall(I, ISD::FSQRT))
5844 case LibFunc::floor:
5845 case LibFunc::floorf:
5846 case LibFunc::floorl:
5847 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5850 case LibFunc::nearbyint:
5851 case LibFunc::nearbyintf:
5852 case LibFunc::nearbyintl:
5853 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5857 case LibFunc::ceilf:
5858 case LibFunc::ceill:
5859 if (visitUnaryFloatCall(I, ISD::FCEIL))
5863 case LibFunc::rintf:
5864 case LibFunc::rintl:
5865 if (visitUnaryFloatCall(I, ISD::FRINT))
5868 case LibFunc::round:
5869 case LibFunc::roundf:
5870 case LibFunc::roundl:
5871 if (visitUnaryFloatCall(I, ISD::FROUND))
5874 case LibFunc::trunc:
5875 case LibFunc::truncf:
5876 case LibFunc::truncl:
5877 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5881 case LibFunc::log2f:
5882 case LibFunc::log2l:
5883 if (visitUnaryFloatCall(I, ISD::FLOG2))
5887 case LibFunc::exp2f:
5888 case LibFunc::exp2l:
5889 if (visitUnaryFloatCall(I, ISD::FEXP2))
5892 case LibFunc::memcmp:
5893 if (visitMemCmpCall(I))
5896 case LibFunc::memchr:
5897 if (visitMemChrCall(I))
5900 case LibFunc::strcpy:
5901 if (visitStrCpyCall(I, false))
5904 case LibFunc::stpcpy:
5905 if (visitStrCpyCall(I, true))
5908 case LibFunc::strcmp:
5909 if (visitStrCmpCall(I))
5912 case LibFunc::strlen:
5913 if (visitStrLenCall(I))
5916 case LibFunc::strnlen:
5917 if (visitStrNLenCall(I))
5926 Callee = getValue(I.getCalledValue());
5928 Callee = DAG.getExternalSymbol(
5930 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5932 // Check if we can potentially perform a tail call. More detailed checking is
5933 // be done within LowerCallTo, after more information about the call is known.
5934 LowerCallTo(&I, Callee, I.isTailCall());
5939 /// AsmOperandInfo - This contains information for each constraint that we are
5941 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5943 /// CallOperand - If this is the result output operand or a clobber
5944 /// this is null, otherwise it is the incoming operand to the CallInst.
5945 /// This gets modified as the asm is processed.
5946 SDValue CallOperand;
5948 /// AssignedRegs - If this is a register or register class operand, this
5949 /// contains the set of register corresponding to the operand.
5950 RegsForValue AssignedRegs;
5952 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5953 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5956 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5957 /// corresponds to. If there is no Value* for this operand, it returns
5959 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5960 const DataLayout &DL) const {
5961 if (!CallOperandVal) return MVT::Other;
5963 if (isa<BasicBlock>(CallOperandVal))
5964 return TLI.getPointerTy(DL);
5966 llvm::Type *OpTy = CallOperandVal->getType();
5968 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5969 // If this is an indirect operand, the operand is a pointer to the
5972 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5974 report_fatal_error("Indirect operand for inline asm not a pointer!");
5975 OpTy = PtrTy->getElementType();
5978 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5979 if (StructType *STy = dyn_cast<StructType>(OpTy))
5980 if (STy->getNumElements() == 1)
5981 OpTy = STy->getElementType(0);
5983 // If OpTy is not a single value, it may be a struct/union that we
5984 // can tile with integers.
5985 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5986 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5995 OpTy = IntegerType::get(Context, BitSize);
6000 return TLI.getValueType(DL, OpTy, true);
6004 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6006 } // end anonymous namespace
6008 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6009 /// specified operand. We prefer to assign virtual registers, to allow the
6010 /// register allocator to handle the assignment process. However, if the asm
6011 /// uses features that we can't model on machineinstrs, we have SDISel do the
6012 /// allocation. This produces generally horrible, but correct, code.
6014 /// OpInfo describes the operand.
6016 static void GetRegistersForValue(SelectionDAG &DAG,
6017 const TargetLowering &TLI,
6019 SDISelAsmOperandInfo &OpInfo) {
6020 LLVMContext &Context = *DAG.getContext();
6022 MachineFunction &MF = DAG.getMachineFunction();
6023 SmallVector<unsigned, 4> Regs;
6025 // If this is a constraint for a single physreg, or a constraint for a
6026 // register class, find it.
6027 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6028 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6029 OpInfo.ConstraintCode,
6030 OpInfo.ConstraintVT);
6032 unsigned NumRegs = 1;
6033 if (OpInfo.ConstraintVT != MVT::Other) {
6034 // If this is a FP input in an integer register (or visa versa) insert a bit
6035 // cast of the input value. More generally, handle any case where the input
6036 // value disagrees with the register class we plan to stick this in.
6037 if (OpInfo.Type == InlineAsm::isInput &&
6038 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6039 // Try to convert to the first EVT that the reg class contains. If the
6040 // types are identical size, use a bitcast to convert (e.g. two differing
6042 MVT RegVT = *PhysReg.second->vt_begin();
6043 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6044 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6045 RegVT, OpInfo.CallOperand);
6046 OpInfo.ConstraintVT = RegVT;
6047 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6048 // If the input is a FP value and we want it in FP registers, do a
6049 // bitcast to the corresponding integer type. This turns an f64 value
6050 // into i64, which can be passed with two i32 values on a 32-bit
6052 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6053 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6054 RegVT, OpInfo.CallOperand);
6055 OpInfo.ConstraintVT = RegVT;
6059 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6063 EVT ValueVT = OpInfo.ConstraintVT;
6065 // If this is a constraint for a specific physical register, like {r17},
6067 if (unsigned AssignedReg = PhysReg.first) {
6068 const TargetRegisterClass *RC = PhysReg.second;
6069 if (OpInfo.ConstraintVT == MVT::Other)
6070 ValueVT = *RC->vt_begin();
6072 // Get the actual register value type. This is important, because the user
6073 // may have asked for (e.g.) the AX register in i32 type. We need to
6074 // remember that AX is actually i16 to get the right extension.
6075 RegVT = *RC->vt_begin();
6077 // This is a explicit reference to a physical register.
6078 Regs.push_back(AssignedReg);
6080 // If this is an expanded reference, add the rest of the regs to Regs.
6082 TargetRegisterClass::iterator I = RC->begin();
6083 for (; *I != AssignedReg; ++I)
6084 assert(I != RC->end() && "Didn't find reg!");
6086 // Already added the first reg.
6088 for (; NumRegs; --NumRegs, ++I) {
6089 assert(I != RC->end() && "Ran out of registers to allocate!");
6094 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6098 // Otherwise, if this was a reference to an LLVM register class, create vregs
6099 // for this reference.
6100 if (const TargetRegisterClass *RC = PhysReg.second) {
6101 RegVT = *RC->vt_begin();
6102 if (OpInfo.ConstraintVT == MVT::Other)
6105 // Create the appropriate number of virtual registers.
6106 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6107 for (; NumRegs; --NumRegs)
6108 Regs.push_back(RegInfo.createVirtualRegister(RC));
6110 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6114 // Otherwise, we couldn't allocate enough registers for this.
6117 /// visitInlineAsm - Handle a call to an InlineAsm object.
6119 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6120 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6122 /// ConstraintOperands - Information about all of the constraints.
6123 SDISelAsmOperandInfoVector ConstraintOperands;
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6127 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6129 bool hasMemory = false;
6131 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6132 unsigned ResNo = 0; // ResNo - The result number of the next output.
6133 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6134 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6135 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6137 MVT OpVT = MVT::Other;
6139 // Compute the value type for each operand.
6140 switch (OpInfo.Type) {
6141 case InlineAsm::isOutput:
6142 // Indirect outputs just consume an argument.
6143 if (OpInfo.isIndirect) {
6144 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6148 // The return value of the call is this value. As such, there is no
6149 // corresponding argument.
6150 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6151 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6152 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6153 STy->getElementType(ResNo));
6155 assert(ResNo == 0 && "Asm only has one result!");
6156 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6160 case InlineAsm::isInput:
6161 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6163 case InlineAsm::isClobber:
6168 // If this is an input or an indirect output, process the call argument.
6169 // BasicBlocks are labels, currently appearing only in asm's.
6170 if (OpInfo.CallOperandVal) {
6171 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6172 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6174 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6177 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6178 DAG.getDataLayout()).getSimpleVT();
6181 OpInfo.ConstraintVT = OpVT;
6183 // Indirect operand accesses access memory.
6184 if (OpInfo.isIndirect)
6187 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6188 TargetLowering::ConstraintType
6189 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6190 if (CType == TargetLowering::C_Memory) {
6198 SDValue Chain, Flag;
6200 // We won't need to flush pending loads if this asm doesn't touch
6201 // memory and is nonvolatile.
6202 if (hasMemory || IA->hasSideEffects())
6205 Chain = DAG.getRoot();
6207 // Second pass over the constraints: compute which constraint option to use
6208 // and assign registers to constraints that want a specific physreg.
6209 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6210 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6212 // If this is an output operand with a matching input operand, look up the
6213 // matching input. If their types mismatch, e.g. one is an integer, the
6214 // other is floating point, or their sizes are different, flag it as an
6216 if (OpInfo.hasMatchingInput()) {
6217 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6219 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6220 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6221 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6222 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6223 OpInfo.ConstraintVT);
6224 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6225 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6226 Input.ConstraintVT);
6227 if ((OpInfo.ConstraintVT.isInteger() !=
6228 Input.ConstraintVT.isInteger()) ||
6229 (MatchRC.second != InputRC.second)) {
6230 report_fatal_error("Unsupported asm: input constraint"
6231 " with a matching output constraint of"
6232 " incompatible type!");
6234 Input.ConstraintVT = OpInfo.ConstraintVT;
6238 // Compute the constraint code and ConstraintType to use.
6239 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6241 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6242 OpInfo.Type == InlineAsm::isClobber)
6245 // If this is a memory input, and if the operand is not indirect, do what we
6246 // need to to provide an address for the memory input.
6247 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6248 !OpInfo.isIndirect) {
6249 assert((OpInfo.isMultipleAlternative ||
6250 (OpInfo.Type == InlineAsm::isInput)) &&
6251 "Can only indirectify direct input operands!");
6253 // Memory operands really want the address of the value. If we don't have
6254 // an indirect input, put it in the constpool if we can, otherwise spill
6255 // it to a stack slot.
6256 // TODO: This isn't quite right. We need to handle these according to
6257 // the addressing mode that the constraint wants. Also, this may take
6258 // an additional register for the computation and we don't want that
6261 // If the operand is a float, integer, or vector constant, spill to a
6262 // constant pool entry to get its address.
6263 const Value *OpVal = OpInfo.CallOperandVal;
6264 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6265 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6266 OpInfo.CallOperand = DAG.getConstantPool(
6267 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6269 // Otherwise, create a stack slot and emit a store to it before the
6271 Type *Ty = OpVal->getType();
6272 auto &DL = DAG.getDataLayout();
6273 uint64_t TySize = DL.getTypeAllocSize(Ty);
6274 unsigned Align = DL.getPrefTypeAlignment(Ty);
6275 MachineFunction &MF = DAG.getMachineFunction();
6276 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6278 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6279 Chain = DAG.getStore(
6280 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6281 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6283 OpInfo.CallOperand = StackSlot;
6286 // There is no longer a Value* corresponding to this operand.
6287 OpInfo.CallOperandVal = nullptr;
6289 // It is now an indirect operand.
6290 OpInfo.isIndirect = true;
6293 // If this constraint is for a specific register, allocate it before
6295 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6296 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6299 // Second pass - Loop over all of the operands, assigning virtual or physregs
6300 // to register class operands.
6301 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6302 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6304 // C_Register operands have already been allocated, Other/Memory don't need
6306 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6307 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6310 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6311 std::vector<SDValue> AsmNodeOperands;
6312 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6313 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6314 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6316 // If we have a !srcloc metadata node associated with it, we want to attach
6317 // this to the ultimately generated inline asm machineinstr. To do this, we
6318 // pass in the third operand as this (potentially null) inline asm MDNode.
6319 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6320 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6322 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6323 // bits as operand 3.
6324 unsigned ExtraInfo = 0;
6325 if (IA->hasSideEffects())
6326 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6327 if (IA->isAlignStack())
6328 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6329 // Set the asm dialect.
6330 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6332 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6333 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6334 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6336 // Compute the constraint code and ConstraintType to use.
6337 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6339 // Ideally, we would only check against memory constraints. However, the
6340 // meaning of an other constraint can be target-specific and we can't easily
6341 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6342 // for other constriants as well.
6343 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6344 OpInfo.ConstraintType == TargetLowering::C_Other) {
6345 if (OpInfo.Type == InlineAsm::isInput)
6346 ExtraInfo |= InlineAsm::Extra_MayLoad;
6347 else if (OpInfo.Type == InlineAsm::isOutput)
6348 ExtraInfo |= InlineAsm::Extra_MayStore;
6349 else if (OpInfo.Type == InlineAsm::isClobber)
6350 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6354 AsmNodeOperands.push_back(DAG.getTargetConstant(
6355 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6357 // Loop over all of the inputs, copying the operand values into the
6358 // appropriate registers and processing the output regs.
6359 RegsForValue RetValRegs;
6361 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6362 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6364 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6365 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6367 switch (OpInfo.Type) {
6368 case InlineAsm::isOutput: {
6369 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6370 OpInfo.ConstraintType != TargetLowering::C_Register) {
6371 // Memory output, or 'other' output (e.g. 'X' constraint).
6372 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6374 unsigned ConstraintID =
6375 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6376 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6377 "Failed to convert memory constraint code to constraint id.");
6379 // Add information to the INLINEASM node to know about this output.
6380 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6381 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6382 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6384 AsmNodeOperands.push_back(OpInfo.CallOperand);
6388 // Otherwise, this is a register or register class output.
6390 // Copy the output from the appropriate register. Find a register that
6392 if (OpInfo.AssignedRegs.Regs.empty()) {
6393 LLVMContext &Ctx = *DAG.getContext();
6394 Ctx.emitError(CS.getInstruction(),
6395 "couldn't allocate output register for constraint '" +
6396 Twine(OpInfo.ConstraintCode) + "'");
6400 // If this is an indirect operand, store through the pointer after the
6402 if (OpInfo.isIndirect) {
6403 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6404 OpInfo.CallOperandVal));
6406 // This is the result value of the call.
6407 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6408 // Concatenate this output onto the outputs list.
6409 RetValRegs.append(OpInfo.AssignedRegs);
6412 // Add information to the INLINEASM node to know that this register is
6415 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6416 ? InlineAsm::Kind_RegDefEarlyClobber
6417 : InlineAsm::Kind_RegDef,
6418 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6421 case InlineAsm::isInput: {
6422 SDValue InOperandVal = OpInfo.CallOperand;
6424 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6425 // If this is required to match an output register we have already set,
6426 // just use its register.
6427 unsigned OperandNo = OpInfo.getMatchedOperand();
6429 // Scan until we find the definition we already emitted of this operand.
6430 // When we find it, create a RegsForValue operand.
6431 unsigned CurOp = InlineAsm::Op_FirstOperand;
6432 for (; OperandNo; --OperandNo) {
6433 // Advance to the next operand.
6435 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6436 assert((InlineAsm::isRegDefKind(OpFlag) ||
6437 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6438 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6439 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6443 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6444 if (InlineAsm::isRegDefKind(OpFlag) ||
6445 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6446 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6447 if (OpInfo.isIndirect) {
6448 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6449 LLVMContext &Ctx = *DAG.getContext();
6450 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6451 " don't know how to handle tied "
6452 "indirect register inputs");
6456 RegsForValue MatchedRegs;
6457 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6458 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6459 MatchedRegs.RegVTs.push_back(RegVT);
6460 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6461 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6463 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6464 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6466 LLVMContext &Ctx = *DAG.getContext();
6467 Ctx.emitError(CS.getInstruction(),
6468 "inline asm error: This value"
6469 " type register class is not natively supported!");
6473 SDLoc dl = getCurSDLoc();
6474 // Use the produced MatchedRegs object to
6475 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6476 Chain, &Flag, CS.getInstruction());
6477 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6478 true, OpInfo.getMatchedOperand(), dl,
6479 DAG, AsmNodeOperands);
6483 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6484 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6485 "Unexpected number of operands");
6486 // Add information to the INLINEASM node to know about this input.
6487 // See InlineAsm.h isUseOperandTiedToDef.
6488 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6489 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6490 OpInfo.getMatchedOperand());
6491 AsmNodeOperands.push_back(DAG.getTargetConstant(
6492 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6493 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6497 // Treat indirect 'X' constraint as memory.
6498 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6500 OpInfo.ConstraintType = TargetLowering::C_Memory;
6502 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6503 std::vector<SDValue> Ops;
6504 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6507 LLVMContext &Ctx = *DAG.getContext();
6508 Ctx.emitError(CS.getInstruction(),
6509 "invalid operand for inline asm constraint '" +
6510 Twine(OpInfo.ConstraintCode) + "'");
6514 // Add information to the INLINEASM node to know about this input.
6515 unsigned ResOpType =
6516 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6517 AsmNodeOperands.push_back(DAG.getTargetConstant(
6518 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6519 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6523 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6524 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6525 assert(InOperandVal.getValueType() ==
6526 TLI.getPointerTy(DAG.getDataLayout()) &&
6527 "Memory operands expect pointer values");
6529 unsigned ConstraintID =
6530 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6531 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6532 "Failed to convert memory constraint code to constraint id.");
6534 // Add information to the INLINEASM node to know about this input.
6535 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6536 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6537 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6540 AsmNodeOperands.push_back(InOperandVal);
6544 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6545 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6546 "Unknown constraint type!");
6548 // TODO: Support this.
6549 if (OpInfo.isIndirect) {
6550 LLVMContext &Ctx = *DAG.getContext();
6551 Ctx.emitError(CS.getInstruction(),
6552 "Don't know how to handle indirect register inputs yet "
6553 "for constraint '" +
6554 Twine(OpInfo.ConstraintCode) + "'");
6558 // Copy the input into the appropriate registers.
6559 if (OpInfo.AssignedRegs.Regs.empty()) {
6560 LLVMContext &Ctx = *DAG.getContext();
6561 Ctx.emitError(CS.getInstruction(),
6562 "couldn't allocate input reg for constraint '" +
6563 Twine(OpInfo.ConstraintCode) + "'");
6567 SDLoc dl = getCurSDLoc();
6569 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6570 Chain, &Flag, CS.getInstruction());
6572 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6573 dl, DAG, AsmNodeOperands);
6576 case InlineAsm::isClobber: {
6577 // Add the clobbered value to the operand list, so that the register
6578 // allocator is aware that the physreg got clobbered.
6579 if (!OpInfo.AssignedRegs.Regs.empty())
6580 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6581 false, 0, getCurSDLoc(), DAG,
6588 // Finish up input operands. Set the input chain and add the flag last.
6589 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6590 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6592 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6593 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6594 Flag = Chain.getValue(1);
6596 // If this asm returns a register value, copy the result from that register
6597 // and set it as the value of the call.
6598 if (!RetValRegs.Regs.empty()) {
6599 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6600 Chain, &Flag, CS.getInstruction());
6602 // FIXME: Why don't we do this for inline asms with MRVs?
6603 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6604 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6606 // If any of the results of the inline asm is a vector, it may have the
6607 // wrong width/num elts. This can happen for register classes that can
6608 // contain multiple different value types. The preg or vreg allocated may
6609 // not have the same VT as was expected. Convert it to the right type
6610 // with bit_convert.
6611 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6612 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6615 } else if (ResultType != Val.getValueType() &&
6616 ResultType.isInteger() && Val.getValueType().isInteger()) {
6617 // If a result value was tied to an input value, the computed result may
6618 // have a wider width than the expected result. Extract the relevant
6620 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6623 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6626 setValue(CS.getInstruction(), Val);
6627 // Don't need to use this as a chain in this case.
6628 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6632 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6634 // Process indirect outputs, first output all of the flagged copies out of
6636 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6637 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6638 const Value *Ptr = IndirectStoresToEmit[i].second;
6639 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6641 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6644 // Emit the non-flagged stores from the physregs.
6645 SmallVector<SDValue, 8> OutChains;
6646 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6647 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6648 StoresToEmit[i].first,
6649 getValue(StoresToEmit[i].second),
6650 MachinePointerInfo(StoresToEmit[i].second),
6652 OutChains.push_back(Val);
6655 if (!OutChains.empty())
6656 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6661 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6662 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6663 MVT::Other, getRoot(),
6664 getValue(I.getArgOperand(0)),
6665 DAG.getSrcValue(I.getArgOperand(0))));
6668 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6669 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6670 const DataLayout &DL = DAG.getDataLayout();
6671 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6672 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6673 DAG.getSrcValue(I.getOperand(0)),
6674 DL.getABITypeAlignment(I.getType()));
6676 DAG.setRoot(V.getValue(1));
6679 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6680 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6681 MVT::Other, getRoot(),
6682 getValue(I.getArgOperand(0)),
6683 DAG.getSrcValue(I.getArgOperand(0))));
6686 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6687 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6688 MVT::Other, getRoot(),
6689 getValue(I.getArgOperand(0)),
6690 getValue(I.getArgOperand(1)),
6691 DAG.getSrcValue(I.getArgOperand(0)),
6692 DAG.getSrcValue(I.getArgOperand(1))));
6695 /// \brief Lower an argument list according to the target calling convention.
6697 /// \return A tuple of <return-value, token-chain>
6699 /// This is a helper for lowering intrinsics that follow a target calling
6700 /// convention or require stack pointer adjustment. Only a subset of the
6701 /// intrinsic's operands need to participate in the calling convention.
6702 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6703 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6704 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6705 TargetLowering::ArgListTy Args;
6706 Args.reserve(NumArgs);
6708 // Populate the argument list.
6709 // Attributes for args start at offset 1, after the return attribute.
6710 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6711 ArgI != ArgE; ++ArgI) {
6712 const Value *V = CS->getOperand(ArgI);
6714 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6716 TargetLowering::ArgListEntry Entry;
6717 Entry.Node = getValue(V);
6718 Entry.Ty = V->getType();
6719 Entry.setAttributes(&CS, AttrI);
6720 Args.push_back(Entry);
6723 TargetLowering::CallLoweringInfo CLI(DAG);
6724 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6725 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6726 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6728 return lowerInvokable(CLI, EHPadBB);
6731 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6732 /// or patchpoint target node's operand list.
6734 /// Constants are converted to TargetConstants purely as an optimization to
6735 /// avoid constant materialization and register allocation.
6737 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6738 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6739 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6740 /// address materialization and register allocation, but may also be required
6741 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6742 /// alloca in the entry block, then the runtime may assume that the alloca's
6743 /// StackMap location can be read immediately after compilation and that the
6744 /// location is valid at any point during execution (this is similar to the
6745 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6746 /// only available in a register, then the runtime would need to trap when
6747 /// execution reaches the StackMap in order to read the alloca's location.
6748 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6749 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6750 SelectionDAGBuilder &Builder) {
6751 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6752 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6753 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6755 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6757 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6758 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6759 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6760 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6761 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6763 Ops.push_back(OpVal);
6767 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6768 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6769 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6770 // [live variables...])
6772 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6774 SDValue Chain, InFlag, Callee, NullPtr;
6775 SmallVector<SDValue, 32> Ops;
6777 SDLoc DL = getCurSDLoc();
6778 Callee = getValue(CI.getCalledValue());
6779 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6781 // The stackmap intrinsic only records the live variables (the arguemnts
6782 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6783 // intrinsic, this won't be lowered to a function call. This means we don't
6784 // have to worry about calling conventions and target specific lowering code.
6785 // Instead we perform the call lowering right here.
6787 // chain, flag = CALLSEQ_START(chain, 0)
6788 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6789 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6791 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6792 InFlag = Chain.getValue(1);
6794 // Add the <id> and <numBytes> constants.
6795 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6796 Ops.push_back(DAG.getTargetConstant(
6797 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6798 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6799 Ops.push_back(DAG.getTargetConstant(
6800 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6803 // Push live variables for the stack map.
6804 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6806 // We are not pushing any register mask info here on the operands list,
6807 // because the stackmap doesn't clobber anything.
6809 // Push the chain and the glue flag.
6810 Ops.push_back(Chain);
6811 Ops.push_back(InFlag);
6813 // Create the STACKMAP node.
6814 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6815 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6816 Chain = SDValue(SM, 0);
6817 InFlag = Chain.getValue(1);
6819 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6821 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6823 // Set the root to the target-lowered call chain.
6826 // Inform the Frame Information that we have a stackmap in this function.
6827 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6830 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6831 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6832 const BasicBlock *EHPadBB) {
6833 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6838 // [live variables...])
6840 CallingConv::ID CC = CS.getCallingConv();
6841 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6842 bool HasDef = !CS->getType()->isVoidTy();
6843 SDLoc dl = getCurSDLoc();
6844 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6846 // Handle immediate and symbolic callees.
6847 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6848 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6850 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6851 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6852 SDLoc(SymbolicCallee),
6853 SymbolicCallee->getValueType(0));
6855 // Get the real number of arguments participating in the call <numArgs>
6856 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6857 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6859 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6860 // Intrinsics include all meta-operands up to but not including CC.
6861 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6862 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6863 "Not enough arguments provided to the patchpoint intrinsic");
6865 // For AnyRegCC the arguments are lowered later on manually.
6866 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6868 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6869 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6870 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6872 SDNode *CallEnd = Result.second.getNode();
6873 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6874 CallEnd = CallEnd->getOperand(0).getNode();
6876 /// Get a call instruction from the call sequence chain.
6877 /// Tail calls are not allowed.
6878 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6879 "Expected a callseq node.");
6880 SDNode *Call = CallEnd->getOperand(0).getNode();
6881 bool HasGlue = Call->getGluedNode();
6883 // Replace the target specific call node with the patchable intrinsic.
6884 SmallVector<SDValue, 8> Ops;
6886 // Add the <id> and <numBytes> constants.
6887 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6888 Ops.push_back(DAG.getTargetConstant(
6889 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6890 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6891 Ops.push_back(DAG.getTargetConstant(
6892 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6896 Ops.push_back(Callee);
6898 // Adjust <numArgs> to account for any arguments that have been passed on the
6900 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6901 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6902 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6903 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6905 // Add the calling convention
6906 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6908 // Add the arguments we omitted previously. The register allocator should
6909 // place these in any free register.
6911 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6912 Ops.push_back(getValue(CS.getArgument(i)));
6914 // Push the arguments from the call instruction up to the register mask.
6915 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6916 Ops.append(Call->op_begin() + 2, e);
6918 // Push live variables for the stack map.
6919 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6921 // Push the register mask info.
6923 Ops.push_back(*(Call->op_end()-2));
6925 Ops.push_back(*(Call->op_end()-1));
6927 // Push the chain (this is originally the first operand of the call, but
6928 // becomes now the last or second to last operand).
6929 Ops.push_back(*(Call->op_begin()));
6931 // Push the glue flag (last operand).
6933 Ops.push_back(*(Call->op_end()-1));
6936 if (IsAnyRegCC && HasDef) {
6937 // Create the return types based on the intrinsic definition
6938 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6939 SmallVector<EVT, 3> ValueVTs;
6940 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6941 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6943 // There is always a chain and a glue type at the end
6944 ValueVTs.push_back(MVT::Other);
6945 ValueVTs.push_back(MVT::Glue);
6946 NodeTys = DAG.getVTList(ValueVTs);
6948 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6950 // Replace the target specific call node with a PATCHPOINT node.
6951 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6954 // Update the NodeMap.
6957 setValue(CS.getInstruction(), SDValue(MN, 0));
6959 setValue(CS.getInstruction(), Result.first);
6962 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6963 // call sequence. Furthermore the location of the chain and glue can change
6964 // when the AnyReg calling convention is used and the intrinsic returns a
6966 if (IsAnyRegCC && HasDef) {
6967 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6968 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6969 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6971 DAG.ReplaceAllUsesWith(Call, MN);
6972 DAG.DeleteNode(Call);
6974 // Inform the Frame Information that we have a patchpoint in this function.
6975 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6978 /// Returns an AttributeSet representing the attributes applied to the return
6979 /// value of the given call.
6980 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6981 SmallVector<Attribute::AttrKind, 2> Attrs;
6983 Attrs.push_back(Attribute::SExt);
6985 Attrs.push_back(Attribute::ZExt);
6987 Attrs.push_back(Attribute::InReg);
6989 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6993 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6994 /// implementation, which just calls LowerCall.
6995 /// FIXME: When all targets are
6996 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6997 std::pair<SDValue, SDValue>
6998 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6999 // Handle the incoming return values from the call.
7001 Type *OrigRetTy = CLI.RetTy;
7002 SmallVector<EVT, 4> RetTys;
7003 SmallVector<uint64_t, 4> Offsets;
7004 auto &DL = CLI.DAG.getDataLayout();
7005 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
7007 SmallVector<ISD::OutputArg, 4> Outs;
7008 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
7010 bool CanLowerReturn =
7011 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7012 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7014 SDValue DemoteStackSlot;
7015 int DemoteStackIdx = -100;
7016 if (!CanLowerReturn) {
7017 // FIXME: equivalent assert?
7018 // assert(!CS.hasInAllocaArgument() &&
7019 // "sret demotion is incompatible with inalloca");
7020 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7021 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7022 MachineFunction &MF = CLI.DAG.getMachineFunction();
7023 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7024 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7026 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7028 Entry.Node = DemoteStackSlot;
7029 Entry.Ty = StackSlotPtrType;
7030 Entry.isSExt = false;
7031 Entry.isZExt = false;
7032 Entry.isInReg = false;
7033 Entry.isSRet = true;
7034 Entry.isNest = false;
7035 Entry.isByVal = false;
7036 Entry.isReturned = false;
7037 Entry.Alignment = Align;
7038 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7039 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7041 // sret demotion isn't compatible with tail-calls, since the sret argument
7042 // points into the callers stack frame.
7043 CLI.IsTailCall = false;
7045 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7047 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7048 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7049 for (unsigned i = 0; i != NumRegs; ++i) {
7050 ISD::InputArg MyFlags;
7051 MyFlags.VT = RegisterVT;
7053 MyFlags.Used = CLI.IsReturnValueUsed;
7055 MyFlags.Flags.setSExt();
7057 MyFlags.Flags.setZExt();
7059 MyFlags.Flags.setInReg();
7060 CLI.Ins.push_back(MyFlags);
7065 // Handle all of the outgoing arguments.
7067 CLI.OutVals.clear();
7068 ArgListTy &Args = CLI.getArgs();
7069 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7070 SmallVector<EVT, 4> ValueVTs;
7071 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7072 Type *FinalType = Args[i].Ty;
7073 if (Args[i].isByVal)
7074 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7075 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7076 FinalType, CLI.CallConv, CLI.IsVarArg);
7077 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7079 EVT VT = ValueVTs[Value];
7080 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7081 SDValue Op = SDValue(Args[i].Node.getNode(),
7082 Args[i].Node.getResNo() + Value);
7083 ISD::ArgFlagsTy Flags;
7084 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7090 if (Args[i].isInReg)
7094 if (Args[i].isByVal)
7096 if (Args[i].isInAlloca) {
7097 Flags.setInAlloca();
7098 // Set the byval flag for CCAssignFn callbacks that don't know about
7099 // inalloca. This way we can know how many bytes we should've allocated
7100 // and how many bytes a callee cleanup function will pop. If we port
7101 // inalloca to more targets, we'll have to add custom inalloca handling
7102 // in the various CC lowering callbacks.
7105 if (Args[i].isByVal || Args[i].isInAlloca) {
7106 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7107 Type *ElementTy = Ty->getElementType();
7108 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7109 // For ByVal, alignment should come from FE. BE will guess if this
7110 // info is not there but there are cases it cannot get right.
7111 unsigned FrameAlign;
7112 if (Args[i].Alignment)
7113 FrameAlign = Args[i].Alignment;
7115 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7116 Flags.setByValAlign(FrameAlign);
7121 Flags.setInConsecutiveRegs();
7122 Flags.setOrigAlign(OriginalAlignment);
7124 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7125 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7126 SmallVector<SDValue, 4> Parts(NumParts);
7127 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7130 ExtendKind = ISD::SIGN_EXTEND;
7131 else if (Args[i].isZExt)
7132 ExtendKind = ISD::ZERO_EXTEND;
7134 // Conservatively only handle 'returned' on non-vectors for now
7135 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7136 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7137 "unexpected use of 'returned'");
7138 // Before passing 'returned' to the target lowering code, ensure that
7139 // either the register MVT and the actual EVT are the same size or that
7140 // the return value and argument are extended in the same way; in these
7141 // cases it's safe to pass the argument register value unchanged as the
7142 // return register value (although it's at the target's option whether
7144 // TODO: allow code generation to take advantage of partially preserved
7145 // registers rather than clobbering the entire register when the
7146 // parameter extension method is not compatible with the return
7148 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7149 (ExtendKind != ISD::ANY_EXTEND &&
7150 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7151 Flags.setReturned();
7154 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7155 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7157 for (unsigned j = 0; j != NumParts; ++j) {
7158 // if it isn't first piece, alignment must be 1
7159 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7160 i < CLI.NumFixedArgs,
7161 i, j*Parts[j].getValueType().getStoreSize());
7162 if (NumParts > 1 && j == 0)
7163 MyFlags.Flags.setSplit();
7165 MyFlags.Flags.setOrigAlign(1);
7167 CLI.Outs.push_back(MyFlags);
7168 CLI.OutVals.push_back(Parts[j]);
7171 if (NeedsRegBlock && Value == NumValues - 1)
7172 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7176 SmallVector<SDValue, 4> InVals;
7177 CLI.Chain = LowerCall(CLI, InVals);
7179 // Verify that the target's LowerCall behaved as expected.
7180 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7181 "LowerCall didn't return a valid chain!");
7182 assert((!CLI.IsTailCall || InVals.empty()) &&
7183 "LowerCall emitted a return value for a tail call!");
7184 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7185 "LowerCall didn't emit the correct number of values!");
7187 // For a tail call, the return value is merely live-out and there aren't
7188 // any nodes in the DAG representing it. Return a special value to
7189 // indicate that a tail call has been emitted and no more Instructions
7190 // should be processed in the current block.
7191 if (CLI.IsTailCall) {
7192 CLI.DAG.setRoot(CLI.Chain);
7193 return std::make_pair(SDValue(), SDValue());
7196 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7197 assert(InVals[i].getNode() &&
7198 "LowerCall emitted a null value!");
7199 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7200 "LowerCall emitted a value with the wrong type!");
7203 SmallVector<SDValue, 4> ReturnValues;
7204 if (!CanLowerReturn) {
7205 // The instruction result is the result of loading from the
7206 // hidden sret parameter.
7207 SmallVector<EVT, 1> PVTs;
7208 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7210 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7211 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7212 EVT PtrVT = PVTs[0];
7214 unsigned NumValues = RetTys.size();
7215 ReturnValues.resize(NumValues);
7216 SmallVector<SDValue, 4> Chains(NumValues);
7218 for (unsigned i = 0; i < NumValues; ++i) {
7219 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7220 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7222 SDValue L = CLI.DAG.getLoad(
7223 RetTys[i], CLI.DL, CLI.Chain, Add,
7224 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7225 DemoteStackIdx, Offsets[i]),
7226 false, false, false, 1);
7227 ReturnValues[i] = L;
7228 Chains[i] = L.getValue(1);
7231 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7233 // Collect the legal value parts into potentially illegal values
7234 // that correspond to the original function's return values.
7235 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7237 AssertOp = ISD::AssertSext;
7238 else if (CLI.RetZExt)
7239 AssertOp = ISD::AssertZext;
7240 unsigned CurReg = 0;
7241 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7243 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7244 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7246 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7247 NumRegs, RegisterVT, VT, nullptr,
7252 // For a function returning void, there is no return value. We can't create
7253 // such a node, so we just return a null return value in that case. In
7254 // that case, nothing will actually look at the value.
7255 if (ReturnValues.empty())
7256 return std::make_pair(SDValue(), CLI.Chain);
7259 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7260 CLI.DAG.getVTList(RetTys), ReturnValues);
7261 return std::make_pair(Res, CLI.Chain);
7264 void TargetLowering::LowerOperationWrapper(SDNode *N,
7265 SmallVectorImpl<SDValue> &Results,
7266 SelectionDAG &DAG) const {
7267 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7269 Results.push_back(Res);
7272 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7273 llvm_unreachable("LowerOperation not implemented for this target!");
7277 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7278 SDValue Op = getNonRegisterValue(V);
7279 assert((Op.getOpcode() != ISD::CopyFromReg ||
7280 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7281 "Copy from a reg to the same reg!");
7282 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7284 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7285 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7287 SDValue Chain = DAG.getEntryNode();
7289 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7290 FuncInfo.PreferredExtendType.end())
7292 : FuncInfo.PreferredExtendType[V];
7293 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7294 PendingExports.push_back(Chain);
7297 #include "llvm/CodeGen/SelectionDAGISel.h"
7299 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7300 /// entry block, return true. This includes arguments used by switches, since
7301 /// the switch may expand into multiple basic blocks.
7302 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7303 // With FastISel active, we may be splitting blocks, so force creation
7304 // of virtual registers for all non-dead arguments.
7306 return A->use_empty();
7308 const BasicBlock &Entry = A->getParent()->front();
7309 for (const User *U : A->users())
7310 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7311 return false; // Use not in entry block.
7316 void SelectionDAGISel::LowerArguments(const Function &F) {
7317 SelectionDAG &DAG = SDB->DAG;
7318 SDLoc dl = SDB->getCurSDLoc();
7319 const DataLayout &DL = DAG.getDataLayout();
7320 SmallVector<ISD::InputArg, 16> Ins;
7322 if (!FuncInfo->CanLowerReturn) {
7323 // Put in an sret pointer parameter before all the other parameters.
7324 SmallVector<EVT, 1> ValueVTs;
7325 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7326 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7328 // NOTE: Assuming that a pointer will never break down to more than one VT
7330 ISD::ArgFlagsTy Flags;
7332 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7333 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7334 ISD::InputArg::NoArgIndex, 0);
7335 Ins.push_back(RetArg);
7338 // Set up the incoming argument description vector.
7340 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7341 I != E; ++I, ++Idx) {
7342 SmallVector<EVT, 4> ValueVTs;
7343 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7344 bool isArgValueUsed = !I->use_empty();
7345 unsigned PartBase = 0;
7346 Type *FinalType = I->getType();
7347 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7348 FinalType = cast<PointerType>(FinalType)->getElementType();
7349 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7350 FinalType, F.getCallingConv(), F.isVarArg());
7351 for (unsigned Value = 0, NumValues = ValueVTs.size();
7352 Value != NumValues; ++Value) {
7353 EVT VT = ValueVTs[Value];
7354 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7355 ISD::ArgFlagsTy Flags;
7356 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7358 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7360 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7362 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7364 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7366 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7368 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7369 Flags.setInAlloca();
7370 // Set the byval flag for CCAssignFn callbacks that don't know about
7371 // inalloca. This way we can know how many bytes we should've allocated
7372 // and how many bytes a callee cleanup function will pop. If we port
7373 // inalloca to more targets, we'll have to add custom inalloca handling
7374 // in the various CC lowering callbacks.
7377 if (Flags.isByVal() || Flags.isInAlloca()) {
7378 PointerType *Ty = cast<PointerType>(I->getType());
7379 Type *ElementTy = Ty->getElementType();
7380 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7381 // For ByVal, alignment should be passed from FE. BE will guess if
7382 // this info is not there but there are cases it cannot get right.
7383 unsigned FrameAlign;
7384 if (F.getParamAlignment(Idx))
7385 FrameAlign = F.getParamAlignment(Idx);
7387 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7388 Flags.setByValAlign(FrameAlign);
7390 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7393 Flags.setInConsecutiveRegs();
7394 Flags.setOrigAlign(OriginalAlignment);
7396 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7397 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7398 for (unsigned i = 0; i != NumRegs; ++i) {
7399 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7400 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7401 if (NumRegs > 1 && i == 0)
7402 MyFlags.Flags.setSplit();
7403 // if it isn't first piece, alignment must be 1
7405 MyFlags.Flags.setOrigAlign(1);
7406 Ins.push_back(MyFlags);
7408 if (NeedsRegBlock && Value == NumValues - 1)
7409 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7410 PartBase += VT.getStoreSize();
7414 // Call the target to set up the argument values.
7415 SmallVector<SDValue, 8> InVals;
7416 SDValue NewRoot = TLI->LowerFormalArguments(
7417 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7419 // Verify that the target's LowerFormalArguments behaved as expected.
7420 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7421 "LowerFormalArguments didn't return a valid chain!");
7422 assert(InVals.size() == Ins.size() &&
7423 "LowerFormalArguments didn't emit the correct number of values!");
7425 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7426 assert(InVals[i].getNode() &&
7427 "LowerFormalArguments emitted a null value!");
7428 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7429 "LowerFormalArguments emitted a value with the wrong type!");
7433 // Update the DAG with the new chain value resulting from argument lowering.
7434 DAG.setRoot(NewRoot);
7436 // Set up the argument values.
7439 if (!FuncInfo->CanLowerReturn) {
7440 // Create a virtual register for the sret pointer, and put in a copy
7441 // from the sret argument into it.
7442 SmallVector<EVT, 1> ValueVTs;
7443 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7444 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7445 MVT VT = ValueVTs[0].getSimpleVT();
7446 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7447 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7448 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7449 RegVT, VT, nullptr, AssertOp);
7451 MachineFunction& MF = SDB->DAG.getMachineFunction();
7452 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7453 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7454 FuncInfo->DemoteRegister = SRetReg;
7456 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7457 DAG.setRoot(NewRoot);
7459 // i indexes lowered arguments. Bump it past the hidden sret argument.
7460 // Idx indexes LLVM arguments. Don't touch it.
7464 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7466 SmallVector<SDValue, 4> ArgValues;
7467 SmallVector<EVT, 4> ValueVTs;
7468 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7469 unsigned NumValues = ValueVTs.size();
7471 // If this argument is unused then remember its value. It is used to generate
7472 // debugging information.
7473 if (I->use_empty() && NumValues) {
7474 SDB->setUnusedArgValue(&*I, InVals[i]);
7476 // Also remember any frame index for use in FastISel.
7477 if (FrameIndexSDNode *FI =
7478 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7479 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7482 for (unsigned Val = 0; Val != NumValues; ++Val) {
7483 EVT VT = ValueVTs[Val];
7484 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7485 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7487 if (!I->use_empty()) {
7488 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7489 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7490 AssertOp = ISD::AssertSext;
7491 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7492 AssertOp = ISD::AssertZext;
7494 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7495 NumParts, PartVT, VT,
7496 nullptr, AssertOp));
7502 // We don't need to do anything else for unused arguments.
7503 if (ArgValues.empty())
7506 // Note down frame index.
7507 if (FrameIndexSDNode *FI =
7508 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7509 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7511 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7512 SDB->getCurSDLoc());
7514 SDB->setValue(&*I, Res);
7515 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7516 if (LoadSDNode *LNode =
7517 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7518 if (FrameIndexSDNode *FI =
7519 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7520 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7523 // If this argument is live outside of the entry block, insert a copy from
7524 // wherever we got it to the vreg that other BB's will reference it as.
7525 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7526 // If we can, though, try to skip creating an unnecessary vreg.
7527 // FIXME: This isn't very clean... it would be nice to make this more
7528 // general. It's also subtly incompatible with the hacks FastISel
7530 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7531 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7532 FuncInfo->ValueMap[&*I] = Reg;
7536 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
7537 FuncInfo->InitializeRegForValue(&*I);
7538 SDB->CopyToExportRegsIfNeeded(&*I);
7542 assert(i == InVals.size() && "Argument register count mismatch!");
7544 // Finally, if the target has anything special to do, allow it to do so.
7545 EmitFunctionEntryCode();
7548 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7549 /// ensure constants are generated when needed. Remember the virtual registers
7550 /// that need to be added to the Machine PHI nodes as input. We cannot just
7551 /// directly add them, because expansion might result in multiple MBB's for one
7552 /// BB. As such, the start of the BB might correspond to a different MBB than
7556 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7557 const TerminatorInst *TI = LLVMBB->getTerminator();
7559 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7561 // Check PHI nodes in successors that expect a value to be available from this
7563 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7564 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7565 if (!isa<PHINode>(SuccBB->begin())) continue;
7566 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7568 // If this terminator has multiple identical successors (common for
7569 // switches), only handle each succ once.
7570 if (!SuccsHandled.insert(SuccMBB).second)
7573 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7575 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7576 // nodes and Machine PHI nodes, but the incoming operands have not been
7578 for (BasicBlock::const_iterator I = SuccBB->begin();
7579 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7580 // Ignore dead phi's.
7581 if (PN->use_empty()) continue;
7584 if (PN->getType()->isEmptyTy())
7588 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7590 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7591 unsigned &RegOut = ConstantsOut[C];
7593 RegOut = FuncInfo.CreateRegs(C->getType());
7594 CopyValueToVirtualRegister(C, RegOut);
7598 DenseMap<const Value *, unsigned>::iterator I =
7599 FuncInfo.ValueMap.find(PHIOp);
7600 if (I != FuncInfo.ValueMap.end())
7603 assert(isa<AllocaInst>(PHIOp) &&
7604 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7605 "Didn't codegen value into a register!??");
7606 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7607 CopyValueToVirtualRegister(PHIOp, Reg);
7611 // Remember that this register needs to added to the machine PHI node as
7612 // the input for this MBB.
7613 SmallVector<EVT, 4> ValueVTs;
7614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7615 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7616 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7617 EVT VT = ValueVTs[vti];
7618 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7619 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7620 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7621 Reg += NumRegisters;
7626 ConstantsOut.clear();
7629 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7632 SelectionDAGBuilder::StackProtectorDescriptor::
7633 AddSuccessorMBB(const BasicBlock *BB,
7634 MachineBasicBlock *ParentMBB,
7636 MachineBasicBlock *SuccMBB) {
7637 // If SuccBB has not been created yet, create it.
7639 MachineFunction *MF = ParentMBB->getParent();
7640 MachineFunction::iterator BBI(ParentMBB);
7641 SuccMBB = MF->CreateMachineBasicBlock(BB);
7642 MF->insert(++BBI, SuccMBB);
7644 // Add it as a successor of ParentMBB.
7645 ParentMBB->addSuccessor(
7646 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7650 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7651 MachineFunction::iterator I(MBB);
7652 if (++I == FuncInfo.MF->end())
7657 /// During lowering new call nodes can be created (such as memset, etc.).
7658 /// Those will become new roots of the current DAG, but complications arise
7659 /// when they are tail calls. In such cases, the call lowering will update
7660 /// the root, but the builder still needs to know that a tail call has been
7661 /// lowered in order to avoid generating an additional return.
7662 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7663 // If the node is null, we do have a tail call.
7664 if (MaybeTC.getNode() != nullptr)
7665 DAG.setRoot(MaybeTC);
7670 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7671 unsigned *TotalCases, unsigned First,
7673 assert(Last >= First);
7674 assert(TotalCases[Last] >= TotalCases[First]);
7676 APInt LowCase = Clusters[First].Low->getValue();
7677 APInt HighCase = Clusters[Last].High->getValue();
7678 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7680 // FIXME: A range of consecutive cases has 100% density, but only requires one
7681 // comparison to lower. We should discriminate against such consecutive ranges
7684 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7685 uint64_t Range = Diff + 1;
7688 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7690 assert(NumCases < UINT64_MAX / 100);
7691 assert(Range >= NumCases);
7693 return NumCases * 100 >= Range * MinJumpTableDensity;
7696 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7697 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7698 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7701 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7702 unsigned First, unsigned Last,
7703 const SwitchInst *SI,
7704 MachineBasicBlock *DefaultMBB,
7705 CaseCluster &JTCluster) {
7706 assert(First <= Last);
7708 uint32_t Weight = 0;
7709 unsigned NumCmps = 0;
7710 std::vector<MachineBasicBlock*> Table;
7711 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7712 for (unsigned I = First; I <= Last; ++I) {
7713 assert(Clusters[I].Kind == CC_Range);
7714 Weight += Clusters[I].Weight;
7715 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7716 APInt Low = Clusters[I].Low->getValue();
7717 APInt High = Clusters[I].High->getValue();
7718 NumCmps += (Low == High) ? 1 : 2;
7720 // Fill the gap between this and the previous cluster.
7721 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7722 assert(PreviousHigh.slt(Low));
7723 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7724 for (uint64_t J = 0; J < Gap; J++)
7725 Table.push_back(DefaultMBB);
7727 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7728 for (uint64_t J = 0; J < ClusterSize; ++J)
7729 Table.push_back(Clusters[I].MBB);
7730 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7733 unsigned NumDests = JTWeights.size();
7734 if (isSuitableForBitTests(NumDests, NumCmps,
7735 Clusters[First].Low->getValue(),
7736 Clusters[Last].High->getValue())) {
7737 // Clusters[First..Last] should be lowered as bit tests instead.
7741 // Create the MBB that will load from and jump through the table.
7742 // Note: We create it here, but it's not inserted into the function yet.
7743 MachineFunction *CurMF = FuncInfo.MF;
7744 MachineBasicBlock *JumpTableMBB =
7745 CurMF->CreateMachineBasicBlock(SI->getParent());
7747 // Add successors. Note: use table order for determinism.
7748 SmallPtrSet<MachineBasicBlock *, 8> Done;
7749 for (MachineBasicBlock *Succ : Table) {
7750 if (Done.count(Succ))
7752 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7756 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7757 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7758 ->createJumpTableIndex(Table);
7760 // Set up the jump table info.
7761 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7762 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7763 Clusters[Last].High->getValue(), SI->getCondition(),
7765 JTCases.emplace_back(std::move(JTH), std::move(JT));
7767 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7768 JTCases.size() - 1, Weight);
7772 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7773 const SwitchInst *SI,
7774 MachineBasicBlock *DefaultMBB) {
7776 // Clusters must be non-empty, sorted, and only contain Range clusters.
7777 assert(!Clusters.empty());
7778 for (CaseCluster &C : Clusters)
7779 assert(C.Kind == CC_Range);
7780 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7781 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7785 if (!areJTsAllowed(TLI))
7788 const int64_t N = Clusters.size();
7789 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7791 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7792 SmallVector<unsigned, 8> TotalCases(N);
7794 for (unsigned i = 0; i < N; ++i) {
7795 APInt Hi = Clusters[i].High->getValue();
7796 APInt Lo = Clusters[i].Low->getValue();
7797 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7799 TotalCases[i] += TotalCases[i - 1];
7802 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7803 // Cheap case: the whole range might be suitable for jump table.
7804 CaseCluster JTCluster;
7805 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7806 Clusters[0] = JTCluster;
7812 // The algorithm below is not suitable for -O0.
7813 if (TM.getOptLevel() == CodeGenOpt::None)
7816 // Split Clusters into minimum number of dense partitions. The algorithm uses
7817 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7818 // for the Case Statement'" (1994), but builds the MinPartitions array in
7819 // reverse order to make it easier to reconstruct the partitions in ascending
7820 // order. In the choice between two optimal partitionings, it picks the one
7821 // which yields more jump tables.
7823 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7824 SmallVector<unsigned, 8> MinPartitions(N);
7825 // LastElement[i] is the last element of the partition starting at i.
7826 SmallVector<unsigned, 8> LastElement(N);
7827 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7828 SmallVector<unsigned, 8> NumTables(N);
7830 // Base case: There is only one way to partition Clusters[N-1].
7831 MinPartitions[N - 1] = 1;
7832 LastElement[N - 1] = N - 1;
7833 assert(MinJumpTableSize > 1);
7834 NumTables[N - 1] = 0;
7836 // Note: loop indexes are signed to avoid underflow.
7837 for (int64_t i = N - 2; i >= 0; i--) {
7838 // Find optimal partitioning of Clusters[i..N-1].
7839 // Baseline: Put Clusters[i] into a partition on its own.
7840 MinPartitions[i] = MinPartitions[i + 1] + 1;
7842 NumTables[i] = NumTables[i + 1];
7844 // Search for a solution that results in fewer partitions.
7845 for (int64_t j = N - 1; j > i; j--) {
7846 // Try building a partition from Clusters[i..j].
7847 if (isDense(Clusters, &TotalCases[0], i, j)) {
7848 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7849 bool IsTable = j - i + 1 >= MinJumpTableSize;
7850 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7852 // If this j leads to fewer partitions, or same number of partitions
7853 // with more lookup tables, it is a better partitioning.
7854 if (NumPartitions < MinPartitions[i] ||
7855 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7856 MinPartitions[i] = NumPartitions;
7858 NumTables[i] = Tables;
7864 // Iterate over the partitions, replacing some with jump tables in-place.
7865 unsigned DstIndex = 0;
7866 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7867 Last = LastElement[First];
7868 assert(Last >= First);
7869 assert(DstIndex <= First);
7870 unsigned NumClusters = Last - First + 1;
7872 CaseCluster JTCluster;
7873 if (NumClusters >= MinJumpTableSize &&
7874 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7875 Clusters[DstIndex++] = JTCluster;
7877 for (unsigned I = First; I <= Last; ++I)
7878 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7881 Clusters.resize(DstIndex);
7884 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7885 // FIXME: Using the pointer type doesn't seem ideal.
7886 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7887 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7891 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7894 const APInt &High) {
7895 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7896 // range of cases both require only one branch to lower. Just looking at the
7897 // number of clusters and destinations should be enough to decide whether to
7900 // To lower a range with bit tests, the range must fit the bitwidth of a
7902 if (!rangeFitsInWord(Low, High))
7905 // Decide whether it's profitable to lower this range with bit tests. Each
7906 // destination requires a bit test and branch, and there is an overall range
7907 // check branch. For a small number of clusters, separate comparisons might be
7908 // cheaper, and for many destinations, splitting the range might be better.
7909 return (NumDests == 1 && NumCmps >= 3) ||
7910 (NumDests == 2 && NumCmps >= 5) ||
7911 (NumDests == 3 && NumCmps >= 6);
7914 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7915 unsigned First, unsigned Last,
7916 const SwitchInst *SI,
7917 CaseCluster &BTCluster) {
7918 assert(First <= Last);
7922 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7923 unsigned NumCmps = 0;
7924 for (int64_t I = First; I <= Last; ++I) {
7925 assert(Clusters[I].Kind == CC_Range);
7926 Dests.set(Clusters[I].MBB->getNumber());
7927 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7929 unsigned NumDests = Dests.count();
7931 APInt Low = Clusters[First].Low->getValue();
7932 APInt High = Clusters[Last].High->getValue();
7933 assert(Low.slt(High));
7935 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7941 const int BitWidth = DAG.getTargetLoweringInfo()
7942 .getPointerTy(DAG.getDataLayout())
7944 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7946 // Check if the clusters cover a contiguous range such that no value in the
7947 // range will jump to the default statement.
7948 bool ContiguousRange = true;
7949 for (int64_t I = First + 1; I <= Last; ++I) {
7950 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7951 ContiguousRange = false;
7956 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7957 // Optimize the case where all the case values fit in a word without having
7958 // to subtract minValue. In this case, we can optimize away the subtraction.
7959 LowBound = APInt::getNullValue(Low.getBitWidth());
7961 ContiguousRange = false;
7964 CmpRange = High - Low;
7968 uint32_t TotalWeight = 0;
7969 for (unsigned i = First; i <= Last; ++i) {
7970 // Find the CaseBits for this destination.
7972 for (j = 0; j < CBV.size(); ++j)
7973 if (CBV[j].BB == Clusters[i].MBB)
7975 if (j == CBV.size())
7976 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7977 CaseBits *CB = &CBV[j];
7979 // Update Mask, Bits and ExtraWeight.
7980 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7981 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7982 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7983 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7984 CB->Bits += Hi - Lo + 1;
7985 CB->ExtraWeight += Clusters[i].Weight;
7986 TotalWeight += Clusters[i].Weight;
7987 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7991 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7992 // Sort by weight first, number of bits second.
7993 if (a.ExtraWeight != b.ExtraWeight)
7994 return a.ExtraWeight > b.ExtraWeight;
7995 return a.Bits > b.Bits;
7998 for (auto &CB : CBV) {
7999 MachineBasicBlock *BitTestBB =
8000 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
8001 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
8003 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
8004 SI->getCondition(), -1U, MVT::Other, false,
8005 ContiguousRange, nullptr, nullptr, std::move(BTI),
8008 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
8009 BitTestCases.size() - 1, TotalWeight);
8013 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8014 const SwitchInst *SI) {
8015 // Partition Clusters into as few subsets as possible, where each subset has a
8016 // range that fits in a machine word and has <= 3 unique destinations.
8019 // Clusters must be sorted and contain Range or JumpTable clusters.
8020 assert(!Clusters.empty());
8021 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8022 for (const CaseCluster &C : Clusters)
8023 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8024 for (unsigned i = 1; i < Clusters.size(); ++i)
8025 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8028 // The algorithm below is not suitable for -O0.
8029 if (TM.getOptLevel() == CodeGenOpt::None)
8032 // If target does not have legal shift left, do not emit bit tests at all.
8033 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8034 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8035 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8038 int BitWidth = PTy.getSizeInBits();
8039 const int64_t N = Clusters.size();
8041 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8042 SmallVector<unsigned, 8> MinPartitions(N);
8043 // LastElement[i] is the last element of the partition starting at i.
8044 SmallVector<unsigned, 8> LastElement(N);
8046 // FIXME: This might not be the best algorithm for finding bit test clusters.
8048 // Base case: There is only one way to partition Clusters[N-1].
8049 MinPartitions[N - 1] = 1;
8050 LastElement[N - 1] = N - 1;
8052 // Note: loop indexes are signed to avoid underflow.
8053 for (int64_t i = N - 2; i >= 0; --i) {
8054 // Find optimal partitioning of Clusters[i..N-1].
8055 // Baseline: Put Clusters[i] into a partition on its own.
8056 MinPartitions[i] = MinPartitions[i + 1] + 1;
8059 // Search for a solution that results in fewer partitions.
8060 // Note: the search is limited by BitWidth, reducing time complexity.
8061 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8062 // Try building a partition from Clusters[i..j].
8065 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8066 Clusters[j].High->getValue()))
8069 // Check nbr of destinations and cluster types.
8070 // FIXME: This works, but doesn't seem very efficient.
8071 bool RangesOnly = true;
8072 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8073 for (int64_t k = i; k <= j; k++) {
8074 if (Clusters[k].Kind != CC_Range) {
8078 Dests.set(Clusters[k].MBB->getNumber());
8080 if (!RangesOnly || Dests.count() > 3)
8083 // Check if it's a better partition.
8084 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8085 if (NumPartitions < MinPartitions[i]) {
8086 // Found a better partition.
8087 MinPartitions[i] = NumPartitions;
8093 // Iterate over the partitions, replacing with bit-test clusters in-place.
8094 unsigned DstIndex = 0;
8095 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8096 Last = LastElement[First];
8097 assert(First <= Last);
8098 assert(DstIndex <= First);
8100 CaseCluster BitTestCluster;
8101 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8102 Clusters[DstIndex++] = BitTestCluster;
8104 size_t NumClusters = Last - First + 1;
8105 std::memmove(&Clusters[DstIndex], &Clusters[First],
8106 sizeof(Clusters[0]) * NumClusters);
8107 DstIndex += NumClusters;
8110 Clusters.resize(DstIndex);
8113 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8114 MachineBasicBlock *SwitchMBB,
8115 MachineBasicBlock *DefaultMBB) {
8116 MachineFunction *CurMF = FuncInfo.MF;
8117 MachineBasicBlock *NextMBB = nullptr;
8118 MachineFunction::iterator BBI(W.MBB);
8119 if (++BBI != FuncInfo.MF->end())
8122 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8124 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8126 if (Size == 2 && W.MBB == SwitchMBB) {
8127 // If any two of the cases has the same destination, and if one value
8128 // is the same as the other, but has one bit unset that the other has set,
8129 // use bit manipulation to do two compares at once. For example:
8130 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8131 // TODO: This could be extended to merge any 2 cases in switches with 3
8133 // TODO: Handle cases where W.CaseBB != SwitchBB.
8134 CaseCluster &Small = *W.FirstCluster;
8135 CaseCluster &Big = *W.LastCluster;
8137 if (Small.Low == Small.High && Big.Low == Big.High &&
8138 Small.MBB == Big.MBB) {
8139 const APInt &SmallValue = Small.Low->getValue();
8140 const APInt &BigValue = Big.Low->getValue();
8142 // Check that there is only one bit different.
8143 APInt CommonBit = BigValue ^ SmallValue;
8144 if (CommonBit.isPowerOf2()) {
8145 SDValue CondLHS = getValue(Cond);
8146 EVT VT = CondLHS.getValueType();
8147 SDLoc DL = getCurSDLoc();
8149 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8150 DAG.getConstant(CommonBit, DL, VT));
8151 SDValue Cond = DAG.getSetCC(
8152 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8155 // Update successor info.
8156 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8157 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8158 addSuccessorWithWeight(
8159 SwitchMBB, DefaultMBB,
8160 // The default destination is the first successor in IR.
8161 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8164 // Insert the true branch.
8166 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8167 DAG.getBasicBlock(Small.MBB));
8168 // Insert the false branch.
8169 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8170 DAG.getBasicBlock(DefaultMBB));
8172 DAG.setRoot(BrCond);
8178 if (TM.getOptLevel() != CodeGenOpt::None) {
8179 // Order cases by weight so the most likely case will be checked first.
8180 std::sort(W.FirstCluster, W.LastCluster + 1,
8181 [](const CaseCluster &a, const CaseCluster &b) {
8182 return a.Weight > b.Weight;
8185 // Rearrange the case blocks so that the last one falls through if possible
8186 // without without changing the order of weights.
8187 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8189 if (I->Weight > W.LastCluster->Weight)
8191 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8192 std::swap(*I, *W.LastCluster);
8198 // Compute total weight.
8199 uint32_t DefaultWeight = W.DefaultWeight;
8200 uint32_t UnhandledWeights = DefaultWeight;
8201 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8202 UnhandledWeights += I->Weight;
8203 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8206 MachineBasicBlock *CurMBB = W.MBB;
8207 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8208 MachineBasicBlock *Fallthrough;
8209 if (I == W.LastCluster) {
8210 // For the last cluster, fall through to the default destination.
8211 Fallthrough = DefaultMBB;
8213 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8214 CurMF->insert(BBI, Fallthrough);
8215 // Put Cond in a virtual register to make it available from the new blocks.
8216 ExportFromCurrentBlock(Cond);
8218 UnhandledWeights -= I->Weight;
8221 case CC_JumpTable: {
8222 // FIXME: Optimize away range check based on pivot comparisons.
8223 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8224 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8226 // The jump block hasn't been inserted yet; insert it here.
8227 MachineBasicBlock *JumpMBB = JT->MBB;
8228 CurMF->insert(BBI, JumpMBB);
8230 uint32_t JumpWeight = I->Weight;
8231 uint32_t FallthroughWeight = UnhandledWeights;
8233 // If the default statement is a target of the jump table, we evenly
8234 // distribute the default weight to successors of CurMBB. Also update
8235 // the weight on the edge from JumpMBB to Fallthrough.
8236 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8237 SE = JumpMBB->succ_end();
8239 if (*SI == DefaultMBB) {
8240 JumpWeight += DefaultWeight / 2;
8241 FallthroughWeight -= DefaultWeight / 2;
8242 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8247 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8248 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8250 // The jump table header will be inserted in our current block, do the
8251 // range check, and fall through to our fallthrough block.
8252 JTH->HeaderBB = CurMBB;
8253 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8255 // If we're in the right place, emit the jump table header right now.
8256 if (CurMBB == SwitchMBB) {
8257 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8258 JTH->Emitted = true;
8263 // FIXME: Optimize away range check based on pivot comparisons.
8264 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8266 // The bit test blocks haven't been inserted yet; insert them here.
8267 for (BitTestCase &BTC : BTB->Cases)
8268 CurMF->insert(BBI, BTC.ThisBB);
8270 // Fill in fields of the BitTestBlock.
8271 BTB->Parent = CurMBB;
8272 BTB->Default = Fallthrough;
8274 BTB->DefaultWeight = UnhandledWeights;
8275 // If the cases in bit test don't form a contiguous range, we evenly
8276 // distribute the weight on the edge to Fallthrough to two successors
8278 if (!BTB->ContiguousRange) {
8279 BTB->Weight += DefaultWeight / 2;
8280 BTB->DefaultWeight -= DefaultWeight / 2;
8283 // If we're in the right place, emit the bit test header right now.
8284 if (CurMBB == SwitchMBB) {
8285 visitBitTestHeader(*BTB, SwitchMBB);
8286 BTB->Emitted = true;
8291 const Value *RHS, *LHS, *MHS;
8293 if (I->Low == I->High) {
8294 // Check Cond == I->Low.
8300 // Check I->Low <= Cond <= I->High.
8307 // The false weight is the sum of all unhandled cases.
8308 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8311 if (CurMBB == SwitchMBB)
8312 visitSwitchCase(CB, SwitchMBB);
8314 SwitchCases.push_back(CB);
8319 CurMBB = Fallthrough;
8323 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8324 CaseClusterIt First,
8325 CaseClusterIt Last) {
8326 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8327 if (X.Weight != CC.Weight)
8328 return X.Weight > CC.Weight;
8330 // Ties are broken by comparing the case value.
8331 return X.Low->getValue().slt(CC.Low->getValue());
8335 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8336 const SwitchWorkListItem &W,
8338 MachineBasicBlock *SwitchMBB) {
8339 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8340 "Clusters not sorted?");
8342 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8344 // Balance the tree based on branch weights to create a near-optimal (in terms
8345 // of search time given key frequency) binary search tree. See e.g. Kurt
8346 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8347 CaseClusterIt LastLeft = W.FirstCluster;
8348 CaseClusterIt FirstRight = W.LastCluster;
8349 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8350 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8352 // Move LastLeft and FirstRight towards each other from opposite directions to
8353 // find a partitioning of the clusters which balances the weight on both
8354 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8355 // taken to ensure 0-weight nodes are distributed evenly.
8357 while (LastLeft + 1 < FirstRight) {
8358 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8359 LeftWeight += (++LastLeft)->Weight;
8361 RightWeight += (--FirstRight)->Weight;
8366 // Our binary search tree differs from a typical BST in that ours can have up
8367 // to three values in each leaf. The pivot selection above doesn't take that
8368 // into account, which means the tree might require more nodes and be less
8369 // efficient. We compensate for this here.
8371 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8372 unsigned NumRight = W.LastCluster - FirstRight + 1;
8374 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8375 // If one side has less than 3 clusters, and the other has more than 3,
8376 // consider taking a cluster from the other side.
8378 if (NumLeft < NumRight) {
8379 // Consider moving the first cluster on the right to the left side.
8380 CaseCluster &CC = *FirstRight;
8381 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8382 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8383 if (LeftSideRank <= RightSideRank) {
8384 // Moving the cluster to the left does not demote it.
8390 assert(NumRight < NumLeft);
8391 // Consider moving the last element on the left to the right side.
8392 CaseCluster &CC = *LastLeft;
8393 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8394 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8395 if (RightSideRank <= LeftSideRank) {
8396 // Moving the cluster to the right does not demot it.
8406 assert(LastLeft + 1 == FirstRight);
8407 assert(LastLeft >= W.FirstCluster);
8408 assert(FirstRight <= W.LastCluster);
8410 // Use the first element on the right as pivot since we will make less-than
8411 // comparisons against it.
8412 CaseClusterIt PivotCluster = FirstRight;
8413 assert(PivotCluster > W.FirstCluster);
8414 assert(PivotCluster <= W.LastCluster);
8416 CaseClusterIt FirstLeft = W.FirstCluster;
8417 CaseClusterIt LastRight = W.LastCluster;
8419 const ConstantInt *Pivot = PivotCluster->Low;
8421 // New blocks will be inserted immediately after the current one.
8422 MachineFunction::iterator BBI(W.MBB);
8425 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8426 // we can branch to its destination directly if it's squeezed exactly in
8427 // between the known lower bound and Pivot - 1.
8428 MachineBasicBlock *LeftMBB;
8429 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8430 FirstLeft->Low == W.GE &&
8431 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8432 LeftMBB = FirstLeft->MBB;
8434 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8435 FuncInfo.MF->insert(BBI, LeftMBB);
8437 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8438 // Put Cond in a virtual register to make it available from the new blocks.
8439 ExportFromCurrentBlock(Cond);
8442 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8443 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8444 // directly if RHS.High equals the current upper bound.
8445 MachineBasicBlock *RightMBB;
8446 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8447 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8448 RightMBB = FirstRight->MBB;
8450 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8451 FuncInfo.MF->insert(BBI, RightMBB);
8453 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8454 // Put Cond in a virtual register to make it available from the new blocks.
8455 ExportFromCurrentBlock(Cond);
8458 // Create the CaseBlock record that will be used to lower the branch.
8459 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8460 LeftWeight, RightWeight);
8462 if (W.MBB == SwitchMBB)
8463 visitSwitchCase(CB, SwitchMBB);
8465 SwitchCases.push_back(CB);
8468 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8469 // Extract cases from the switch.
8470 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8471 CaseClusterVector Clusters;
8472 Clusters.reserve(SI.getNumCases());
8473 for (auto I : SI.cases()) {
8474 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8475 const ConstantInt *CaseVal = I.getCaseValue();
8477 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8478 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8481 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8483 // Cluster adjacent cases with the same destination. We do this at all
8484 // optimization levels because it's cheap to do and will make codegen faster
8485 // if there are many clusters.
8486 sortAndRangeify(Clusters);
8488 if (TM.getOptLevel() != CodeGenOpt::None) {
8489 // Replace an unreachable default with the most popular destination.
8490 // FIXME: Exploit unreachable default more aggressively.
8491 bool UnreachableDefault =
8492 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8493 if (UnreachableDefault && !Clusters.empty()) {
8494 DenseMap<const BasicBlock *, unsigned> Popularity;
8495 unsigned MaxPop = 0;
8496 const BasicBlock *MaxBB = nullptr;
8497 for (auto I : SI.cases()) {
8498 const BasicBlock *BB = I.getCaseSuccessor();
8499 if (++Popularity[BB] > MaxPop) {
8500 MaxPop = Popularity[BB];
8505 assert(MaxPop > 0 && MaxBB);
8506 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8508 // Remove cases that were pointing to the destination that is now the
8510 CaseClusterVector New;
8511 New.reserve(Clusters.size());
8512 for (CaseCluster &CC : Clusters) {
8513 if (CC.MBB != DefaultMBB)
8516 Clusters = std::move(New);
8520 // If there is only the default destination, jump there directly.
8521 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8522 if (Clusters.empty()) {
8523 SwitchMBB->addSuccessor(DefaultMBB);
8524 if (DefaultMBB != NextBlock(SwitchMBB)) {
8525 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8526 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8531 findJumpTables(Clusters, &SI, DefaultMBB);
8532 findBitTestClusters(Clusters, &SI);
8535 dbgs() << "Case clusters: ";
8536 for (const CaseCluster &C : Clusters) {
8537 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8538 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8540 C.Low->getValue().print(dbgs(), true);
8541 if (C.Low != C.High) {
8543 C.High->getValue().print(dbgs(), true);
8550 assert(!Clusters.empty());
8551 SwitchWorkList WorkList;
8552 CaseClusterIt First = Clusters.begin();
8553 CaseClusterIt Last = Clusters.end() - 1;
8554 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8555 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8557 while (!WorkList.empty()) {
8558 SwitchWorkListItem W = WorkList.back();
8559 WorkList.pop_back();
8560 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8562 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8563 // For optimized builds, lower large range as a balanced binary tree.
8564 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8568 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);