1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
70 #define DEBUG_TYPE "isel"
72 /// LimitFloatPrecision - Generate low-precision inline sequences for
73 /// some float libcalls (6, 8 or 12 bits).
74 static unsigned LimitFloatPrecision;
76 static cl::opt<unsigned, true>
77 LimitFPPrecision("limit-float-precision",
78 cl::desc("Generate low-precision inline sequences "
79 "for some float libcalls"),
80 cl::location(LimitFloatPrecision),
84 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
85 cl::desc("Enable fast-math-flags for DAG nodes"));
87 // Limit the width of DAG chains. This is important in general to prevent
88 // DAG-based analysis from blowing up. For example, alias analysis and
89 // load clustering may not complete in reasonable time. It is difficult to
90 // recognize and avoid this situation within each individual analysis, and
91 // future analyses are likely to have the same behavior. Limiting DAG width is
92 // the safe approach and will be especially important with global DAGs.
94 // MaxParallelChains default is arbitrarily high to avoid affecting
95 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
96 // sequence over this should have been converted to llvm.memcpy by the
97 // frontend. It easy to induce this behavior with .ll code such as:
98 // %buffer = alloca [4096 x i8]
99 // %data = load [4096 x i8]* %argPtr
100 // store [4096 x i8] %data, [4096 x i8]* %buffer
101 static const unsigned MaxParallelChains = 64;
103 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts, unsigned NumParts,
105 MVT PartVT, EVT ValueVT, const Value *V);
107 /// getCopyFromParts - Create a value that contains the specified legal parts
108 /// combined into the value they represent. If the parts combine to a type
109 /// larger then ValueVT then AssertOp can be used to specify whether the extra
110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
111 /// (ISD::AssertSext).
112 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
113 const SDValue *Parts,
114 unsigned NumParts, MVT PartVT, EVT ValueVT,
116 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
117 if (ValueVT.isVector())
118 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
121 assert(NumParts > 0 && "No parts to assemble!");
122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 SDValue Val = Parts[0];
126 // Assemble the value from multiple parts.
127 if (ValueVT.isInteger()) {
128 unsigned PartBits = PartVT.getSizeInBits();
129 unsigned ValueBits = ValueVT.getSizeInBits();
131 // Assemble the power of 2 part.
132 unsigned RoundParts = NumParts & (NumParts - 1) ?
133 1 << Log2_32(NumParts) : NumParts;
134 unsigned RoundBits = PartBits * RoundParts;
135 EVT RoundVT = RoundBits == ValueBits ?
136 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
139 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
141 if (RoundParts > 2) {
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
145 RoundParts / 2, PartVT, HalfVT, V);
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
151 if (DAG.getDataLayout().isBigEndian())
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 if (RoundParts < NumParts) {
157 // Assemble the trailing non-power-of-2 part.
158 unsigned OddParts = NumParts - RoundParts;
159 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
160 Hi = getCopyFromParts(DAG, DL,
161 Parts + RoundParts, OddParts, PartVT, OddVT, V);
163 // Combine the round and odd parts.
165 if (DAG.getDataLayout().isBigEndian())
167 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
172 TLI.getPointerTy(DAG.getDataLayout())));
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
174 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
176 } else if (PartVT.isFloatingPoint()) {
177 // FP split into multiple FP parts (for ppcf128)
178 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
181 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
182 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
183 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
187 // FP split into integer parts (soft fp)
188 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
189 !PartVT.isVector() && "Unexpected split");
190 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
191 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
195 // There is now one part, held in Val. Correct it to match ValueVT.
196 EVT PartEVT = Val.getValueType();
198 if (PartEVT == ValueVT)
201 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
202 ValueVT.bitsLT(PartEVT)) {
203 // For an FP value in an integer part, we need to truncate to the right
205 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
206 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
209 if (PartEVT.isInteger() && ValueVT.isInteger()) {
210 if (ValueVT.bitsLT(PartEVT)) {
211 // For a truncate, see if we have any information to
212 // indicate whether the truncated bits will always be
213 // zero or sign-extension.
214 if (AssertOp != ISD::DELETED_NODE)
215 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
216 DAG.getValueType(ValueVT));
217 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
219 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
223 // FP_ROUND's are always exact here.
224 if (ValueVT.bitsLT(Val.getValueType()))
226 ISD::FP_ROUND, DL, ValueVT, Val,
227 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
229 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
232 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
233 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
235 llvm_unreachable("Unknown mismatch!");
238 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
239 const Twine &ErrMsg) {
240 const Instruction *I = dyn_cast_or_null<Instruction>(V);
242 return Ctx.emitError(ErrMsg);
244 const char *AsmError = ", possible invalid constraint for vector type";
245 if (const CallInst *CI = dyn_cast<CallInst>(I))
246 if (isa<InlineAsm>(CI->getCalledValue()))
247 return Ctx.emitError(I, ErrMsg + AsmError);
249 return Ctx.emitError(I, ErrMsg);
252 /// getCopyFromPartsVector - Create a value that contains the specified legal
253 /// parts combined into the value they represent. If the parts combine to a
254 /// type larger then ValueVT then AssertOp can be used to specify whether the
255 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
256 /// ValueVT (ISD::AssertSext).
257 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
258 const SDValue *Parts, unsigned NumParts,
259 MVT PartVT, EVT ValueVT, const Value *V) {
260 assert(ValueVT.isVector() && "Not a vector value");
261 assert(NumParts > 0 && "No parts to assemble!");
262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
263 SDValue Val = Parts[0];
265 // Handle a multi-element vector.
269 unsigned NumIntermediates;
271 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
272 NumIntermediates, RegisterVT);
273 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
274 NumParts = NumRegs; // Silence a compiler warning.
275 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
276 assert(RegisterVT.getSizeInBits() ==
277 Parts[0].getSimpleValueType().getSizeInBits() &&
278 "Part type sizes don't match!");
280 // Assemble the parts into intermediate operands.
281 SmallVector<SDValue, 8> Ops(NumIntermediates);
282 if (NumIntermediates == NumParts) {
283 // If the register was not expanded, truncate or copy the value,
285 for (unsigned i = 0; i != NumParts; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
287 PartVT, IntermediateVT, V);
288 } else if (NumParts > 0) {
289 // If the intermediate type was expanded, build the intermediate
290 // operands from the parts.
291 assert(NumParts % NumIntermediates == 0 &&
292 "Must expand into a divisible number of parts!");
293 unsigned Factor = NumParts / NumIntermediates;
294 for (unsigned i = 0; i != NumIntermediates; ++i)
295 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
296 PartVT, IntermediateVT, V);
299 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
300 // intermediate operands.
301 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
306 // There is now one part, held in Val. Correct it to match ValueVT.
307 EVT PartEVT = Val.getValueType();
309 if (PartEVT == ValueVT)
312 if (PartEVT.isVector()) {
313 // If the element type of the source/dest vectors are the same, but the
314 // parts vector has more elements than the value vector, then we have a
315 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
317 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
318 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
319 "Cannot narrow, it would be a lossy transformation");
321 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
322 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
325 // Vector/Vector bitcast.
326 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
327 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
329 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
330 "Cannot handle this kind of promotion");
331 // Promoted vector extract
332 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
336 // Trivial bitcast if the types are the same size and the destination
337 // vector type is legal.
338 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
339 TLI.isTypeLegal(ValueVT))
340 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
342 // Handle cases such as i8 -> <1 x i1>
343 if (ValueVT.getVectorNumElements() != 1) {
344 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
345 "non-trivial scalar-to-vector conversion");
346 return DAG.getUNDEF(ValueVT);
349 if (ValueVT.getVectorNumElements() == 1 &&
350 ValueVT.getVectorElementType() != PartEVT)
351 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
353 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
356 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
357 SDValue Val, SDValue *Parts, unsigned NumParts,
358 MVT PartVT, const Value *V);
360 /// getCopyToParts - Create a series of nodes that contain the specified value
361 /// split into legal parts. If the parts contain more bits than Val, then, for
362 /// integers, ExtendKind can be used to specify how to generate the extra bits.
363 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
364 SDValue Val, SDValue *Parts, unsigned NumParts,
365 MVT PartVT, const Value *V,
366 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
367 EVT ValueVT = Val.getValueType();
369 // Handle the vector case separately.
370 if (ValueVT.isVector())
371 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
373 unsigned PartBits = PartVT.getSizeInBits();
374 unsigned OrigNumParts = NumParts;
375 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
376 "Copying to an illegal type!");
381 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
382 EVT PartEVT = PartVT;
383 if (PartEVT == ValueVT) {
384 assert(NumParts == 1 && "No-op copy with multiple parts!");
389 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
390 // If the parts cover more bits than the value has, promote the value.
391 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
392 assert(NumParts == 1 && "Do not know what to promote to!");
393 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
395 if (ValueVT.isFloatingPoint()) {
396 // FP values need to be bitcast, then extended if they are being put
397 // into a larger container.
398 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
399 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
401 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
402 ValueVT.isInteger() &&
403 "Unknown mismatch!");
404 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
405 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
406 if (PartVT == MVT::x86mmx)
407 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 } else if (PartBits == ValueVT.getSizeInBits()) {
410 // Different types of the same size.
411 assert(NumParts == 1 && PartEVT != ValueVT);
412 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
413 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
414 // If the parts cover less bits than value has, truncate the value.
415 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
416 ValueVT.isInteger() &&
417 "Unknown mismatch!");
418 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
419 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
420 if (PartVT == MVT::x86mmx)
421 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
424 // The value may have changed - recompute ValueVT.
425 ValueVT = Val.getValueType();
426 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
427 "Failed to tile the value with PartVT!");
430 if (PartEVT != ValueVT)
431 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
432 "scalar-to-vector conversion failed");
438 // Expand the value into multiple parts.
439 if (NumParts & (NumParts - 1)) {
440 // The number of parts is not a power of 2. Split off and copy the tail.
441 assert(PartVT.isInteger() && ValueVT.isInteger() &&
442 "Do not know what to expand to!");
443 unsigned RoundParts = 1 << Log2_32(NumParts);
444 unsigned RoundBits = RoundParts * PartBits;
445 unsigned OddParts = NumParts - RoundParts;
446 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
447 DAG.getIntPtrConstant(RoundBits, DL));
448 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
450 if (DAG.getDataLayout().isBigEndian())
451 // The odd parts were reversed by getCopyToParts - unreverse them.
452 std::reverse(Parts + RoundParts, Parts + NumParts);
454 NumParts = RoundParts;
455 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
456 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
459 // The number of parts is a power of 2. Repeatedly bisect the value using
461 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
462 EVT::getIntegerVT(*DAG.getContext(),
463 ValueVT.getSizeInBits()),
466 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
467 for (unsigned i = 0; i < NumParts; i += StepSize) {
468 unsigned ThisBits = StepSize * PartBits / 2;
469 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
470 SDValue &Part0 = Parts[i];
471 SDValue &Part1 = Parts[i+StepSize/2];
473 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
474 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
475 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
476 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
478 if (ThisBits == PartBits && ThisVT != PartVT) {
479 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
480 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
485 if (DAG.getDataLayout().isBigEndian())
486 std::reverse(Parts, Parts + OrigNumParts);
490 /// getCopyToPartsVector - Create a series of nodes that contain the specified
491 /// value split into legal parts.
492 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
493 SDValue Val, SDValue *Parts, unsigned NumParts,
494 MVT PartVT, const Value *V) {
495 EVT ValueVT = Val.getValueType();
496 assert(ValueVT.isVector() && "Not a vector");
497 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
500 EVT PartEVT = PartVT;
501 if (PartEVT == ValueVT) {
503 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
504 // Bitconvert vector->vector case.
505 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
508 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
509 EVT ElementVT = PartVT.getVectorElementType();
510 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
512 SmallVector<SDValue, 16> Ops;
513 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
514 Ops.push_back(DAG.getNode(
515 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
516 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
518 for (unsigned i = ValueVT.getVectorNumElements(),
519 e = PartVT.getVectorNumElements(); i != e; ++i)
520 Ops.push_back(DAG.getUNDEF(ElementVT));
522 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
524 // FIXME: Use CONCAT for 2x -> 4x.
526 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
527 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
528 } else if (PartVT.isVector() &&
529 PartEVT.getVectorElementType().bitsGE(
530 ValueVT.getVectorElementType()) &&
531 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
533 // Promoted vector extract
534 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
536 // Vector -> scalar conversion.
537 assert(ValueVT.getVectorNumElements() == 1 &&
538 "Only trivial vector-to-scalar conversions should get here!");
540 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
541 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
543 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
550 // Handle a multi-element vector.
553 unsigned NumIntermediates;
554 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
556 NumIntermediates, RegisterVT);
557 unsigned NumElements = ValueVT.getVectorNumElements();
559 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
560 NumParts = NumRegs; // Silence a compiler warning.
561 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
563 // Split the vector into intermediate operands.
564 SmallVector<SDValue, 8> Ops(NumIntermediates);
565 for (unsigned i = 0; i != NumIntermediates; ++i) {
566 if (IntermediateVT.isVector())
568 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
569 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
570 TLI.getVectorIdxTy(DAG.getDataLayout())));
572 Ops[i] = DAG.getNode(
573 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
574 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
577 // Split the intermediate operands into legal parts.
578 if (NumParts == NumIntermediates) {
579 // If the register was not expanded, promote or copy the value,
581 for (unsigned i = 0; i != NumParts; ++i)
582 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
583 } else if (NumParts > 0) {
584 // If the intermediate type was expanded, split each the value into
586 assert(NumIntermediates != 0 && "division by zero");
587 assert(NumParts % NumIntermediates == 0 &&
588 "Must expand into a divisible number of parts!");
589 unsigned Factor = NumParts / NumIntermediates;
590 for (unsigned i = 0; i != NumIntermediates; ++i)
591 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
595 RegsForValue::RegsForValue() {}
597 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
599 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
601 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
602 const DataLayout &DL, unsigned Reg, Type *Ty) {
603 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
605 for (EVT ValueVT : ValueVTs) {
606 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
607 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
608 for (unsigned i = 0; i != NumRegs; ++i)
609 Regs.push_back(Reg + i);
610 RegVTs.push_back(RegisterVT);
615 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
616 /// this value and returns the result as a ValueVT value. This uses
617 /// Chain/Flag as the input and updates them for the output Chain/Flag.
618 /// If the Flag pointer is NULL, no flag is used.
619 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
620 FunctionLoweringInfo &FuncInfo,
622 SDValue &Chain, SDValue *Flag,
623 const Value *V) const {
624 // A Value with type {} or [0 x %t] needs no registers.
625 if (ValueVTs.empty())
628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
630 // Assemble the legal parts into the final values.
631 SmallVector<SDValue, 4> Values(ValueVTs.size());
632 SmallVector<SDValue, 8> Parts;
633 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
634 // Copy the legal parts from the registers.
635 EVT ValueVT = ValueVTs[Value];
636 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
637 MVT RegisterVT = RegVTs[Value];
639 Parts.resize(NumRegs);
640 for (unsigned i = 0; i != NumRegs; ++i) {
643 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
646 *Flag = P.getValue(2);
649 Chain = P.getValue(1);
652 // If the source register was virtual and if we know something about it,
653 // add an assert node.
654 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
655 !RegisterVT.isInteger() || RegisterVT.isVector())
658 const FunctionLoweringInfo::LiveOutInfo *LOI =
659 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
663 unsigned RegSize = RegisterVT.getSizeInBits();
664 unsigned NumSignBits = LOI->NumSignBits;
665 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
667 if (NumZeroBits == RegSize) {
668 // The current value is a zero.
669 // Explicitly express that as it would be easier for
670 // optimizations to kick in.
671 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
675 // FIXME: We capture more information than the dag can represent. For
676 // now, just use the tightest assertzext/assertsext possible.
678 EVT FromVT(MVT::Other);
679 if (NumSignBits == RegSize)
680 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
681 else if (NumZeroBits >= RegSize-1)
682 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
683 else if (NumSignBits > RegSize-8)
684 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
685 else if (NumZeroBits >= RegSize-8)
686 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
687 else if (NumSignBits > RegSize-16)
688 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
689 else if (NumZeroBits >= RegSize-16)
690 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
691 else if (NumSignBits > RegSize-32)
692 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
693 else if (NumZeroBits >= RegSize-32)
694 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
698 // Add an assertion node.
699 assert(FromVT != MVT::Other);
700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
701 RegisterVT, P, DAG.getValueType(FromVT));
704 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
705 NumRegs, RegisterVT, ValueVT, V);
710 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
713 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
714 /// specified value into the registers specified by this object. This uses
715 /// Chain/Flag as the input and updates them for the output Chain/Flag.
716 /// If the Flag pointer is NULL, no flag is used.
717 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
718 SDValue &Chain, SDValue *Flag, const Value *V,
719 ISD::NodeType PreferredExtendType) const {
720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
721 ISD::NodeType ExtendKind = PreferredExtendType;
723 // Get the list of the values's legal parts.
724 unsigned NumRegs = Regs.size();
725 SmallVector<SDValue, 8> Parts(NumRegs);
726 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
727 EVT ValueVT = ValueVTs[Value];
728 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
729 MVT RegisterVT = RegVTs[Value];
731 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
732 ExtendKind = ISD::ZERO_EXTEND;
734 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
735 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
739 // Copy the parts into the registers.
740 SmallVector<SDValue, 8> Chains(NumRegs);
741 for (unsigned i = 0; i != NumRegs; ++i) {
744 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
746 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
747 *Flag = Part.getValue(1);
750 Chains[i] = Part.getValue(0);
753 if (NumRegs == 1 || Flag)
754 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
755 // flagged to it. That is the CopyToReg nodes and the user are considered
756 // a single scheduling unit. If we create a TokenFactor and return it as
757 // chain, then the TokenFactor is both a predecessor (operand) of the
758 // user as well as a successor (the TF operands are flagged to the user).
759 // c1, f1 = CopyToReg
760 // c2, f2 = CopyToReg
761 // c3 = TokenFactor c1, c2
764 Chain = Chains[NumRegs-1];
766 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
769 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
770 /// operand list. This adds the code marker and includes the number of
771 /// values added into it.
772 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
773 unsigned MatchingIdx, SDLoc dl,
775 std::vector<SDValue> &Ops) const {
776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
780 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
781 else if (!Regs.empty() &&
782 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
783 // Put the register class of the virtual registers in the flag word. That
784 // way, later passes can recompute register class constraints for inline
785 // assembly as well as normal instructions.
786 // Don't do this for tied operands that can use the regclass information
788 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
789 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
790 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
793 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
796 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
797 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
798 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
799 MVT RegisterVT = RegVTs[Value];
800 for (unsigned i = 0; i != NumRegs; ++i) {
801 assert(Reg < Regs.size() && "Mismatch in # registers expected");
802 unsigned TheReg = Regs[Reg++];
803 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
805 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
806 // If we clobbered the stack pointer, MFI should know about it.
807 assert(DAG.getMachineFunction().getFrameInfo()->
808 hasOpaqueSPAdjustment());
814 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
815 const TargetLibraryInfo *li) {
819 DL = &DAG.getDataLayout();
820 Context = DAG.getContext();
821 LPadToCallSiteMap.clear();
824 /// clear - Clear out the current SelectionDAG and the associated
825 /// state and prepare this SelectionDAGBuilder object to be used
826 /// for a new block. This doesn't clear out information about
827 /// additional blocks that are needed to complete switch lowering
828 /// or PHI node updating; that information is cleared out as it is
830 void SelectionDAGBuilder::clear() {
832 UnusedArgNodeMap.clear();
833 PendingLoads.clear();
834 PendingExports.clear();
837 SDNodeOrder = LowestSDNodeOrder;
838 StatepointLowering.clear();
841 /// clearDanglingDebugInfo - Clear the dangling debug information
842 /// map. This function is separated from the clear so that debug
843 /// information that is dangling in a basic block can be properly
844 /// resolved in a different basic block. This allows the
845 /// SelectionDAG to resolve dangling debug information attached
847 void SelectionDAGBuilder::clearDanglingDebugInfo() {
848 DanglingDebugInfoMap.clear();
851 /// getRoot - Return the current virtual root of the Selection DAG,
852 /// flushing any PendingLoad items. This must be done before emitting
853 /// a store or any other node that may need to be ordered after any
854 /// prior load instructions.
856 SDValue SelectionDAGBuilder::getRoot() {
857 if (PendingLoads.empty())
858 return DAG.getRoot();
860 if (PendingLoads.size() == 1) {
861 SDValue Root = PendingLoads[0];
863 PendingLoads.clear();
867 // Otherwise, we have to make a token factor node.
868 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
870 PendingLoads.clear();
875 /// getControlRoot - Similar to getRoot, but instead of flushing all the
876 /// PendingLoad items, flush all the PendingExports items. It is necessary
877 /// to do this before emitting a terminator instruction.
879 SDValue SelectionDAGBuilder::getControlRoot() {
880 SDValue Root = DAG.getRoot();
882 if (PendingExports.empty())
885 // Turn all of the CopyToReg chains into one factored node.
886 if (Root.getOpcode() != ISD::EntryToken) {
887 unsigned i = 0, e = PendingExports.size();
888 for (; i != e; ++i) {
889 assert(PendingExports[i].getNode()->getNumOperands() > 1);
890 if (PendingExports[i].getNode()->getOperand(0) == Root)
891 break; // Don't add the root if we already indirectly depend on it.
895 PendingExports.push_back(Root);
898 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
900 PendingExports.clear();
905 void SelectionDAGBuilder::visit(const Instruction &I) {
906 // Set up outgoing PHI node register values before emitting the terminator.
907 if (isa<TerminatorInst>(&I))
908 HandlePHINodesInSuccessorBlocks(I.getParent());
914 visit(I.getOpcode(), I);
916 if (!isa<TerminatorInst>(&I) && !HasTailCall &&
917 !isStatepoint(&I)) // statepoints handle their exports internally
918 CopyToExportRegsIfNeeded(&I);
923 void SelectionDAGBuilder::visitPHI(const PHINode &) {
924 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
927 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
928 // Note: this doesn't use InstVisitor, because it has to work with
929 // ConstantExpr's in addition to instructions.
931 default: llvm_unreachable("Unknown instruction type encountered!");
932 // Build the switch statement using the Instruction.def file.
933 #define HANDLE_INST(NUM, OPCODE, CLASS) \
934 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
935 #include "llvm/IR/Instruction.def"
939 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
940 // generate the debug data structures now that we've seen its definition.
941 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
943 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
945 const DbgValueInst *DI = DDI.getDI();
946 DebugLoc dl = DDI.getdl();
947 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
948 DILocalVariable *Variable = DI->getVariable();
949 DIExpression *Expr = DI->getExpression();
950 assert(Variable->isValidLocationForIntrinsic(dl) &&
951 "Expected inlined-at fields to agree");
952 uint64_t Offset = DI->getOffset();
955 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, false,
957 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
958 false, Offset, dl, DbgSDNodeOrder);
959 DAG.AddDbgValue(SDV, Val.getNode(), false);
962 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
963 DanglingDebugInfoMap[V] = DanglingDebugInfo();
967 /// getCopyFromRegs - If there was virtual register allocated for the value V
968 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
969 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
970 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
973 if (It != FuncInfo.ValueMap.end()) {
974 unsigned InReg = It->second;
975 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
976 DAG.getDataLayout(), InReg, Ty);
977 SDValue Chain = DAG.getEntryNode();
978 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
979 resolveDanglingDebugInfo(V, Result);
985 /// getValue - Return an SDValue for the given Value.
986 SDValue SelectionDAGBuilder::getValue(const Value *V) {
987 // If we already have an SDValue for this value, use it. It's important
988 // to do this first, so that we don't create a CopyFromReg if we already
989 // have a regular SDValue.
990 SDValue &N = NodeMap[V];
991 if (N.getNode()) return N;
993 // If there's a virtual register allocated and initialized for this
995 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
996 if (copyFromReg.getNode()) {
1000 // Otherwise create a new SDValue and remember it.
1001 SDValue Val = getValueImpl(V);
1003 resolveDanglingDebugInfo(V, Val);
1007 // Return true if SDValue exists for the given Value
1008 bool SelectionDAGBuilder::findValue(const Value *V) const {
1009 return (NodeMap.find(V) != NodeMap.end()) ||
1010 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1013 /// getNonRegisterValue - Return an SDValue for the given Value, but
1014 /// don't look in FuncInfo.ValueMap for a virtual register.
1015 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1016 // If we already have an SDValue for this value, use it.
1017 SDValue &N = NodeMap[V];
1019 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1020 // Remove the debug location from the node as the node is about to be used
1021 // in a location which may differ from the original debug location. This
1022 // is relevant to Constant and ConstantFP nodes because they can appear
1023 // as constant expressions inside PHI nodes.
1024 N->setDebugLoc(DebugLoc());
1029 // Otherwise create a new SDValue and remember it.
1030 SDValue Val = getValueImpl(V);
1032 resolveDanglingDebugInfo(V, Val);
1036 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1037 /// Create an SDValue for the given value.
1038 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1041 if (const Constant *C = dyn_cast<Constant>(V)) {
1042 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1044 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1045 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1047 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1048 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1050 if (isa<ConstantPointerNull>(C)) {
1051 unsigned AS = V->getType()->getPointerAddressSpace();
1052 return DAG.getConstant(0, getCurSDLoc(),
1053 TLI.getPointerTy(DAG.getDataLayout(), AS));
1056 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1057 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1059 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1060 return DAG.getUNDEF(VT);
1062 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1063 visit(CE->getOpcode(), *CE);
1064 SDValue N1 = NodeMap[V];
1065 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1069 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1070 SmallVector<SDValue, 4> Constants;
1071 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1073 SDNode *Val = getValue(*OI).getNode();
1074 // If the operand is an empty aggregate, there are no values.
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Constants.push_back(SDValue(Val, i));
1082 return DAG.getMergeValues(Constants, getCurSDLoc());
1085 if (const ConstantDataSequential *CDS =
1086 dyn_cast<ConstantDataSequential>(C)) {
1087 SmallVector<SDValue, 4> Ops;
1088 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1089 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1090 // Add each leaf value from the operand to the Constants list
1091 // to form a flattened list of all the values.
1092 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1093 Ops.push_back(SDValue(Val, i));
1096 if (isa<ArrayType>(CDS->getType()))
1097 return DAG.getMergeValues(Ops, getCurSDLoc());
1098 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1102 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1103 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1104 "Unknown struct or array constant!");
1106 SmallVector<EVT, 4> ValueVTs;
1107 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1108 unsigned NumElts = ValueVTs.size();
1110 return SDValue(); // empty struct
1111 SmallVector<SDValue, 4> Constants(NumElts);
1112 for (unsigned i = 0; i != NumElts; ++i) {
1113 EVT EltVT = ValueVTs[i];
1114 if (isa<UndefValue>(C))
1115 Constants[i] = DAG.getUNDEF(EltVT);
1116 else if (EltVT.isFloatingPoint())
1117 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1119 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1122 return DAG.getMergeValues(Constants, getCurSDLoc());
1125 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1126 return DAG.getBlockAddress(BA, VT);
1128 VectorType *VecTy = cast<VectorType>(V->getType());
1129 unsigned NumElements = VecTy->getNumElements();
1131 // Now that we know the number and type of the elements, get that number of
1132 // elements into the Ops array based on what kind of constant it is.
1133 SmallVector<SDValue, 16> Ops;
1134 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1135 for (unsigned i = 0; i != NumElements; ++i)
1136 Ops.push_back(getValue(CV->getOperand(i)));
1138 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1140 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1143 if (EltVT.isFloatingPoint())
1144 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1146 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1147 Ops.assign(NumElements, Op);
1150 // Create a BUILD_VECTOR node.
1151 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1154 // If this is a static alloca, generate it as the frameindex instead of
1156 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1157 DenseMap<const AllocaInst*, int>::iterator SI =
1158 FuncInfo.StaticAllocaMap.find(AI);
1159 if (SI != FuncInfo.StaticAllocaMap.end())
1160 return DAG.getFrameIndex(SI->second,
1161 TLI.getPointerTy(DAG.getDataLayout()));
1164 // If this is an instruction which fast-isel has deferred, select it now.
1165 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1166 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1167 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1169 SDValue Chain = DAG.getEntryNode();
1170 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1173 llvm_unreachable("Can't get register for value!");
1176 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1177 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1178 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1179 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1180 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1181 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1182 if (IsMSVCCXX || IsCoreCLR)
1183 CatchPadMBB->setIsEHFuncletEntry();
1185 DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot()));
1188 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1189 // Update machine-CFG edge.
1190 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1191 FuncInfo.MBB->addSuccessor(TargetMBB);
1193 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1194 bool IsSEH = isAsynchronousEHPersonality(Pers);
1196 // If this is not a fall-through branch or optimizations are switched off,
1198 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1199 TM.getOptLevel() == CodeGenOpt::None)
1200 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1201 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1205 // Figure out the funclet membership for the catchret's successor.
1206 // This will be used by the FuncletLayout pass to determine how to order the
1208 // A 'catchret' returns to the outer scope's color.
1209 Value *ParentPad = I.getParentPad();
1210 const BasicBlock *SuccessorColor;
1211 if (isa<ConstantTokenNone>(ParentPad))
1212 SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1214 SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1215 assert(SuccessorColor && "No parent funclet for catchret!");
1216 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1217 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1219 // Create the terminator node.
1220 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1221 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1222 DAG.getBasicBlock(SuccessorColorMBB));
1226 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1227 // Don't emit any special code for the cleanuppad instruction. It just marks
1228 // the start of a funclet.
1229 FuncInfo.MBB->setIsEHFuncletEntry();
1230 FuncInfo.MBB->setIsCleanupFuncletEntry();
1233 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1234 /// many places it could ultimately go. In the IR, we have a single unwind
1235 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1236 /// This function skips over imaginary basic blocks that hold catchswitch
1237 /// instructions, and finds all the "real" machine
1238 /// basic block destinations. As those destinations may not be successors of
1239 /// EHPadBB, here we also calculate the edge probability to those destinations.
1240 /// The passed-in Prob is the edge probability to EHPadBB.
1241 static void findUnwindDestinations(
1242 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1243 BranchProbability Prob,
1244 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1246 EHPersonality Personality =
1247 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1248 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1249 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1252 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1253 BasicBlock *NewEHPadBB = nullptr;
1254 if (isa<LandingPadInst>(Pad)) {
1255 // Stop on landingpads. They are not funclets.
1256 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1258 } else if (isa<CleanupPadInst>(Pad)) {
1259 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1261 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1262 UnwindDests.back().first->setIsEHFuncletEntry();
1264 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1265 // Add the catchpad handlers to the possible destinations.
1266 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1267 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1268 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1269 if (IsMSVCCXX || IsCoreCLR)
1270 UnwindDests.back().first->setIsEHFuncletEntry();
1272 NewEHPadBB = CatchSwitch->getUnwindDest();
1277 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1278 if (BPI && NewEHPadBB)
1279 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1280 EHPadBB = NewEHPadBB;
1284 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1285 // Update successor info.
1286 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1287 auto UnwindDest = I.getUnwindDest();
1288 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1289 BranchProbability UnwindDestProb =
1291 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1292 : BranchProbability::getZero();
1293 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1294 for (auto &UnwindDest : UnwindDests) {
1295 UnwindDest.first->setIsEHPad();
1296 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1298 FuncInfo.MBB->normalizeSuccProbs();
1300 // Create the terminator node.
1302 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1306 void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1307 report_fatal_error("visitCatchSwitch not yet implemented!");
1310 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1312 auto &DL = DAG.getDataLayout();
1313 SDValue Chain = getControlRoot();
1314 SmallVector<ISD::OutputArg, 8> Outs;
1315 SmallVector<SDValue, 8> OutVals;
1317 if (!FuncInfo.CanLowerReturn) {
1318 unsigned DemoteReg = FuncInfo.DemoteRegister;
1319 const Function *F = I.getParent()->getParent();
1321 // Emit a store of the return value through the virtual register.
1322 // Leave Outs empty so that LowerReturn won't try to load return
1323 // registers the usual way.
1324 SmallVector<EVT, 1> PtrValueVTs;
1325 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1328 SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1329 DemoteReg, PtrValueVTs[0]);
1330 SDValue RetOp = getValue(I.getOperand(0));
1332 SmallVector<EVT, 4> ValueVTs;
1333 SmallVector<uint64_t, 4> Offsets;
1334 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1335 unsigned NumValues = ValueVTs.size();
1337 // An aggregate return value cannot wrap around the address space, so
1338 // offsets to its parts don't wrap either.
1340 Flags.setNoUnsignedWrap(true);
1342 SmallVector<SDValue, 4> Chains(NumValues);
1343 for (unsigned i = 0; i != NumValues; ++i) {
1344 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1345 RetPtr.getValueType(), RetPtr,
1346 DAG.getIntPtrConstant(Offsets[i],
1350 DAG.getStore(Chain, getCurSDLoc(),
1351 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1352 // FIXME: better loc info would be nice.
1353 Add, MachinePointerInfo(), false, false, 0);
1356 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1357 MVT::Other, Chains);
1358 } else if (I.getNumOperands() != 0) {
1359 SmallVector<EVT, 4> ValueVTs;
1360 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1361 unsigned NumValues = ValueVTs.size();
1363 SDValue RetOp = getValue(I.getOperand(0));
1365 const Function *F = I.getParent()->getParent();
1367 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1368 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1370 ExtendKind = ISD::SIGN_EXTEND;
1371 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1373 ExtendKind = ISD::ZERO_EXTEND;
1375 LLVMContext &Context = F->getContext();
1376 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1379 for (unsigned j = 0; j != NumValues; ++j) {
1380 EVT VT = ValueVTs[j];
1382 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1383 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1385 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1386 MVT PartVT = TLI.getRegisterType(Context, VT);
1387 SmallVector<SDValue, 4> Parts(NumParts);
1388 getCopyToParts(DAG, getCurSDLoc(),
1389 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1390 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1392 // 'inreg' on function refers to return value
1393 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1397 // Propagate extension type if any
1398 if (ExtendKind == ISD::SIGN_EXTEND)
1400 else if (ExtendKind == ISD::ZERO_EXTEND)
1403 for (unsigned i = 0; i < NumParts; ++i) {
1404 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1405 VT, /*isfixed=*/true, 0, 0));
1406 OutVals.push_back(Parts[i]);
1412 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1413 CallingConv::ID CallConv =
1414 DAG.getMachineFunction().getFunction()->getCallingConv();
1415 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1416 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1418 // Verify that the target's LowerReturn behaved as expected.
1419 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1420 "LowerReturn didn't return a valid chain!");
1422 // Update the DAG with the new chain value resulting from return lowering.
1426 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1427 /// created for it, emit nodes to copy the value into the virtual
1429 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1431 if (V->getType()->isEmptyTy())
1434 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1435 if (VMI != FuncInfo.ValueMap.end()) {
1436 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1437 CopyValueToVirtualRegister(V, VMI->second);
1441 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1442 /// the current basic block, add it to ValueMap now so that we'll get a
1444 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1445 // No need to export constants.
1446 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1448 // Already exported?
1449 if (FuncInfo.isExportedInst(V)) return;
1451 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1452 CopyValueToVirtualRegister(V, Reg);
1455 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1456 const BasicBlock *FromBB) {
1457 // The operands of the setcc have to be in this block. We don't know
1458 // how to export them from some other block.
1459 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1460 // Can export from current BB.
1461 if (VI->getParent() == FromBB)
1464 // Is already exported, noop.
1465 return FuncInfo.isExportedInst(V);
1468 // If this is an argument, we can export it if the BB is the entry block or
1469 // if it is already exported.
1470 if (isa<Argument>(V)) {
1471 if (FromBB == &FromBB->getParent()->getEntryBlock())
1474 // Otherwise, can only export this if it is already exported.
1475 return FuncInfo.isExportedInst(V);
1478 // Otherwise, constants can always be exported.
1482 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1484 SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1485 const MachineBasicBlock *Dst) const {
1486 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1487 const BasicBlock *SrcBB = Src->getBasicBlock();
1488 const BasicBlock *DstBB = Dst->getBasicBlock();
1490 // If BPI is not available, set the default probability as 1 / N, where N is
1491 // the number of successors.
1492 auto SuccSize = std::max<uint32_t>(
1493 std::distance(succ_begin(SrcBB), succ_end(SrcBB)), 1);
1494 return BranchProbability(1, SuccSize);
1496 return BPI->getEdgeProbability(SrcBB, DstBB);
1499 void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
1500 MachineBasicBlock *Dst,
1501 BranchProbability Prob) {
1503 Src->addSuccessorWithoutProb(Dst);
1505 if (Prob.isUnknown())
1506 Prob = getEdgeProbability(Src, Dst);
1507 Src->addSuccessor(Dst, Prob);
1511 static bool InBlock(const Value *V, const BasicBlock *BB) {
1512 if (const Instruction *I = dyn_cast<Instruction>(V))
1513 return I->getParent() == BB;
1517 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1518 /// This function emits a branch and is used at the leaves of an OR or an
1519 /// AND operator tree.
1522 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1523 MachineBasicBlock *TBB,
1524 MachineBasicBlock *FBB,
1525 MachineBasicBlock *CurBB,
1526 MachineBasicBlock *SwitchBB,
1527 BranchProbability TProb,
1528 BranchProbability FProb) {
1529 const BasicBlock *BB = CurBB->getBasicBlock();
1531 // If the leaf of the tree is a comparison, merge the condition into
1533 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1534 // The operands of the cmp have to be in this block. We don't know
1535 // how to export them from some other block. If this is the first block
1536 // of the sequence, no exporting is needed.
1537 if (CurBB == SwitchBB ||
1538 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1539 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1540 ISD::CondCode Condition;
1541 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1542 Condition = getICmpCondCode(IC->getPredicate());
1544 const FCmpInst *FC = cast<FCmpInst>(Cond);
1545 Condition = getFCmpCondCode(FC->getPredicate());
1546 if (TM.Options.NoNaNsFPMath)
1547 Condition = getFCmpCodeWithoutNaN(Condition);
1550 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1551 TBB, FBB, CurBB, TProb, FProb);
1552 SwitchCases.push_back(CB);
1557 // Create a CaseBlock record representing this branch.
1558 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1559 nullptr, TBB, FBB, CurBB, TProb, FProb);
1560 SwitchCases.push_back(CB);
1563 /// FindMergedConditions - If Cond is an expression like
1564 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1565 MachineBasicBlock *TBB,
1566 MachineBasicBlock *FBB,
1567 MachineBasicBlock *CurBB,
1568 MachineBasicBlock *SwitchBB,
1569 Instruction::BinaryOps Opc,
1570 BranchProbability TProb,
1571 BranchProbability FProb) {
1572 // If this node is not part of the or/and tree, emit it as a branch.
1573 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1574 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1575 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1576 BOp->getParent() != CurBB->getBasicBlock() ||
1577 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1578 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1579 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1584 // Create TmpBB after CurBB.
1585 MachineFunction::iterator BBI(CurBB);
1586 MachineFunction &MF = DAG.getMachineFunction();
1587 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1588 CurBB->getParent()->insert(++BBI, TmpBB);
1590 if (Opc == Instruction::Or) {
1591 // Codegen X | Y as:
1600 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1601 // The requirement is that
1602 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1603 // = TrueProb for original BB.
1604 // Assuming the original probabilities are A and B, one choice is to set
1605 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
1606 // A/(1+B) and 2B/(1+B). This choice assumes that
1607 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1608 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1609 // TmpBB, but the math is more complicated.
1611 auto NewTrueProb = TProb / 2;
1612 auto NewFalseProb = TProb / 2 + FProb;
1613 // Emit the LHS condition.
1614 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1615 NewTrueProb, NewFalseProb);
1617 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
1618 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
1619 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1620 // Emit the RHS condition into TmpBB.
1621 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1622 Probs[0], Probs[1]);
1624 assert(Opc == Instruction::And && "Unknown merge op!");
1625 // Codegen X & Y as:
1633 // This requires creation of TmpBB after CurBB.
1635 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1636 // The requirement is that
1637 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1638 // = FalseProb for original BB.
1639 // Assuming the original probabilities are A and B, one choice is to set
1640 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
1641 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
1642 // TrueProb for BB1 * FalseProb for TmpBB.
1644 auto NewTrueProb = TProb + FProb / 2;
1645 auto NewFalseProb = FProb / 2;
1646 // Emit the LHS condition.
1647 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1648 NewTrueProb, NewFalseProb);
1650 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
1651 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
1652 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1653 // Emit the RHS condition into TmpBB.
1654 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1655 Probs[0], Probs[1]);
1659 /// If the set of cases should be emitted as a series of branches, return true.
1660 /// If we should emit this as a bunch of and/or'd together conditions, return
1663 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1664 if (Cases.size() != 2) return true;
1666 // If this is two comparisons of the same values or'd or and'd together, they
1667 // will get folded into a single comparison, so don't emit two blocks.
1668 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1669 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1670 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1671 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1675 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1676 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1677 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1678 Cases[0].CC == Cases[1].CC &&
1679 isa<Constant>(Cases[0].CmpRHS) &&
1680 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1681 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1683 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1690 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1691 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1693 // Update machine-CFG edges.
1694 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1696 if (I.isUnconditional()) {
1697 // Update machine-CFG edges.
1698 BrMBB->addSuccessor(Succ0MBB);
1700 // If this is not a fall-through branch or optimizations are switched off,
1702 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1703 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1704 MVT::Other, getControlRoot(),
1705 DAG.getBasicBlock(Succ0MBB)));
1710 // If this condition is one of the special cases we handle, do special stuff
1712 const Value *CondVal = I.getCondition();
1713 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1715 // If this is a series of conditions that are or'd or and'd together, emit
1716 // this as a sequence of branches instead of setcc's with and/or operations.
1717 // As long as jumps are not expensive, this should improve performance.
1718 // For example, instead of something like:
1731 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1732 Instruction::BinaryOps Opcode = BOp->getOpcode();
1733 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1734 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1735 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1736 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1738 getEdgeProbability(BrMBB, Succ0MBB),
1739 getEdgeProbability(BrMBB, Succ1MBB));
1740 // If the compares in later blocks need to use values not currently
1741 // exported from this block, export them now. This block should always
1742 // be the first entry.
1743 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1745 // Allow some cases to be rejected.
1746 if (ShouldEmitAsBranches(SwitchCases)) {
1747 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1748 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1749 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1752 // Emit the branch for this block.
1753 visitSwitchCase(SwitchCases[0], BrMBB);
1754 SwitchCases.erase(SwitchCases.begin());
1758 // Okay, we decided not to do this, remove any inserted MBB's and clear
1760 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1761 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1763 SwitchCases.clear();
1767 // Create a CaseBlock record representing this branch.
1768 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1769 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1771 // Use visitSwitchCase to actually insert the fast branch sequence for this
1773 visitSwitchCase(CB, BrMBB);
1776 /// visitSwitchCase - Emits the necessary code to represent a single node in
1777 /// the binary search tree resulting from lowering a switch instruction.
1778 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1779 MachineBasicBlock *SwitchBB) {
1781 SDValue CondLHS = getValue(CB.CmpLHS);
1782 SDLoc dl = getCurSDLoc();
1784 // Build the setcc now.
1786 // Fold "(X == true)" to X and "(X == false)" to !X to
1787 // handle common cases produced by branch lowering.
1788 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1789 CB.CC == ISD::SETEQ)
1791 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1792 CB.CC == ISD::SETEQ) {
1793 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1794 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1796 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1798 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1800 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1801 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1803 SDValue CmpOp = getValue(CB.CmpMHS);
1804 EVT VT = CmpOp.getValueType();
1806 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1807 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1810 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1811 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1812 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1813 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1817 // Update successor info
1818 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
1819 // TrueBB and FalseBB are always different unless the incoming IR is
1820 // degenerate. This only happens when running llc on weird IR.
1821 if (CB.TrueBB != CB.FalseBB)
1822 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
1823 SwitchBB->normalizeSuccProbs();
1825 // If the lhs block is the next block, invert the condition so that we can
1826 // fall through to the lhs instead of the rhs block.
1827 if (CB.TrueBB == NextBlock(SwitchBB)) {
1828 std::swap(CB.TrueBB, CB.FalseBB);
1829 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1830 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1833 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1834 MVT::Other, getControlRoot(), Cond,
1835 DAG.getBasicBlock(CB.TrueBB));
1837 // Insert the false branch. Do this even if it's a fall through branch,
1838 // this makes it easier to do DAG optimizations which require inverting
1839 // the branch condition.
1840 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1841 DAG.getBasicBlock(CB.FalseBB));
1843 DAG.setRoot(BrCond);
1846 /// visitJumpTable - Emit JumpTable node in the current MBB
1847 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1848 // Emit the code for the jump table
1849 assert(JT.Reg != -1U && "Should lower JT Header first!");
1850 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1851 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1853 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1854 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1855 MVT::Other, Index.getValue(1),
1857 DAG.setRoot(BrJumpTable);
1860 /// visitJumpTableHeader - This function emits necessary code to produce index
1861 /// in the JumpTable from switch case.
1862 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1863 JumpTableHeader &JTH,
1864 MachineBasicBlock *SwitchBB) {
1865 SDLoc dl = getCurSDLoc();
1867 // Subtract the lowest switch case value from the value being switched on and
1868 // conditional branch to default mbb if the result is greater than the
1869 // difference between smallest and largest cases.
1870 SDValue SwitchOp = getValue(JTH.SValue);
1871 EVT VT = SwitchOp.getValueType();
1872 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1873 DAG.getConstant(JTH.First, dl, VT));
1875 // The SDNode we just created, which holds the value being switched on minus
1876 // the smallest case value, needs to be copied to a virtual register so it
1877 // can be used as an index into the jump table in a subsequent basic block.
1878 // This value may be smaller or larger than the target's pointer type, and
1879 // therefore require extension or truncating.
1880 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1881 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1883 unsigned JumpTableReg =
1884 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1885 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1886 JumpTableReg, SwitchOp);
1887 JT.Reg = JumpTableReg;
1889 // Emit the range check for the jump table, and branch to the default block
1890 // for the switch statement if the value being switched on exceeds the largest
1891 // case in the switch.
1892 SDValue CMP = DAG.getSetCC(
1893 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1894 Sub.getValueType()),
1895 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1897 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1898 MVT::Other, CopyTo, CMP,
1899 DAG.getBasicBlock(JT.Default));
1901 // Avoid emitting unnecessary branches to the next block.
1902 if (JT.MBB != NextBlock(SwitchBB))
1903 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1904 DAG.getBasicBlock(JT.MBB));
1906 DAG.setRoot(BrCond);
1909 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1910 /// tail spliced into a stack protector check success bb.
1912 /// For a high level explanation of how this fits into the stack protector
1913 /// generation see the comment on the declaration of class
1914 /// StackProtectorDescriptor.
1915 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1916 MachineBasicBlock *ParentBB) {
1918 // First create the loads to the guard/stack slot for the comparison.
1919 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1920 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1922 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1923 int FI = MFI->getStackProtectorIndex();
1925 const Value *IRGuard = SPD.getGuard();
1926 SDValue GuardPtr = getValue(IRGuard);
1927 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1929 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1932 SDLoc dl = getCurSDLoc();
1934 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1935 // guard value from the virtual register holding the value. Otherwise, emit a
1936 // volatile load to retrieve the stack guard value.
1937 unsigned GuardReg = SPD.getGuardReg();
1939 if (GuardReg && TLI.useLoadStackGuardNode())
1940 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1943 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1944 GuardPtr, MachinePointerInfo(IRGuard, 0),
1945 true, false, false, Align);
1947 SDValue StackSlot = DAG.getLoad(
1948 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1949 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1950 false, false, Align);
1952 // Perform the comparison via a subtract/getsetcc.
1953 EVT VT = Guard.getValueType();
1954 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1956 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1958 Sub.getValueType()),
1959 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1961 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1962 // branch to failure MBB.
1963 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1964 MVT::Other, StackSlot.getOperand(0),
1965 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1966 // Otherwise branch to success MBB.
1967 SDValue Br = DAG.getNode(ISD::BR, dl,
1969 DAG.getBasicBlock(SPD.getSuccessMBB()));
1974 /// Codegen the failure basic block for a stack protector check.
1976 /// A failure stack protector machine basic block consists simply of a call to
1977 /// __stack_chk_fail().
1979 /// For a high level explanation of how this fits into the stack protector
1980 /// generation see the comment on the declaration of class
1981 /// StackProtectorDescriptor.
1983 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1984 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1986 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1987 None, false, getCurSDLoc(), false, false).second;
1991 /// visitBitTestHeader - This function emits necessary code to produce value
1992 /// suitable for "bit tests"
1993 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1994 MachineBasicBlock *SwitchBB) {
1995 SDLoc dl = getCurSDLoc();
1997 // Subtract the minimum value
1998 SDValue SwitchOp = getValue(B.SValue);
1999 EVT VT = SwitchOp.getValueType();
2000 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2001 DAG.getConstant(B.First, dl, VT));
2004 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2005 SDValue RangeCmp = DAG.getSetCC(
2006 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2007 Sub.getValueType()),
2008 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2010 // Determine the type of the test operands.
2011 bool UsePtrType = false;
2012 if (!TLI.isTypeLegal(VT))
2015 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2016 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2017 // Switch table case range are encoded into series of masks.
2018 // Just use pointer type, it's guaranteed to fit.
2024 VT = TLI.getPointerTy(DAG.getDataLayout());
2025 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2028 B.RegVT = VT.getSimpleVT();
2029 B.Reg = FuncInfo.CreateReg(B.RegVT);
2030 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2032 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2034 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2035 addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2036 SwitchBB->normalizeSuccProbs();
2038 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2039 MVT::Other, CopyTo, RangeCmp,
2040 DAG.getBasicBlock(B.Default));
2042 // Avoid emitting unnecessary branches to the next block.
2043 if (MBB != NextBlock(SwitchBB))
2044 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2045 DAG.getBasicBlock(MBB));
2047 DAG.setRoot(BrRange);
2050 /// visitBitTestCase - this function produces one "bit test"
2051 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2052 MachineBasicBlock* NextMBB,
2053 BranchProbability BranchProbToNext,
2056 MachineBasicBlock *SwitchBB) {
2057 SDLoc dl = getCurSDLoc();
2059 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2061 unsigned PopCount = countPopulation(B.Mask);
2062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2063 if (PopCount == 1) {
2064 // Testing for a single bit; just compare the shift count with what it
2065 // would need to be to shift a 1 bit in that position.
2067 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2068 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2070 } else if (PopCount == BB.Range) {
2071 // There is only one zero bit in the range, test for it directly.
2073 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2074 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2077 // Make desired shift
2078 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2079 DAG.getConstant(1, dl, VT), ShiftOp);
2081 // Emit bit tests and jumps
2082 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2083 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2085 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2086 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2089 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2090 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2091 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2092 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2093 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2094 // one as they are relative probabilities (and thus work more like weights),
2095 // and hence we need to normalize them to let the sum of them become one.
2096 SwitchBB->normalizeSuccProbs();
2098 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2099 MVT::Other, getControlRoot(),
2100 Cmp, DAG.getBasicBlock(B.TargetBB));
2102 // Avoid emitting unnecessary branches to the next block.
2103 if (NextMBB != NextBlock(SwitchBB))
2104 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2105 DAG.getBasicBlock(NextMBB));
2110 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2111 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2113 // Retrieve successors. Look through artificial IR level blocks like
2114 // catchswitch for successors.
2115 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2116 const BasicBlock *EHPadBB = I.getSuccessor(1);
2118 const Value *Callee(I.getCalledValue());
2119 const Function *Fn = dyn_cast<Function>(Callee);
2120 if (isa<InlineAsm>(Callee))
2122 else if (Fn && Fn->isIntrinsic()) {
2123 switch (Fn->getIntrinsicID()) {
2125 llvm_unreachable("Cannot invoke this intrinsic");
2126 case Intrinsic::donothing:
2127 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2129 case Intrinsic::experimental_patchpoint_void:
2130 case Intrinsic::experimental_patchpoint_i64:
2131 visitPatchpoint(&I, EHPadBB);
2133 case Intrinsic::experimental_gc_statepoint:
2134 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2138 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2140 // If the value of the invoke is used outside of its defining block, make it
2141 // available as a virtual register.
2142 // We already took care of the exported value for the statepoint instruction
2143 // during call to the LowerStatepoint.
2144 if (!isStatepoint(I)) {
2145 CopyToExportRegsIfNeeded(&I);
2148 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2149 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2150 BranchProbability EHPadBBProb =
2151 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2152 : BranchProbability::getZero();
2153 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2155 // Update successor info.
2156 addSuccessorWithProb(InvokeMBB, Return);
2157 for (auto &UnwindDest : UnwindDests) {
2158 UnwindDest.first->setIsEHPad();
2159 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2161 InvokeMBB->normalizeSuccProbs();
2163 // Drop into normal successor.
2164 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2165 MVT::Other, getControlRoot(),
2166 DAG.getBasicBlock(Return)));
2169 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2170 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2173 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2174 assert(FuncInfo.MBB->isEHPad() &&
2175 "Call to landingpad not in landing pad!");
2177 MachineBasicBlock *MBB = FuncInfo.MBB;
2178 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2179 AddLandingPadInfo(LP, MMI, MBB);
2181 // If there aren't registers to copy the values into (e.g., during SjLj
2182 // exceptions), then don't bother to create these DAG nodes.
2183 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2184 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2185 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2186 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2189 // If landingpad's return type is token type, we don't create DAG nodes
2190 // for its exception pointer and selector value. The extraction of exception
2191 // pointer or selector value from token type landingpads is not currently
2193 if (LP.getType()->isTokenTy())
2196 SmallVector<EVT, 2> ValueVTs;
2197 SDLoc dl = getCurSDLoc();
2198 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2199 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2201 // Get the two live-in registers as SDValues. The physregs have already been
2202 // copied into virtual registers.
2204 if (FuncInfo.ExceptionPointerVirtReg) {
2205 Ops[0] = DAG.getZExtOrTrunc(
2206 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2207 FuncInfo.ExceptionPointerVirtReg,
2208 TLI.getPointerTy(DAG.getDataLayout())),
2211 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2213 Ops[1] = DAG.getZExtOrTrunc(
2214 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2215 FuncInfo.ExceptionSelectorVirtReg,
2216 TLI.getPointerTy(DAG.getDataLayout())),
2220 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2221 DAG.getVTList(ValueVTs), Ops);
2225 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2227 for (const CaseCluster &CC : Clusters)
2228 assert(CC.Low == CC.High && "Input clusters must be single-case");
2231 std::sort(Clusters.begin(), Clusters.end(),
2232 [](const CaseCluster &a, const CaseCluster &b) {
2233 return a.Low->getValue().slt(b.Low->getValue());
2236 // Merge adjacent clusters with the same destination.
2237 const unsigned N = Clusters.size();
2238 unsigned DstIndex = 0;
2239 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2240 CaseCluster &CC = Clusters[SrcIndex];
2241 const ConstantInt *CaseVal = CC.Low;
2242 MachineBasicBlock *Succ = CC.MBB;
2244 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2245 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2246 // If this case has the same successor and is a neighbour, merge it into
2247 // the previous cluster.
2248 Clusters[DstIndex - 1].High = CaseVal;
2249 Clusters[DstIndex - 1].Prob += CC.Prob;
2251 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2252 sizeof(Clusters[SrcIndex]));
2255 Clusters.resize(DstIndex);
2258 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2259 MachineBasicBlock *Last) {
2261 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2262 if (JTCases[i].first.HeaderBB == First)
2263 JTCases[i].first.HeaderBB = Last;
2265 // Update BitTestCases.
2266 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2267 if (BitTestCases[i].Parent == First)
2268 BitTestCases[i].Parent = Last;
2271 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2272 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2274 // Update machine-CFG edges with unique successors.
2275 SmallSet<BasicBlock*, 32> Done;
2276 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2277 BasicBlock *BB = I.getSuccessor(i);
2278 bool Inserted = Done.insert(BB).second;
2282 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2283 addSuccessorWithProb(IndirectBrMBB, Succ);
2285 IndirectBrMBB->normalizeSuccProbs();
2287 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2288 MVT::Other, getControlRoot(),
2289 getValue(I.getAddress())));
2292 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2293 if (DAG.getTarget().Options.TrapUnreachable)
2295 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2298 void SelectionDAGBuilder::visitFSub(const User &I) {
2299 // -0.0 - X --> fneg
2300 Type *Ty = I.getType();
2301 if (isa<Constant>(I.getOperand(0)) &&
2302 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2303 SDValue Op2 = getValue(I.getOperand(1));
2304 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2305 Op2.getValueType(), Op2));
2309 visitBinary(I, ISD::FSUB);
2312 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2313 SDValue Op1 = getValue(I.getOperand(0));
2314 SDValue Op2 = getValue(I.getOperand(1));
2321 if (const OverflowingBinaryOperator *OFBinOp =
2322 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2323 nuw = OFBinOp->hasNoUnsignedWrap();
2324 nsw = OFBinOp->hasNoSignedWrap();
2326 if (const PossiblyExactOperator *ExactOp =
2327 dyn_cast<const PossiblyExactOperator>(&I))
2328 exact = ExactOp->isExact();
2329 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2330 FMF = FPOp->getFastMathFlags();
2333 Flags.setExact(exact);
2334 Flags.setNoSignedWrap(nsw);
2335 Flags.setNoUnsignedWrap(nuw);
2336 if (EnableFMFInDAG) {
2337 Flags.setAllowReciprocal(FMF.allowReciprocal());
2338 Flags.setNoInfs(FMF.noInfs());
2339 Flags.setNoNaNs(FMF.noNaNs());
2340 Flags.setNoSignedZeros(FMF.noSignedZeros());
2341 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2343 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2345 setValue(&I, BinNodeValue);
2348 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2349 SDValue Op1 = getValue(I.getOperand(0));
2350 SDValue Op2 = getValue(I.getOperand(1));
2352 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2353 Op2.getValueType(), DAG.getDataLayout());
2355 // Coerce the shift amount to the right type if we can.
2356 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2357 unsigned ShiftSize = ShiftTy.getSizeInBits();
2358 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2359 SDLoc DL = getCurSDLoc();
2361 // If the operand is smaller than the shift count type, promote it.
2362 if (ShiftSize > Op2Size)
2363 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2365 // If the operand is larger than the shift count type but the shift
2366 // count type has enough bits to represent any shift value, truncate
2367 // it now. This is a common case and it exposes the truncate to
2368 // optimization early.
2369 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2370 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2371 // Otherwise we'll need to temporarily settle for some other convenient
2372 // type. Type legalization will make adjustments once the shiftee is split.
2374 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2381 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2383 if (const OverflowingBinaryOperator *OFBinOp =
2384 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2385 nuw = OFBinOp->hasNoUnsignedWrap();
2386 nsw = OFBinOp->hasNoSignedWrap();
2388 if (const PossiblyExactOperator *ExactOp =
2389 dyn_cast<const PossiblyExactOperator>(&I))
2390 exact = ExactOp->isExact();
2393 Flags.setExact(exact);
2394 Flags.setNoSignedWrap(nsw);
2395 Flags.setNoUnsignedWrap(nuw);
2396 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2401 void SelectionDAGBuilder::visitSDiv(const User &I) {
2402 SDValue Op1 = getValue(I.getOperand(0));
2403 SDValue Op2 = getValue(I.getOperand(1));
2406 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2407 cast<PossiblyExactOperator>(&I)->isExact());
2408 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2412 void SelectionDAGBuilder::visitICmp(const User &I) {
2413 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2414 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2415 predicate = IC->getPredicate();
2416 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2417 predicate = ICmpInst::Predicate(IC->getPredicate());
2418 SDValue Op1 = getValue(I.getOperand(0));
2419 SDValue Op2 = getValue(I.getOperand(1));
2420 ISD::CondCode Opcode = getICmpCondCode(predicate);
2422 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2424 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2427 void SelectionDAGBuilder::visitFCmp(const User &I) {
2428 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2429 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2430 predicate = FC->getPredicate();
2431 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2432 predicate = FCmpInst::Predicate(FC->getPredicate());
2433 SDValue Op1 = getValue(I.getOperand(0));
2434 SDValue Op2 = getValue(I.getOperand(1));
2435 ISD::CondCode Condition = getFCmpCondCode(predicate);
2437 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2438 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2439 // further optimization, but currently FMF is only applicable to binary nodes.
2440 if (TM.Options.NoNaNsFPMath)
2441 Condition = getFCmpCodeWithoutNaN(Condition);
2442 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2444 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2447 void SelectionDAGBuilder::visitSelect(const User &I) {
2448 SmallVector<EVT, 4> ValueVTs;
2449 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2451 unsigned NumValues = ValueVTs.size();
2452 if (NumValues == 0) return;
2454 SmallVector<SDValue, 4> Values(NumValues);
2455 SDValue Cond = getValue(I.getOperand(0));
2456 SDValue LHSVal = getValue(I.getOperand(1));
2457 SDValue RHSVal = getValue(I.getOperand(2));
2458 auto BaseOps = {Cond};
2459 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2460 ISD::VSELECT : ISD::SELECT;
2462 // Min/max matching is only viable if all output VTs are the same.
2463 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2464 EVT VT = ValueVTs[0];
2465 LLVMContext &Ctx = *DAG.getContext();
2466 auto &TLI = DAG.getTargetLoweringInfo();
2468 // We care about the legality of the operation after it has been type
2470 while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
2471 VT != TLI.getTypeToTransformTo(Ctx, VT))
2472 VT = TLI.getTypeToTransformTo(Ctx, VT);
2474 // If the vselect is legal, assume we want to leave this as a vector setcc +
2475 // vselect. Otherwise, if this is going to be scalarized, we want to see if
2476 // min/max is legal on the scalar type.
2477 bool UseScalarMinMax = VT.isVector() &&
2478 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
2481 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2482 ISD::NodeType Opc = ISD::DELETED_NODE;
2483 switch (SPR.Flavor) {
2484 case SPF_UMAX: Opc = ISD::UMAX; break;
2485 case SPF_UMIN: Opc = ISD::UMIN; break;
2486 case SPF_SMAX: Opc = ISD::SMAX; break;
2487 case SPF_SMIN: Opc = ISD::SMIN; break;
2489 switch (SPR.NaNBehavior) {
2490 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2491 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2492 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2493 case SPNB_RETURNS_ANY: {
2494 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
2496 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT))
2498 else if (UseScalarMinMax)
2499 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
2500 ISD::FMINNUM : ISD::FMINNAN;
2506 switch (SPR.NaNBehavior) {
2507 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2508 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2509 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2510 case SPNB_RETURNS_ANY:
2512 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
2514 else if (TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT))
2516 else if (UseScalarMinMax)
2517 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
2518 ISD::FMAXNUM : ISD::FMAXNAN;
2525 if (Opc != ISD::DELETED_NODE &&
2526 (TLI.isOperationLegalOrCustom(Opc, VT) ||
2528 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
2529 // If the underlying comparison instruction is used by any other
2530 // instruction, the consumed instructions won't be destroyed, so it is
2531 // not profitable to convert to a min/max.
2532 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2534 LHSVal = getValue(LHS);
2535 RHSVal = getValue(RHS);
2540 for (unsigned i = 0; i != NumValues; ++i) {
2541 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2542 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2543 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2544 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2545 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2549 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2550 DAG.getVTList(ValueVTs), Values));
2553 void SelectionDAGBuilder::visitTrunc(const User &I) {
2554 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2555 SDValue N = getValue(I.getOperand(0));
2556 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2558 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2561 void SelectionDAGBuilder::visitZExt(const User &I) {
2562 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2563 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2564 SDValue N = getValue(I.getOperand(0));
2565 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2567 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2570 void SelectionDAGBuilder::visitSExt(const User &I) {
2571 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2572 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2573 SDValue N = getValue(I.getOperand(0));
2574 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2576 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2579 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2580 // FPTrunc is never a no-op cast, no need to check
2581 SDValue N = getValue(I.getOperand(0));
2582 SDLoc dl = getCurSDLoc();
2583 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2584 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2585 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2586 DAG.getTargetConstant(
2587 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2590 void SelectionDAGBuilder::visitFPExt(const User &I) {
2591 // FPExt is never a no-op cast, no need to check
2592 SDValue N = getValue(I.getOperand(0));
2593 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2595 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2598 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2599 // FPToUI is never a no-op cast, no need to check
2600 SDValue N = getValue(I.getOperand(0));
2601 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2603 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2606 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2607 // FPToSI is never a no-op cast, no need to check
2608 SDValue N = getValue(I.getOperand(0));
2609 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2611 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2614 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2615 // UIToFP is never a no-op cast, no need to check
2616 SDValue N = getValue(I.getOperand(0));
2617 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2619 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2622 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2623 // SIToFP is never a no-op cast, no need to check
2624 SDValue N = getValue(I.getOperand(0));
2625 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2627 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2630 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2631 // What to do depends on the size of the integer and the size of the pointer.
2632 // We can either truncate, zero extend, or no-op, accordingly.
2633 SDValue N = getValue(I.getOperand(0));
2634 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2636 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2639 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2640 // What to do depends on the size of the integer and the size of the pointer.
2641 // We can either truncate, zero extend, or no-op, accordingly.
2642 SDValue N = getValue(I.getOperand(0));
2643 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2645 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2648 void SelectionDAGBuilder::visitBitCast(const User &I) {
2649 SDValue N = getValue(I.getOperand(0));
2650 SDLoc dl = getCurSDLoc();
2651 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2654 // BitCast assures us that source and destination are the same size so this is
2655 // either a BITCAST or a no-op.
2656 if (DestVT != N.getValueType())
2657 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2658 DestVT, N)); // convert types.
2659 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2660 // might fold any kind of constant expression to an integer constant and that
2661 // is not what we are looking for. Only regcognize a bitcast of a genuine
2662 // constant integer as an opaque constant.
2663 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2664 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2667 setValue(&I, N); // noop cast.
2670 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2671 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2672 const Value *SV = I.getOperand(0);
2673 SDValue N = getValue(SV);
2674 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2676 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2677 unsigned DestAS = I.getType()->getPointerAddressSpace();
2679 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2680 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2685 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2687 SDValue InVec = getValue(I.getOperand(0));
2688 SDValue InVal = getValue(I.getOperand(1));
2689 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2690 TLI.getVectorIdxTy(DAG.getDataLayout()));
2691 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2692 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2693 InVec, InVal, InIdx));
2696 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2697 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2698 SDValue InVec = getValue(I.getOperand(0));
2699 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2700 TLI.getVectorIdxTy(DAG.getDataLayout()));
2701 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2702 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2706 // Utility for visitShuffleVector - Return true if every element in Mask,
2707 // beginning from position Pos and ending in Pos+Size, falls within the
2708 // specified sequential range [L, L+Pos). or is undef.
2709 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2710 unsigned Pos, unsigned Size, int Low) {
2711 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2712 if (Mask[i] >= 0 && Mask[i] != Low)
2717 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2718 SDValue Src1 = getValue(I.getOperand(0));
2719 SDValue Src2 = getValue(I.getOperand(1));
2721 SmallVector<int, 8> Mask;
2722 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2723 unsigned MaskNumElts = Mask.size();
2725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2726 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2727 EVT SrcVT = Src1.getValueType();
2728 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2730 if (SrcNumElts == MaskNumElts) {
2731 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2736 // Normalize the shuffle vector since mask and vector length don't match.
2737 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2738 // Mask is longer than the source vectors and is a multiple of the source
2739 // vectors. We can use concatenate vector to make the mask and vectors
2741 if (SrcNumElts*2 == MaskNumElts) {
2742 // First check for Src1 in low and Src2 in high
2743 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2744 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2745 // The shuffle is concatenating two vectors together.
2746 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2750 // Then check for Src2 in low and Src1 in high
2751 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2752 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2753 // The shuffle is concatenating two vectors together.
2754 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2760 // Pad both vectors with undefs to make them the same length as the mask.
2761 unsigned NumConcat = MaskNumElts / SrcNumElts;
2762 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2763 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2764 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2766 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2767 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2771 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2772 getCurSDLoc(), VT, MOps1);
2773 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2774 getCurSDLoc(), VT, MOps2);
2776 // Readjust mask for new input vector length.
2777 SmallVector<int, 8> MappedOps;
2778 for (unsigned i = 0; i != MaskNumElts; ++i) {
2780 if (Idx >= (int)SrcNumElts)
2781 Idx -= SrcNumElts - MaskNumElts;
2782 MappedOps.push_back(Idx);
2785 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2790 if (SrcNumElts > MaskNumElts) {
2791 // Analyze the access pattern of the vector to see if we can extract
2792 // two subvectors and do the shuffle. The analysis is done by calculating
2793 // the range of elements the mask access on both vectors.
2794 int MinRange[2] = { static_cast<int>(SrcNumElts),
2795 static_cast<int>(SrcNumElts)};
2796 int MaxRange[2] = {-1, -1};
2798 for (unsigned i = 0; i != MaskNumElts; ++i) {
2804 if (Idx >= (int)SrcNumElts) {
2808 if (Idx > MaxRange[Input])
2809 MaxRange[Input] = Idx;
2810 if (Idx < MinRange[Input])
2811 MinRange[Input] = Idx;
2814 // Check if the access is smaller than the vector size and can we find
2815 // a reasonable extract index.
2816 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2818 int StartIdx[2]; // StartIdx to extract from
2819 for (unsigned Input = 0; Input < 2; ++Input) {
2820 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2821 RangeUse[Input] = 0; // Unused
2822 StartIdx[Input] = 0;
2826 // Find a good start index that is a multiple of the mask length. Then
2827 // see if the rest of the elements are in range.
2828 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2829 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2830 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2831 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2834 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2835 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2838 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2839 // Extract appropriate subvector and generate a vector shuffle
2840 for (unsigned Input = 0; Input < 2; ++Input) {
2841 SDValue &Src = Input == 0 ? Src1 : Src2;
2842 if (RangeUse[Input] == 0)
2843 Src = DAG.getUNDEF(VT);
2845 SDLoc dl = getCurSDLoc();
2847 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2848 DAG.getConstant(StartIdx[Input], dl,
2849 TLI.getVectorIdxTy(DAG.getDataLayout())));
2853 // Calculate new mask.
2854 SmallVector<int, 8> MappedOps;
2855 for (unsigned i = 0; i != MaskNumElts; ++i) {
2858 if (Idx < (int)SrcNumElts)
2861 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2863 MappedOps.push_back(Idx);
2866 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2872 // We can't use either concat vectors or extract subvectors so fall back to
2873 // replacing the shuffle with extract and build vector.
2874 // to insert and build vector.
2875 EVT EltVT = VT.getVectorElementType();
2876 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2877 SDLoc dl = getCurSDLoc();
2878 SmallVector<SDValue,8> Ops;
2879 for (unsigned i = 0; i != MaskNumElts; ++i) {
2884 Res = DAG.getUNDEF(EltVT);
2886 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2887 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2889 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2890 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2896 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2899 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2900 const Value *Op0 = I.getOperand(0);
2901 const Value *Op1 = I.getOperand(1);
2902 Type *AggTy = I.getType();
2903 Type *ValTy = Op1->getType();
2904 bool IntoUndef = isa<UndefValue>(Op0);
2905 bool FromUndef = isa<UndefValue>(Op1);
2907 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2909 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2910 SmallVector<EVT, 4> AggValueVTs;
2911 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2912 SmallVector<EVT, 4> ValValueVTs;
2913 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2915 unsigned NumAggValues = AggValueVTs.size();
2916 unsigned NumValValues = ValValueVTs.size();
2917 SmallVector<SDValue, 4> Values(NumAggValues);
2919 // Ignore an insertvalue that produces an empty object
2920 if (!NumAggValues) {
2921 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2925 SDValue Agg = getValue(Op0);
2927 // Copy the beginning value(s) from the original aggregate.
2928 for (; i != LinearIndex; ++i)
2929 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2930 SDValue(Agg.getNode(), Agg.getResNo() + i);
2931 // Copy values from the inserted value(s).
2933 SDValue Val = getValue(Op1);
2934 for (; i != LinearIndex + NumValValues; ++i)
2935 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2936 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2938 // Copy remaining value(s) from the original aggregate.
2939 for (; i != NumAggValues; ++i)
2940 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2941 SDValue(Agg.getNode(), Agg.getResNo() + i);
2943 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2944 DAG.getVTList(AggValueVTs), Values));
2947 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2948 const Value *Op0 = I.getOperand(0);
2949 Type *AggTy = Op0->getType();
2950 Type *ValTy = I.getType();
2951 bool OutOfUndef = isa<UndefValue>(Op0);
2953 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2956 SmallVector<EVT, 4> ValValueVTs;
2957 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2959 unsigned NumValValues = ValValueVTs.size();
2961 // Ignore a extractvalue that produces an empty object
2962 if (!NumValValues) {
2963 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2967 SmallVector<SDValue, 4> Values(NumValValues);
2969 SDValue Agg = getValue(Op0);
2970 // Copy out the selected value(s).
2971 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2972 Values[i - LinearIndex] =
2974 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2975 SDValue(Agg.getNode(), Agg.getResNo() + i);
2977 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2978 DAG.getVTList(ValValueVTs), Values));
2981 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2982 Value *Op0 = I.getOperand(0);
2983 // Note that the pointer operand may be a vector of pointers. Take the scalar
2984 // element which holds a pointer.
2985 Type *Ty = Op0->getType()->getScalarType();
2986 unsigned AS = Ty->getPointerAddressSpace();
2987 SDValue N = getValue(Op0);
2988 SDLoc dl = getCurSDLoc();
2990 // Normalize Vector GEP - all scalar operands should be converted to the
2992 unsigned VectorWidth = I.getType()->isVectorTy() ?
2993 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2995 if (VectorWidth && !N.getValueType().isVector()) {
2996 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2997 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2998 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3000 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3002 const Value *Idx = *OI;
3003 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3004 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3007 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3009 // In an inbouds GEP with an offset that is nonnegative even when
3010 // interpreted as signed, assume there is no unsigned overflow.
3012 if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3013 Flags.setNoUnsignedWrap(true);
3015 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3016 DAG.getConstant(Offset, dl, N.getValueType()), &Flags);
3019 Ty = StTy->getElementType(Field);
3021 Ty = cast<SequentialType>(Ty)->getElementType();
3023 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
3024 unsigned PtrSize = PtrTy.getSizeInBits();
3025 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
3027 // If this is a scalar constant or a splat vector of constants,
3028 // handle it quickly.
3029 const auto *CI = dyn_cast<ConstantInt>(Idx);
3030 if (!CI && isa<ConstantDataVector>(Idx) &&
3031 cast<ConstantDataVector>(Idx)->getSplatValue())
3032 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3037 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3038 SDValue OffsVal = VectorWidth ?
3039 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
3040 DAG.getConstant(Offs, dl, PtrTy);
3042 // In an inbouds GEP with an offset that is nonnegative even when
3043 // interpreted as signed, assume there is no unsigned overflow.
3045 if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3046 Flags.setNoUnsignedWrap(true);
3048 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, &Flags);
3052 // N = N + Idx * ElementSize;
3053 SDValue IdxN = getValue(Idx);
3055 if (!IdxN.getValueType().isVector() && VectorWidth) {
3056 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3057 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
3058 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3060 // If the index is smaller or larger than intptr_t, truncate or extend
3062 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3064 // If this is a multiply by a power of two, turn it into a shl
3065 // immediately. This is a very common case.
3066 if (ElementSize != 1) {
3067 if (ElementSize.isPowerOf2()) {
3068 unsigned Amt = ElementSize.logBase2();
3069 IdxN = DAG.getNode(ISD::SHL, dl,
3070 N.getValueType(), IdxN,
3071 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3073 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3074 IdxN = DAG.getNode(ISD::MUL, dl,
3075 N.getValueType(), IdxN, Scale);
3079 N = DAG.getNode(ISD::ADD, dl,
3080 N.getValueType(), N, IdxN);
3087 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3088 // If this is a fixed sized alloca in the entry block of the function,
3089 // allocate it statically on the stack.
3090 if (FuncInfo.StaticAllocaMap.count(&I))
3091 return; // getValue will auto-populate this.
3093 SDLoc dl = getCurSDLoc();
3094 Type *Ty = I.getAllocatedType();
3095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3096 auto &DL = DAG.getDataLayout();
3097 uint64_t TySize = DL.getTypeAllocSize(Ty);
3099 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3101 SDValue AllocSize = getValue(I.getArraySize());
3103 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3104 if (AllocSize.getValueType() != IntPtr)
3105 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3107 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3109 DAG.getConstant(TySize, dl, IntPtr));
3111 // Handle alignment. If the requested alignment is less than or equal to
3112 // the stack alignment, ignore it. If the size is greater than or equal to
3113 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3114 unsigned StackAlign =
3115 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3116 if (Align <= StackAlign)
3119 // Round the size of the allocation up to the stack alignment size
3120 // by add SA-1 to the size. This doesn't overflow because we're computing
3121 // an address inside an alloca.
3123 Flags.setNoUnsignedWrap(true);
3124 AllocSize = DAG.getNode(ISD::ADD, dl,
3125 AllocSize.getValueType(), AllocSize,
3126 DAG.getIntPtrConstant(StackAlign - 1, dl), &Flags);
3128 // Mask out the low bits for alignment purposes.
3129 AllocSize = DAG.getNode(ISD::AND, dl,
3130 AllocSize.getValueType(), AllocSize,
3131 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3134 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3135 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3136 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3138 DAG.setRoot(DSA.getValue(1));
3140 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3143 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3145 return visitAtomicLoad(I);
3147 const Value *SV = I.getOperand(0);
3148 SDValue Ptr = getValue(SV);
3150 Type *Ty = I.getType();
3152 bool isVolatile = I.isVolatile();
3153 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3155 // The IR notion of invariant_load only guarantees that all *non-faulting*
3156 // invariant loads result in the same value. The MI notion of invariant load
3157 // guarantees that the load can be legally moved to any location within its
3158 // containing function. The MI notion of invariant_load is stronger than the
3159 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3160 // with a guarantee that the location being loaded from is dereferenceable
3161 // throughout the function's lifetime.
3163 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3164 isDereferenceablePointer(SV, DAG.getDataLayout());
3165 unsigned Alignment = I.getAlignment();
3168 I.getAAMetadata(AAInfo);
3169 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3172 SmallVector<EVT, 4> ValueVTs;
3173 SmallVector<uint64_t, 4> Offsets;
3174 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3175 unsigned NumValues = ValueVTs.size();
3180 bool ConstantMemory = false;
3181 if (isVolatile || NumValues > MaxParallelChains)
3182 // Serialize volatile loads with other side effects.
3184 else if (AA->pointsToConstantMemory(MemoryLocation(
3185 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3186 // Do not serialize (non-volatile) loads of constant memory with anything.
3187 Root = DAG.getEntryNode();
3188 ConstantMemory = true;
3190 // Do not serialize non-volatile loads against each other.
3191 Root = DAG.getRoot();
3194 SDLoc dl = getCurSDLoc();
3197 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3199 // An aggregate load cannot wrap around the address space, so offsets to its
3200 // parts don't wrap either.
3202 Flags.setNoUnsignedWrap(true);
3204 SmallVector<SDValue, 4> Values(NumValues);
3205 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3206 EVT PtrVT = Ptr.getValueType();
3207 unsigned ChainI = 0;
3208 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3209 // Serializing loads here may result in excessive register pressure, and
3210 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3211 // could recover a bit by hoisting nodes upward in the chain by recognizing
3212 // they are side-effect free or do not alias. The optimizer should really
3213 // avoid this case by converting large object/array copies to llvm.memcpy
3214 // (MaxParallelChains should always remain as failsafe).
3215 if (ChainI == MaxParallelChains) {
3216 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3217 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3218 makeArrayRef(Chains.data(), ChainI));
3222 SDValue A = DAG.getNode(ISD::ADD, dl,
3224 DAG.getConstant(Offsets[i], dl, PtrVT),
3226 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3227 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3228 isNonTemporal, isInvariant, Alignment, AAInfo,
3232 Chains[ChainI] = L.getValue(1);
3235 if (!ConstantMemory) {
3236 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3237 makeArrayRef(Chains.data(), ChainI));
3241 PendingLoads.push_back(Chain);
3244 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3245 DAG.getVTList(ValueVTs), Values));
3248 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3250 return visitAtomicStore(I);
3252 const Value *SrcV = I.getOperand(0);
3253 const Value *PtrV = I.getOperand(1);
3255 SmallVector<EVT, 4> ValueVTs;
3256 SmallVector<uint64_t, 4> Offsets;
3257 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3258 SrcV->getType(), ValueVTs, &Offsets);
3259 unsigned NumValues = ValueVTs.size();
3263 // Get the lowered operands. Note that we do this after
3264 // checking if NumResults is zero, because with zero results
3265 // the operands won't have values in the map.
3266 SDValue Src = getValue(SrcV);
3267 SDValue Ptr = getValue(PtrV);
3269 SDValue Root = getRoot();
3270 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3271 EVT PtrVT = Ptr.getValueType();
3272 bool isVolatile = I.isVolatile();
3273 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3274 unsigned Alignment = I.getAlignment();
3275 SDLoc dl = getCurSDLoc();
3278 I.getAAMetadata(AAInfo);
3280 // An aggregate load cannot wrap around the address space, so offsets to its
3281 // parts don't wrap either.
3283 Flags.setNoUnsignedWrap(true);
3285 unsigned ChainI = 0;
3286 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3287 // See visitLoad comments.
3288 if (ChainI == MaxParallelChains) {
3289 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3290 makeArrayRef(Chains.data(), ChainI));
3294 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3295 DAG.getConstant(Offsets[i], dl, PtrVT), &Flags);
3296 SDValue St = DAG.getStore(Root, dl,
3297 SDValue(Src.getNode(), Src.getResNo() + i),
3298 Add, MachinePointerInfo(PtrV, Offsets[i]),
3299 isVolatile, isNonTemporal, Alignment, AAInfo);
3300 Chains[ChainI] = St;
3303 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3304 makeArrayRef(Chains.data(), ChainI));
3305 DAG.setRoot(StoreNode);
3308 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3309 SDLoc sdl = getCurSDLoc();
3311 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3312 Value *PtrOperand = I.getArgOperand(1);
3313 SDValue Ptr = getValue(PtrOperand);
3314 SDValue Src0 = getValue(I.getArgOperand(0));
3315 SDValue Mask = getValue(I.getArgOperand(3));
3316 EVT VT = Src0.getValueType();
3317 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3319 Alignment = DAG.getEVTAlignment(VT);
3322 I.getAAMetadata(AAInfo);
3324 MachineMemOperand *MMO =
3325 DAG.getMachineFunction().
3326 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3327 MachineMemOperand::MOStore, VT.getStoreSize(),
3329 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3331 DAG.setRoot(StoreNode);
3332 setValue(&I, StoreNode);
3335 // Get a uniform base for the Gather/Scatter intrinsic.
3336 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3337 // We try to represent it as a base pointer + vector of indices.
3338 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3339 // The first operand of the GEP may be a single pointer or a vector of pointers
3341 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3343 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3344 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3346 // When the first GEP operand is a single pointer - it is the uniform base we
3347 // are looking for. If first operand of the GEP is a splat vector - we
3348 // extract the spalt value and use it as a uniform base.
3349 // In all other cases the function returns 'false'.
3351 static bool getUniformBase(const Value *& Ptr, SDValue& Base, SDValue& Index,
3352 SelectionDAGBuilder* SDB) {
3354 SelectionDAG& DAG = SDB->DAG;
3355 LLVMContext &Context = *DAG.getContext();
3357 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3358 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3359 if (!GEP || GEP->getNumOperands() > 2)
3362 const Value *GEPPtr = GEP->getPointerOperand();
3363 if (!GEPPtr->getType()->isVectorTy())
3365 else if (!(Ptr = getSplatValue(GEPPtr)))
3368 Value *IndexVal = GEP->getOperand(1);
3370 // The operands of the GEP may be defined in another basic block.
3371 // In this case we'll not find nodes for the operands.
3372 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3375 Base = SDB->getValue(Ptr);
3376 Index = SDB->getValue(IndexVal);
3378 // Suppress sign extension.
3379 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3380 if (SDB->findValue(Sext->getOperand(0))) {
3381 IndexVal = Sext->getOperand(0);
3382 Index = SDB->getValue(IndexVal);
3385 if (!Index.getValueType().isVector()) {
3386 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3387 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3388 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3389 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3394 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3395 SDLoc sdl = getCurSDLoc();
3397 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3398 const Value *Ptr = I.getArgOperand(1);
3399 SDValue Src0 = getValue(I.getArgOperand(0));
3400 SDValue Mask = getValue(I.getArgOperand(3));
3401 EVT VT = Src0.getValueType();
3402 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3404 Alignment = DAG.getEVTAlignment(VT);
3405 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3408 I.getAAMetadata(AAInfo);
3412 const Value *BasePtr = Ptr;
3413 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3415 const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3416 MachineMemOperand *MMO = DAG.getMachineFunction().
3417 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3418 MachineMemOperand::MOStore, VT.getStoreSize(),
3421 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3422 Index = getValue(Ptr);
3424 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3425 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3427 DAG.setRoot(Scatter);
3428 setValue(&I, Scatter);
3431 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3432 SDLoc sdl = getCurSDLoc();
3434 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3435 Value *PtrOperand = I.getArgOperand(0);
3436 SDValue Ptr = getValue(PtrOperand);
3437 SDValue Src0 = getValue(I.getArgOperand(3));
3438 SDValue Mask = getValue(I.getArgOperand(2));
3440 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3441 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3442 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3444 Alignment = DAG.getEVTAlignment(VT);
3447 I.getAAMetadata(AAInfo);
3448 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3450 SDValue InChain = DAG.getRoot();
3451 if (AA->pointsToConstantMemory(MemoryLocation(
3452 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3454 // Do not serialize (non-volatile) loads of constant memory with anything.
3455 InChain = DAG.getEntryNode();
3458 MachineMemOperand *MMO =
3459 DAG.getMachineFunction().
3460 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3461 MachineMemOperand::MOLoad, VT.getStoreSize(),
3462 Alignment, AAInfo, Ranges);
3464 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3466 SDValue OutChain = Load.getValue(1);
3467 DAG.setRoot(OutChain);
3471 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3472 SDLoc sdl = getCurSDLoc();
3474 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3475 const Value *Ptr = I.getArgOperand(0);
3476 SDValue Src0 = getValue(I.getArgOperand(3));
3477 SDValue Mask = getValue(I.getArgOperand(2));
3479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3480 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3481 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3483 Alignment = DAG.getEVTAlignment(VT);
3486 I.getAAMetadata(AAInfo);
3487 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3489 SDValue Root = DAG.getRoot();
3492 const Value *BasePtr = Ptr;
3493 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3494 bool ConstantMemory = false;
3496 AA->pointsToConstantMemory(MemoryLocation(
3497 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3499 // Do not serialize (non-volatile) loads of constant memory with anything.
3500 Root = DAG.getEntryNode();
3501 ConstantMemory = true;
3504 MachineMemOperand *MMO =
3505 DAG.getMachineFunction().
3506 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3507 MachineMemOperand::MOLoad, VT.getStoreSize(),
3508 Alignment, AAInfo, Ranges);
3511 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3512 Index = getValue(Ptr);
3514 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3515 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3518 SDValue OutChain = Gather.getValue(1);
3519 if (!ConstantMemory)
3520 PendingLoads.push_back(OutChain);
3521 setValue(&I, Gather);
3524 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3525 SDLoc dl = getCurSDLoc();
3526 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3527 AtomicOrdering FailureOrder = I.getFailureOrdering();
3528 SynchronizationScope Scope = I.getSynchScope();
3530 SDValue InChain = getRoot();
3532 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3533 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3534 SDValue L = DAG.getAtomicCmpSwap(
3535 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3536 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3537 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3538 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3540 SDValue OutChain = L.getValue(2);
3543 DAG.setRoot(OutChain);
3546 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3547 SDLoc dl = getCurSDLoc();
3549 switch (I.getOperation()) {
3550 default: llvm_unreachable("Unknown atomicrmw operation");
3551 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3552 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3553 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3554 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3555 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3556 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3557 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3558 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3559 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3560 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3561 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3563 AtomicOrdering Order = I.getOrdering();
3564 SynchronizationScope Scope = I.getSynchScope();
3566 SDValue InChain = getRoot();
3569 DAG.getAtomic(NT, dl,
3570 getValue(I.getValOperand()).getSimpleValueType(),
3572 getValue(I.getPointerOperand()),
3573 getValue(I.getValOperand()),
3574 I.getPointerOperand(),
3575 /* Alignment=*/ 0, Order, Scope);
3577 SDValue OutChain = L.getValue(1);
3580 DAG.setRoot(OutChain);
3583 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3584 SDLoc dl = getCurSDLoc();
3585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3588 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3589 TLI.getPointerTy(DAG.getDataLayout()));
3590 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3591 TLI.getPointerTy(DAG.getDataLayout()));
3592 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3595 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3596 SDLoc dl = getCurSDLoc();
3597 AtomicOrdering Order = I.getOrdering();
3598 SynchronizationScope Scope = I.getSynchScope();
3600 SDValue InChain = getRoot();
3602 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3603 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3605 if (I.getAlignment() < VT.getSizeInBits() / 8)
3606 report_fatal_error("Cannot generate unaligned atomic load");
3608 MachineMemOperand *MMO =
3609 DAG.getMachineFunction().
3610 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3611 MachineMemOperand::MOVolatile |
3612 MachineMemOperand::MOLoad,
3614 I.getAlignment() ? I.getAlignment() :
3615 DAG.getEVTAlignment(VT));
3617 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3619 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3620 getValue(I.getPointerOperand()), MMO,
3623 SDValue OutChain = L.getValue(1);
3626 DAG.setRoot(OutChain);
3629 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3630 SDLoc dl = getCurSDLoc();
3632 AtomicOrdering Order = I.getOrdering();
3633 SynchronizationScope Scope = I.getSynchScope();
3635 SDValue InChain = getRoot();
3637 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3639 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3641 if (I.getAlignment() < VT.getSizeInBits() / 8)
3642 report_fatal_error("Cannot generate unaligned atomic store");
3645 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3647 getValue(I.getPointerOperand()),
3648 getValue(I.getValueOperand()),
3649 I.getPointerOperand(), I.getAlignment(),
3652 DAG.setRoot(OutChain);
3655 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3657 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3658 unsigned Intrinsic) {
3659 bool HasChain = !I.doesNotAccessMemory();
3660 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3662 // Build the operand list.
3663 SmallVector<SDValue, 8> Ops;
3664 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3666 // We don't need to serialize loads against other loads.
3667 Ops.push_back(DAG.getRoot());
3669 Ops.push_back(getRoot());
3673 // Info is set by getTgtMemInstrinsic
3674 TargetLowering::IntrinsicInfo Info;
3675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3676 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3678 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3679 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3680 Info.opc == ISD::INTRINSIC_W_CHAIN)
3681 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3682 TLI.getPointerTy(DAG.getDataLayout())));
3684 // Add all operands of the call to the operand list.
3685 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3686 SDValue Op = getValue(I.getArgOperand(i));
3690 SmallVector<EVT, 4> ValueVTs;
3691 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3694 ValueVTs.push_back(MVT::Other);
3696 SDVTList VTs = DAG.getVTList(ValueVTs);
3700 if (IsTgtIntrinsic) {
3701 // This is target intrinsic that touches memory
3702 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3703 VTs, Ops, Info.memVT,
3704 MachinePointerInfo(Info.ptrVal, Info.offset),
3705 Info.align, Info.vol,
3706 Info.readMem, Info.writeMem, Info.size);
3707 } else if (!HasChain) {
3708 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3709 } else if (!I.getType()->isVoidTy()) {
3710 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3712 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3716 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3718 PendingLoads.push_back(Chain);
3723 if (!I.getType()->isVoidTy()) {
3724 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3725 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3726 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3729 setValue(&I, Result);
3733 /// GetSignificand - Get the significand and build it into a floating-point
3734 /// number with exponent of 1:
3736 /// Op = (Op & 0x007fffff) | 0x3f800000;
3738 /// where Op is the hexadecimal representation of floating point value.
3740 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3741 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3742 DAG.getConstant(0x007fffff, dl, MVT::i32));
3743 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3744 DAG.getConstant(0x3f800000, dl, MVT::i32));
3745 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3748 /// GetExponent - Get the exponent:
3750 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3752 /// where Op is the hexadecimal representation of floating point value.
3754 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3756 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3757 DAG.getConstant(0x7f800000, dl, MVT::i32));
3758 SDValue t1 = DAG.getNode(
3759 ISD::SRL, dl, MVT::i32, t0,
3760 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3761 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3762 DAG.getConstant(127, dl, MVT::i32));
3763 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3766 /// getF32Constant - Get 32-bit floating point constant.
3768 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3769 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3773 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3774 SelectionDAG &DAG) {
3775 // TODO: What fast-math-flags should be set on the floating-point nodes?
3777 // IntegerPartOfX = ((int32_t)(t0);
3778 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3780 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3781 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3782 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3784 // IntegerPartOfX <<= 23;
3785 IntegerPartOfX = DAG.getNode(
3786 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3787 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3788 DAG.getDataLayout())));
3790 SDValue TwoToFractionalPartOfX;
3791 if (LimitFloatPrecision <= 6) {
3792 // For floating-point precision of 6:
3794 // TwoToFractionalPartOfX =
3796 // (0.735607626f + 0.252464424f * x) * x;
3798 // error 0.0144103317, which is 6 bits
3799 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3800 getF32Constant(DAG, 0x3e814304, dl));
3801 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3802 getF32Constant(DAG, 0x3f3c50c8, dl));
3803 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3804 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3805 getF32Constant(DAG, 0x3f7f5e7e, dl));
3806 } else if (LimitFloatPrecision <= 12) {
3807 // For floating-point precision of 12:
3809 // TwoToFractionalPartOfX =
3812 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3814 // error 0.000107046256, which is 13 to 14 bits
3815 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3816 getF32Constant(DAG, 0x3da235e3, dl));
3817 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3818 getF32Constant(DAG, 0x3e65b8f3, dl));
3819 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3820 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3821 getF32Constant(DAG, 0x3f324b07, dl));
3822 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3823 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3824 getF32Constant(DAG, 0x3f7ff8fd, dl));
3825 } else { // LimitFloatPrecision <= 18
3826 // For floating-point precision of 18:
3828 // TwoToFractionalPartOfX =
3832 // (0.554906021e-1f +
3833 // (0.961591928e-2f +
3834 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3835 // error 2.47208000*10^(-7), which is better than 18 bits
3836 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3837 getF32Constant(DAG, 0x3924b03e, dl));
3838 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3839 getF32Constant(DAG, 0x3ab24b87, dl));
3840 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3841 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3842 getF32Constant(DAG, 0x3c1d8c17, dl));
3843 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3844 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3845 getF32Constant(DAG, 0x3d634a1d, dl));
3846 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3847 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3848 getF32Constant(DAG, 0x3e75fe14, dl));
3849 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3850 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3851 getF32Constant(DAG, 0x3f317234, dl));
3852 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3853 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3854 getF32Constant(DAG, 0x3f800000, dl));
3857 // Add the exponent into the result in integer domain.
3858 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3859 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3860 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3863 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3864 /// limited-precision mode.
3865 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3866 const TargetLowering &TLI) {
3867 if (Op.getValueType() == MVT::f32 &&
3868 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3870 // Put the exponent in the right bit position for later addition to the
3873 // #define LOG2OFe 1.4426950f
3874 // t0 = Op * LOG2OFe
3876 // TODO: What fast-math-flags should be set here?
3877 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3878 getF32Constant(DAG, 0x3fb8aa3b, dl));
3879 return getLimitedPrecisionExp2(t0, dl, DAG);
3882 // No special expansion.
3883 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3886 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3887 /// limited-precision mode.
3888 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3889 const TargetLowering &TLI) {
3891 // TODO: What fast-math-flags should be set on the floating-point nodes?
3893 if (Op.getValueType() == MVT::f32 &&
3894 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3895 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3897 // Scale the exponent by log(2) [0.69314718f].
3898 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3899 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3900 getF32Constant(DAG, 0x3f317218, dl));
3902 // Get the significand and build it into a floating-point number with
3904 SDValue X = GetSignificand(DAG, Op1, dl);
3906 SDValue LogOfMantissa;
3907 if (LimitFloatPrecision <= 6) {
3908 // For floating-point precision of 6:
3912 // (1.4034025f - 0.23903021f * x) * x;
3914 // error 0.0034276066, which is better than 8 bits
3915 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3916 getF32Constant(DAG, 0xbe74c456, dl));
3917 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3918 getF32Constant(DAG, 0x3fb3a2b1, dl));
3919 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3920 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3921 getF32Constant(DAG, 0x3f949a29, dl));
3922 } else if (LimitFloatPrecision <= 12) {
3923 // For floating-point precision of 12:
3929 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3931 // error 0.000061011436, which is 14 bits
3932 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3933 getF32Constant(DAG, 0xbd67b6d6, dl));
3934 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3935 getF32Constant(DAG, 0x3ee4f4b8, dl));
3936 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3937 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3938 getF32Constant(DAG, 0x3fbc278b, dl));
3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3940 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3941 getF32Constant(DAG, 0x40348e95, dl));
3942 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3943 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3944 getF32Constant(DAG, 0x3fdef31a, dl));
3945 } else { // LimitFloatPrecision <= 18
3946 // For floating-point precision of 18:
3954 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3956 // error 0.0000023660568, which is better than 18 bits
3957 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3958 getF32Constant(DAG, 0xbc91e5ac, dl));
3959 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3960 getF32Constant(DAG, 0x3e4350aa, dl));
3961 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3962 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3963 getF32Constant(DAG, 0x3f60d3e3, dl));
3964 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3965 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3966 getF32Constant(DAG, 0x4011cdf0, dl));
3967 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3968 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3969 getF32Constant(DAG, 0x406cfd1c, dl));
3970 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3971 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3972 getF32Constant(DAG, 0x408797cb, dl));
3973 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3974 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3975 getF32Constant(DAG, 0x4006dcab, dl));
3978 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3981 // No special expansion.
3982 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3985 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3986 /// limited-precision mode.
3987 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3988 const TargetLowering &TLI) {
3990 // TODO: What fast-math-flags should be set on the floating-point nodes?
3992 if (Op.getValueType() == MVT::f32 &&
3993 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3994 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3996 // Get the exponent.
3997 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3999 // Get the significand and build it into a floating-point number with
4001 SDValue X = GetSignificand(DAG, Op1, dl);
4003 // Different possible minimax approximations of significand in
4004 // floating-point for various degrees of accuracy over [1,2].
4005 SDValue Log2ofMantissa;
4006 if (LimitFloatPrecision <= 6) {
4007 // For floating-point precision of 6:
4009 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4011 // error 0.0049451742, which is more than 7 bits
4012 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4013 getF32Constant(DAG, 0xbeb08fe0, dl));
4014 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4015 getF32Constant(DAG, 0x40019463, dl));
4016 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4017 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4018 getF32Constant(DAG, 0x3fd6633d, dl));
4019 } else if (LimitFloatPrecision <= 12) {
4020 // For floating-point precision of 12:
4026 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4028 // error 0.0000876136000, which is better than 13 bits
4029 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4030 getF32Constant(DAG, 0xbda7262e, dl));
4031 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4032 getF32Constant(DAG, 0x3f25280b, dl));
4033 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4034 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4035 getF32Constant(DAG, 0x4007b923, dl));
4036 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4037 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4038 getF32Constant(DAG, 0x40823e2f, dl));
4039 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4040 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4041 getF32Constant(DAG, 0x4020d29c, dl));
4042 } else { // LimitFloatPrecision <= 18
4043 // For floating-point precision of 18:
4052 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4054 // error 0.0000018516, which is better than 18 bits
4055 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4056 getF32Constant(DAG, 0xbcd2769e, dl));
4057 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4058 getF32Constant(DAG, 0x3e8ce0b9, dl));
4059 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4060 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4061 getF32Constant(DAG, 0x3fa22ae7, dl));
4062 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4063 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4064 getF32Constant(DAG, 0x40525723, dl));
4065 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4066 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4067 getF32Constant(DAG, 0x40aaf200, dl));
4068 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4069 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4070 getF32Constant(DAG, 0x40c39dad, dl));
4071 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4072 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4073 getF32Constant(DAG, 0x4042902c, dl));
4076 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4079 // No special expansion.
4080 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4083 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4084 /// limited-precision mode.
4085 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4086 const TargetLowering &TLI) {
4088 // TODO: What fast-math-flags should be set on the floating-point nodes?
4090 if (Op.getValueType() == MVT::f32 &&
4091 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4092 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4094 // Scale the exponent by log10(2) [0.30102999f].
4095 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4096 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4097 getF32Constant(DAG, 0x3e9a209a, dl));
4099 // Get the significand and build it into a floating-point number with
4101 SDValue X = GetSignificand(DAG, Op1, dl);
4103 SDValue Log10ofMantissa;
4104 if (LimitFloatPrecision <= 6) {
4105 // For floating-point precision of 6:
4107 // Log10ofMantissa =
4109 // (0.60948995f - 0.10380950f * x) * x;
4111 // error 0.0014886165, which is 6 bits
4112 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4113 getF32Constant(DAG, 0xbdd49a13, dl));
4114 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4115 getF32Constant(DAG, 0x3f1c0789, dl));
4116 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4117 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4118 getF32Constant(DAG, 0x3f011300, dl));
4119 } else if (LimitFloatPrecision <= 12) {
4120 // For floating-point precision of 12:
4122 // Log10ofMantissa =
4125 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4127 // error 0.00019228036, which is better than 12 bits
4128 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4129 getF32Constant(DAG, 0x3d431f31, dl));
4130 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4131 getF32Constant(DAG, 0x3ea21fb2, dl));
4132 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4133 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4134 getF32Constant(DAG, 0x3f6ae232, dl));
4135 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4136 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4137 getF32Constant(DAG, 0x3f25f7c3, dl));
4138 } else { // LimitFloatPrecision <= 18
4139 // For floating-point precision of 18:
4141 // Log10ofMantissa =
4146 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4148 // error 0.0000037995730, which is better than 18 bits
4149 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4150 getF32Constant(DAG, 0x3c5d51ce, dl));
4151 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4152 getF32Constant(DAG, 0x3e00685a, dl));
4153 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4154 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4155 getF32Constant(DAG, 0x3efb6798, dl));
4156 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4157 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4158 getF32Constant(DAG, 0x3f88d192, dl));
4159 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4160 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4161 getF32Constant(DAG, 0x3fc4316c, dl));
4162 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4163 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4164 getF32Constant(DAG, 0x3f57ce70, dl));
4167 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4170 // No special expansion.
4171 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4174 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4175 /// limited-precision mode.
4176 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4177 const TargetLowering &TLI) {
4178 if (Op.getValueType() == MVT::f32 &&
4179 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4180 return getLimitedPrecisionExp2(Op, dl, DAG);
4182 // No special expansion.
4183 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4186 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4187 /// limited-precision mode with x == 10.0f.
4188 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4189 SelectionDAG &DAG, const TargetLowering &TLI) {
4190 bool IsExp10 = false;
4191 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4192 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4193 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4195 IsExp10 = LHSC->isExactlyValue(Ten);
4199 // TODO: What fast-math-flags should be set on the FMUL node?
4201 // Put the exponent in the right bit position for later addition to the
4204 // #define LOG2OF10 3.3219281f
4205 // t0 = Op * LOG2OF10;
4206 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4207 getF32Constant(DAG, 0x40549a78, dl));
4208 return getLimitedPrecisionExp2(t0, dl, DAG);
4211 // No special expansion.
4212 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4216 /// ExpandPowI - Expand a llvm.powi intrinsic.
4217 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4218 SelectionDAG &DAG) {
4219 // If RHS is a constant, we can expand this out to a multiplication tree,
4220 // otherwise we end up lowering to a call to __powidf2 (for example). When
4221 // optimizing for size, we only want to do this if the expansion would produce
4222 // a small number of multiplies, otherwise we do the full expansion.
4223 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4224 // Get the exponent as a positive value.
4225 unsigned Val = RHSC->getSExtValue();
4226 if ((int)Val < 0) Val = -Val;
4228 // powi(x, 0) -> 1.0
4230 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4232 const Function *F = DAG.getMachineFunction().getFunction();
4233 if (!F->optForSize() ||
4234 // If optimizing for size, don't insert too many multiplies.
4235 // This inserts up to 5 multiplies.
4236 countPopulation(Val) + Log2_32(Val) < 7) {
4237 // We use the simple binary decomposition method to generate the multiply
4238 // sequence. There are more optimal ways to do this (for example,
4239 // powi(x,15) generates one more multiply than it should), but this has
4240 // the benefit of being both really simple and much better than a libcall.
4241 SDValue Res; // Logically starts equal to 1.0
4242 SDValue CurSquare = LHS;
4243 // TODO: Intrinsics should have fast-math-flags that propagate to these
4248 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4250 Res = CurSquare; // 1.0*CurSquare.
4253 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4254 CurSquare, CurSquare);
4258 // If the original was negative, invert the result, producing 1/(x*x*x).
4259 if (RHSC->getSExtValue() < 0)
4260 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4261 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4266 // Otherwise, expand to a libcall.
4267 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4270 // getUnderlyingArgReg - Find underlying register used for a truncated or
4271 // bitcasted argument.
4272 static unsigned getUnderlyingArgReg(const SDValue &N) {
4273 switch (N.getOpcode()) {
4274 case ISD::CopyFromReg:
4275 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4277 case ISD::AssertZext:
4278 case ISD::AssertSext:
4280 return getUnderlyingArgReg(N.getOperand(0));
4286 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4287 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4288 /// At the end of instruction selection, they will be inserted to the entry BB.
4289 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4290 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4291 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4292 const Argument *Arg = dyn_cast<Argument>(V);
4296 MachineFunction &MF = DAG.getMachineFunction();
4297 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4299 // Ignore inlined function arguments here.
4301 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4302 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4305 Optional<MachineOperand> Op;
4306 // Some arguments' frame index is recorded during argument lowering.
4307 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4308 Op = MachineOperand::CreateFI(FI);
4310 if (!Op && N.getNode()) {
4311 unsigned Reg = getUnderlyingArgReg(N);
4312 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4313 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4314 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4319 Op = MachineOperand::CreateReg(Reg, false);
4323 // Check if ValueMap has reg number.
4324 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4325 if (VMI != FuncInfo.ValueMap.end())
4326 Op = MachineOperand::CreateReg(VMI->second, false);
4329 if (!Op && N.getNode())
4330 // Check if frame index is available.
4331 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4332 if (FrameIndexSDNode *FINode =
4333 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4334 Op = MachineOperand::CreateFI(FINode->getIndex());
4339 assert(Variable->isValidLocationForIntrinsic(DL) &&
4340 "Expected inlined-at fields to agree");
4342 FuncInfo.ArgDbgValues.push_back(
4343 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4344 Op->getReg(), Offset, Variable, Expr));
4346 FuncInfo.ArgDbgValues.push_back(
4347 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4350 .addMetadata(Variable)
4351 .addMetadata(Expr));
4356 // VisualStudio defines setjmp as _setjmp
4357 #if defined(_MSC_VER) && defined(setjmp) && \
4358 !defined(setjmp_undefined_for_msvc)
4359 # pragma push_macro("setjmp")
4361 # define setjmp_undefined_for_msvc
4364 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4365 /// we want to emit this as a call to a named external function, return the name
4366 /// otherwise lower it and return null.
4368 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4369 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4370 SDLoc sdl = getCurSDLoc();
4371 DebugLoc dl = getCurDebugLoc();
4374 switch (Intrinsic) {
4376 // By default, turn this into a target intrinsic node.
4377 visitTargetIntrinsic(I, Intrinsic);
4379 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4380 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4381 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4382 case Intrinsic::returnaddress:
4383 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4384 TLI.getPointerTy(DAG.getDataLayout()),
4385 getValue(I.getArgOperand(0))));
4387 case Intrinsic::frameaddress:
4388 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4389 TLI.getPointerTy(DAG.getDataLayout()),
4390 getValue(I.getArgOperand(0))));
4392 case Intrinsic::read_register: {
4393 Value *Reg = I.getArgOperand(0);
4394 SDValue Chain = getRoot();
4396 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4397 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4398 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4399 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4401 DAG.setRoot(Res.getValue(1));
4404 case Intrinsic::write_register: {
4405 Value *Reg = I.getArgOperand(0);
4406 Value *RegValue = I.getArgOperand(1);
4407 SDValue Chain = getRoot();
4409 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4410 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4411 RegName, getValue(RegValue)));
4414 case Intrinsic::setjmp:
4415 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4416 case Intrinsic::longjmp:
4417 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4418 case Intrinsic::memcpy: {
4419 SDValue Op1 = getValue(I.getArgOperand(0));
4420 SDValue Op2 = getValue(I.getArgOperand(1));
4421 SDValue Op3 = getValue(I.getArgOperand(2));
4422 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4424 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4425 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4426 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4427 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4429 MachinePointerInfo(I.getArgOperand(0)),
4430 MachinePointerInfo(I.getArgOperand(1)));
4431 updateDAGForMaybeTailCall(MC);
4434 case Intrinsic::memset: {
4435 SDValue Op1 = getValue(I.getArgOperand(0));
4436 SDValue Op2 = getValue(I.getArgOperand(1));
4437 SDValue Op3 = getValue(I.getArgOperand(2));
4438 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4440 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4441 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4442 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4443 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4444 isTC, MachinePointerInfo(I.getArgOperand(0)));
4445 updateDAGForMaybeTailCall(MS);
4448 case Intrinsic::memmove: {
4449 SDValue Op1 = getValue(I.getArgOperand(0));
4450 SDValue Op2 = getValue(I.getArgOperand(1));
4451 SDValue Op3 = getValue(I.getArgOperand(2));
4452 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4454 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4455 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4456 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4457 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4458 isTC, MachinePointerInfo(I.getArgOperand(0)),
4459 MachinePointerInfo(I.getArgOperand(1)));
4460 updateDAGForMaybeTailCall(MM);
4463 case Intrinsic::dbg_declare: {
4464 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4465 DILocalVariable *Variable = DI.getVariable();
4466 DIExpression *Expression = DI.getExpression();
4467 const Value *Address = DI.getAddress();
4468 assert(Variable && "Missing variable");
4470 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4474 // Check if address has undef value.
4475 if (isa<UndefValue>(Address) ||
4476 (Address->use_empty() && !isa<Argument>(Address))) {
4477 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4481 SDValue &N = NodeMap[Address];
4482 if (!N.getNode() && isa<Argument>(Address))
4483 // Check unused arguments map.
4484 N = UnusedArgNodeMap[Address];
4487 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4488 Address = BCI->getOperand(0);
4489 // Parameters are handled specially.
4490 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4491 auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4492 if (isParameter && FINode) {
4493 // Byval parameter. We have a frame index at this point.
4494 SDV = DAG.getFrameIndexDbgValue(Variable, Expression,
4495 FINode->getIndex(), 0, dl, SDNodeOrder);
4496 } else if (isa<Argument>(Address)) {
4497 // Address is an argument, so try to emit its dbg value using
4498 // virtual register info from the FuncInfo.ValueMap.
4499 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4503 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4504 true, 0, dl, SDNodeOrder);
4506 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4508 // If Address is an argument then try to emit its dbg value using
4509 // virtual register info from the FuncInfo.ValueMap.
4510 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4512 // If variable is pinned by a alloca in dominating bb then
4513 // use StaticAllocaMap.
4514 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4515 if (AI->getParent() != DI.getParent()) {
4516 DenseMap<const AllocaInst*, int>::iterator SI =
4517 FuncInfo.StaticAllocaMap.find(AI);
4518 if (SI != FuncInfo.StaticAllocaMap.end()) {
4519 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4520 0, dl, SDNodeOrder);
4521 DAG.AddDbgValue(SDV, nullptr, false);
4526 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4531 case Intrinsic::dbg_value: {
4532 const DbgValueInst &DI = cast<DbgValueInst>(I);
4533 assert(DI.getVariable() && "Missing variable");
4535 DILocalVariable *Variable = DI.getVariable();
4536 DIExpression *Expression = DI.getExpression();
4537 uint64_t Offset = DI.getOffset();
4538 const Value *V = DI.getValue();
4543 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4544 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4546 DAG.AddDbgValue(SDV, nullptr, false);
4548 // Do not use getValue() in here; we don't want to generate code at
4549 // this point if it hasn't been done yet.
4550 SDValue N = NodeMap[V];
4551 if (!N.getNode() && isa<Argument>(V))
4552 // Check unused arguments map.
4553 N = UnusedArgNodeMap[V];
4555 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4557 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4558 false, Offset, dl, SDNodeOrder);
4559 DAG.AddDbgValue(SDV, N.getNode(), false);
4561 } else if (!V->use_empty() ) {
4562 // Do not call getValue(V) yet, as we don't want to generate code.
4563 // Remember it for later.
4564 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4565 DanglingDebugInfoMap[V] = DDI;
4567 // We may expand this to cover more cases. One case where we have no
4568 // data available is an unreferenced parameter.
4569 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4573 // Build a debug info table entry.
4574 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4575 V = BCI->getOperand(0);
4576 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4577 // Don't handle byval struct arguments or VLAs, for example.
4579 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4580 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4583 DenseMap<const AllocaInst*, int>::iterator SI =
4584 FuncInfo.StaticAllocaMap.find(AI);
4585 if (SI == FuncInfo.StaticAllocaMap.end())
4586 return nullptr; // VLAs.
4590 case Intrinsic::eh_typeid_for: {
4591 // Find the type id for the given typeinfo.
4592 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4593 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4594 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4599 case Intrinsic::eh_return_i32:
4600 case Intrinsic::eh_return_i64:
4601 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4602 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4605 getValue(I.getArgOperand(0)),
4606 getValue(I.getArgOperand(1))));
4608 case Intrinsic::eh_unwind_init:
4609 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4611 case Intrinsic::eh_dwarf_cfa: {
4612 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4613 TLI.getPointerTy(DAG.getDataLayout()));
4614 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4615 CfaArg.getValueType(),
4616 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4617 CfaArg.getValueType()),
4619 SDValue FA = DAG.getNode(
4620 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4621 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4622 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4626 case Intrinsic::eh_sjlj_callsite: {
4627 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4628 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4629 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4630 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4632 MMI.setCurrentCallSite(CI->getZExtValue());
4635 case Intrinsic::eh_sjlj_functioncontext: {
4636 // Get and store the index of the function context.
4637 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4639 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4640 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4641 MFI->setFunctionContextIndex(FI);
4644 case Intrinsic::eh_sjlj_setjmp: {
4647 Ops[1] = getValue(I.getArgOperand(0));
4648 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4649 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4650 setValue(&I, Op.getValue(0));
4651 DAG.setRoot(Op.getValue(1));
4654 case Intrinsic::eh_sjlj_longjmp: {
4655 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4656 getRoot(), getValue(I.getArgOperand(0))));
4659 case Intrinsic::eh_sjlj_setup_dispatch: {
4660 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4665 case Intrinsic::masked_gather:
4666 visitMaskedGather(I);
4668 case Intrinsic::masked_load:
4671 case Intrinsic::masked_scatter:
4672 visitMaskedScatter(I);
4674 case Intrinsic::masked_store:
4675 visitMaskedStore(I);
4677 case Intrinsic::x86_mmx_pslli_w:
4678 case Intrinsic::x86_mmx_pslli_d:
4679 case Intrinsic::x86_mmx_pslli_q:
4680 case Intrinsic::x86_mmx_psrli_w:
4681 case Intrinsic::x86_mmx_psrli_d:
4682 case Intrinsic::x86_mmx_psrli_q:
4683 case Intrinsic::x86_mmx_psrai_w:
4684 case Intrinsic::x86_mmx_psrai_d: {
4685 SDValue ShAmt = getValue(I.getArgOperand(1));
4686 if (isa<ConstantSDNode>(ShAmt)) {
4687 visitTargetIntrinsic(I, Intrinsic);
4690 unsigned NewIntrinsic = 0;
4691 EVT ShAmtVT = MVT::v2i32;
4692 switch (Intrinsic) {
4693 case Intrinsic::x86_mmx_pslli_w:
4694 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4696 case Intrinsic::x86_mmx_pslli_d:
4697 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4699 case Intrinsic::x86_mmx_pslli_q:
4700 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4702 case Intrinsic::x86_mmx_psrli_w:
4703 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4705 case Intrinsic::x86_mmx_psrli_d:
4706 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4708 case Intrinsic::x86_mmx_psrli_q:
4709 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4711 case Intrinsic::x86_mmx_psrai_w:
4712 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4714 case Intrinsic::x86_mmx_psrai_d:
4715 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4717 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4720 // The vector shift intrinsics with scalars uses 32b shift amounts but
4721 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4723 // We must do this early because v2i32 is not a legal type.
4726 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4727 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4728 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4729 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4730 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4731 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4732 getValue(I.getArgOperand(0)), ShAmt);
4736 case Intrinsic::convertff:
4737 case Intrinsic::convertfsi:
4738 case Intrinsic::convertfui:
4739 case Intrinsic::convertsif:
4740 case Intrinsic::convertuif:
4741 case Intrinsic::convertss:
4742 case Intrinsic::convertsu:
4743 case Intrinsic::convertus:
4744 case Intrinsic::convertuu: {
4745 ISD::CvtCode Code = ISD::CVT_INVALID;
4746 switch (Intrinsic) {
4747 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4748 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4749 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4750 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4751 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4752 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4753 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4754 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4755 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4756 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4758 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4759 const Value *Op1 = I.getArgOperand(0);
4760 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4761 DAG.getValueType(DestVT),
4762 DAG.getValueType(getValue(Op1).getValueType()),
4763 getValue(I.getArgOperand(1)),
4764 getValue(I.getArgOperand(2)),
4769 case Intrinsic::powi:
4770 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4771 getValue(I.getArgOperand(1)), DAG));
4773 case Intrinsic::log:
4774 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4776 case Intrinsic::log2:
4777 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4779 case Intrinsic::log10:
4780 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4782 case Intrinsic::exp:
4783 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4785 case Intrinsic::exp2:
4786 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4788 case Intrinsic::pow:
4789 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4790 getValue(I.getArgOperand(1)), DAG, TLI));
4792 case Intrinsic::sqrt:
4793 case Intrinsic::fabs:
4794 case Intrinsic::sin:
4795 case Intrinsic::cos:
4796 case Intrinsic::floor:
4797 case Intrinsic::ceil:
4798 case Intrinsic::trunc:
4799 case Intrinsic::rint:
4800 case Intrinsic::nearbyint:
4801 case Intrinsic::round: {
4803 switch (Intrinsic) {
4804 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4805 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4806 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4807 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4808 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4809 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4810 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4811 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4812 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4813 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4814 case Intrinsic::round: Opcode = ISD::FROUND; break;
4817 setValue(&I, DAG.getNode(Opcode, sdl,
4818 getValue(I.getArgOperand(0)).getValueType(),
4819 getValue(I.getArgOperand(0))));
4822 case Intrinsic::minnum:
4823 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4824 getValue(I.getArgOperand(0)).getValueType(),
4825 getValue(I.getArgOperand(0)),
4826 getValue(I.getArgOperand(1))));
4828 case Intrinsic::maxnum:
4829 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4830 getValue(I.getArgOperand(0)).getValueType(),
4831 getValue(I.getArgOperand(0)),
4832 getValue(I.getArgOperand(1))));
4834 case Intrinsic::copysign:
4835 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4836 getValue(I.getArgOperand(0)).getValueType(),
4837 getValue(I.getArgOperand(0)),
4838 getValue(I.getArgOperand(1))));
4840 case Intrinsic::fma:
4841 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4842 getValue(I.getArgOperand(0)).getValueType(),
4843 getValue(I.getArgOperand(0)),
4844 getValue(I.getArgOperand(1)),
4845 getValue(I.getArgOperand(2))));
4847 case Intrinsic::fmuladd: {
4848 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4849 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4850 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4851 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4852 getValue(I.getArgOperand(0)).getValueType(),
4853 getValue(I.getArgOperand(0)),
4854 getValue(I.getArgOperand(1)),
4855 getValue(I.getArgOperand(2))));
4857 // TODO: Intrinsic calls should have fast-math-flags.
4858 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4859 getValue(I.getArgOperand(0)).getValueType(),
4860 getValue(I.getArgOperand(0)),
4861 getValue(I.getArgOperand(1)));
4862 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4863 getValue(I.getArgOperand(0)).getValueType(),
4865 getValue(I.getArgOperand(2)));
4870 case Intrinsic::convert_to_fp16:
4871 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4872 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4873 getValue(I.getArgOperand(0)),
4874 DAG.getTargetConstant(0, sdl,
4877 case Intrinsic::convert_from_fp16:
4878 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4879 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4880 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4881 getValue(I.getArgOperand(0)))));
4883 case Intrinsic::pcmarker: {
4884 SDValue Tmp = getValue(I.getArgOperand(0));
4885 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4888 case Intrinsic::readcyclecounter: {
4889 SDValue Op = getRoot();
4890 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4891 DAG.getVTList(MVT::i64, MVT::Other), Op);
4893 DAG.setRoot(Res.getValue(1));
4896 case Intrinsic::bitreverse:
4897 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
4898 getValue(I.getArgOperand(0)).getValueType(),
4899 getValue(I.getArgOperand(0))));
4901 case Intrinsic::bswap:
4902 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4903 getValue(I.getArgOperand(0)).getValueType(),
4904 getValue(I.getArgOperand(0))));
4906 case Intrinsic::cttz: {
4907 SDValue Arg = getValue(I.getArgOperand(0));
4908 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4909 EVT Ty = Arg.getValueType();
4910 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4914 case Intrinsic::ctlz: {
4915 SDValue Arg = getValue(I.getArgOperand(0));
4916 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4917 EVT Ty = Arg.getValueType();
4918 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4922 case Intrinsic::ctpop: {
4923 SDValue Arg = getValue(I.getArgOperand(0));
4924 EVT Ty = Arg.getValueType();
4925 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4928 case Intrinsic::stacksave: {
4929 SDValue Op = getRoot();
4931 ISD::STACKSAVE, sdl,
4932 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4934 DAG.setRoot(Res.getValue(1));
4937 case Intrinsic::stackrestore: {
4938 Res = getValue(I.getArgOperand(0));
4939 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4942 case Intrinsic::get_dynamic_area_offset: {
4943 SDValue Op = getRoot();
4944 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4945 EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
4946 // Result type for @llvm.get.dynamic.area.offset should match PtrTy for
4949 report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset"
4951 Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),
4957 case Intrinsic::stackprotector: {
4958 // Emit code into the DAG to store the stack guard onto the stack.
4959 MachineFunction &MF = DAG.getMachineFunction();
4960 MachineFrameInfo *MFI = MF.getFrameInfo();
4961 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4962 SDValue Src, Chain = getRoot();
4963 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4964 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4966 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4967 // global variable __stack_chk_guard.
4969 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4970 if (BC->getOpcode() == Instruction::BitCast)
4971 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4973 if (GV && TLI.useLoadStackGuardNode()) {
4974 // Emit a LOAD_STACK_GUARD node.
4975 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4977 MachinePointerInfo MPInfo(GV);
4978 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4979 unsigned Flags = MachineMemOperand::MOLoad |
4980 MachineMemOperand::MOInvariant;
4981 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4982 PtrTy.getSizeInBits() / 8,
4983 DAG.getEVTAlignment(PtrTy));
4984 Node->setMemRefs(MemRefs, MemRefs + 1);
4986 // Copy the guard value to a virtual register so that it can be
4987 // retrieved in the epilogue.
4988 Src = SDValue(Node, 0);
4989 const TargetRegisterClass *RC =
4990 TLI.getRegClassFor(Src.getSimpleValueType());
4991 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4993 SPDescriptor.setGuardReg(Reg);
4994 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4996 Src = getValue(I.getArgOperand(0)); // The guard's value.
4999 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5001 int FI = FuncInfo.StaticAllocaMap[Slot];
5002 MFI->setStackProtectorIndex(FI);
5004 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5006 // Store the stack protector onto the stack.
5007 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
5008 DAG.getMachineFunction(), FI),
5014 case Intrinsic::objectsize: {
5015 // If we don't know by now, we're never going to know.
5016 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5018 assert(CI && "Non-constant type in __builtin_object_size?");
5020 SDValue Arg = getValue(I.getCalledValue());
5021 EVT Ty = Arg.getValueType();
5024 Res = DAG.getConstant(-1ULL, sdl, Ty);
5026 Res = DAG.getConstant(0, sdl, Ty);
5031 case Intrinsic::annotation:
5032 case Intrinsic::ptr_annotation:
5033 // Drop the intrinsic, but forward the value
5034 setValue(&I, getValue(I.getOperand(0)));
5036 case Intrinsic::assume:
5037 case Intrinsic::var_annotation:
5038 // Discard annotate attributes and assumptions
5041 case Intrinsic::init_trampoline: {
5042 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5046 Ops[1] = getValue(I.getArgOperand(0));
5047 Ops[2] = getValue(I.getArgOperand(1));
5048 Ops[3] = getValue(I.getArgOperand(2));
5049 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5050 Ops[5] = DAG.getSrcValue(F);
5052 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5057 case Intrinsic::adjust_trampoline: {
5058 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5059 TLI.getPointerTy(DAG.getDataLayout()),
5060 getValue(I.getArgOperand(0))));
5063 case Intrinsic::gcroot:
5065 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5066 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5068 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5069 GFI->addStackRoot(FI->getIndex(), TypeMap);
5072 case Intrinsic::gcread:
5073 case Intrinsic::gcwrite:
5074 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5075 case Intrinsic::flt_rounds:
5076 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5079 case Intrinsic::expect: {
5080 // Just replace __builtin_expect(exp, c) with EXP.
5081 setValue(&I, getValue(I.getArgOperand(0)));
5085 case Intrinsic::debugtrap:
5086 case Intrinsic::trap: {
5087 StringRef TrapFuncName =
5089 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5090 .getValueAsString();
5091 if (TrapFuncName.empty()) {
5092 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5093 ISD::TRAP : ISD::DEBUGTRAP;
5094 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5097 TargetLowering::ArgListTy Args;
5099 TargetLowering::CallLoweringInfo CLI(DAG);
5100 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5101 CallingConv::C, I.getType(),
5102 DAG.getExternalSymbol(TrapFuncName.data(),
5103 TLI.getPointerTy(DAG.getDataLayout())),
5104 std::move(Args), 0);
5106 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5107 DAG.setRoot(Result.second);
5111 case Intrinsic::uadd_with_overflow:
5112 case Intrinsic::sadd_with_overflow:
5113 case Intrinsic::usub_with_overflow:
5114 case Intrinsic::ssub_with_overflow:
5115 case Intrinsic::umul_with_overflow:
5116 case Intrinsic::smul_with_overflow: {
5118 switch (Intrinsic) {
5119 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5120 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5121 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5122 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5123 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5124 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5125 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5127 SDValue Op1 = getValue(I.getArgOperand(0));
5128 SDValue Op2 = getValue(I.getArgOperand(1));
5130 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5131 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5134 case Intrinsic::prefetch: {
5136 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5138 Ops[1] = getValue(I.getArgOperand(0));
5139 Ops[2] = getValue(I.getArgOperand(1));
5140 Ops[3] = getValue(I.getArgOperand(2));
5141 Ops[4] = getValue(I.getArgOperand(3));
5142 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5143 DAG.getVTList(MVT::Other), Ops,
5144 EVT::getIntegerVT(*Context, 8),
5145 MachinePointerInfo(I.getArgOperand(0)),
5147 false, /* volatile */
5149 rw==1)); /* write */
5152 case Intrinsic::lifetime_start:
5153 case Intrinsic::lifetime_end: {
5154 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5155 // Stack coloring is not enabled in O0, discard region information.
5156 if (TM.getOptLevel() == CodeGenOpt::None)
5159 SmallVector<Value *, 4> Allocas;
5160 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5162 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5163 E = Allocas.end(); Object != E; ++Object) {
5164 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5166 // Could not find an Alloca.
5167 if (!LifetimeObject)
5170 // First check that the Alloca is static, otherwise it won't have a
5171 // valid frame index.
5172 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5173 if (SI == FuncInfo.StaticAllocaMap.end())
5176 int FI = SI->second;
5181 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5182 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5184 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5189 case Intrinsic::invariant_start:
5190 // Discard region information.
5191 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5193 case Intrinsic::invariant_end:
5194 // Discard region information.
5196 case Intrinsic::stackprotectorcheck: {
5197 // Do not actually emit anything for this basic block. Instead we initialize
5198 // the stack protector descriptor and export the guard variable so we can
5199 // access it in FinishBasicBlock.
5200 const BasicBlock *BB = I.getParent();
5201 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5202 ExportFromCurrentBlock(SPDescriptor.getGuard());
5204 // Flush our exports since we are going to process a terminator.
5205 (void)getControlRoot();
5208 case Intrinsic::clear_cache:
5209 return TLI.getClearCacheBuiltinName();
5210 case Intrinsic::donothing:
5213 case Intrinsic::experimental_stackmap: {
5217 case Intrinsic::experimental_patchpoint_void:
5218 case Intrinsic::experimental_patchpoint_i64: {
5219 visitPatchpoint(&I);
5222 case Intrinsic::experimental_gc_statepoint: {
5226 case Intrinsic::experimental_gc_result: {
5230 case Intrinsic::experimental_gc_relocate: {
5231 visitGCRelocate(cast<GCRelocateInst>(I));
5234 case Intrinsic::instrprof_increment:
5235 llvm_unreachable("instrprof failed to lower an increment");
5236 case Intrinsic::instrprof_value_profile:
5237 llvm_unreachable("instrprof failed to lower a value profiling call");
5238 case Intrinsic::localescape: {
5239 MachineFunction &MF = DAG.getMachineFunction();
5240 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5242 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5243 // is the same on all targets.
5244 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5245 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5246 if (isa<ConstantPointerNull>(Arg))
5247 continue; // Skip null pointers. They represent a hole in index space.
5248 AllocaInst *Slot = cast<AllocaInst>(Arg);
5249 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5250 "can only escape static allocas");
5251 int FI = FuncInfo.StaticAllocaMap[Slot];
5252 MCSymbol *FrameAllocSym =
5253 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5254 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5255 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5256 TII->get(TargetOpcode::LOCAL_ESCAPE))
5257 .addSym(FrameAllocSym)
5264 case Intrinsic::localrecover: {
5265 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5266 MachineFunction &MF = DAG.getMachineFunction();
5267 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5269 // Get the symbol that defines the frame offset.
5270 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5271 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5272 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5273 MCSymbol *FrameAllocSym =
5274 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5275 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5277 // Create a MCSymbol for the label to avoid any target lowering
5278 // that would make this PC relative.
5279 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5281 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5283 // Add the offset to the FP.
5284 Value *FP = I.getArgOperand(1);
5285 SDValue FPVal = getValue(FP);
5286 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5292 case Intrinsic::eh_exceptionpointer:
5293 case Intrinsic::eh_exceptioncode: {
5294 // Get the exception pointer vreg, copy from it, and resize it to fit.
5295 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5296 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5297 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5298 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5300 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5301 if (Intrinsic == Intrinsic::eh_exceptioncode)
5302 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5309 std::pair<SDValue, SDValue>
5310 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5311 const BasicBlock *EHPadBB) {
5312 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5313 MCSymbol *BeginLabel = nullptr;
5316 // Insert a label before the invoke call to mark the try range. This can be
5317 // used to detect deletion of the invoke via the MachineModuleInfo.
5318 BeginLabel = MMI.getContext().createTempSymbol();
5320 // For SjLj, keep track of which landing pads go with which invokes
5321 // so as to maintain the ordering of pads in the LSDA.
5322 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5323 if (CallSiteIndex) {
5324 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5325 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5327 // Now that the call site is handled, stop tracking it.
5328 MMI.setCurrentCallSite(0);
5331 // Both PendingLoads and PendingExports must be flushed here;
5332 // this call might not return.
5334 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5336 CLI.setChain(getRoot());
5338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5339 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5341 assert((CLI.IsTailCall || Result.second.getNode()) &&
5342 "Non-null chain expected with non-tail call!");
5343 assert((Result.second.getNode() || !Result.first.getNode()) &&
5344 "Null value expected with tail call!");
5346 if (!Result.second.getNode()) {
5347 // As a special case, a null chain means that a tail call has been emitted
5348 // and the DAG root is already updated.
5351 // Since there's no actual continuation from this block, nothing can be
5352 // relying on us setting vregs for them.
5353 PendingExports.clear();
5355 DAG.setRoot(Result.second);
5359 // Insert a label at the end of the invoke call to mark the try range. This
5360 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5361 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5362 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5364 // Inform MachineModuleInfo of range.
5365 if (MMI.hasEHFunclets()) {
5367 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
5368 EHInfo->addIPToStateRange(cast<InvokeInst>(CLI.CS->getInstruction()),
5369 BeginLabel, EndLabel);
5371 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5378 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5380 const BasicBlock *EHPadBB) {
5381 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5382 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5383 Type *RetTy = FTy->getReturnType();
5385 TargetLowering::ArgListTy Args;
5386 TargetLowering::ArgListEntry Entry;
5387 Args.reserve(CS.arg_size());
5389 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5391 const Value *V = *i;
5394 if (V->getType()->isEmptyTy())
5397 SDValue ArgNode = getValue(V);
5398 Entry.Node = ArgNode; Entry.Ty = V->getType();
5400 // Skip the first return-type Attribute to get to params.
5401 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5402 Args.push_back(Entry);
5404 // If we have an explicit sret argument that is an Instruction, (i.e., it
5405 // might point to function-local memory), we can't meaningfully tail-call.
5406 if (Entry.isSRet && isa<Instruction>(V))
5410 // Check if target-independent constraints permit a tail call here.
5411 // Target-dependent constraints are checked within TLI->LowerCallTo.
5412 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5415 TargetLowering::CallLoweringInfo CLI(DAG);
5416 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5417 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5418 .setTailCall(isTailCall);
5419 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5421 if (Result.first.getNode())
5422 setValue(CS.getInstruction(), Result.first);
5425 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5426 /// value is equal or not-equal to zero.
5427 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5428 for (const User *U : V->users()) {
5429 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5430 if (IC->isEquality())
5431 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5432 if (C->isNullValue())
5434 // Unknown instruction.
5440 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5442 SelectionDAGBuilder &Builder) {
5444 // Check to see if this load can be trivially constant folded, e.g. if the
5445 // input is from a string literal.
5446 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5447 // Cast pointer to the type we really want to load.
5448 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5449 PointerType::getUnqual(LoadTy));
5451 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5452 const_cast<Constant *>(LoadInput), *Builder.DL))
5453 return Builder.getValue(LoadCst);
5456 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5457 // still constant memory, the input chain can be the entry node.
5459 bool ConstantMemory = false;
5461 // Do not serialize (non-volatile) loads of constant memory with anything.
5462 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5463 Root = Builder.DAG.getEntryNode();
5464 ConstantMemory = true;
5466 // Do not serialize non-volatile loads against each other.
5467 Root = Builder.DAG.getRoot();
5470 SDValue Ptr = Builder.getValue(PtrVal);
5471 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5472 Ptr, MachinePointerInfo(PtrVal),
5474 false /*nontemporal*/,
5475 false /*isinvariant*/, 1 /* align=1 */);
5477 if (!ConstantMemory)
5478 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5482 /// processIntegerCallValue - Record the value for an instruction that
5483 /// produces an integer result, converting the type where necessary.
5484 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5487 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5490 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5492 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5493 setValue(&I, Value);
5496 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5497 /// If so, return true and lower it, otherwise return false and it will be
5498 /// lowered like a normal call.
5499 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5500 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5501 if (I.getNumArgOperands() != 3)
5504 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5505 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5506 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5507 !I.getType()->isIntegerTy())
5510 const Value *Size = I.getArgOperand(2);
5511 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5512 if (CSize && CSize->getZExtValue() == 0) {
5513 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5515 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5519 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5520 std::pair<SDValue, SDValue> Res =
5521 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5522 getValue(LHS), getValue(RHS), getValue(Size),
5523 MachinePointerInfo(LHS),
5524 MachinePointerInfo(RHS));
5525 if (Res.first.getNode()) {
5526 processIntegerCallValue(I, Res.first, true);
5527 PendingLoads.push_back(Res.second);
5531 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5532 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5533 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5534 bool ActuallyDoIt = true;
5537 switch (CSize->getZExtValue()) {
5539 LoadVT = MVT::Other;
5541 ActuallyDoIt = false;
5545 LoadTy = Type::getInt16Ty(CSize->getContext());
5549 LoadTy = Type::getInt32Ty(CSize->getContext());
5553 LoadTy = Type::getInt64Ty(CSize->getContext());
5557 LoadVT = MVT::v4i32;
5558 LoadTy = Type::getInt32Ty(CSize->getContext());
5559 LoadTy = VectorType::get(LoadTy, 4);
5564 // This turns into unaligned loads. We only do this if the target natively
5565 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5566 // we'll only produce a small number of byte loads.
5568 // Require that we can find a legal MVT, and only do this if the target
5569 // supports unaligned loads of that type. Expanding into byte loads would
5571 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5572 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5573 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5574 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5575 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5576 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5577 // TODO: Check alignment of src and dest ptrs.
5578 if (!TLI.isTypeLegal(LoadVT) ||
5579 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5580 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5581 ActuallyDoIt = false;
5585 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5586 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5588 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5590 processIntegerCallValue(I, Res, false);
5599 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5600 /// form. If so, return true and lower it, otherwise return false and it
5601 /// will be lowered like a normal call.
5602 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5603 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5604 if (I.getNumArgOperands() != 3)
5607 const Value *Src = I.getArgOperand(0);
5608 const Value *Char = I.getArgOperand(1);
5609 const Value *Length = I.getArgOperand(2);
5610 if (!Src->getType()->isPointerTy() ||
5611 !Char->getType()->isIntegerTy() ||
5612 !Length->getType()->isIntegerTy() ||
5613 !I.getType()->isPointerTy())
5616 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5617 std::pair<SDValue, SDValue> Res =
5618 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5619 getValue(Src), getValue(Char), getValue(Length),
5620 MachinePointerInfo(Src));
5621 if (Res.first.getNode()) {
5622 setValue(&I, Res.first);
5623 PendingLoads.push_back(Res.second);
5630 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5631 /// optimized form. If so, return true and lower it, otherwise return false
5632 /// and it will be lowered like a normal call.
5633 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5634 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5635 if (I.getNumArgOperands() != 2)
5638 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5639 if (!Arg0->getType()->isPointerTy() ||
5640 !Arg1->getType()->isPointerTy() ||
5641 !I.getType()->isPointerTy())
5644 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5645 std::pair<SDValue, SDValue> Res =
5646 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5647 getValue(Arg0), getValue(Arg1),
5648 MachinePointerInfo(Arg0),
5649 MachinePointerInfo(Arg1), isStpcpy);
5650 if (Res.first.getNode()) {
5651 setValue(&I, Res.first);
5652 DAG.setRoot(Res.second);
5659 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5660 /// If so, return true and lower it, otherwise return false and it will be
5661 /// lowered like a normal call.
5662 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5663 // Verify that the prototype makes sense. int strcmp(void*,void*)
5664 if (I.getNumArgOperands() != 2)
5667 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5668 if (!Arg0->getType()->isPointerTy() ||
5669 !Arg1->getType()->isPointerTy() ||
5670 !I.getType()->isIntegerTy())
5673 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5674 std::pair<SDValue, SDValue> Res =
5675 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5676 getValue(Arg0), getValue(Arg1),
5677 MachinePointerInfo(Arg0),
5678 MachinePointerInfo(Arg1));
5679 if (Res.first.getNode()) {
5680 processIntegerCallValue(I, Res.first, true);
5681 PendingLoads.push_back(Res.second);
5688 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5689 /// form. If so, return true and lower it, otherwise return false and it
5690 /// will be lowered like a normal call.
5691 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5692 // Verify that the prototype makes sense. size_t strlen(char *)
5693 if (I.getNumArgOperands() != 1)
5696 const Value *Arg0 = I.getArgOperand(0);
5697 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5700 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5701 std::pair<SDValue, SDValue> Res =
5702 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5703 getValue(Arg0), MachinePointerInfo(Arg0));
5704 if (Res.first.getNode()) {
5705 processIntegerCallValue(I, Res.first, false);
5706 PendingLoads.push_back(Res.second);
5713 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5714 /// form. If so, return true and lower it, otherwise return false and it
5715 /// will be lowered like a normal call.
5716 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5717 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5718 if (I.getNumArgOperands() != 2)
5721 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5722 if (!Arg0->getType()->isPointerTy() ||
5723 !Arg1->getType()->isIntegerTy() ||
5724 !I.getType()->isIntegerTy())
5727 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5728 std::pair<SDValue, SDValue> Res =
5729 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5730 getValue(Arg0), getValue(Arg1),
5731 MachinePointerInfo(Arg0));
5732 if (Res.first.getNode()) {
5733 processIntegerCallValue(I, Res.first, false);
5734 PendingLoads.push_back(Res.second);
5741 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5742 /// operation (as expected), translate it to an SDNode with the specified opcode
5743 /// and return true.
5744 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5746 // Sanity check that it really is a unary floating-point call.
5747 if (I.getNumArgOperands() != 1 ||
5748 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5749 I.getType() != I.getArgOperand(0)->getType() ||
5750 !I.onlyReadsMemory())
5753 SDValue Tmp = getValue(I.getArgOperand(0));
5754 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5758 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5759 /// operation (as expected), translate it to an SDNode with the specified opcode
5760 /// and return true.
5761 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5763 // Sanity check that it really is a binary floating-point call.
5764 if (I.getNumArgOperands() != 2 ||
5765 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5766 I.getType() != I.getArgOperand(0)->getType() ||
5767 I.getType() != I.getArgOperand(1)->getType() ||
5768 !I.onlyReadsMemory())
5771 SDValue Tmp0 = getValue(I.getArgOperand(0));
5772 SDValue Tmp1 = getValue(I.getArgOperand(1));
5773 EVT VT = Tmp0.getValueType();
5774 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5778 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5779 // Handle inline assembly differently.
5780 if (isa<InlineAsm>(I.getCalledValue())) {
5785 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5786 ComputeUsesVAFloatArgument(I, &MMI);
5788 const char *RenameFn = nullptr;
5789 if (Function *F = I.getCalledFunction()) {
5790 if (F->isDeclaration()) {
5791 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5792 if (unsigned IID = II->getIntrinsicID(F)) {
5793 RenameFn = visitIntrinsicCall(I, IID);
5798 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5799 RenameFn = visitIntrinsicCall(I, IID);
5805 // Check for well-known libc/libm calls. If the function is internal, it
5806 // can't be a library call.
5808 if (!F->hasLocalLinkage() && F->hasName() &&
5809 LibInfo->getLibFunc(F->getName(), Func) &&
5810 LibInfo->hasOptimizedCodeGen(Func)) {
5813 case LibFunc::copysign:
5814 case LibFunc::copysignf:
5815 case LibFunc::copysignl:
5816 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5817 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5818 I.getType() == I.getArgOperand(0)->getType() &&
5819 I.getType() == I.getArgOperand(1)->getType() &&
5820 I.onlyReadsMemory()) {
5821 SDValue LHS = getValue(I.getArgOperand(0));
5822 SDValue RHS = getValue(I.getArgOperand(1));
5823 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5824 LHS.getValueType(), LHS, RHS));
5829 case LibFunc::fabsf:
5830 case LibFunc::fabsl:
5831 if (visitUnaryFloatCall(I, ISD::FABS))
5835 case LibFunc::fminf:
5836 case LibFunc::fminl:
5837 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5841 case LibFunc::fmaxf:
5842 case LibFunc::fmaxl:
5843 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5849 if (visitUnaryFloatCall(I, ISD::FSIN))
5855 if (visitUnaryFloatCall(I, ISD::FCOS))
5859 case LibFunc::sqrtf:
5860 case LibFunc::sqrtl:
5861 case LibFunc::sqrt_finite:
5862 case LibFunc::sqrtf_finite:
5863 case LibFunc::sqrtl_finite:
5864 if (visitUnaryFloatCall(I, ISD::FSQRT))
5867 case LibFunc::floor:
5868 case LibFunc::floorf:
5869 case LibFunc::floorl:
5870 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5873 case LibFunc::nearbyint:
5874 case LibFunc::nearbyintf:
5875 case LibFunc::nearbyintl:
5876 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5880 case LibFunc::ceilf:
5881 case LibFunc::ceill:
5882 if (visitUnaryFloatCall(I, ISD::FCEIL))
5886 case LibFunc::rintf:
5887 case LibFunc::rintl:
5888 if (visitUnaryFloatCall(I, ISD::FRINT))
5891 case LibFunc::round:
5892 case LibFunc::roundf:
5893 case LibFunc::roundl:
5894 if (visitUnaryFloatCall(I, ISD::FROUND))
5897 case LibFunc::trunc:
5898 case LibFunc::truncf:
5899 case LibFunc::truncl:
5900 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5904 case LibFunc::log2f:
5905 case LibFunc::log2l:
5906 if (visitUnaryFloatCall(I, ISD::FLOG2))
5910 case LibFunc::exp2f:
5911 case LibFunc::exp2l:
5912 if (visitUnaryFloatCall(I, ISD::FEXP2))
5915 case LibFunc::memcmp:
5916 if (visitMemCmpCall(I))
5919 case LibFunc::memchr:
5920 if (visitMemChrCall(I))
5923 case LibFunc::strcpy:
5924 if (visitStrCpyCall(I, false))
5927 case LibFunc::stpcpy:
5928 if (visitStrCpyCall(I, true))
5931 case LibFunc::strcmp:
5932 if (visitStrCmpCall(I))
5935 case LibFunc::strlen:
5936 if (visitStrLenCall(I))
5939 case LibFunc::strnlen:
5940 if (visitStrNLenCall(I))
5949 Callee = getValue(I.getCalledValue());
5951 Callee = DAG.getExternalSymbol(
5953 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5955 // Check if we can potentially perform a tail call. More detailed checking is
5956 // be done within LowerCallTo, after more information about the call is known.
5957 LowerCallTo(&I, Callee, I.isTailCall());
5962 /// AsmOperandInfo - This contains information for each constraint that we are
5964 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5966 /// CallOperand - If this is the result output operand or a clobber
5967 /// this is null, otherwise it is the incoming operand to the CallInst.
5968 /// This gets modified as the asm is processed.
5969 SDValue CallOperand;
5971 /// AssignedRegs - If this is a register or register class operand, this
5972 /// contains the set of register corresponding to the operand.
5973 RegsForValue AssignedRegs;
5975 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5976 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5979 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5980 /// corresponds to. If there is no Value* for this operand, it returns
5982 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5983 const DataLayout &DL) const {
5984 if (!CallOperandVal) return MVT::Other;
5986 if (isa<BasicBlock>(CallOperandVal))
5987 return TLI.getPointerTy(DL);
5989 llvm::Type *OpTy = CallOperandVal->getType();
5991 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5992 // If this is an indirect operand, the operand is a pointer to the
5995 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5997 report_fatal_error("Indirect operand for inline asm not a pointer!");
5998 OpTy = PtrTy->getElementType();
6001 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6002 if (StructType *STy = dyn_cast<StructType>(OpTy))
6003 if (STy->getNumElements() == 1)
6004 OpTy = STy->getElementType(0);
6006 // If OpTy is not a single value, it may be a struct/union that we
6007 // can tile with integers.
6008 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6009 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
6018 OpTy = IntegerType::get(Context, BitSize);
6023 return TLI.getValueType(DL, OpTy, true);
6027 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6029 } // end anonymous namespace
6031 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6032 /// specified operand. We prefer to assign virtual registers, to allow the
6033 /// register allocator to handle the assignment process. However, if the asm
6034 /// uses features that we can't model on machineinstrs, we have SDISel do the
6035 /// allocation. This produces generally horrible, but correct, code.
6037 /// OpInfo describes the operand.
6039 static void GetRegistersForValue(SelectionDAG &DAG,
6040 const TargetLowering &TLI,
6042 SDISelAsmOperandInfo &OpInfo) {
6043 LLVMContext &Context = *DAG.getContext();
6045 MachineFunction &MF = DAG.getMachineFunction();
6046 SmallVector<unsigned, 4> Regs;
6048 // If this is a constraint for a single physreg, or a constraint for a
6049 // register class, find it.
6050 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6051 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6052 OpInfo.ConstraintCode,
6053 OpInfo.ConstraintVT);
6055 unsigned NumRegs = 1;
6056 if (OpInfo.ConstraintVT != MVT::Other) {
6057 // If this is a FP input in an integer register (or visa versa) insert a bit
6058 // cast of the input value. More generally, handle any case where the input
6059 // value disagrees with the register class we plan to stick this in.
6060 if (OpInfo.Type == InlineAsm::isInput &&
6061 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6062 // Try to convert to the first EVT that the reg class contains. If the
6063 // types are identical size, use a bitcast to convert (e.g. two differing
6065 MVT RegVT = *PhysReg.second->vt_begin();
6066 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6067 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6068 RegVT, OpInfo.CallOperand);
6069 OpInfo.ConstraintVT = RegVT;
6070 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6071 // If the input is a FP value and we want it in FP registers, do a
6072 // bitcast to the corresponding integer type. This turns an f64 value
6073 // into i64, which can be passed with two i32 values on a 32-bit
6075 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6076 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6077 RegVT, OpInfo.CallOperand);
6078 OpInfo.ConstraintVT = RegVT;
6082 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6086 EVT ValueVT = OpInfo.ConstraintVT;
6088 // If this is a constraint for a specific physical register, like {r17},
6090 if (unsigned AssignedReg = PhysReg.first) {
6091 const TargetRegisterClass *RC = PhysReg.second;
6092 if (OpInfo.ConstraintVT == MVT::Other)
6093 ValueVT = *RC->vt_begin();
6095 // Get the actual register value type. This is important, because the user
6096 // may have asked for (e.g.) the AX register in i32 type. We need to
6097 // remember that AX is actually i16 to get the right extension.
6098 RegVT = *RC->vt_begin();
6100 // This is a explicit reference to a physical register.
6101 Regs.push_back(AssignedReg);
6103 // If this is an expanded reference, add the rest of the regs to Regs.
6105 TargetRegisterClass::iterator I = RC->begin();
6106 for (; *I != AssignedReg; ++I)
6107 assert(I != RC->end() && "Didn't find reg!");
6109 // Already added the first reg.
6111 for (; NumRegs; --NumRegs, ++I) {
6112 assert(I != RC->end() && "Ran out of registers to allocate!");
6117 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6121 // Otherwise, if this was a reference to an LLVM register class, create vregs
6122 // for this reference.
6123 if (const TargetRegisterClass *RC = PhysReg.second) {
6124 RegVT = *RC->vt_begin();
6125 if (OpInfo.ConstraintVT == MVT::Other)
6128 // Create the appropriate number of virtual registers.
6129 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6130 for (; NumRegs; --NumRegs)
6131 Regs.push_back(RegInfo.createVirtualRegister(RC));
6133 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6137 // Otherwise, we couldn't allocate enough registers for this.
6140 /// visitInlineAsm - Handle a call to an InlineAsm object.
6142 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6143 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6145 /// ConstraintOperands - Information about all of the constraints.
6146 SDISelAsmOperandInfoVector ConstraintOperands;
6148 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6149 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6150 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6152 bool hasMemory = false;
6154 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6155 unsigned ResNo = 0; // ResNo - The result number of the next output.
6156 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6157 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6158 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6160 MVT OpVT = MVT::Other;
6162 // Compute the value type for each operand.
6163 switch (OpInfo.Type) {
6164 case InlineAsm::isOutput:
6165 // Indirect outputs just consume an argument.
6166 if (OpInfo.isIndirect) {
6167 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6171 // The return value of the call is this value. As such, there is no
6172 // corresponding argument.
6173 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6174 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6175 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6176 STy->getElementType(ResNo));
6178 assert(ResNo == 0 && "Asm only has one result!");
6179 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6183 case InlineAsm::isInput:
6184 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6186 case InlineAsm::isClobber:
6191 // If this is an input or an indirect output, process the call argument.
6192 // BasicBlocks are labels, currently appearing only in asm's.
6193 if (OpInfo.CallOperandVal) {
6194 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6195 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6197 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6200 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6201 DAG.getDataLayout()).getSimpleVT();
6204 OpInfo.ConstraintVT = OpVT;
6206 // Indirect operand accesses access memory.
6207 if (OpInfo.isIndirect)
6210 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6211 TargetLowering::ConstraintType
6212 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6213 if (CType == TargetLowering::C_Memory) {
6221 SDValue Chain, Flag;
6223 // We won't need to flush pending loads if this asm doesn't touch
6224 // memory and is nonvolatile.
6225 if (hasMemory || IA->hasSideEffects())
6228 Chain = DAG.getRoot();
6230 // Second pass over the constraints: compute which constraint option to use
6231 // and assign registers to constraints that want a specific physreg.
6232 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6233 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6235 // If this is an output operand with a matching input operand, look up the
6236 // matching input. If their types mismatch, e.g. one is an integer, the
6237 // other is floating point, or their sizes are different, flag it as an
6239 if (OpInfo.hasMatchingInput()) {
6240 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6242 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6243 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6244 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6245 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6246 OpInfo.ConstraintVT);
6247 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6248 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6249 Input.ConstraintVT);
6250 if ((OpInfo.ConstraintVT.isInteger() !=
6251 Input.ConstraintVT.isInteger()) ||
6252 (MatchRC.second != InputRC.second)) {
6253 report_fatal_error("Unsupported asm: input constraint"
6254 " with a matching output constraint of"
6255 " incompatible type!");
6257 Input.ConstraintVT = OpInfo.ConstraintVT;
6261 // Compute the constraint code and ConstraintType to use.
6262 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6264 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6265 OpInfo.Type == InlineAsm::isClobber)
6268 // If this is a memory input, and if the operand is not indirect, do what we
6269 // need to to provide an address for the memory input.
6270 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6271 !OpInfo.isIndirect) {
6272 assert((OpInfo.isMultipleAlternative ||
6273 (OpInfo.Type == InlineAsm::isInput)) &&
6274 "Can only indirectify direct input operands!");
6276 // Memory operands really want the address of the value. If we don't have
6277 // an indirect input, put it in the constpool if we can, otherwise spill
6278 // it to a stack slot.
6279 // TODO: This isn't quite right. We need to handle these according to
6280 // the addressing mode that the constraint wants. Also, this may take
6281 // an additional register for the computation and we don't want that
6284 // If the operand is a float, integer, or vector constant, spill to a
6285 // constant pool entry to get its address.
6286 const Value *OpVal = OpInfo.CallOperandVal;
6287 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6288 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6289 OpInfo.CallOperand = DAG.getConstantPool(
6290 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6292 // Otherwise, create a stack slot and emit a store to it before the
6294 Type *Ty = OpVal->getType();
6295 auto &DL = DAG.getDataLayout();
6296 uint64_t TySize = DL.getTypeAllocSize(Ty);
6297 unsigned Align = DL.getPrefTypeAlignment(Ty);
6298 MachineFunction &MF = DAG.getMachineFunction();
6299 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6301 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6302 Chain = DAG.getStore(
6303 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6304 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6306 OpInfo.CallOperand = StackSlot;
6309 // There is no longer a Value* corresponding to this operand.
6310 OpInfo.CallOperandVal = nullptr;
6312 // It is now an indirect operand.
6313 OpInfo.isIndirect = true;
6316 // If this constraint is for a specific register, allocate it before
6318 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6319 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6322 // Second pass - Loop over all of the operands, assigning virtual or physregs
6323 // to register class operands.
6324 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6325 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6327 // C_Register operands have already been allocated, Other/Memory don't need
6329 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6330 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6333 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6334 std::vector<SDValue> AsmNodeOperands;
6335 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6336 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6337 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6339 // If we have a !srcloc metadata node associated with it, we want to attach
6340 // this to the ultimately generated inline asm machineinstr. To do this, we
6341 // pass in the third operand as this (potentially null) inline asm MDNode.
6342 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6343 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6345 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6346 // bits as operand 3.
6347 unsigned ExtraInfo = 0;
6348 if (IA->hasSideEffects())
6349 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6350 if (IA->isAlignStack())
6351 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6352 // Set the asm dialect.
6353 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6355 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6356 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6357 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6359 // Compute the constraint code and ConstraintType to use.
6360 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6362 // Ideally, we would only check against memory constraints. However, the
6363 // meaning of an other constraint can be target-specific and we can't easily
6364 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6365 // for other constriants as well.
6366 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6367 OpInfo.ConstraintType == TargetLowering::C_Other) {
6368 if (OpInfo.Type == InlineAsm::isInput)
6369 ExtraInfo |= InlineAsm::Extra_MayLoad;
6370 else if (OpInfo.Type == InlineAsm::isOutput)
6371 ExtraInfo |= InlineAsm::Extra_MayStore;
6372 else if (OpInfo.Type == InlineAsm::isClobber)
6373 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6377 AsmNodeOperands.push_back(DAG.getTargetConstant(
6378 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6380 // Loop over all of the inputs, copying the operand values into the
6381 // appropriate registers and processing the output regs.
6382 RegsForValue RetValRegs;
6384 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6385 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6387 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6388 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6390 switch (OpInfo.Type) {
6391 case InlineAsm::isOutput: {
6392 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6393 OpInfo.ConstraintType != TargetLowering::C_Register) {
6394 // Memory output, or 'other' output (e.g. 'X' constraint).
6395 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6397 unsigned ConstraintID =
6398 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6399 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6400 "Failed to convert memory constraint code to constraint id.");
6402 // Add information to the INLINEASM node to know about this output.
6403 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6404 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6405 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6407 AsmNodeOperands.push_back(OpInfo.CallOperand);
6411 // Otherwise, this is a register or register class output.
6413 // Copy the output from the appropriate register. Find a register that
6415 if (OpInfo.AssignedRegs.Regs.empty()) {
6416 LLVMContext &Ctx = *DAG.getContext();
6417 Ctx.emitError(CS.getInstruction(),
6418 "couldn't allocate output register for constraint '" +
6419 Twine(OpInfo.ConstraintCode) + "'");
6423 // If this is an indirect operand, store through the pointer after the
6425 if (OpInfo.isIndirect) {
6426 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6427 OpInfo.CallOperandVal));
6429 // This is the result value of the call.
6430 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6431 // Concatenate this output onto the outputs list.
6432 RetValRegs.append(OpInfo.AssignedRegs);
6435 // Add information to the INLINEASM node to know that this register is
6438 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6439 ? InlineAsm::Kind_RegDefEarlyClobber
6440 : InlineAsm::Kind_RegDef,
6441 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6444 case InlineAsm::isInput: {
6445 SDValue InOperandVal = OpInfo.CallOperand;
6447 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6448 // If this is required to match an output register we have already set,
6449 // just use its register.
6450 unsigned OperandNo = OpInfo.getMatchedOperand();
6452 // Scan until we find the definition we already emitted of this operand.
6453 // When we find it, create a RegsForValue operand.
6454 unsigned CurOp = InlineAsm::Op_FirstOperand;
6455 for (; OperandNo; --OperandNo) {
6456 // Advance to the next operand.
6458 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6459 assert((InlineAsm::isRegDefKind(OpFlag) ||
6460 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6461 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6462 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6466 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6467 if (InlineAsm::isRegDefKind(OpFlag) ||
6468 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6469 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6470 if (OpInfo.isIndirect) {
6471 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6472 LLVMContext &Ctx = *DAG.getContext();
6473 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6474 " don't know how to handle tied "
6475 "indirect register inputs");
6479 RegsForValue MatchedRegs;
6480 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6481 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6482 MatchedRegs.RegVTs.push_back(RegVT);
6483 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6484 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6486 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6487 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6489 LLVMContext &Ctx = *DAG.getContext();
6490 Ctx.emitError(CS.getInstruction(),
6491 "inline asm error: This value"
6492 " type register class is not natively supported!");
6496 SDLoc dl = getCurSDLoc();
6497 // Use the produced MatchedRegs object to
6498 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6499 Chain, &Flag, CS.getInstruction());
6500 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6501 true, OpInfo.getMatchedOperand(), dl,
6502 DAG, AsmNodeOperands);
6506 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6507 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6508 "Unexpected number of operands");
6509 // Add information to the INLINEASM node to know about this input.
6510 // See InlineAsm.h isUseOperandTiedToDef.
6511 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6512 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6513 OpInfo.getMatchedOperand());
6514 AsmNodeOperands.push_back(DAG.getTargetConstant(
6515 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6516 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6520 // Treat indirect 'X' constraint as memory.
6521 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6523 OpInfo.ConstraintType = TargetLowering::C_Memory;
6525 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6526 std::vector<SDValue> Ops;
6527 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6530 LLVMContext &Ctx = *DAG.getContext();
6531 Ctx.emitError(CS.getInstruction(),
6532 "invalid operand for inline asm constraint '" +
6533 Twine(OpInfo.ConstraintCode) + "'");
6537 // Add information to the INLINEASM node to know about this input.
6538 unsigned ResOpType =
6539 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6540 AsmNodeOperands.push_back(DAG.getTargetConstant(
6541 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6542 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6546 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6547 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6548 assert(InOperandVal.getValueType() ==
6549 TLI.getPointerTy(DAG.getDataLayout()) &&
6550 "Memory operands expect pointer values");
6552 unsigned ConstraintID =
6553 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6554 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6555 "Failed to convert memory constraint code to constraint id.");
6557 // Add information to the INLINEASM node to know about this input.
6558 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6559 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6560 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6563 AsmNodeOperands.push_back(InOperandVal);
6567 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6568 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6569 "Unknown constraint type!");
6571 // TODO: Support this.
6572 if (OpInfo.isIndirect) {
6573 LLVMContext &Ctx = *DAG.getContext();
6574 Ctx.emitError(CS.getInstruction(),
6575 "Don't know how to handle indirect register inputs yet "
6576 "for constraint '" +
6577 Twine(OpInfo.ConstraintCode) + "'");
6581 // Copy the input into the appropriate registers.
6582 if (OpInfo.AssignedRegs.Regs.empty()) {
6583 LLVMContext &Ctx = *DAG.getContext();
6584 Ctx.emitError(CS.getInstruction(),
6585 "couldn't allocate input reg for constraint '" +
6586 Twine(OpInfo.ConstraintCode) + "'");
6590 SDLoc dl = getCurSDLoc();
6592 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6593 Chain, &Flag, CS.getInstruction());
6595 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6596 dl, DAG, AsmNodeOperands);
6599 case InlineAsm::isClobber: {
6600 // Add the clobbered value to the operand list, so that the register
6601 // allocator is aware that the physreg got clobbered.
6602 if (!OpInfo.AssignedRegs.Regs.empty())
6603 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6604 false, 0, getCurSDLoc(), DAG,
6611 // Finish up input operands. Set the input chain and add the flag last.
6612 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6613 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6615 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6616 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6617 Flag = Chain.getValue(1);
6619 // If this asm returns a register value, copy the result from that register
6620 // and set it as the value of the call.
6621 if (!RetValRegs.Regs.empty()) {
6622 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6623 Chain, &Flag, CS.getInstruction());
6625 // FIXME: Why don't we do this for inline asms with MRVs?
6626 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6627 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6629 // If any of the results of the inline asm is a vector, it may have the
6630 // wrong width/num elts. This can happen for register classes that can
6631 // contain multiple different value types. The preg or vreg allocated may
6632 // not have the same VT as was expected. Convert it to the right type
6633 // with bit_convert.
6634 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6635 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6638 } else if (ResultType != Val.getValueType() &&
6639 ResultType.isInteger() && Val.getValueType().isInteger()) {
6640 // If a result value was tied to an input value, the computed result may
6641 // have a wider width than the expected result. Extract the relevant
6643 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6646 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6649 setValue(CS.getInstruction(), Val);
6650 // Don't need to use this as a chain in this case.
6651 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6655 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6657 // Process indirect outputs, first output all of the flagged copies out of
6659 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6660 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6661 const Value *Ptr = IndirectStoresToEmit[i].second;
6662 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6664 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6667 // Emit the non-flagged stores from the physregs.
6668 SmallVector<SDValue, 8> OutChains;
6669 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6670 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6671 StoresToEmit[i].first,
6672 getValue(StoresToEmit[i].second),
6673 MachinePointerInfo(StoresToEmit[i].second),
6675 OutChains.push_back(Val);
6678 if (!OutChains.empty())
6679 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6684 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6685 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6686 MVT::Other, getRoot(),
6687 getValue(I.getArgOperand(0)),
6688 DAG.getSrcValue(I.getArgOperand(0))));
6691 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6692 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6693 const DataLayout &DL = DAG.getDataLayout();
6694 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6695 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6696 DAG.getSrcValue(I.getOperand(0)),
6697 DL.getABITypeAlignment(I.getType()));
6699 DAG.setRoot(V.getValue(1));
6702 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6703 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6704 MVT::Other, getRoot(),
6705 getValue(I.getArgOperand(0)),
6706 DAG.getSrcValue(I.getArgOperand(0))));
6709 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6710 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6711 MVT::Other, getRoot(),
6712 getValue(I.getArgOperand(0)),
6713 getValue(I.getArgOperand(1)),
6714 DAG.getSrcValue(I.getArgOperand(0)),
6715 DAG.getSrcValue(I.getArgOperand(1))));
6718 /// \brief Lower an argument list according to the target calling convention.
6720 /// \return A tuple of <return-value, token-chain>
6722 /// This is a helper for lowering intrinsics that follow a target calling
6723 /// convention or require stack pointer adjustment. Only a subset of the
6724 /// intrinsic's operands need to participate in the calling convention.
6725 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6726 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6727 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6728 TargetLowering::ArgListTy Args;
6729 Args.reserve(NumArgs);
6731 // Populate the argument list.
6732 // Attributes for args start at offset 1, after the return attribute.
6733 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6734 ArgI != ArgE; ++ArgI) {
6735 const Value *V = CS->getOperand(ArgI);
6737 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6739 TargetLowering::ArgListEntry Entry;
6740 Entry.Node = getValue(V);
6741 Entry.Ty = V->getType();
6742 Entry.setAttributes(&CS, AttrI);
6743 Args.push_back(Entry);
6746 TargetLowering::CallLoweringInfo CLI(DAG);
6747 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6748 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6749 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6751 return lowerInvokable(CLI, EHPadBB);
6754 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6755 /// or patchpoint target node's operand list.
6757 /// Constants are converted to TargetConstants purely as an optimization to
6758 /// avoid constant materialization and register allocation.
6760 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6761 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6762 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6763 /// address materialization and register allocation, but may also be required
6764 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6765 /// alloca in the entry block, then the runtime may assume that the alloca's
6766 /// StackMap location can be read immediately after compilation and that the
6767 /// location is valid at any point during execution (this is similar to the
6768 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6769 /// only available in a register, then the runtime would need to trap when
6770 /// execution reaches the StackMap in order to read the alloca's location.
6771 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6772 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6773 SelectionDAGBuilder &Builder) {
6774 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6775 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6776 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6778 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6780 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6781 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6782 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6783 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6784 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6786 Ops.push_back(OpVal);
6790 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6791 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6792 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6793 // [live variables...])
6795 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6797 SDValue Chain, InFlag, Callee, NullPtr;
6798 SmallVector<SDValue, 32> Ops;
6800 SDLoc DL = getCurSDLoc();
6801 Callee = getValue(CI.getCalledValue());
6802 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6804 // The stackmap intrinsic only records the live variables (the arguemnts
6805 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6806 // intrinsic, this won't be lowered to a function call. This means we don't
6807 // have to worry about calling conventions and target specific lowering code.
6808 // Instead we perform the call lowering right here.
6810 // chain, flag = CALLSEQ_START(chain, 0)
6811 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6812 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6814 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6815 InFlag = Chain.getValue(1);
6817 // Add the <id> and <numBytes> constants.
6818 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6819 Ops.push_back(DAG.getTargetConstant(
6820 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6821 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6822 Ops.push_back(DAG.getTargetConstant(
6823 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6826 // Push live variables for the stack map.
6827 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6829 // We are not pushing any register mask info here on the operands list,
6830 // because the stackmap doesn't clobber anything.
6832 // Push the chain and the glue flag.
6833 Ops.push_back(Chain);
6834 Ops.push_back(InFlag);
6836 // Create the STACKMAP node.
6837 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6838 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6839 Chain = SDValue(SM, 0);
6840 InFlag = Chain.getValue(1);
6842 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6844 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6846 // Set the root to the target-lowered call chain.
6849 // Inform the Frame Information that we have a stackmap in this function.
6850 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6853 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6854 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6855 const BasicBlock *EHPadBB) {
6856 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6861 // [live variables...])
6863 CallingConv::ID CC = CS.getCallingConv();
6864 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6865 bool HasDef = !CS->getType()->isVoidTy();
6866 SDLoc dl = getCurSDLoc();
6867 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6869 // Handle immediate and symbolic callees.
6870 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6871 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6873 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6874 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6875 SDLoc(SymbolicCallee),
6876 SymbolicCallee->getValueType(0));
6878 // Get the real number of arguments participating in the call <numArgs>
6879 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6880 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6882 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6883 // Intrinsics include all meta-operands up to but not including CC.
6884 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6885 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6886 "Not enough arguments provided to the patchpoint intrinsic");
6888 // For AnyRegCC the arguments are lowered later on manually.
6889 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6891 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6892 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6893 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6895 SDNode *CallEnd = Result.second.getNode();
6896 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6897 CallEnd = CallEnd->getOperand(0).getNode();
6899 /// Get a call instruction from the call sequence chain.
6900 /// Tail calls are not allowed.
6901 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6902 "Expected a callseq node.");
6903 SDNode *Call = CallEnd->getOperand(0).getNode();
6904 bool HasGlue = Call->getGluedNode();
6906 // Replace the target specific call node with the patchable intrinsic.
6907 SmallVector<SDValue, 8> Ops;
6909 // Add the <id> and <numBytes> constants.
6910 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6911 Ops.push_back(DAG.getTargetConstant(
6912 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6913 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6914 Ops.push_back(DAG.getTargetConstant(
6915 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6919 Ops.push_back(Callee);
6921 // Adjust <numArgs> to account for any arguments that have been passed on the
6923 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6924 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6925 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6926 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6928 // Add the calling convention
6929 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6931 // Add the arguments we omitted previously. The register allocator should
6932 // place these in any free register.
6934 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6935 Ops.push_back(getValue(CS.getArgument(i)));
6937 // Push the arguments from the call instruction up to the register mask.
6938 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6939 Ops.append(Call->op_begin() + 2, e);
6941 // Push live variables for the stack map.
6942 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6944 // Push the register mask info.
6946 Ops.push_back(*(Call->op_end()-2));
6948 Ops.push_back(*(Call->op_end()-1));
6950 // Push the chain (this is originally the first operand of the call, but
6951 // becomes now the last or second to last operand).
6952 Ops.push_back(*(Call->op_begin()));
6954 // Push the glue flag (last operand).
6956 Ops.push_back(*(Call->op_end()-1));
6959 if (IsAnyRegCC && HasDef) {
6960 // Create the return types based on the intrinsic definition
6961 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6962 SmallVector<EVT, 3> ValueVTs;
6963 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6964 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6966 // There is always a chain and a glue type at the end
6967 ValueVTs.push_back(MVT::Other);
6968 ValueVTs.push_back(MVT::Glue);
6969 NodeTys = DAG.getVTList(ValueVTs);
6971 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6973 // Replace the target specific call node with a PATCHPOINT node.
6974 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6977 // Update the NodeMap.
6980 setValue(CS.getInstruction(), SDValue(MN, 0));
6982 setValue(CS.getInstruction(), Result.first);
6985 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6986 // call sequence. Furthermore the location of the chain and glue can change
6987 // when the AnyReg calling convention is used and the intrinsic returns a
6989 if (IsAnyRegCC && HasDef) {
6990 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6991 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6992 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6994 DAG.ReplaceAllUsesWith(Call, MN);
6995 DAG.DeleteNode(Call);
6997 // Inform the Frame Information that we have a patchpoint in this function.
6998 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7001 /// Returns an AttributeSet representing the attributes applied to the return
7002 /// value of the given call.
7003 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7004 SmallVector<Attribute::AttrKind, 2> Attrs;
7006 Attrs.push_back(Attribute::SExt);
7008 Attrs.push_back(Attribute::ZExt);
7010 Attrs.push_back(Attribute::InReg);
7012 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7016 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7017 /// implementation, which just calls LowerCall.
7018 /// FIXME: When all targets are
7019 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7020 std::pair<SDValue, SDValue>
7021 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7022 // Handle the incoming return values from the call.
7024 Type *OrigRetTy = CLI.RetTy;
7025 SmallVector<EVT, 4> RetTys;
7026 SmallVector<uint64_t, 4> Offsets;
7027 auto &DL = CLI.DAG.getDataLayout();
7028 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
7030 SmallVector<ISD::OutputArg, 4> Outs;
7031 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
7033 bool CanLowerReturn =
7034 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7035 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7037 SDValue DemoteStackSlot;
7038 int DemoteStackIdx = -100;
7039 if (!CanLowerReturn) {
7040 // FIXME: equivalent assert?
7041 // assert(!CS.hasInAllocaArgument() &&
7042 // "sret demotion is incompatible with inalloca");
7043 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7044 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7045 MachineFunction &MF = CLI.DAG.getMachineFunction();
7046 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7047 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7049 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7051 Entry.Node = DemoteStackSlot;
7052 Entry.Ty = StackSlotPtrType;
7053 Entry.isSExt = false;
7054 Entry.isZExt = false;
7055 Entry.isInReg = false;
7056 Entry.isSRet = true;
7057 Entry.isNest = false;
7058 Entry.isByVal = false;
7059 Entry.isReturned = false;
7060 Entry.Alignment = Align;
7061 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7062 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7064 // sret demotion isn't compatible with tail-calls, since the sret argument
7065 // points into the callers stack frame.
7066 CLI.IsTailCall = false;
7068 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7070 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7071 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7072 for (unsigned i = 0; i != NumRegs; ++i) {
7073 ISD::InputArg MyFlags;
7074 MyFlags.VT = RegisterVT;
7076 MyFlags.Used = CLI.IsReturnValueUsed;
7078 MyFlags.Flags.setSExt();
7080 MyFlags.Flags.setZExt();
7082 MyFlags.Flags.setInReg();
7083 CLI.Ins.push_back(MyFlags);
7088 // Handle all of the outgoing arguments.
7090 CLI.OutVals.clear();
7091 ArgListTy &Args = CLI.getArgs();
7092 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7093 SmallVector<EVT, 4> ValueVTs;
7094 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7095 Type *FinalType = Args[i].Ty;
7096 if (Args[i].isByVal)
7097 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7098 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7099 FinalType, CLI.CallConv, CLI.IsVarArg);
7100 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7102 EVT VT = ValueVTs[Value];
7103 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7104 SDValue Op = SDValue(Args[i].Node.getNode(),
7105 Args[i].Node.getResNo() + Value);
7106 ISD::ArgFlagsTy Flags;
7107 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7113 if (Args[i].isInReg)
7117 if (Args[i].isByVal)
7119 if (Args[i].isInAlloca) {
7120 Flags.setInAlloca();
7121 // Set the byval flag for CCAssignFn callbacks that don't know about
7122 // inalloca. This way we can know how many bytes we should've allocated
7123 // and how many bytes a callee cleanup function will pop. If we port
7124 // inalloca to more targets, we'll have to add custom inalloca handling
7125 // in the various CC lowering callbacks.
7128 if (Args[i].isByVal || Args[i].isInAlloca) {
7129 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7130 Type *ElementTy = Ty->getElementType();
7131 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7132 // For ByVal, alignment should come from FE. BE will guess if this
7133 // info is not there but there are cases it cannot get right.
7134 unsigned FrameAlign;
7135 if (Args[i].Alignment)
7136 FrameAlign = Args[i].Alignment;
7138 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7139 Flags.setByValAlign(FrameAlign);
7144 Flags.setInConsecutiveRegs();
7145 Flags.setOrigAlign(OriginalAlignment);
7147 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7148 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7149 SmallVector<SDValue, 4> Parts(NumParts);
7150 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7153 ExtendKind = ISD::SIGN_EXTEND;
7154 else if (Args[i].isZExt)
7155 ExtendKind = ISD::ZERO_EXTEND;
7157 // Conservatively only handle 'returned' on non-vectors for now
7158 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7159 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7160 "unexpected use of 'returned'");
7161 // Before passing 'returned' to the target lowering code, ensure that
7162 // either the register MVT and the actual EVT are the same size or that
7163 // the return value and argument are extended in the same way; in these
7164 // cases it's safe to pass the argument register value unchanged as the
7165 // return register value (although it's at the target's option whether
7167 // TODO: allow code generation to take advantage of partially preserved
7168 // registers rather than clobbering the entire register when the
7169 // parameter extension method is not compatible with the return
7171 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7172 (ExtendKind != ISD::ANY_EXTEND &&
7173 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7174 Flags.setReturned();
7177 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7178 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7180 for (unsigned j = 0; j != NumParts; ++j) {
7181 // if it isn't first piece, alignment must be 1
7182 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7183 i < CLI.NumFixedArgs,
7184 i, j*Parts[j].getValueType().getStoreSize());
7185 if (NumParts > 1 && j == 0)
7186 MyFlags.Flags.setSplit();
7188 MyFlags.Flags.setOrigAlign(1);
7189 if (j == NumParts - 1)
7190 MyFlags.Flags.setSplitEnd();
7193 CLI.Outs.push_back(MyFlags);
7194 CLI.OutVals.push_back(Parts[j]);
7197 if (NeedsRegBlock && Value == NumValues - 1)
7198 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7202 SmallVector<SDValue, 4> InVals;
7203 CLI.Chain = LowerCall(CLI, InVals);
7205 // Verify that the target's LowerCall behaved as expected.
7206 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7207 "LowerCall didn't return a valid chain!");
7208 assert((!CLI.IsTailCall || InVals.empty()) &&
7209 "LowerCall emitted a return value for a tail call!");
7210 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7211 "LowerCall didn't emit the correct number of values!");
7213 // For a tail call, the return value is merely live-out and there aren't
7214 // any nodes in the DAG representing it. Return a special value to
7215 // indicate that a tail call has been emitted and no more Instructions
7216 // should be processed in the current block.
7217 if (CLI.IsTailCall) {
7218 CLI.DAG.setRoot(CLI.Chain);
7219 return std::make_pair(SDValue(), SDValue());
7222 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7223 assert(InVals[i].getNode() &&
7224 "LowerCall emitted a null value!");
7225 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7226 "LowerCall emitted a value with the wrong type!");
7229 SmallVector<SDValue, 4> ReturnValues;
7230 if (!CanLowerReturn) {
7231 // The instruction result is the result of loading from the
7232 // hidden sret parameter.
7233 SmallVector<EVT, 1> PVTs;
7234 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7236 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7237 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7238 EVT PtrVT = PVTs[0];
7240 unsigned NumValues = RetTys.size();
7241 ReturnValues.resize(NumValues);
7242 SmallVector<SDValue, 4> Chains(NumValues);
7244 // An aggregate return value cannot wrap around the address space, so
7245 // offsets to its parts don't wrap either.
7247 Flags.setNoUnsignedWrap(true);
7249 for (unsigned i = 0; i < NumValues; ++i) {
7250 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7251 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7253 SDValue L = CLI.DAG.getLoad(
7254 RetTys[i], CLI.DL, CLI.Chain, Add,
7255 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7256 DemoteStackIdx, Offsets[i]),
7257 false, false, false, 1);
7258 ReturnValues[i] = L;
7259 Chains[i] = L.getValue(1);
7262 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7264 // Collect the legal value parts into potentially illegal values
7265 // that correspond to the original function's return values.
7266 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7268 AssertOp = ISD::AssertSext;
7269 else if (CLI.RetZExt)
7270 AssertOp = ISD::AssertZext;
7271 unsigned CurReg = 0;
7272 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7274 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7275 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7277 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7278 NumRegs, RegisterVT, VT, nullptr,
7283 // For a function returning void, there is no return value. We can't create
7284 // such a node, so we just return a null return value in that case. In
7285 // that case, nothing will actually look at the value.
7286 if (ReturnValues.empty())
7287 return std::make_pair(SDValue(), CLI.Chain);
7290 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7291 CLI.DAG.getVTList(RetTys), ReturnValues);
7292 return std::make_pair(Res, CLI.Chain);
7295 void TargetLowering::LowerOperationWrapper(SDNode *N,
7296 SmallVectorImpl<SDValue> &Results,
7297 SelectionDAG &DAG) const {
7298 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7300 Results.push_back(Res);
7303 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7304 llvm_unreachable("LowerOperation not implemented for this target!");
7308 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7309 SDValue Op = getNonRegisterValue(V);
7310 assert((Op.getOpcode() != ISD::CopyFromReg ||
7311 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7312 "Copy from a reg to the same reg!");
7313 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7316 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7318 SDValue Chain = DAG.getEntryNode();
7320 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7321 FuncInfo.PreferredExtendType.end())
7323 : FuncInfo.PreferredExtendType[V];
7324 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7325 PendingExports.push_back(Chain);
7328 #include "llvm/CodeGen/SelectionDAGISel.h"
7330 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7331 /// entry block, return true. This includes arguments used by switches, since
7332 /// the switch may expand into multiple basic blocks.
7333 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7334 // With FastISel active, we may be splitting blocks, so force creation
7335 // of virtual registers for all non-dead arguments.
7337 return A->use_empty();
7339 const BasicBlock &Entry = A->getParent()->front();
7340 for (const User *U : A->users())
7341 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7342 return false; // Use not in entry block.
7347 void SelectionDAGISel::LowerArguments(const Function &F) {
7348 SelectionDAG &DAG = SDB->DAG;
7349 SDLoc dl = SDB->getCurSDLoc();
7350 const DataLayout &DL = DAG.getDataLayout();
7351 SmallVector<ISD::InputArg, 16> Ins;
7353 if (!FuncInfo->CanLowerReturn) {
7354 // Put in an sret pointer parameter before all the other parameters.
7355 SmallVector<EVT, 1> ValueVTs;
7356 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7357 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7359 // NOTE: Assuming that a pointer will never break down to more than one VT
7361 ISD::ArgFlagsTy Flags;
7363 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7364 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7365 ISD::InputArg::NoArgIndex, 0);
7366 Ins.push_back(RetArg);
7369 // Set up the incoming argument description vector.
7371 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7372 I != E; ++I, ++Idx) {
7373 SmallVector<EVT, 4> ValueVTs;
7374 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7375 bool isArgValueUsed = !I->use_empty();
7376 unsigned PartBase = 0;
7377 Type *FinalType = I->getType();
7378 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7379 FinalType = cast<PointerType>(FinalType)->getElementType();
7380 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7381 FinalType, F.getCallingConv(), F.isVarArg());
7382 for (unsigned Value = 0, NumValues = ValueVTs.size();
7383 Value != NumValues; ++Value) {
7384 EVT VT = ValueVTs[Value];
7385 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7386 ISD::ArgFlagsTy Flags;
7387 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7389 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7391 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7393 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7395 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7397 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7399 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7400 Flags.setInAlloca();
7401 // Set the byval flag for CCAssignFn callbacks that don't know about
7402 // inalloca. This way we can know how many bytes we should've allocated
7403 // and how many bytes a callee cleanup function will pop. If we port
7404 // inalloca to more targets, we'll have to add custom inalloca handling
7405 // in the various CC lowering callbacks.
7408 if (F.getCallingConv() == CallingConv::X86_INTR) {
7409 // IA Interrupt passes frame (1st parameter) by value in the stack.
7413 if (Flags.isByVal() || Flags.isInAlloca()) {
7414 PointerType *Ty = cast<PointerType>(I->getType());
7415 Type *ElementTy = Ty->getElementType();
7416 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7417 // For ByVal, alignment should be passed from FE. BE will guess if
7418 // this info is not there but there are cases it cannot get right.
7419 unsigned FrameAlign;
7420 if (F.getParamAlignment(Idx))
7421 FrameAlign = F.getParamAlignment(Idx);
7423 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7424 Flags.setByValAlign(FrameAlign);
7426 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7429 Flags.setInConsecutiveRegs();
7430 Flags.setOrigAlign(OriginalAlignment);
7432 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7433 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7434 for (unsigned i = 0; i != NumRegs; ++i) {
7435 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7436 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7437 if (NumRegs > 1 && i == 0)
7438 MyFlags.Flags.setSplit();
7439 // if it isn't first piece, alignment must be 1
7441 MyFlags.Flags.setOrigAlign(1);
7442 if (i == NumRegs - 1)
7443 MyFlags.Flags.setSplitEnd();
7445 Ins.push_back(MyFlags);
7447 if (NeedsRegBlock && Value == NumValues - 1)
7448 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7449 PartBase += VT.getStoreSize();
7453 // Call the target to set up the argument values.
7454 SmallVector<SDValue, 8> InVals;
7455 SDValue NewRoot = TLI->LowerFormalArguments(
7456 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7458 // Verify that the target's LowerFormalArguments behaved as expected.
7459 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7460 "LowerFormalArguments didn't return a valid chain!");
7461 assert(InVals.size() == Ins.size() &&
7462 "LowerFormalArguments didn't emit the correct number of values!");
7464 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7465 assert(InVals[i].getNode() &&
7466 "LowerFormalArguments emitted a null value!");
7467 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7468 "LowerFormalArguments emitted a value with the wrong type!");
7472 // Update the DAG with the new chain value resulting from argument lowering.
7473 DAG.setRoot(NewRoot);
7475 // Set up the argument values.
7478 if (!FuncInfo->CanLowerReturn) {
7479 // Create a virtual register for the sret pointer, and put in a copy
7480 // from the sret argument into it.
7481 SmallVector<EVT, 1> ValueVTs;
7482 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7483 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7484 MVT VT = ValueVTs[0].getSimpleVT();
7485 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7486 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7487 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7488 RegVT, VT, nullptr, AssertOp);
7490 MachineFunction& MF = SDB->DAG.getMachineFunction();
7491 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7492 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7493 FuncInfo->DemoteRegister = SRetReg;
7495 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7496 DAG.setRoot(NewRoot);
7498 // i indexes lowered arguments. Bump it past the hidden sret argument.
7499 // Idx indexes LLVM arguments. Don't touch it.
7503 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7505 SmallVector<SDValue, 4> ArgValues;
7506 SmallVector<EVT, 4> ValueVTs;
7507 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7508 unsigned NumValues = ValueVTs.size();
7510 // If this argument is unused then remember its value. It is used to generate
7511 // debugging information.
7512 if (I->use_empty() && NumValues) {
7513 SDB->setUnusedArgValue(&*I, InVals[i]);
7515 // Also remember any frame index for use in FastISel.
7516 if (FrameIndexSDNode *FI =
7517 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7518 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7521 for (unsigned Val = 0; Val != NumValues; ++Val) {
7522 EVT VT = ValueVTs[Val];
7523 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7524 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7526 if (!I->use_empty()) {
7527 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7528 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7529 AssertOp = ISD::AssertSext;
7530 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7531 AssertOp = ISD::AssertZext;
7533 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7534 NumParts, PartVT, VT,
7535 nullptr, AssertOp));
7541 // We don't need to do anything else for unused arguments.
7542 if (ArgValues.empty())
7545 // Note down frame index.
7546 if (FrameIndexSDNode *FI =
7547 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7548 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7550 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7551 SDB->getCurSDLoc());
7553 SDB->setValue(&*I, Res);
7554 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7555 if (LoadSDNode *LNode =
7556 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7557 if (FrameIndexSDNode *FI =
7558 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7559 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7562 // If this argument is live outside of the entry block, insert a copy from
7563 // wherever we got it to the vreg that other BB's will reference it as.
7564 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7565 // If we can, though, try to skip creating an unnecessary vreg.
7566 // FIXME: This isn't very clean... it would be nice to make this more
7567 // general. It's also subtly incompatible with the hacks FastISel
7569 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7570 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7571 FuncInfo->ValueMap[&*I] = Reg;
7575 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
7576 FuncInfo->InitializeRegForValue(&*I);
7577 SDB->CopyToExportRegsIfNeeded(&*I);
7581 assert(i == InVals.size() && "Argument register count mismatch!");
7583 // Finally, if the target has anything special to do, allow it to do so.
7584 EmitFunctionEntryCode();
7587 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7588 /// ensure constants are generated when needed. Remember the virtual registers
7589 /// that need to be added to the Machine PHI nodes as input. We cannot just
7590 /// directly add them, because expansion might result in multiple MBB's for one
7591 /// BB. As such, the start of the BB might correspond to a different MBB than
7595 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7596 const TerminatorInst *TI = LLVMBB->getTerminator();
7598 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7600 // Check PHI nodes in successors that expect a value to be available from this
7602 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7603 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7604 if (!isa<PHINode>(SuccBB->begin())) continue;
7605 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7607 // If this terminator has multiple identical successors (common for
7608 // switches), only handle each succ once.
7609 if (!SuccsHandled.insert(SuccMBB).second)
7612 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7614 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7615 // nodes and Machine PHI nodes, but the incoming operands have not been
7617 for (BasicBlock::const_iterator I = SuccBB->begin();
7618 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7619 // Ignore dead phi's.
7620 if (PN->use_empty()) continue;
7623 if (PN->getType()->isEmptyTy())
7627 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7629 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7630 unsigned &RegOut = ConstantsOut[C];
7632 RegOut = FuncInfo.CreateRegs(C->getType());
7633 CopyValueToVirtualRegister(C, RegOut);
7637 DenseMap<const Value *, unsigned>::iterator I =
7638 FuncInfo.ValueMap.find(PHIOp);
7639 if (I != FuncInfo.ValueMap.end())
7642 assert(isa<AllocaInst>(PHIOp) &&
7643 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7644 "Didn't codegen value into a register!??");
7645 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7646 CopyValueToVirtualRegister(PHIOp, Reg);
7650 // Remember that this register needs to added to the machine PHI node as
7651 // the input for this MBB.
7652 SmallVector<EVT, 4> ValueVTs;
7653 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7654 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7655 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7656 EVT VT = ValueVTs[vti];
7657 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7658 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7659 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7660 Reg += NumRegisters;
7665 ConstantsOut.clear();
7668 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7671 SelectionDAGBuilder::StackProtectorDescriptor::
7672 AddSuccessorMBB(const BasicBlock *BB,
7673 MachineBasicBlock *ParentMBB,
7675 MachineBasicBlock *SuccMBB) {
7676 // If SuccBB has not been created yet, create it.
7678 MachineFunction *MF = ParentMBB->getParent();
7679 MachineFunction::iterator BBI(ParentMBB);
7680 SuccMBB = MF->CreateMachineBasicBlock(BB);
7681 MF->insert(++BBI, SuccMBB);
7683 // Add it as a successor of ParentMBB.
7684 ParentMBB->addSuccessor(
7685 SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
7689 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7690 MachineFunction::iterator I(MBB);
7691 if (++I == FuncInfo.MF->end())
7696 /// During lowering new call nodes can be created (such as memset, etc.).
7697 /// Those will become new roots of the current DAG, but complications arise
7698 /// when they are tail calls. In such cases, the call lowering will update
7699 /// the root, but the builder still needs to know that a tail call has been
7700 /// lowered in order to avoid generating an additional return.
7701 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7702 // If the node is null, we do have a tail call.
7703 if (MaybeTC.getNode() != nullptr)
7704 DAG.setRoot(MaybeTC);
7709 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7710 unsigned *TotalCases, unsigned First,
7712 assert(Last >= First);
7713 assert(TotalCases[Last] >= TotalCases[First]);
7715 APInt LowCase = Clusters[First].Low->getValue();
7716 APInt HighCase = Clusters[Last].High->getValue();
7717 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7719 // FIXME: A range of consecutive cases has 100% density, but only requires one
7720 // comparison to lower. We should discriminate against such consecutive ranges
7723 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7724 uint64_t Range = Diff + 1;
7727 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7729 assert(NumCases < UINT64_MAX / 100);
7730 assert(Range >= NumCases);
7732 return NumCases * 100 >= Range * MinJumpTableDensity;
7735 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7736 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7737 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7740 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7741 unsigned First, unsigned Last,
7742 const SwitchInst *SI,
7743 MachineBasicBlock *DefaultMBB,
7744 CaseCluster &JTCluster) {
7745 assert(First <= Last);
7747 auto Prob = BranchProbability::getZero();
7748 unsigned NumCmps = 0;
7749 std::vector<MachineBasicBlock*> Table;
7750 DenseMap<MachineBasicBlock*, BranchProbability> JTProbs;
7752 // Initialize probabilities in JTProbs.
7753 for (unsigned I = First; I <= Last; ++I)
7754 JTProbs[Clusters[I].MBB] = BranchProbability::getZero();
7756 for (unsigned I = First; I <= Last; ++I) {
7757 assert(Clusters[I].Kind == CC_Range);
7758 Prob += Clusters[I].Prob;
7759 APInt Low = Clusters[I].Low->getValue();
7760 APInt High = Clusters[I].High->getValue();
7761 NumCmps += (Low == High) ? 1 : 2;
7763 // Fill the gap between this and the previous cluster.
7764 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7765 assert(PreviousHigh.slt(Low));
7766 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7767 for (uint64_t J = 0; J < Gap; J++)
7768 Table.push_back(DefaultMBB);
7770 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7771 for (uint64_t J = 0; J < ClusterSize; ++J)
7772 Table.push_back(Clusters[I].MBB);
7773 JTProbs[Clusters[I].MBB] += Clusters[I].Prob;
7776 unsigned NumDests = JTProbs.size();
7777 if (isSuitableForBitTests(NumDests, NumCmps,
7778 Clusters[First].Low->getValue(),
7779 Clusters[Last].High->getValue())) {
7780 // Clusters[First..Last] should be lowered as bit tests instead.
7784 // Create the MBB that will load from and jump through the table.
7785 // Note: We create it here, but it's not inserted into the function yet.
7786 MachineFunction *CurMF = FuncInfo.MF;
7787 MachineBasicBlock *JumpTableMBB =
7788 CurMF->CreateMachineBasicBlock(SI->getParent());
7790 // Add successors. Note: use table order for determinism.
7791 SmallPtrSet<MachineBasicBlock *, 8> Done;
7792 for (MachineBasicBlock *Succ : Table) {
7793 if (Done.count(Succ))
7795 addSuccessorWithProb(JumpTableMBB, Succ, JTProbs[Succ]);
7798 JumpTableMBB->normalizeSuccProbs();
7800 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7801 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7802 ->createJumpTableIndex(Table);
7804 // Set up the jump table info.
7805 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7806 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7807 Clusters[Last].High->getValue(), SI->getCondition(),
7809 JTCases.emplace_back(std::move(JTH), std::move(JT));
7811 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7812 JTCases.size() - 1, Prob);
7816 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7817 const SwitchInst *SI,
7818 MachineBasicBlock *DefaultMBB) {
7820 // Clusters must be non-empty, sorted, and only contain Range clusters.
7821 assert(!Clusters.empty());
7822 for (CaseCluster &C : Clusters)
7823 assert(C.Kind == CC_Range);
7824 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7825 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7828 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7829 if (!areJTsAllowed(TLI))
7832 const int64_t N = Clusters.size();
7833 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7835 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7836 SmallVector<unsigned, 8> TotalCases(N);
7838 for (unsigned i = 0; i < N; ++i) {
7839 APInt Hi = Clusters[i].High->getValue();
7840 APInt Lo = Clusters[i].Low->getValue();
7841 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7843 TotalCases[i] += TotalCases[i - 1];
7846 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7847 // Cheap case: the whole range might be suitable for jump table.
7848 CaseCluster JTCluster;
7849 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7850 Clusters[0] = JTCluster;
7856 // The algorithm below is not suitable for -O0.
7857 if (TM.getOptLevel() == CodeGenOpt::None)
7860 // Split Clusters into minimum number of dense partitions. The algorithm uses
7861 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7862 // for the Case Statement'" (1994), but builds the MinPartitions array in
7863 // reverse order to make it easier to reconstruct the partitions in ascending
7864 // order. In the choice between two optimal partitionings, it picks the one
7865 // which yields more jump tables.
7867 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7868 SmallVector<unsigned, 8> MinPartitions(N);
7869 // LastElement[i] is the last element of the partition starting at i.
7870 SmallVector<unsigned, 8> LastElement(N);
7871 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7872 SmallVector<unsigned, 8> NumTables(N);
7874 // Base case: There is only one way to partition Clusters[N-1].
7875 MinPartitions[N - 1] = 1;
7876 LastElement[N - 1] = N - 1;
7877 assert(MinJumpTableSize > 1);
7878 NumTables[N - 1] = 0;
7880 // Note: loop indexes are signed to avoid underflow.
7881 for (int64_t i = N - 2; i >= 0; i--) {
7882 // Find optimal partitioning of Clusters[i..N-1].
7883 // Baseline: Put Clusters[i] into a partition on its own.
7884 MinPartitions[i] = MinPartitions[i + 1] + 1;
7886 NumTables[i] = NumTables[i + 1];
7888 // Search for a solution that results in fewer partitions.
7889 for (int64_t j = N - 1; j > i; j--) {
7890 // Try building a partition from Clusters[i..j].
7891 if (isDense(Clusters, &TotalCases[0], i, j)) {
7892 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7893 bool IsTable = j - i + 1 >= MinJumpTableSize;
7894 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7896 // If this j leads to fewer partitions, or same number of partitions
7897 // with more lookup tables, it is a better partitioning.
7898 if (NumPartitions < MinPartitions[i] ||
7899 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7900 MinPartitions[i] = NumPartitions;
7902 NumTables[i] = Tables;
7908 // Iterate over the partitions, replacing some with jump tables in-place.
7909 unsigned DstIndex = 0;
7910 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7911 Last = LastElement[First];
7912 assert(Last >= First);
7913 assert(DstIndex <= First);
7914 unsigned NumClusters = Last - First + 1;
7916 CaseCluster JTCluster;
7917 if (NumClusters >= MinJumpTableSize &&
7918 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7919 Clusters[DstIndex++] = JTCluster;
7921 for (unsigned I = First; I <= Last; ++I)
7922 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7925 Clusters.resize(DstIndex);
7928 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7929 // FIXME: Using the pointer type doesn't seem ideal.
7930 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7931 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7935 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7938 const APInt &High) {
7939 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7940 // range of cases both require only one branch to lower. Just looking at the
7941 // number of clusters and destinations should be enough to decide whether to
7944 // To lower a range with bit tests, the range must fit the bitwidth of a
7946 if (!rangeFitsInWord(Low, High))
7949 // Decide whether it's profitable to lower this range with bit tests. Each
7950 // destination requires a bit test and branch, and there is an overall range
7951 // check branch. For a small number of clusters, separate comparisons might be
7952 // cheaper, and for many destinations, splitting the range might be better.
7953 return (NumDests == 1 && NumCmps >= 3) ||
7954 (NumDests == 2 && NumCmps >= 5) ||
7955 (NumDests == 3 && NumCmps >= 6);
7958 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7959 unsigned First, unsigned Last,
7960 const SwitchInst *SI,
7961 CaseCluster &BTCluster) {
7962 assert(First <= Last);
7966 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7967 unsigned NumCmps = 0;
7968 for (int64_t I = First; I <= Last; ++I) {
7969 assert(Clusters[I].Kind == CC_Range);
7970 Dests.set(Clusters[I].MBB->getNumber());
7971 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7973 unsigned NumDests = Dests.count();
7975 APInt Low = Clusters[First].Low->getValue();
7976 APInt High = Clusters[Last].High->getValue();
7977 assert(Low.slt(High));
7979 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7985 const int BitWidth = DAG.getTargetLoweringInfo()
7986 .getPointerTy(DAG.getDataLayout())
7988 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7990 // Check if the clusters cover a contiguous range such that no value in the
7991 // range will jump to the default statement.
7992 bool ContiguousRange = true;
7993 for (int64_t I = First + 1; I <= Last; ++I) {
7994 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7995 ContiguousRange = false;
8000 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
8001 // Optimize the case where all the case values fit in a word without having
8002 // to subtract minValue. In this case, we can optimize away the subtraction.
8003 LowBound = APInt::getNullValue(Low.getBitWidth());
8005 ContiguousRange = false;
8008 CmpRange = High - Low;
8012 auto TotalProb = BranchProbability::getZero();
8013 for (unsigned i = First; i <= Last; ++i) {
8014 // Find the CaseBits for this destination.
8016 for (j = 0; j < CBV.size(); ++j)
8017 if (CBV[j].BB == Clusters[i].MBB)
8019 if (j == CBV.size())
8021 CaseBits(0, Clusters[i].MBB, 0, BranchProbability::getZero()));
8022 CaseBits *CB = &CBV[j];
8024 // Update Mask, Bits and ExtraProb.
8025 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
8026 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
8027 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
8028 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
8029 CB->Bits += Hi - Lo + 1;
8030 CB->ExtraProb += Clusters[i].Prob;
8031 TotalProb += Clusters[i].Prob;
8035 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
8036 // Sort by probability first, number of bits second.
8037 if (a.ExtraProb != b.ExtraProb)
8038 return a.ExtraProb > b.ExtraProb;
8039 return a.Bits > b.Bits;
8042 for (auto &CB : CBV) {
8043 MachineBasicBlock *BitTestBB =
8044 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
8045 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
8047 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
8048 SI->getCondition(), -1U, MVT::Other, false,
8049 ContiguousRange, nullptr, nullptr, std::move(BTI),
8052 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
8053 BitTestCases.size() - 1, TotalProb);
8057 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8058 const SwitchInst *SI) {
8059 // Partition Clusters into as few subsets as possible, where each subset has a
8060 // range that fits in a machine word and has <= 3 unique destinations.
8063 // Clusters must be sorted and contain Range or JumpTable clusters.
8064 assert(!Clusters.empty());
8065 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8066 for (const CaseCluster &C : Clusters)
8067 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8068 for (unsigned i = 1; i < Clusters.size(); ++i)
8069 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8072 // The algorithm below is not suitable for -O0.
8073 if (TM.getOptLevel() == CodeGenOpt::None)
8076 // If target does not have legal shift left, do not emit bit tests at all.
8077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8078 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8079 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8082 int BitWidth = PTy.getSizeInBits();
8083 const int64_t N = Clusters.size();
8085 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8086 SmallVector<unsigned, 8> MinPartitions(N);
8087 // LastElement[i] is the last element of the partition starting at i.
8088 SmallVector<unsigned, 8> LastElement(N);
8090 // FIXME: This might not be the best algorithm for finding bit test clusters.
8092 // Base case: There is only one way to partition Clusters[N-1].
8093 MinPartitions[N - 1] = 1;
8094 LastElement[N - 1] = N - 1;
8096 // Note: loop indexes are signed to avoid underflow.
8097 for (int64_t i = N - 2; i >= 0; --i) {
8098 // Find optimal partitioning of Clusters[i..N-1].
8099 // Baseline: Put Clusters[i] into a partition on its own.
8100 MinPartitions[i] = MinPartitions[i + 1] + 1;
8103 // Search for a solution that results in fewer partitions.
8104 // Note: the search is limited by BitWidth, reducing time complexity.
8105 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8106 // Try building a partition from Clusters[i..j].
8109 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8110 Clusters[j].High->getValue()))
8113 // Check nbr of destinations and cluster types.
8114 // FIXME: This works, but doesn't seem very efficient.
8115 bool RangesOnly = true;
8116 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8117 for (int64_t k = i; k <= j; k++) {
8118 if (Clusters[k].Kind != CC_Range) {
8122 Dests.set(Clusters[k].MBB->getNumber());
8124 if (!RangesOnly || Dests.count() > 3)
8127 // Check if it's a better partition.
8128 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8129 if (NumPartitions < MinPartitions[i]) {
8130 // Found a better partition.
8131 MinPartitions[i] = NumPartitions;
8137 // Iterate over the partitions, replacing with bit-test clusters in-place.
8138 unsigned DstIndex = 0;
8139 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8140 Last = LastElement[First];
8141 assert(First <= Last);
8142 assert(DstIndex <= First);
8144 CaseCluster BitTestCluster;
8145 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8146 Clusters[DstIndex++] = BitTestCluster;
8148 size_t NumClusters = Last - First + 1;
8149 std::memmove(&Clusters[DstIndex], &Clusters[First],
8150 sizeof(Clusters[0]) * NumClusters);
8151 DstIndex += NumClusters;
8154 Clusters.resize(DstIndex);
8157 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8158 MachineBasicBlock *SwitchMBB,
8159 MachineBasicBlock *DefaultMBB) {
8160 MachineFunction *CurMF = FuncInfo.MF;
8161 MachineBasicBlock *NextMBB = nullptr;
8162 MachineFunction::iterator BBI(W.MBB);
8163 if (++BBI != FuncInfo.MF->end())
8166 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8168 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8170 if (Size == 2 && W.MBB == SwitchMBB) {
8171 // If any two of the cases has the same destination, and if one value
8172 // is the same as the other, but has one bit unset that the other has set,
8173 // use bit manipulation to do two compares at once. For example:
8174 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8175 // TODO: This could be extended to merge any 2 cases in switches with 3
8177 // TODO: Handle cases where W.CaseBB != SwitchBB.
8178 CaseCluster &Small = *W.FirstCluster;
8179 CaseCluster &Big = *W.LastCluster;
8181 if (Small.Low == Small.High && Big.Low == Big.High &&
8182 Small.MBB == Big.MBB) {
8183 const APInt &SmallValue = Small.Low->getValue();
8184 const APInt &BigValue = Big.Low->getValue();
8186 // Check that there is only one bit different.
8187 APInt CommonBit = BigValue ^ SmallValue;
8188 if (CommonBit.isPowerOf2()) {
8189 SDValue CondLHS = getValue(Cond);
8190 EVT VT = CondLHS.getValueType();
8191 SDLoc DL = getCurSDLoc();
8193 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8194 DAG.getConstant(CommonBit, DL, VT));
8195 SDValue Cond = DAG.getSetCC(
8196 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8199 // Update successor info.
8200 // Both Small and Big will jump to Small.BB, so we sum up the
8202 addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob);
8204 addSuccessorWithProb(
8205 SwitchMBB, DefaultMBB,
8206 // The default destination is the first successor in IR.
8207 BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0));
8209 addSuccessorWithProb(SwitchMBB, DefaultMBB);
8211 // Insert the true branch.
8213 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8214 DAG.getBasicBlock(Small.MBB));
8215 // Insert the false branch.
8216 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8217 DAG.getBasicBlock(DefaultMBB));
8219 DAG.setRoot(BrCond);
8225 if (TM.getOptLevel() != CodeGenOpt::None) {
8226 // Order cases by probability so the most likely case will be checked first.
8227 std::sort(W.FirstCluster, W.LastCluster + 1,
8228 [](const CaseCluster &a, const CaseCluster &b) {
8229 return a.Prob > b.Prob;
8232 // Rearrange the case blocks so that the last one falls through if possible
8233 // without without changing the order of probabilities.
8234 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8236 if (I->Prob > W.LastCluster->Prob)
8238 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8239 std::swap(*I, *W.LastCluster);
8245 // Compute total probability.
8246 BranchProbability DefaultProb = W.DefaultProb;
8247 BranchProbability UnhandledProbs = DefaultProb;
8248 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
8249 UnhandledProbs += I->Prob;
8251 MachineBasicBlock *CurMBB = W.MBB;
8252 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8253 MachineBasicBlock *Fallthrough;
8254 if (I == W.LastCluster) {
8255 // For the last cluster, fall through to the default destination.
8256 Fallthrough = DefaultMBB;
8258 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8259 CurMF->insert(BBI, Fallthrough);
8260 // Put Cond in a virtual register to make it available from the new blocks.
8261 ExportFromCurrentBlock(Cond);
8263 UnhandledProbs -= I->Prob;
8266 case CC_JumpTable: {
8267 // FIXME: Optimize away range check based on pivot comparisons.
8268 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8269 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8271 // The jump block hasn't been inserted yet; insert it here.
8272 MachineBasicBlock *JumpMBB = JT->MBB;
8273 CurMF->insert(BBI, JumpMBB);
8275 auto JumpProb = I->Prob;
8276 auto FallthroughProb = UnhandledProbs;
8278 // If the default statement is a target of the jump table, we evenly
8279 // distribute the default probability to successors of CurMBB. Also
8280 // update the probability on the edge from JumpMBB to Fallthrough.
8281 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8282 SE = JumpMBB->succ_end();
8284 if (*SI == DefaultMBB) {
8285 JumpProb += DefaultProb / 2;
8286 FallthroughProb -= DefaultProb / 2;
8287 JumpMBB->setSuccProbability(SI, DefaultProb / 2);
8288 JumpMBB->normalizeSuccProbs();
8293 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
8294 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
8295 CurMBB->normalizeSuccProbs();
8297 // The jump table header will be inserted in our current block, do the
8298 // range check, and fall through to our fallthrough block.
8299 JTH->HeaderBB = CurMBB;
8300 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8302 // If we're in the right place, emit the jump table header right now.
8303 if (CurMBB == SwitchMBB) {
8304 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8305 JTH->Emitted = true;
8310 // FIXME: Optimize away range check based on pivot comparisons.
8311 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8313 // The bit test blocks haven't been inserted yet; insert them here.
8314 for (BitTestCase &BTC : BTB->Cases)
8315 CurMF->insert(BBI, BTC.ThisBB);
8317 // Fill in fields of the BitTestBlock.
8318 BTB->Parent = CurMBB;
8319 BTB->Default = Fallthrough;
8321 BTB->DefaultProb = UnhandledProbs;
8322 // If the cases in bit test don't form a contiguous range, we evenly
8323 // distribute the probability on the edge to Fallthrough to two
8324 // successors of CurMBB.
8325 if (!BTB->ContiguousRange) {
8326 BTB->Prob += DefaultProb / 2;
8327 BTB->DefaultProb -= DefaultProb / 2;
8330 // If we're in the right place, emit the bit test header right now.
8331 if (CurMBB == SwitchMBB) {
8332 visitBitTestHeader(*BTB, SwitchMBB);
8333 BTB->Emitted = true;
8338 const Value *RHS, *LHS, *MHS;
8340 if (I->Low == I->High) {
8341 // Check Cond == I->Low.
8347 // Check I->Low <= Cond <= I->High.
8354 // The false probability is the sum of all unhandled cases.
8355 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Prob,
8358 if (CurMBB == SwitchMBB)
8359 visitSwitchCase(CB, SwitchMBB);
8361 SwitchCases.push_back(CB);
8366 CurMBB = Fallthrough;
8370 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8371 CaseClusterIt First,
8372 CaseClusterIt Last) {
8373 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8374 if (X.Prob != CC.Prob)
8375 return X.Prob > CC.Prob;
8377 // Ties are broken by comparing the case value.
8378 return X.Low->getValue().slt(CC.Low->getValue());
8382 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8383 const SwitchWorkListItem &W,
8385 MachineBasicBlock *SwitchMBB) {
8386 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8387 "Clusters not sorted?");
8389 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8391 // Balance the tree based on branch probabilities to create a near-optimal (in
8392 // terms of search time given key frequency) binary search tree. See e.g. Kurt
8393 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8394 CaseClusterIt LastLeft = W.FirstCluster;
8395 CaseClusterIt FirstRight = W.LastCluster;
8396 auto LeftProb = LastLeft->Prob + W.DefaultProb / 2;
8397 auto RightProb = FirstRight->Prob + W.DefaultProb / 2;
8399 // Move LastLeft and FirstRight towards each other from opposite directions to
8400 // find a partitioning of the clusters which balances the probability on both
8401 // sides. If LeftProb and RightProb are equal, alternate which side is
8402 // taken to ensure 0-probability nodes are distributed evenly.
8404 while (LastLeft + 1 < FirstRight) {
8405 if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1)))
8406 LeftProb += (++LastLeft)->Prob;
8408 RightProb += (--FirstRight)->Prob;
8413 // Our binary search tree differs from a typical BST in that ours can have up
8414 // to three values in each leaf. The pivot selection above doesn't take that
8415 // into account, which means the tree might require more nodes and be less
8416 // efficient. We compensate for this here.
8418 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8419 unsigned NumRight = W.LastCluster - FirstRight + 1;
8421 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8422 // If one side has less than 3 clusters, and the other has more than 3,
8423 // consider taking a cluster from the other side.
8425 if (NumLeft < NumRight) {
8426 // Consider moving the first cluster on the right to the left side.
8427 CaseCluster &CC = *FirstRight;
8428 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8429 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8430 if (LeftSideRank <= RightSideRank) {
8431 // Moving the cluster to the left does not demote it.
8437 assert(NumRight < NumLeft);
8438 // Consider moving the last element on the left to the right side.
8439 CaseCluster &CC = *LastLeft;
8440 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8441 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8442 if (RightSideRank <= LeftSideRank) {
8443 // Moving the cluster to the right does not demot it.
8453 assert(LastLeft + 1 == FirstRight);
8454 assert(LastLeft >= W.FirstCluster);
8455 assert(FirstRight <= W.LastCluster);
8457 // Use the first element on the right as pivot since we will make less-than
8458 // comparisons against it.
8459 CaseClusterIt PivotCluster = FirstRight;
8460 assert(PivotCluster > W.FirstCluster);
8461 assert(PivotCluster <= W.LastCluster);
8463 CaseClusterIt FirstLeft = W.FirstCluster;
8464 CaseClusterIt LastRight = W.LastCluster;
8466 const ConstantInt *Pivot = PivotCluster->Low;
8468 // New blocks will be inserted immediately after the current one.
8469 MachineFunction::iterator BBI(W.MBB);
8472 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8473 // we can branch to its destination directly if it's squeezed exactly in
8474 // between the known lower bound and Pivot - 1.
8475 MachineBasicBlock *LeftMBB;
8476 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8477 FirstLeft->Low == W.GE &&
8478 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8479 LeftMBB = FirstLeft->MBB;
8481 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8482 FuncInfo.MF->insert(BBI, LeftMBB);
8484 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2});
8485 // Put Cond in a virtual register to make it available from the new blocks.
8486 ExportFromCurrentBlock(Cond);
8489 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8490 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8491 // directly if RHS.High equals the current upper bound.
8492 MachineBasicBlock *RightMBB;
8493 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8494 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8495 RightMBB = FirstRight->MBB;
8497 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8498 FuncInfo.MF->insert(BBI, RightMBB);
8500 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2});
8501 // Put Cond in a virtual register to make it available from the new blocks.
8502 ExportFromCurrentBlock(Cond);
8505 // Create the CaseBlock record that will be used to lower the branch.
8506 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8507 LeftProb, RightProb);
8509 if (W.MBB == SwitchMBB)
8510 visitSwitchCase(CB, SwitchMBB);
8512 SwitchCases.push_back(CB);
8515 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8516 // Extract cases from the switch.
8517 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8518 CaseClusterVector Clusters;
8519 Clusters.reserve(SI.getNumCases());
8520 for (auto I : SI.cases()) {
8521 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8522 const ConstantInt *CaseVal = I.getCaseValue();
8523 BranchProbability Prob =
8524 BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
8525 : BranchProbability(1, SI.getNumCases() + 1);
8526 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
8529 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8531 // Cluster adjacent cases with the same destination. We do this at all
8532 // optimization levels because it's cheap to do and will make codegen faster
8533 // if there are many clusters.
8534 sortAndRangeify(Clusters);
8536 if (TM.getOptLevel() != CodeGenOpt::None) {
8537 // Replace an unreachable default with the most popular destination.
8538 // FIXME: Exploit unreachable default more aggressively.
8539 bool UnreachableDefault =
8540 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8541 if (UnreachableDefault && !Clusters.empty()) {
8542 DenseMap<const BasicBlock *, unsigned> Popularity;
8543 unsigned MaxPop = 0;
8544 const BasicBlock *MaxBB = nullptr;
8545 for (auto I : SI.cases()) {
8546 const BasicBlock *BB = I.getCaseSuccessor();
8547 if (++Popularity[BB] > MaxPop) {
8548 MaxPop = Popularity[BB];
8553 assert(MaxPop > 0 && MaxBB);
8554 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8556 // Remove cases that were pointing to the destination that is now the
8558 CaseClusterVector New;
8559 New.reserve(Clusters.size());
8560 for (CaseCluster &CC : Clusters) {
8561 if (CC.MBB != DefaultMBB)
8564 Clusters = std::move(New);
8568 // If there is only the default destination, jump there directly.
8569 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8570 if (Clusters.empty()) {
8571 SwitchMBB->addSuccessor(DefaultMBB);
8572 if (DefaultMBB != NextBlock(SwitchMBB)) {
8573 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8574 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8579 findJumpTables(Clusters, &SI, DefaultMBB);
8580 findBitTestClusters(Clusters, &SI);
8583 dbgs() << "Case clusters: ";
8584 for (const CaseCluster &C : Clusters) {
8585 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8586 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8588 C.Low->getValue().print(dbgs(), true);
8589 if (C.Low != C.High) {
8591 C.High->getValue().print(dbgs(), true);
8598 assert(!Clusters.empty());
8599 SwitchWorkList WorkList;
8600 CaseClusterIt First = Clusters.begin();
8601 CaseClusterIt Last = Clusters.end() - 1;
8602 auto DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB);
8603 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
8605 while (!WorkList.empty()) {
8606 SwitchWorkListItem W = WorkList.back();
8607 WorkList.pop_back();
8608 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8610 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8611 // For optimized builds, lower large range as a balanced binary tree.
8612 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8616 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);