1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
60 #include "llvm/Target/TargetSelectionDAGInfo.h"
61 #include "llvm/Target/TargetSubtargetInfo.h"
65 #define DEBUG_TYPE "isel"
67 /// LimitFloatPrecision - Generate low-precision inline sequences for
68 /// some float libcalls (6, 8 or 12 bits).
69 static unsigned LimitFloatPrecision;
71 static cl::opt<unsigned, true>
72 LimitFPPrecision("limit-float-precision",
73 cl::desc("Generate low-precision inline sequences "
74 "for some float libcalls"),
75 cl::location(LimitFloatPrecision),
78 // Limit the width of DAG chains. This is important in general to prevent
79 // prevent DAG-based analysis from blowing up. For example, alias analysis and
80 // load clustering may not complete in reasonable time. It is difficult to
81 // recognize and avoid this situation within each individual analysis, and
82 // future analyses are likely to have the same behavior. Limiting DAG width is
83 // the safe approach, and will be especially important with global DAGs.
85 // MaxParallelChains default is arbitrarily high to avoid affecting
86 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
87 // sequence over this should have been converted to llvm.memcpy by the
88 // frontend. It easy to induce this behavior with .ll code such as:
89 // %buffer = alloca [4096 x i8]
90 // %data = load [4096 x i8]* %argPtr
91 // store [4096 x i8] %data, [4096 x i8]* %buffer
92 static const unsigned MaxParallelChains = 64;
94 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
95 const SDValue *Parts, unsigned NumParts,
96 MVT PartVT, EVT ValueVT, const Value *V);
98 /// getCopyFromParts - Create a value that contains the specified legal parts
99 /// combined into the value they represent. If the parts combine to a type
100 /// larger then ValueVT then AssertOp can be used to specify whether the extra
101 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
102 /// (ISD::AssertSext).
103 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts,
105 unsigned NumParts, MVT PartVT, EVT ValueVT,
107 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
108 if (ValueVT.isVector())
109 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
112 assert(NumParts > 0 && "No parts to assemble!");
113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
114 SDValue Val = Parts[0];
117 // Assemble the value from multiple parts.
118 if (ValueVT.isInteger()) {
119 unsigned PartBits = PartVT.getSizeInBits();
120 unsigned ValueBits = ValueVT.getSizeInBits();
122 // Assemble the power of 2 part.
123 unsigned RoundParts = NumParts & (NumParts - 1) ?
124 1 << Log2_32(NumParts) : NumParts;
125 unsigned RoundBits = PartBits * RoundParts;
126 EVT RoundVT = RoundBits == ValueBits ?
127 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
130 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
132 if (RoundParts > 2) {
133 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
135 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
136 RoundParts / 2, PartVT, HalfVT, V);
138 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
139 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
142 if (TLI.isBigEndian())
145 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
147 if (RoundParts < NumParts) {
148 // Assemble the trailing non-power-of-2 part.
149 unsigned OddParts = NumParts - RoundParts;
150 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
151 Hi = getCopyFromParts(DAG, DL,
152 Parts + RoundParts, OddParts, PartVT, OddVT, V);
154 // Combine the round and odd parts.
156 if (TLI.isBigEndian())
158 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
159 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
160 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
161 DAG.getConstant(Lo.getValueType().getSizeInBits(),
162 TLI.getPointerTy()));
163 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
164 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
166 } else if (PartVT.isFloatingPoint()) {
167 // FP split into multiple FP parts (for ppcf128)
168 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
171 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
172 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
173 if (TLI.hasBigEndianPartOrdering(ValueVT))
175 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
177 // FP split into integer parts (soft fp)
178 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
179 !PartVT.isVector() && "Unexpected split");
180 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
181 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
185 // There is now one part, held in Val. Correct it to match ValueVT.
186 EVT PartEVT = Val.getValueType();
188 if (PartEVT == ValueVT)
191 if (PartEVT.isInteger() && ValueVT.isInteger()) {
192 if (ValueVT.bitsLT(PartEVT)) {
193 // For a truncate, see if we have any information to
194 // indicate whether the truncated bits will always be
195 // zero or sign-extension.
196 if (AssertOp != ISD::DELETED_NODE)
197 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
198 DAG.getValueType(ValueVT));
199 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
201 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
204 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
205 // FP_ROUND's are always exact here.
206 if (ValueVT.bitsLT(Val.getValueType()))
207 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
208 DAG.getTargetConstant(1, TLI.getPointerTy()));
210 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
214 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
216 llvm_unreachable("Unknown mismatch!");
219 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
220 const Twine &ErrMsg) {
221 const Instruction *I = dyn_cast_or_null<Instruction>(V);
223 return Ctx.emitError(ErrMsg);
225 const char *AsmError = ", possible invalid constraint for vector type";
226 if (const CallInst *CI = dyn_cast<CallInst>(I))
227 if (isa<InlineAsm>(CI->getCalledValue()))
228 return Ctx.emitError(I, ErrMsg + AsmError);
230 return Ctx.emitError(I, ErrMsg);
233 /// getCopyFromPartsVector - Create a value that contains the specified legal
234 /// parts combined into the value they represent. If the parts combine to a
235 /// type larger then ValueVT then AssertOp can be used to specify whether the
236 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
237 /// ValueVT (ISD::AssertSext).
238 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
239 const SDValue *Parts, unsigned NumParts,
240 MVT PartVT, EVT ValueVT, const Value *V) {
241 assert(ValueVT.isVector() && "Not a vector value");
242 assert(NumParts > 0 && "No parts to assemble!");
243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
244 SDValue Val = Parts[0];
246 // Handle a multi-element vector.
250 unsigned NumIntermediates;
252 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
253 NumIntermediates, RegisterVT);
254 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
255 NumParts = NumRegs; // Silence a compiler warning.
256 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
257 assert(RegisterVT == Parts[0].getSimpleValueType() &&
258 "Part type doesn't match part!");
260 // Assemble the parts into intermediate operands.
261 SmallVector<SDValue, 8> Ops(NumIntermediates);
262 if (NumIntermediates == NumParts) {
263 // If the register was not expanded, truncate or copy the value,
265 for (unsigned i = 0; i != NumParts; ++i)
266 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
267 PartVT, IntermediateVT, V);
268 } else if (NumParts > 0) {
269 // If the intermediate type was expanded, build the intermediate
270 // operands from the parts.
271 assert(NumParts % NumIntermediates == 0 &&
272 "Must expand into a divisible number of parts!");
273 unsigned Factor = NumParts / NumIntermediates;
274 for (unsigned i = 0; i != NumIntermediates; ++i)
275 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
276 PartVT, IntermediateVT, V);
279 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
280 // intermediate operands.
281 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
286 // There is now one part, held in Val. Correct it to match ValueVT.
287 EVT PartEVT = Val.getValueType();
289 if (PartEVT == ValueVT)
292 if (PartEVT.isVector()) {
293 // If the element type of the source/dest vectors are the same, but the
294 // parts vector has more elements than the value vector, then we have a
295 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
297 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
298 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
299 "Cannot narrow, it would be a lossy transformation");
300 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
301 DAG.getConstant(0, TLI.getVectorIdxTy()));
304 // Vector/Vector bitcast.
305 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
306 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
308 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
309 "Cannot handle this kind of promotion");
310 // Promoted vector extract
311 bool Smaller = ValueVT.bitsLE(PartEVT);
312 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
317 // Trivial bitcast if the types are the same size and the destination
318 // vector type is legal.
319 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
320 TLI.isTypeLegal(ValueVT))
321 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
323 // Handle cases such as i8 -> <1 x i1>
324 if (ValueVT.getVectorNumElements() != 1) {
325 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
326 "non-trivial scalar-to-vector conversion");
327 return DAG.getUNDEF(ValueVT);
330 if (ValueVT.getVectorNumElements() == 1 &&
331 ValueVT.getVectorElementType() != PartEVT) {
332 bool Smaller = ValueVT.bitsLE(PartEVT);
333 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
334 DL, ValueVT.getScalarType(), Val);
337 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
340 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
341 SDValue Val, SDValue *Parts, unsigned NumParts,
342 MVT PartVT, const Value *V);
344 /// getCopyToParts - Create a series of nodes that contain the specified value
345 /// split into legal parts. If the parts contain more bits than Val, then, for
346 /// integers, ExtendKind can be used to specify how to generate the extra bits.
347 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V,
350 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
351 EVT ValueVT = Val.getValueType();
353 // Handle the vector case separately.
354 if (ValueVT.isVector())
355 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
358 unsigned PartBits = PartVT.getSizeInBits();
359 unsigned OrigNumParts = NumParts;
360 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
365 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
366 EVT PartEVT = PartVT;
367 if (PartEVT == ValueVT) {
368 assert(NumParts == 1 && "No-op copy with multiple parts!");
373 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
374 // If the parts cover more bits than the value has, promote the value.
375 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
376 assert(NumParts == 1 && "Do not know what to promote to!");
377 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
379 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
380 ValueVT.isInteger() &&
381 "Unknown mismatch!");
382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
383 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
384 if (PartVT == MVT::x86mmx)
385 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
387 } else if (PartBits == ValueVT.getSizeInBits()) {
388 // Different types of the same size.
389 assert(NumParts == 1 && PartEVT != ValueVT);
390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
392 // If the parts cover less bits than value has, truncate the value.
393 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
394 ValueVT.isInteger() &&
395 "Unknown mismatch!");
396 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
397 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
398 if (PartVT == MVT::x86mmx)
399 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
402 // The value may have changed - recompute ValueVT.
403 ValueVT = Val.getValueType();
404 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
405 "Failed to tile the value with PartVT!");
408 if (PartEVT != ValueVT)
409 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
410 "scalar-to-vector conversion failed");
416 // Expand the value into multiple parts.
417 if (NumParts & (NumParts - 1)) {
418 // The number of parts is not a power of 2. Split off and copy the tail.
419 assert(PartVT.isInteger() && ValueVT.isInteger() &&
420 "Do not know what to expand to!");
421 unsigned RoundParts = 1 << Log2_32(NumParts);
422 unsigned RoundBits = RoundParts * PartBits;
423 unsigned OddParts = NumParts - RoundParts;
424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
425 DAG.getIntPtrConstant(RoundBits));
426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
428 if (TLI.isBigEndian())
429 // The odd parts were reversed by getCopyToParts - unreverse them.
430 std::reverse(Parts + RoundParts, Parts + NumParts);
432 NumParts = RoundParts;
433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
437 // The number of parts is a power of 2. Repeatedly bisect the value using
439 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
440 EVT::getIntegerVT(*DAG.getContext(),
441 ValueVT.getSizeInBits()),
444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
445 for (unsigned i = 0; i < NumParts; i += StepSize) {
446 unsigned ThisBits = StepSize * PartBits / 2;
447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
448 SDValue &Part0 = Parts[i];
449 SDValue &Part1 = Parts[i+StepSize/2];
451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(1));
453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(0));
456 if (ThisBits == PartBits && ThisVT != PartVT) {
457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
468 /// getCopyToPartsVector - Create a series of nodes that contain the specified
469 /// value split into legal parts.
470 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
471 SDValue Val, SDValue *Parts, unsigned NumParts,
472 MVT PartVT, const Value *V) {
473 EVT ValueVT = Val.getValueType();
474 assert(ValueVT.isVector() && "Not a vector");
475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
478 EVT PartEVT = PartVT;
479 if (PartEVT == ValueVT) {
481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
482 // Bitconvert vector->vector case.
483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
484 } else if (PartVT.isVector() &&
485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
487 EVT ElementVT = PartVT.getVectorElementType();
488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
490 SmallVector<SDValue, 16> Ops;
491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
493 ElementVT, Val, DAG.getConstant(i,
494 TLI.getVectorIdxTy())));
496 for (unsigned i = ValueVT.getVectorNumElements(),
497 e = PartVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getUNDEF(ElementVT));
500 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
502 // FIXME: Use CONCAT for 2x -> 4x.
504 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
505 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType().bitsGE(
508 ValueVT.getVectorElementType()) &&
509 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
511 // Promoted vector extract
512 bool Smaller = PartEVT.bitsLE(ValueVT);
513 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
516 // Vector -> scalar conversion.
517 assert(ValueVT.getVectorNumElements() == 1 &&
518 "Only trivial vector-to-scalar conversions should get here!");
519 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
520 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
522 bool Smaller = ValueVT.bitsLE(PartVT);
523 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
531 // Handle a multi-element vector.
534 unsigned NumIntermediates;
535 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
537 NumIntermediates, RegisterVT);
538 unsigned NumElements = ValueVT.getVectorNumElements();
540 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
541 NumParts = NumRegs; // Silence a compiler warning.
542 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
544 // Split the vector into intermediate operands.
545 SmallVector<SDValue, 8> Ops(NumIntermediates);
546 for (unsigned i = 0; i != NumIntermediates; ++i) {
547 if (IntermediateVT.isVector())
548 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
550 DAG.getConstant(i * (NumElements / NumIntermediates),
551 TLI.getVectorIdxTy()));
553 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
555 DAG.getConstant(i, TLI.getVectorIdxTy()));
558 // Split the intermediate operands into legal parts.
559 if (NumParts == NumIntermediates) {
560 // If the register was not expanded, promote or copy the value,
562 for (unsigned i = 0; i != NumParts; ++i)
563 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
564 } else if (NumParts > 0) {
565 // If the intermediate type was expanded, split each the value into
567 assert(NumParts % NumIntermediates == 0 &&
568 "Must expand into a divisible number of parts!");
569 unsigned Factor = NumParts / NumIntermediates;
570 for (unsigned i = 0; i != NumIntermediates; ++i)
571 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
576 /// RegsForValue - This struct represents the registers (physical or virtual)
577 /// that a particular set of values is assigned, and the type information
578 /// about the value. The most common situation is to represent one value at a
579 /// time, but struct or array values are handled element-wise as multiple
580 /// values. The splitting of aggregates is performed recursively, so that we
581 /// never have aggregate-typed registers. The values at this point do not
582 /// necessarily have legal types, so each value may require one or more
583 /// registers of some legal type.
585 struct RegsForValue {
586 /// ValueVTs - The value types of the values, which may not be legal, and
587 /// may need be promoted or synthesized from one or more registers.
589 SmallVector<EVT, 4> ValueVTs;
591 /// RegVTs - The value types of the registers. This is the same size as
592 /// ValueVTs and it records, for each value, what the type of the assigned
593 /// register or registers are. (Individual values are never synthesized
594 /// from more than one type of register.)
596 /// With virtual registers, the contents of RegVTs is redundant with TLI's
597 /// getRegisterType member function, however when with physical registers
598 /// it is necessary to have a separate record of the types.
600 SmallVector<MVT, 4> RegVTs;
602 /// Regs - This list holds the registers assigned to the values.
603 /// Each legal or promoted value requires one register, and each
604 /// expanded value requires multiple registers.
606 SmallVector<unsigned, 4> Regs;
610 RegsForValue(const SmallVector<unsigned, 4> ®s,
611 MVT regvt, EVT valuevt)
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
614 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
615 unsigned Reg, Type *Ty) {
616 ComputeValueVTs(tli, Ty, ValueVTs);
618 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
621 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
622 for (unsigned i = 0; i != NumRegs; ++i)
623 Regs.push_back(Reg + i);
624 RegVTs.push_back(RegisterVT);
629 /// append - Add the specified values to this one.
630 void append(const RegsForValue &RHS) {
631 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
632 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
633 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
636 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
637 /// this value and returns the result as a ValueVTs value. This uses
638 /// Chain/Flag as the input and updates them for the output Chain/Flag.
639 /// If the Flag pointer is NULL, no flag is used.
640 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
642 SDValue &Chain, SDValue *Flag,
643 const Value *V = nullptr) const;
645 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
646 /// specified value into the registers specified by this object. This uses
647 /// Chain/Flag as the input and updates them for the output Chain/Flag.
648 /// If the Flag pointer is NULL, no flag is used.
649 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
650 SDValue &Chain, SDValue *Flag, const Value *V) const;
652 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
653 /// operand list. This adds the code marker, matching input operand index
654 /// (if applicable), and includes the number of values added into it.
655 void AddInlineAsmOperands(unsigned Kind,
656 bool HasMatching, unsigned MatchingIdx,
658 std::vector<SDValue> &Ops) const;
662 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
663 /// this value and returns the result as a ValueVT value. This uses
664 /// Chain/Flag as the input and updates them for the output Chain/Flag.
665 /// If the Flag pointer is NULL, no flag is used.
666 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
667 FunctionLoweringInfo &FuncInfo,
669 SDValue &Chain, SDValue *Flag,
670 const Value *V) const {
671 // A Value with type {} or [0 x %t] needs no registers.
672 if (ValueVTs.empty())
675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
677 // Assemble the legal parts into the final values.
678 SmallVector<SDValue, 4> Values(ValueVTs.size());
679 SmallVector<SDValue, 8> Parts;
680 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
681 // Copy the legal parts from the registers.
682 EVT ValueVT = ValueVTs[Value];
683 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
684 MVT RegisterVT = RegVTs[Value];
686 Parts.resize(NumRegs);
687 for (unsigned i = 0; i != NumRegs; ++i) {
690 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
692 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
693 *Flag = P.getValue(2);
696 Chain = P.getValue(1);
699 // If the source register was virtual and if we know something about it,
700 // add an assert node.
701 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
702 !RegisterVT.isInteger() || RegisterVT.isVector())
705 const FunctionLoweringInfo::LiveOutInfo *LOI =
706 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
710 unsigned RegSize = RegisterVT.getSizeInBits();
711 unsigned NumSignBits = LOI->NumSignBits;
712 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
714 if (NumZeroBits == RegSize) {
715 // The current value is a zero.
716 // Explicitly express that as it would be easier for
717 // optimizations to kick in.
718 Parts[i] = DAG.getConstant(0, RegisterVT);
722 // FIXME: We capture more information than the dag can represent. For
723 // now, just use the tightest assertzext/assertsext possible.
725 EVT FromVT(MVT::Other);
726 if (NumSignBits == RegSize)
727 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
728 else if (NumZeroBits >= RegSize-1)
729 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
730 else if (NumSignBits > RegSize-8)
731 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
732 else if (NumZeroBits >= RegSize-8)
733 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
734 else if (NumSignBits > RegSize-16)
735 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
736 else if (NumZeroBits >= RegSize-16)
737 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
738 else if (NumSignBits > RegSize-32)
739 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
740 else if (NumZeroBits >= RegSize-32)
741 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
745 // Add an assertion node.
746 assert(FromVT != MVT::Other);
747 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
748 RegisterVT, P, DAG.getValueType(FromVT));
751 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
752 NumRegs, RegisterVT, ValueVT, V);
757 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
760 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
761 /// specified value into the registers specified by this object. This uses
762 /// Chain/Flag as the input and updates them for the output Chain/Flag.
763 /// If the Flag pointer is NULL, no flag is used.
764 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
765 SDValue &Chain, SDValue *Flag,
766 const Value *V) const {
767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
769 // Get the list of the values's legal parts.
770 unsigned NumRegs = Regs.size();
771 SmallVector<SDValue, 8> Parts(NumRegs);
772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
773 EVT ValueVT = ValueVTs[Value];
774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
775 MVT RegisterVT = RegVTs[Value];
776 ISD::NodeType ExtendKind =
777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
784 // Copy the parts into the registers.
785 SmallVector<SDValue, 8> Chains(NumRegs);
786 for (unsigned i = 0; i != NumRegs; ++i) {
789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
792 *Flag = Part.getValue(1);
795 Chains[i] = Part.getValue(0);
798 if (NumRegs == 1 || Flag)
799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
800 // flagged to it. That is the CopyToReg nodes and the user are considered
801 // a single scheduling unit. If we create a TokenFactor and return it as
802 // chain, then the TokenFactor is both a predecessor (operand) of the
803 // user as well as a successor (the TF operands are flagged to the user).
804 // c1, f1 = CopyToReg
805 // c2, f2 = CopyToReg
806 // c3 = TokenFactor c1, c2
809 Chain = Chains[NumRegs-1];
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
814 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
815 /// operand list. This adds the code marker and includes the number of
816 /// values added into it.
817 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
818 unsigned MatchingIdx,
820 std::vector<SDValue> &Ops) const {
821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
826 else if (!Regs.empty() &&
827 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
828 // Put the register class of the virtual registers in the flag word. That
829 // way, later passes can recompute register class constraints for inline
830 // assembly as well as normal instructions.
831 // Don't do this for tied operands that can use the regclass information
833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
841 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
842 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
843 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
844 MVT RegisterVT = RegVTs[Value];
845 for (unsigned i = 0; i != NumRegs; ++i) {
846 assert(Reg < Regs.size() && "Mismatch in # registers expected");
847 unsigned TheReg = Regs[Reg++];
848 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
850 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
851 // If we clobbered the stack pointer, MFI should know about it.
852 assert(DAG.getMachineFunction().getFrameInfo()->
853 hasInlineAsmWithSPAdjust());
859 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
860 const TargetLibraryInfo *li) {
864 DL = DAG.getSubtarget().getDataLayout();
865 Context = DAG.getContext();
866 LPadToCallSiteMap.clear();
869 /// clear - Clear out the current SelectionDAG and the associated
870 /// state and prepare this SelectionDAGBuilder object to be used
871 /// for a new block. This doesn't clear out information about
872 /// additional blocks that are needed to complete switch lowering
873 /// or PHI node updating; that information is cleared out as it is
875 void SelectionDAGBuilder::clear() {
877 UnusedArgNodeMap.clear();
878 PendingLoads.clear();
879 PendingExports.clear();
882 SDNodeOrder = LowestSDNodeOrder;
885 /// clearDanglingDebugInfo - Clear the dangling debug information
886 /// map. This function is separated from the clear so that debug
887 /// information that is dangling in a basic block can be properly
888 /// resolved in a different basic block. This allows the
889 /// SelectionDAG to resolve dangling debug information attached
891 void SelectionDAGBuilder::clearDanglingDebugInfo() {
892 DanglingDebugInfoMap.clear();
895 /// getRoot - Return the current virtual root of the Selection DAG,
896 /// flushing any PendingLoad items. This must be done before emitting
897 /// a store or any other node that may need to be ordered after any
898 /// prior load instructions.
900 SDValue SelectionDAGBuilder::getRoot() {
901 if (PendingLoads.empty())
902 return DAG.getRoot();
904 if (PendingLoads.size() == 1) {
905 SDValue Root = PendingLoads[0];
907 PendingLoads.clear();
911 // Otherwise, we have to make a token factor node.
912 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
914 PendingLoads.clear();
919 /// getControlRoot - Similar to getRoot, but instead of flushing all the
920 /// PendingLoad items, flush all the PendingExports items. It is necessary
921 /// to do this before emitting a terminator instruction.
923 SDValue SelectionDAGBuilder::getControlRoot() {
924 SDValue Root = DAG.getRoot();
926 if (PendingExports.empty())
929 // Turn all of the CopyToReg chains into one factored node.
930 if (Root.getOpcode() != ISD::EntryToken) {
931 unsigned i = 0, e = PendingExports.size();
932 for (; i != e; ++i) {
933 assert(PendingExports[i].getNode()->getNumOperands() > 1);
934 if (PendingExports[i].getNode()->getOperand(0) == Root)
935 break; // Don't add the root if we already indirectly depend on it.
939 PendingExports.push_back(Root);
942 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
944 PendingExports.clear();
949 void SelectionDAGBuilder::visit(const Instruction &I) {
950 // Set up outgoing PHI node register values before emitting the terminator.
951 if (isa<TerminatorInst>(&I))
952 HandlePHINodesInSuccessorBlocks(I.getParent());
958 visit(I.getOpcode(), I);
960 if (!isa<TerminatorInst>(&I) && !HasTailCall)
961 CopyToExportRegsIfNeeded(&I);
966 void SelectionDAGBuilder::visitPHI(const PHINode &) {
967 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
970 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
971 // Note: this doesn't use InstVisitor, because it has to work with
972 // ConstantExpr's in addition to instructions.
974 default: llvm_unreachable("Unknown instruction type encountered!");
975 // Build the switch statement using the Instruction.def file.
976 #define HANDLE_INST(NUM, OPCODE, CLASS) \
977 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
978 #include "llvm/IR/Instruction.def"
982 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
983 // generate the debug data structures now that we've seen its definition.
984 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
986 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
988 const DbgValueInst *DI = DDI.getDI();
989 DebugLoc dl = DDI.getdl();
990 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
991 MDNode *Variable = DI->getVariable();
992 uint64_t Offset = DI->getOffset();
993 // A dbg.value for an alloca is always indirect.
994 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
997 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, Val)) {
998 SDV = DAG.getDbgValue(Variable, Val.getNode(),
999 Val.getResNo(), IsIndirect,
1000 Offset, dl, DbgSDNodeOrder);
1001 DAG.AddDbgValue(SDV, Val.getNode(), false);
1004 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1005 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1009 /// getValue - Return an SDValue for the given Value.
1010 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1011 // If we already have an SDValue for this value, use it. It's important
1012 // to do this first, so that we don't create a CopyFromReg if we already
1013 // have a regular SDValue.
1014 SDValue &N = NodeMap[V];
1015 if (N.getNode()) return N;
1017 // If there's a virtual register allocated and initialized for this
1019 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1020 if (It != FuncInfo.ValueMap.end()) {
1021 unsigned InReg = It->second;
1022 RegsForValue RFV(*DAG.getContext(),
1023 *TM.getSubtargetImpl()->getTargetLowering(), InReg,
1025 SDValue Chain = DAG.getEntryNode();
1026 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1027 resolveDanglingDebugInfo(V, N);
1031 // Otherwise create a new SDValue and remember it.
1032 SDValue Val = getValueImpl(V);
1034 resolveDanglingDebugInfo(V, Val);
1038 /// getNonRegisterValue - Return an SDValue for the given Value, but
1039 /// don't look in FuncInfo.ValueMap for a virtual register.
1040 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1041 // If we already have an SDValue for this value, use it.
1042 SDValue &N = NodeMap[V];
1043 if (N.getNode()) return N;
1045 // Otherwise create a new SDValue and remember it.
1046 SDValue Val = getValueImpl(V);
1048 resolveDanglingDebugInfo(V, Val);
1052 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1053 /// Create an SDValue for the given value.
1054 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1055 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1057 if (const Constant *C = dyn_cast<Constant>(V)) {
1058 EVT VT = TLI->getValueType(V->getType(), true);
1060 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1061 return DAG.getConstant(*CI, VT);
1063 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1064 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1066 if (isa<ConstantPointerNull>(C)) {
1067 unsigned AS = V->getType()->getPointerAddressSpace();
1068 return DAG.getConstant(0, TLI->getPointerTy(AS));
1071 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1072 return DAG.getConstantFP(*CFP, VT);
1074 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1075 return DAG.getUNDEF(VT);
1077 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1078 visit(CE->getOpcode(), *CE);
1079 SDValue N1 = NodeMap[V];
1080 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1084 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1085 SmallVector<SDValue, 4> Constants;
1086 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1088 SDNode *Val = getValue(*OI).getNode();
1089 // If the operand is an empty aggregate, there are no values.
1091 // Add each leaf value from the operand to the Constants list
1092 // to form a flattened list of all the values.
1093 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1094 Constants.push_back(SDValue(Val, i));
1097 return DAG.getMergeValues(Constants, getCurSDLoc());
1100 if (const ConstantDataSequential *CDS =
1101 dyn_cast<ConstantDataSequential>(C)) {
1102 SmallVector<SDValue, 4> Ops;
1103 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1104 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1105 // Add each leaf value from the operand to the Constants list
1106 // to form a flattened list of all the values.
1107 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1108 Ops.push_back(SDValue(Val, i));
1111 if (isa<ArrayType>(CDS->getType()))
1112 return DAG.getMergeValues(Ops, getCurSDLoc());
1113 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1117 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1118 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1119 "Unknown struct or array constant!");
1121 SmallVector<EVT, 4> ValueVTs;
1122 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1123 unsigned NumElts = ValueVTs.size();
1125 return SDValue(); // empty struct
1126 SmallVector<SDValue, 4> Constants(NumElts);
1127 for (unsigned i = 0; i != NumElts; ++i) {
1128 EVT EltVT = ValueVTs[i];
1129 if (isa<UndefValue>(C))
1130 Constants[i] = DAG.getUNDEF(EltVT);
1131 else if (EltVT.isFloatingPoint())
1132 Constants[i] = DAG.getConstantFP(0, EltVT);
1134 Constants[i] = DAG.getConstant(0, EltVT);
1137 return DAG.getMergeValues(Constants, getCurSDLoc());
1140 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1141 return DAG.getBlockAddress(BA, VT);
1143 VectorType *VecTy = cast<VectorType>(V->getType());
1144 unsigned NumElements = VecTy->getNumElements();
1146 // Now that we know the number and type of the elements, get that number of
1147 // elements into the Ops array based on what kind of constant it is.
1148 SmallVector<SDValue, 16> Ops;
1149 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1150 for (unsigned i = 0; i != NumElements; ++i)
1151 Ops.push_back(getValue(CV->getOperand(i)));
1153 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1154 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1157 if (EltVT.isFloatingPoint())
1158 Op = DAG.getConstantFP(0, EltVT);
1160 Op = DAG.getConstant(0, EltVT);
1161 Ops.assign(NumElements, Op);
1164 // Create a BUILD_VECTOR node.
1165 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1168 // If this is a static alloca, generate it as the frameindex instead of
1170 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1171 DenseMap<const AllocaInst*, int>::iterator SI =
1172 FuncInfo.StaticAllocaMap.find(AI);
1173 if (SI != FuncInfo.StaticAllocaMap.end())
1174 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1177 // If this is an instruction which fast-isel has deferred, select it now.
1178 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1179 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1180 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1181 SDValue Chain = DAG.getEntryNode();
1182 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1185 llvm_unreachable("Can't get register for value!");
1188 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1189 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1190 SDValue Chain = getControlRoot();
1191 SmallVector<ISD::OutputArg, 8> Outs;
1192 SmallVector<SDValue, 8> OutVals;
1194 if (!FuncInfo.CanLowerReturn) {
1195 unsigned DemoteReg = FuncInfo.DemoteRegister;
1196 const Function *F = I.getParent()->getParent();
1198 // Emit a store of the return value through the virtual register.
1199 // Leave Outs empty so that LowerReturn won't try to load return
1200 // registers the usual way.
1201 SmallVector<EVT, 1> PtrValueVTs;
1202 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1205 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1206 SDValue RetOp = getValue(I.getOperand(0));
1208 SmallVector<EVT, 4> ValueVTs;
1209 SmallVector<uint64_t, 4> Offsets;
1210 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1211 unsigned NumValues = ValueVTs.size();
1213 SmallVector<SDValue, 4> Chains(NumValues);
1214 for (unsigned i = 0; i != NumValues; ++i) {
1215 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1216 RetPtr.getValueType(), RetPtr,
1217 DAG.getIntPtrConstant(Offsets[i]));
1219 DAG.getStore(Chain, getCurSDLoc(),
1220 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1221 // FIXME: better loc info would be nice.
1222 Add, MachinePointerInfo(), false, false, 0);
1225 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1226 MVT::Other, Chains);
1227 } else if (I.getNumOperands() != 0) {
1228 SmallVector<EVT, 4> ValueVTs;
1229 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1230 unsigned NumValues = ValueVTs.size();
1232 SDValue RetOp = getValue(I.getOperand(0));
1233 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1234 EVT VT = ValueVTs[j];
1236 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1238 const Function *F = I.getParent()->getParent();
1239 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241 ExtendKind = ISD::SIGN_EXTEND;
1242 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1244 ExtendKind = ISD::ZERO_EXTEND;
1246 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1247 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1249 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1250 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1251 SmallVector<SDValue, 4> Parts(NumParts);
1252 getCopyToParts(DAG, getCurSDLoc(),
1253 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1254 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1256 // 'inreg' on function refers to return value
1257 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1258 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1262 // Propagate extension type if any
1263 if (ExtendKind == ISD::SIGN_EXTEND)
1265 else if (ExtendKind == ISD::ZERO_EXTEND)
1268 for (unsigned i = 0; i < NumParts; ++i) {
1269 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1270 VT, /*isfixed=*/true, 0, 0));
1271 OutVals.push_back(Parts[i]);
1277 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1278 CallingConv::ID CallConv =
1279 DAG.getMachineFunction().getFunction()->getCallingConv();
1280 Chain = TM.getSubtargetImpl()->getTargetLowering()->LowerReturn(
1281 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1283 // Verify that the target's LowerReturn behaved as expected.
1284 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1285 "LowerReturn didn't return a valid chain!");
1287 // Update the DAG with the new chain value resulting from return lowering.
1291 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1292 /// created for it, emit nodes to copy the value into the virtual
1294 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1296 if (V->getType()->isEmptyTy())
1299 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1300 if (VMI != FuncInfo.ValueMap.end()) {
1301 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1302 CopyValueToVirtualRegister(V, VMI->second);
1306 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1307 /// the current basic block, add it to ValueMap now so that we'll get a
1309 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1310 // No need to export constants.
1311 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1313 // Already exported?
1314 if (FuncInfo.isExportedInst(V)) return;
1316 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1317 CopyValueToVirtualRegister(V, Reg);
1320 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1321 const BasicBlock *FromBB) {
1322 // The operands of the setcc have to be in this block. We don't know
1323 // how to export them from some other block.
1324 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1325 // Can export from current BB.
1326 if (VI->getParent() == FromBB)
1329 // Is already exported, noop.
1330 return FuncInfo.isExportedInst(V);
1333 // If this is an argument, we can export it if the BB is the entry block or
1334 // if it is already exported.
1335 if (isa<Argument>(V)) {
1336 if (FromBB == &FromBB->getParent()->getEntryBlock())
1339 // Otherwise, can only export this if it is already exported.
1340 return FuncInfo.isExportedInst(V);
1343 // Otherwise, constants can always be exported.
1347 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1348 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1349 const MachineBasicBlock *Dst) const {
1350 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1353 const BasicBlock *SrcBB = Src->getBasicBlock();
1354 const BasicBlock *DstBB = Dst->getBasicBlock();
1355 return BPI->getEdgeWeight(SrcBB, DstBB);
1358 void SelectionDAGBuilder::
1359 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1360 uint32_t Weight /* = 0 */) {
1362 Weight = getEdgeWeight(Src, Dst);
1363 Src->addSuccessor(Dst, Weight);
1367 static bool InBlock(const Value *V, const BasicBlock *BB) {
1368 if (const Instruction *I = dyn_cast<Instruction>(V))
1369 return I->getParent() == BB;
1373 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1374 /// This function emits a branch and is used at the leaves of an OR or an
1375 /// AND operator tree.
1378 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1379 MachineBasicBlock *TBB,
1380 MachineBasicBlock *FBB,
1381 MachineBasicBlock *CurBB,
1382 MachineBasicBlock *SwitchBB,
1385 const BasicBlock *BB = CurBB->getBasicBlock();
1387 // If the leaf of the tree is a comparison, merge the condition into
1389 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1390 // The operands of the cmp have to be in this block. We don't know
1391 // how to export them from some other block. If this is the first block
1392 // of the sequence, no exporting is needed.
1393 if (CurBB == SwitchBB ||
1394 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1395 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1396 ISD::CondCode Condition;
1397 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1398 Condition = getICmpCondCode(IC->getPredicate());
1399 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1400 Condition = getFCmpCondCode(FC->getPredicate());
1401 if (TM.Options.NoNaNsFPMath)
1402 Condition = getFCmpCodeWithoutNaN(Condition);
1404 Condition = ISD::SETEQ; // silence warning.
1405 llvm_unreachable("Unknown compare instruction");
1408 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1409 TBB, FBB, CurBB, TWeight, FWeight);
1410 SwitchCases.push_back(CB);
1415 // Create a CaseBlock record representing this branch.
1416 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1417 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1418 SwitchCases.push_back(CB);
1421 /// Scale down both weights to fit into uint32_t.
1422 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1423 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1424 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1425 NewTrue = NewTrue / Scale;
1426 NewFalse = NewFalse / Scale;
1429 /// FindMergedConditions - If Cond is an expression like
1430 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1431 MachineBasicBlock *TBB,
1432 MachineBasicBlock *FBB,
1433 MachineBasicBlock *CurBB,
1434 MachineBasicBlock *SwitchBB,
1435 unsigned Opc, uint32_t TWeight,
1437 // If this node is not part of the or/and tree, emit it as a branch.
1438 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1439 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1440 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1441 BOp->getParent() != CurBB->getBasicBlock() ||
1442 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1443 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1444 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1449 // Create TmpBB after CurBB.
1450 MachineFunction::iterator BBI = CurBB;
1451 MachineFunction &MF = DAG.getMachineFunction();
1452 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1453 CurBB->getParent()->insert(++BBI, TmpBB);
1455 if (Opc == Instruction::Or) {
1456 // Codegen X | Y as:
1465 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1466 // The requirement is that
1467 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1468 // = TrueProb for orignal BB.
1469 // Assuming the orignal weights are A and B, one choice is to set BB1's
1470 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1472 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1473 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1474 // TmpBB, but the math is more complicated.
1476 uint64_t NewTrueWeight = TWeight;
1477 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1478 ScaleWeights(NewTrueWeight, NewFalseWeight);
1479 // Emit the LHS condition.
1480 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1481 NewTrueWeight, NewFalseWeight);
1483 NewTrueWeight = TWeight;
1484 NewFalseWeight = 2 * (uint64_t)FWeight;
1485 ScaleWeights(NewTrueWeight, NewFalseWeight);
1486 // Emit the RHS condition into TmpBB.
1487 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1488 NewTrueWeight, NewFalseWeight);
1490 assert(Opc == Instruction::And && "Unknown merge op!");
1491 // Codegen X & Y as:
1499 // This requires creation of TmpBB after CurBB.
1501 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1502 // The requirement is that
1503 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1504 // = FalseProb for orignal BB.
1505 // Assuming the orignal weights are A and B, one choice is to set BB1's
1506 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1508 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1510 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1511 uint64_t NewFalseWeight = FWeight;
1512 ScaleWeights(NewTrueWeight, NewFalseWeight);
1513 // Emit the LHS condition.
1514 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1515 NewTrueWeight, NewFalseWeight);
1517 NewTrueWeight = 2 * (uint64_t)TWeight;
1518 NewFalseWeight = FWeight;
1519 ScaleWeights(NewTrueWeight, NewFalseWeight);
1520 // Emit the RHS condition into TmpBB.
1521 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1522 NewTrueWeight, NewFalseWeight);
1526 /// If the set of cases should be emitted as a series of branches, return true.
1527 /// If we should emit this as a bunch of and/or'd together conditions, return
1530 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1531 if (Cases.size() != 2) return true;
1533 // If this is two comparisons of the same values or'd or and'd together, they
1534 // will get folded into a single comparison, so don't emit two blocks.
1535 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1536 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1537 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1538 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1542 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1543 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1544 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1545 Cases[0].CC == Cases[1].CC &&
1546 isa<Constant>(Cases[0].CmpRHS) &&
1547 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1548 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1550 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1557 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1558 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1560 // Update machine-CFG edges.
1561 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1563 // Figure out which block is immediately after the current one.
1564 MachineBasicBlock *NextBlock = nullptr;
1565 MachineFunction::iterator BBI = BrMBB;
1566 if (++BBI != FuncInfo.MF->end())
1569 if (I.isUnconditional()) {
1570 // Update machine-CFG edges.
1571 BrMBB->addSuccessor(Succ0MBB);
1573 // If this is not a fall-through branch or optimizations are switched off,
1575 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1576 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1577 MVT::Other, getControlRoot(),
1578 DAG.getBasicBlock(Succ0MBB)));
1583 // If this condition is one of the special cases we handle, do special stuff
1585 const Value *CondVal = I.getCondition();
1586 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1588 // If this is a series of conditions that are or'd or and'd together, emit
1589 // this as a sequence of branches instead of setcc's with and/or operations.
1590 // As long as jumps are not expensive, this should improve performance.
1591 // For example, instead of something like:
1604 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1605 if (!TM.getSubtargetImpl()->getTargetLowering()->isJumpExpensive() &&
1606 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1607 BOp->getOpcode() == Instruction::Or)) {
1608 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1609 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1610 getEdgeWeight(BrMBB, Succ1MBB));
1611 // If the compares in later blocks need to use values not currently
1612 // exported from this block, export them now. This block should always
1613 // be the first entry.
1614 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1616 // Allow some cases to be rejected.
1617 if (ShouldEmitAsBranches(SwitchCases)) {
1618 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1619 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1620 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1623 // Emit the branch for this block.
1624 visitSwitchCase(SwitchCases[0], BrMBB);
1625 SwitchCases.erase(SwitchCases.begin());
1629 // Okay, we decided not to do this, remove any inserted MBB's and clear
1631 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1632 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1634 SwitchCases.clear();
1638 // Create a CaseBlock record representing this branch.
1639 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1640 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1642 // Use visitSwitchCase to actually insert the fast branch sequence for this
1644 visitSwitchCase(CB, BrMBB);
1647 /// visitSwitchCase - Emits the necessary code to represent a single node in
1648 /// the binary search tree resulting from lowering a switch instruction.
1649 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1650 MachineBasicBlock *SwitchBB) {
1652 SDValue CondLHS = getValue(CB.CmpLHS);
1653 SDLoc dl = getCurSDLoc();
1655 // Build the setcc now.
1657 // Fold "(X == true)" to X and "(X == false)" to !X to
1658 // handle common cases produced by branch lowering.
1659 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1660 CB.CC == ISD::SETEQ)
1662 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1663 CB.CC == ISD::SETEQ) {
1664 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1665 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1667 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1669 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1671 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1672 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1674 SDValue CmpOp = getValue(CB.CmpMHS);
1675 EVT VT = CmpOp.getValueType();
1677 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1678 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1681 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1682 VT, CmpOp, DAG.getConstant(Low, VT));
1683 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1684 DAG.getConstant(High-Low, VT), ISD::SETULE);
1688 // Update successor info
1689 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1690 // TrueBB and FalseBB are always different unless the incoming IR is
1691 // degenerate. This only happens when running llc on weird IR.
1692 if (CB.TrueBB != CB.FalseBB)
1693 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1695 // Set NextBlock to be the MBB immediately after the current one, if any.
1696 // This is used to avoid emitting unnecessary branches to the next block.
1697 MachineBasicBlock *NextBlock = nullptr;
1698 MachineFunction::iterator BBI = SwitchBB;
1699 if (++BBI != FuncInfo.MF->end())
1702 // If the lhs block is the next block, invert the condition so that we can
1703 // fall through to the lhs instead of the rhs block.
1704 if (CB.TrueBB == NextBlock) {
1705 std::swap(CB.TrueBB, CB.FalseBB);
1706 SDValue True = DAG.getConstant(1, Cond.getValueType());
1707 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1710 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1711 MVT::Other, getControlRoot(), Cond,
1712 DAG.getBasicBlock(CB.TrueBB));
1714 // Insert the false branch. Do this even if it's a fall through branch,
1715 // this makes it easier to do DAG optimizations which require inverting
1716 // the branch condition.
1717 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1718 DAG.getBasicBlock(CB.FalseBB));
1720 DAG.setRoot(BrCond);
1723 /// visitJumpTable - Emit JumpTable node in the current MBB
1724 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1725 // Emit the code for the jump table
1726 assert(JT.Reg != -1U && "Should lower JT Header first!");
1727 EVT PTy = TM.getSubtargetImpl()->getTargetLowering()->getPointerTy();
1728 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1730 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1731 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1732 MVT::Other, Index.getValue(1),
1734 DAG.setRoot(BrJumpTable);
1737 /// visitJumpTableHeader - This function emits necessary code to produce index
1738 /// in the JumpTable from switch case.
1739 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1740 JumpTableHeader &JTH,
1741 MachineBasicBlock *SwitchBB) {
1742 // Subtract the lowest switch case value from the value being switched on and
1743 // conditional branch to default mbb if the result is greater than the
1744 // difference between smallest and largest cases.
1745 SDValue SwitchOp = getValue(JTH.SValue);
1746 EVT VT = SwitchOp.getValueType();
1747 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1748 DAG.getConstant(JTH.First, VT));
1750 // The SDNode we just created, which holds the value being switched on minus
1751 // the smallest case value, needs to be copied to a virtual register so it
1752 // can be used as an index into the jump table in a subsequent basic block.
1753 // This value may be smaller or larger than the target's pointer type, and
1754 // therefore require extension or truncating.
1755 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1756 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1758 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1759 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1760 JumpTableReg, SwitchOp);
1761 JT.Reg = JumpTableReg;
1763 // Emit the range check for the jump table, and branch to the default block
1764 // for the switch statement if the value being switched on exceeds the largest
1765 // case in the switch.
1766 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1767 TLI->getSetCCResultType(*DAG.getContext(),
1768 Sub.getValueType()),
1770 DAG.getConstant(JTH.Last - JTH.First,VT),
1773 // Set NextBlock to be the MBB immediately after the current one, if any.
1774 // This is used to avoid emitting unnecessary branches to the next block.
1775 MachineBasicBlock *NextBlock = nullptr;
1776 MachineFunction::iterator BBI = SwitchBB;
1778 if (++BBI != FuncInfo.MF->end())
1781 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1782 MVT::Other, CopyTo, CMP,
1783 DAG.getBasicBlock(JT.Default));
1785 if (JT.MBB != NextBlock)
1786 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1787 DAG.getBasicBlock(JT.MBB));
1789 DAG.setRoot(BrCond);
1792 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1793 /// tail spliced into a stack protector check success bb.
1795 /// For a high level explanation of how this fits into the stack protector
1796 /// generation see the comment on the declaration of class
1797 /// StackProtectorDescriptor.
1798 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1799 MachineBasicBlock *ParentBB) {
1801 // First create the loads to the guard/stack slot for the comparison.
1802 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1803 EVT PtrTy = TLI->getPointerTy();
1805 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1806 int FI = MFI->getStackProtectorIndex();
1808 const Value *IRGuard = SPD.getGuard();
1809 SDValue GuardPtr = getValue(IRGuard);
1810 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1813 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1817 // If useLoadStackGuardNode returns true, retrieve the guard value from
1818 // the virtual register holding the value. Otherwise, emit a volatile load
1819 // to retrieve the stack guard value.
1820 if (TLI->useLoadStackGuardNode())
1821 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1822 SPD.getGuardReg(), PtrTy);
1824 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1825 GuardPtr, MachinePointerInfo(IRGuard, 0),
1826 true, false, false, Align);
1828 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1830 MachinePointerInfo::getFixedStack(FI),
1831 true, false, false, Align);
1833 // Perform the comparison via a subtract/getsetcc.
1834 EVT VT = Guard.getValueType();
1835 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1837 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1838 TLI->getSetCCResultType(*DAG.getContext(),
1839 Sub.getValueType()),
1840 Sub, DAG.getConstant(0, VT),
1843 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1844 // branch to failure MBB.
1845 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1846 MVT::Other, StackSlot.getOperand(0),
1847 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1848 // Otherwise branch to success MBB.
1849 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1851 DAG.getBasicBlock(SPD.getSuccessMBB()));
1856 /// Codegen the failure basic block for a stack protector check.
1858 /// A failure stack protector machine basic block consists simply of a call to
1859 /// __stack_chk_fail().
1861 /// For a high level explanation of how this fits into the stack protector
1862 /// generation see the comment on the declaration of class
1863 /// StackProtectorDescriptor.
1865 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1866 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1867 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1868 MVT::isVoid, nullptr, 0, false,
1869 getCurSDLoc(), false, false).second;
1873 /// visitBitTestHeader - This function emits necessary code to produce value
1874 /// suitable for "bit tests"
1875 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1876 MachineBasicBlock *SwitchBB) {
1877 // Subtract the minimum value
1878 SDValue SwitchOp = getValue(B.SValue);
1879 EVT VT = SwitchOp.getValueType();
1880 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1881 DAG.getConstant(B.First, VT));
1884 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1885 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1886 TLI->getSetCCResultType(*DAG.getContext(),
1887 Sub.getValueType()),
1888 Sub, DAG.getConstant(B.Range, VT),
1891 // Determine the type of the test operands.
1892 bool UsePtrType = false;
1893 if (!TLI->isTypeLegal(VT))
1896 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1897 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1898 // Switch table case range are encoded into series of masks.
1899 // Just use pointer type, it's guaranteed to fit.
1905 VT = TLI->getPointerTy();
1906 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1909 B.RegVT = VT.getSimpleVT();
1910 B.Reg = FuncInfo.CreateReg(B.RegVT);
1911 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1914 // Set NextBlock to be the MBB immediately after the current one, if any.
1915 // This is used to avoid emitting unnecessary branches to the next block.
1916 MachineBasicBlock *NextBlock = nullptr;
1917 MachineFunction::iterator BBI = SwitchBB;
1918 if (++BBI != FuncInfo.MF->end())
1921 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1923 addSuccessorWithWeight(SwitchBB, B.Default);
1924 addSuccessorWithWeight(SwitchBB, MBB);
1926 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1927 MVT::Other, CopyTo, RangeCmp,
1928 DAG.getBasicBlock(B.Default));
1930 if (MBB != NextBlock)
1931 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1932 DAG.getBasicBlock(MBB));
1934 DAG.setRoot(BrRange);
1937 /// visitBitTestCase - this function produces one "bit test"
1938 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1939 MachineBasicBlock* NextMBB,
1940 uint32_t BranchWeightToNext,
1943 MachineBasicBlock *SwitchBB) {
1945 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1948 unsigned PopCount = CountPopulation_64(B.Mask);
1949 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
1950 if (PopCount == 1) {
1951 // Testing for a single bit; just compare the shift count with what it
1952 // would need to be to shift a 1 bit in that position.
1953 Cmp = DAG.getSetCC(getCurSDLoc(),
1954 TLI->getSetCCResultType(*DAG.getContext(), VT),
1956 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1958 } else if (PopCount == BB.Range) {
1959 // There is only one zero bit in the range, test for it directly.
1960 Cmp = DAG.getSetCC(getCurSDLoc(),
1961 TLI->getSetCCResultType(*DAG.getContext(), VT),
1963 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1966 // Make desired shift
1967 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1968 DAG.getConstant(1, VT), ShiftOp);
1970 // Emit bit tests and jumps
1971 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1972 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1973 Cmp = DAG.getSetCC(getCurSDLoc(),
1974 TLI->getSetCCResultType(*DAG.getContext(), VT),
1975 AndOp, DAG.getConstant(0, VT),
1979 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1980 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1981 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1982 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1984 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1985 MVT::Other, getControlRoot(),
1986 Cmp, DAG.getBasicBlock(B.TargetBB));
1988 // Set NextBlock to be the MBB immediately after the current one, if any.
1989 // This is used to avoid emitting unnecessary branches to the next block.
1990 MachineBasicBlock *NextBlock = nullptr;
1991 MachineFunction::iterator BBI = SwitchBB;
1992 if (++BBI != FuncInfo.MF->end())
1995 if (NextMBB != NextBlock)
1996 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1997 DAG.getBasicBlock(NextMBB));
2002 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2003 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2005 // Retrieve successors.
2006 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2007 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2009 const Value *Callee(I.getCalledValue());
2010 const Function *Fn = dyn_cast<Function>(Callee);
2011 if (isa<InlineAsm>(Callee))
2013 else if (Fn && Fn->isIntrinsic()) {
2014 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2015 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2017 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2019 // If the value of the invoke is used outside of its defining block, make it
2020 // available as a virtual register.
2021 CopyToExportRegsIfNeeded(&I);
2023 // Update successor info
2024 addSuccessorWithWeight(InvokeMBB, Return);
2025 addSuccessorWithWeight(InvokeMBB, LandingPad);
2027 // Drop into normal successor.
2028 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2029 MVT::Other, getControlRoot(),
2030 DAG.getBasicBlock(Return)));
2033 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2034 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2037 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2038 assert(FuncInfo.MBB->isLandingPad() &&
2039 "Call to landingpad not in landing pad!");
2041 MachineBasicBlock *MBB = FuncInfo.MBB;
2042 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2043 AddLandingPadInfo(LP, MMI, MBB);
2045 // If there aren't registers to copy the values into (e.g., during SjLj
2046 // exceptions), then don't bother to create these DAG nodes.
2047 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2048 if (TLI->getExceptionPointerRegister() == 0 &&
2049 TLI->getExceptionSelectorRegister() == 0)
2052 SmallVector<EVT, 2> ValueVTs;
2053 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2054 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2056 // Get the two live-in registers as SDValues. The physregs have already been
2057 // copied into virtual registers.
2059 Ops[0] = DAG.getZExtOrTrunc(
2060 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2061 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2062 getCurSDLoc(), ValueVTs[0]);
2063 Ops[1] = DAG.getZExtOrTrunc(
2064 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2065 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2066 getCurSDLoc(), ValueVTs[1]);
2069 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2070 DAG.getVTList(ValueVTs), Ops);
2074 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2075 /// small case ranges).
2076 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2077 CaseRecVector& WorkList,
2079 MachineBasicBlock *Default,
2080 MachineBasicBlock *SwitchBB) {
2081 // Size is the number of Cases represented by this range.
2082 size_t Size = CR.Range.second - CR.Range.first;
2086 // Get the MachineFunction which holds the current MBB. This is used when
2087 // inserting any additional MBBs necessary to represent the switch.
2088 MachineFunction *CurMF = FuncInfo.MF;
2090 // Figure out which block is immediately after the current one.
2091 MachineBasicBlock *NextBlock = nullptr;
2092 MachineFunction::iterator BBI = CR.CaseBB;
2094 if (++BBI != FuncInfo.MF->end())
2097 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2098 // If any two of the cases has the same destination, and if one value
2099 // is the same as the other, but has one bit unset that the other has set,
2100 // use bit manipulation to do two compares at once. For example:
2101 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2102 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2103 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2104 if (Size == 2 && CR.CaseBB == SwitchBB) {
2105 Case &Small = *CR.Range.first;
2106 Case &Big = *(CR.Range.second-1);
2108 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2109 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2110 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2112 // Check that there is only one bit different.
2113 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2114 (SmallValue | BigValue) == BigValue) {
2115 // Isolate the common bit.
2116 APInt CommonBit = BigValue & ~SmallValue;
2117 assert((SmallValue | CommonBit) == BigValue &&
2118 CommonBit.countPopulation() == 1 && "Not a common bit?");
2120 SDValue CondLHS = getValue(SV);
2121 EVT VT = CondLHS.getValueType();
2122 SDLoc DL = getCurSDLoc();
2124 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2125 DAG.getConstant(CommonBit, VT));
2126 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2127 Or, DAG.getConstant(BigValue, VT),
2130 // Update successor info.
2131 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2132 addSuccessorWithWeight(SwitchBB, Small.BB,
2133 Small.ExtraWeight + Big.ExtraWeight);
2134 addSuccessorWithWeight(SwitchBB, Default,
2135 // The default destination is the first successor in IR.
2136 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2138 // Insert the true branch.
2139 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2140 getControlRoot(), Cond,
2141 DAG.getBasicBlock(Small.BB));
2143 // Insert the false branch.
2144 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2145 DAG.getBasicBlock(Default));
2147 DAG.setRoot(BrCond);
2153 // Order cases by weight so the most likely case will be checked first.
2154 uint32_t UnhandledWeights = 0;
2156 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2157 uint32_t IWeight = I->ExtraWeight;
2158 UnhandledWeights += IWeight;
2159 for (CaseItr J = CR.Range.first; J < I; ++J) {
2160 uint32_t JWeight = J->ExtraWeight;
2161 if (IWeight > JWeight)
2166 // Rearrange the case blocks so that the last one falls through if possible.
2167 Case &BackCase = *(CR.Range.second-1);
2169 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2170 // The last case block won't fall through into 'NextBlock' if we emit the
2171 // branches in this order. See if rearranging a case value would help.
2172 // We start at the bottom as it's the case with the least weight.
2173 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2174 if (I->BB == NextBlock) {
2175 std::swap(*I, BackCase);
2180 // Create a CaseBlock record representing a conditional branch to
2181 // the Case's target mbb if the value being switched on SV is equal
2183 MachineBasicBlock *CurBlock = CR.CaseBB;
2184 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2185 MachineBasicBlock *FallThrough;
2187 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2188 CurMF->insert(BBI, FallThrough);
2190 // Put SV in a virtual register to make it available from the new blocks.
2191 ExportFromCurrentBlock(SV);
2193 // If the last case doesn't match, go to the default block.
2194 FallThrough = Default;
2197 const Value *RHS, *LHS, *MHS;
2199 if (I->High == I->Low) {
2200 // This is just small small case range :) containing exactly 1 case
2202 LHS = SV; RHS = I->High; MHS = nullptr;
2205 LHS = I->Low; MHS = SV; RHS = I->High;
2208 // The false weight should be sum of all un-handled cases.
2209 UnhandledWeights -= I->ExtraWeight;
2210 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2212 /* trueweight */ I->ExtraWeight,
2213 /* falseweight */ UnhandledWeights);
2215 // If emitting the first comparison, just call visitSwitchCase to emit the
2216 // code into the current block. Otherwise, push the CaseBlock onto the
2217 // vector to be later processed by SDISel, and insert the node's MBB
2218 // before the next MBB.
2219 if (CurBlock == SwitchBB)
2220 visitSwitchCase(CB, SwitchBB);
2222 SwitchCases.push_back(CB);
2224 CurBlock = FallThrough;
2230 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2231 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2232 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2235 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2236 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2237 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2238 return (LastExt - FirstExt + 1ULL);
2241 /// handleJTSwitchCase - Emit jumptable for current switch case range
2242 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2243 CaseRecVector &WorkList,
2245 MachineBasicBlock *Default,
2246 MachineBasicBlock *SwitchBB) {
2247 Case& FrontCase = *CR.Range.first;
2248 Case& BackCase = *(CR.Range.second-1);
2250 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2251 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2253 APInt TSize(First.getBitWidth(), 0);
2254 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2257 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2258 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2261 APInt Range = ComputeRange(First, Last);
2262 // The density is TSize / Range. Require at least 40%.
2263 // It should not be possible for IntTSize to saturate for sane code, but make
2264 // sure we handle Range saturation correctly.
2265 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2266 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2267 if (IntTSize * 10 < IntRange * 4)
2270 DEBUG(dbgs() << "Lowering jump table\n"
2271 << "First entry: " << First << ". Last entry: " << Last << '\n'
2272 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2274 // Get the MachineFunction which holds the current MBB. This is used when
2275 // inserting any additional MBBs necessary to represent the switch.
2276 MachineFunction *CurMF = FuncInfo.MF;
2278 // Figure out which block is immediately after the current one.
2279 MachineFunction::iterator BBI = CR.CaseBB;
2282 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2284 // Create a new basic block to hold the code for loading the address
2285 // of the jump table, and jumping to it. Update successor information;
2286 // we will either branch to the default case for the switch, or the jump
2288 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2289 CurMF->insert(BBI, JumpTableBB);
2291 addSuccessorWithWeight(CR.CaseBB, Default);
2292 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2294 // Build a vector of destination BBs, corresponding to each target
2295 // of the jump table. If the value of the jump table slot corresponds to
2296 // a case statement, push the case's BB onto the vector, otherwise, push
2298 std::vector<MachineBasicBlock*> DestBBs;
2300 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2301 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2302 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2304 if (Low.sle(TEI) && TEI.sle(High)) {
2305 DestBBs.push_back(I->BB);
2309 DestBBs.push_back(Default);
2313 // Calculate weight for each unique destination in CR.
2314 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2316 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2317 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2318 DestWeights.find(I->BB);
2319 if (Itr != DestWeights.end())
2320 Itr->second += I->ExtraWeight;
2322 DestWeights[I->BB] = I->ExtraWeight;
2325 // Update successor info. Add one edge to each unique successor.
2326 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2327 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2328 E = DestBBs.end(); I != E; ++I) {
2329 if (!SuccsHandled[(*I)->getNumber()]) {
2330 SuccsHandled[(*I)->getNumber()] = true;
2331 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2332 DestWeights.find(*I);
2333 addSuccessorWithWeight(JumpTableBB, *I,
2334 Itr != DestWeights.end() ? Itr->second : 0);
2338 // Create a jump table index for this jump table.
2339 unsigned JTEncoding = TLI->getJumpTableEncoding();
2340 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2341 ->createJumpTableIndex(DestBBs);
2343 // Set the jump table information so that we can codegen it as a second
2344 // MachineBasicBlock
2345 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2346 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2347 if (CR.CaseBB == SwitchBB)
2348 visitJumpTableHeader(JT, JTH, SwitchBB);
2350 JTCases.push_back(JumpTableBlock(JTH, JT));
2354 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2356 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2357 CaseRecVector& WorkList,
2359 MachineBasicBlock* Default,
2360 MachineBasicBlock* SwitchBB) {
2361 // Get the MachineFunction which holds the current MBB. This is used when
2362 // inserting any additional MBBs necessary to represent the switch.
2363 MachineFunction *CurMF = FuncInfo.MF;
2365 // Figure out which block is immediately after the current one.
2366 MachineFunction::iterator BBI = CR.CaseBB;
2369 Case& FrontCase = *CR.Range.first;
2370 Case& BackCase = *(CR.Range.second-1);
2371 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2373 // Size is the number of Cases represented by this range.
2374 unsigned Size = CR.Range.second - CR.Range.first;
2376 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2377 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2379 CaseItr Pivot = CR.Range.first + Size/2;
2381 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2382 // (heuristically) allow us to emit JumpTable's later.
2383 APInt TSize(First.getBitWidth(), 0);
2384 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2388 APInt LSize = FrontCase.size();
2389 APInt RSize = TSize-LSize;
2390 DEBUG(dbgs() << "Selecting best pivot: \n"
2391 << "First: " << First << ", Last: " << Last <<'\n'
2392 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2393 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2395 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2396 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2397 APInt Range = ComputeRange(LEnd, RBegin);
2398 assert((Range - 2ULL).isNonNegative() &&
2399 "Invalid case distance");
2400 // Use volatile double here to avoid excess precision issues on some hosts,
2401 // e.g. that use 80-bit X87 registers.
2402 volatile double LDensity =
2403 (double)LSize.roundToDouble() /
2404 (LEnd - First + 1ULL).roundToDouble();
2405 volatile double RDensity =
2406 (double)RSize.roundToDouble() /
2407 (Last - RBegin + 1ULL).roundToDouble();
2408 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2409 // Should always split in some non-trivial place
2410 DEBUG(dbgs() <<"=>Step\n"
2411 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2412 << "LDensity: " << LDensity
2413 << ", RDensity: " << RDensity << '\n'
2414 << "Metric: " << Metric << '\n');
2415 if (FMetric < Metric) {
2418 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2425 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2426 if (areJTsAllowed(*TLI)) {
2427 // If our case is dense we *really* should handle it earlier!
2428 assert((FMetric > 0) && "Should handle dense range earlier!");
2430 Pivot = CR.Range.first + Size/2;
2433 CaseRange LHSR(CR.Range.first, Pivot);
2434 CaseRange RHSR(Pivot, CR.Range.second);
2435 const Constant *C = Pivot->Low;
2436 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2438 // We know that we branch to the LHS if the Value being switched on is
2439 // less than the Pivot value, C. We use this to optimize our binary
2440 // tree a bit, by recognizing that if SV is greater than or equal to the
2441 // LHS's Case Value, and that Case Value is exactly one less than the
2442 // Pivot's Value, then we can branch directly to the LHS's Target,
2443 // rather than creating a leaf node for it.
2444 if ((LHSR.second - LHSR.first) == 1 &&
2445 LHSR.first->High == CR.GE &&
2446 cast<ConstantInt>(C)->getValue() ==
2447 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2448 TrueBB = LHSR.first->BB;
2450 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2451 CurMF->insert(BBI, TrueBB);
2452 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2454 // Put SV in a virtual register to make it available from the new blocks.
2455 ExportFromCurrentBlock(SV);
2458 // Similar to the optimization above, if the Value being switched on is
2459 // known to be less than the Constant CR.LT, and the current Case Value
2460 // is CR.LT - 1, then we can branch directly to the target block for
2461 // the current Case Value, rather than emitting a RHS leaf node for it.
2462 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2463 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2464 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2465 FalseBB = RHSR.first->BB;
2467 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2468 CurMF->insert(BBI, FalseBB);
2469 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2471 // Put SV in a virtual register to make it available from the new blocks.
2472 ExportFromCurrentBlock(SV);
2475 // Create a CaseBlock record representing a conditional branch to
2476 // the LHS node if the value being switched on SV is less than C.
2477 // Otherwise, branch to LHS.
2478 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2480 if (CR.CaseBB == SwitchBB)
2481 visitSwitchCase(CB, SwitchBB);
2483 SwitchCases.push_back(CB);
2488 /// handleBitTestsSwitchCase - if current case range has few destination and
2489 /// range span less, than machine word bitwidth, encode case range into series
2490 /// of masks and emit bit tests with these masks.
2491 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2492 CaseRecVector& WorkList,
2494 MachineBasicBlock* Default,
2495 MachineBasicBlock* SwitchBB) {
2496 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2497 EVT PTy = TLI->getPointerTy();
2498 unsigned IntPtrBits = PTy.getSizeInBits();
2500 Case& FrontCase = *CR.Range.first;
2501 Case& BackCase = *(CR.Range.second-1);
2503 // Get the MachineFunction which holds the current MBB. This is used when
2504 // inserting any additional MBBs necessary to represent the switch.
2505 MachineFunction *CurMF = FuncInfo.MF;
2507 // If target does not have legal shift left, do not emit bit tests at all.
2508 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2512 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2514 // Single case counts one, case range - two.
2515 numCmps += (I->Low == I->High ? 1 : 2);
2518 // Count unique destinations
2519 SmallSet<MachineBasicBlock*, 4> Dests;
2520 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2521 Dests.insert(I->BB);
2522 if (Dests.size() > 3)
2523 // Don't bother the code below, if there are too much unique destinations
2526 DEBUG(dbgs() << "Total number of unique destinations: "
2527 << Dests.size() << '\n'
2528 << "Total number of comparisons: " << numCmps << '\n');
2530 // Compute span of values.
2531 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2532 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2533 APInt cmpRange = maxValue - minValue;
2535 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2536 << "Low bound: " << minValue << '\n'
2537 << "High bound: " << maxValue << '\n');
2539 if (cmpRange.uge(IntPtrBits) ||
2540 (!(Dests.size() == 1 && numCmps >= 3) &&
2541 !(Dests.size() == 2 && numCmps >= 5) &&
2542 !(Dests.size() >= 3 && numCmps >= 6)))
2545 DEBUG(dbgs() << "Emitting bit tests\n");
2546 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2548 // Optimize the case where all the case values fit in a
2549 // word without having to subtract minValue. In this case,
2550 // we can optimize away the subtraction.
2551 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2552 cmpRange = maxValue;
2554 lowBound = minValue;
2557 CaseBitsVector CasesBits;
2558 unsigned i, count = 0;
2560 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2561 MachineBasicBlock* Dest = I->BB;
2562 for (i = 0; i < count; ++i)
2563 if (Dest == CasesBits[i].BB)
2567 assert((count < 3) && "Too much destinations to test!");
2568 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2572 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2573 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2575 uint64_t lo = (lowValue - lowBound).getZExtValue();
2576 uint64_t hi = (highValue - lowBound).getZExtValue();
2577 CasesBits[i].ExtraWeight += I->ExtraWeight;
2579 for (uint64_t j = lo; j <= hi; j++) {
2580 CasesBits[i].Mask |= 1ULL << j;
2581 CasesBits[i].Bits++;
2585 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2589 // Figure out which block is immediately after the current one.
2590 MachineFunction::iterator BBI = CR.CaseBB;
2593 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2595 DEBUG(dbgs() << "Cases:\n");
2596 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2597 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2598 << ", Bits: " << CasesBits[i].Bits
2599 << ", BB: " << CasesBits[i].BB << '\n');
2601 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2602 CurMF->insert(BBI, CaseBB);
2603 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2605 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2607 // Put SV in a virtual register to make it available from the new blocks.
2608 ExportFromCurrentBlock(SV);
2611 BitTestBlock BTB(lowBound, cmpRange, SV,
2612 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2613 CR.CaseBB, Default, BTC);
2615 if (CR.CaseBB == SwitchBB)
2616 visitBitTestHeader(BTB, SwitchBB);
2618 BitTestCases.push_back(BTB);
2623 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2624 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2625 const SwitchInst& SI) {
2628 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2629 // Start with "simple" cases
2630 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2632 const BasicBlock *SuccBB = i.getCaseSuccessor();
2633 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2635 uint32_t ExtraWeight =
2636 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2638 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2639 SMBB, ExtraWeight));
2641 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2643 // Merge case into clusters
2644 if (Cases.size() >= 2)
2645 // Must recompute end() each iteration because it may be
2646 // invalidated by erase if we hold on to it
2647 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2648 J != Cases.end(); ) {
2649 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2650 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2651 MachineBasicBlock* nextBB = J->BB;
2652 MachineBasicBlock* currentBB = I->BB;
2654 // If the two neighboring cases go to the same destination, merge them
2655 // into a single case.
2656 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2658 I->ExtraWeight += J->ExtraWeight;
2665 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2666 if (I->Low != I->High)
2667 // A range counts double, since it requires two compares.
2674 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2675 MachineBasicBlock *Last) {
2677 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2678 if (JTCases[i].first.HeaderBB == First)
2679 JTCases[i].first.HeaderBB = Last;
2681 // Update BitTestCases.
2682 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2683 if (BitTestCases[i].Parent == First)
2684 BitTestCases[i].Parent = Last;
2687 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2688 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2690 // Figure out which block is immediately after the current one.
2691 MachineBasicBlock *NextBlock = nullptr;
2692 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2694 // If there is only the default destination, branch to it if it is not the
2695 // next basic block. Otherwise, just fall through.
2696 if (!SI.getNumCases()) {
2697 // Update machine-CFG edges.
2699 // If this is not a fall-through branch, emit the branch.
2700 SwitchMBB->addSuccessor(Default);
2701 if (Default != NextBlock)
2702 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2703 MVT::Other, getControlRoot(),
2704 DAG.getBasicBlock(Default)));
2709 // If there are any non-default case statements, create a vector of Cases
2710 // representing each one, and sort the vector so that we can efficiently
2711 // create a binary search tree from them.
2713 size_t numCmps = Clusterify(Cases, SI);
2714 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2715 << ". Total compares: " << numCmps << '\n');
2718 // Get the Value to be switched on and default basic blocks, which will be
2719 // inserted into CaseBlock records, representing basic blocks in the binary
2721 const Value *SV = SI.getCondition();
2723 // Push the initial CaseRec onto the worklist
2724 CaseRecVector WorkList;
2725 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2726 CaseRange(Cases.begin(),Cases.end())));
2728 while (!WorkList.empty()) {
2729 // Grab a record representing a case range to process off the worklist
2730 CaseRec CR = WorkList.back();
2731 WorkList.pop_back();
2733 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2736 // If the range has few cases (two or less) emit a series of specific
2738 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2741 // If the switch has more than N blocks, and is at least 40% dense, and the
2742 // target supports indirect branches, then emit a jump table rather than
2743 // lowering the switch to a binary tree of conditional branches.
2744 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2745 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2748 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2749 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2750 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2754 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2755 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2757 // Update machine-CFG edges with unique successors.
2758 SmallSet<BasicBlock*, 32> Done;
2759 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2760 BasicBlock *BB = I.getSuccessor(i);
2761 bool Inserted = Done.insert(BB);
2765 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2766 addSuccessorWithWeight(IndirectBrMBB, Succ);
2769 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2770 MVT::Other, getControlRoot(),
2771 getValue(I.getAddress())));
2774 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2775 if (DAG.getTarget().Options.TrapUnreachable)
2776 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2779 void SelectionDAGBuilder::visitFSub(const User &I) {
2780 // -0.0 - X --> fneg
2781 Type *Ty = I.getType();
2782 if (isa<Constant>(I.getOperand(0)) &&
2783 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2784 SDValue Op2 = getValue(I.getOperand(1));
2785 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2786 Op2.getValueType(), Op2));
2790 visitBinary(I, ISD::FSUB);
2793 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2794 SDValue Op1 = getValue(I.getOperand(0));
2795 SDValue Op2 = getValue(I.getOperand(1));
2800 if (const OverflowingBinaryOperator *OFBinOp =
2801 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2802 nuw = OFBinOp->hasNoUnsignedWrap();
2803 nsw = OFBinOp->hasNoSignedWrap();
2805 if (const PossiblyExactOperator *ExactOp =
2806 dyn_cast<const PossiblyExactOperator>(&I))
2807 exact = ExactOp->isExact();
2809 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2810 Op1, Op2, nuw, nsw, exact);
2811 setValue(&I, BinNodeValue);
2814 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2815 SDValue Op1 = getValue(I.getOperand(0));
2816 SDValue Op2 = getValue(I.getOperand(1));
2818 EVT ShiftTy = TM.getSubtargetImpl()->getTargetLowering()->getShiftAmountTy(
2819 Op2.getValueType());
2821 // Coerce the shift amount to the right type if we can.
2822 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2823 unsigned ShiftSize = ShiftTy.getSizeInBits();
2824 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2825 SDLoc DL = getCurSDLoc();
2827 // If the operand is smaller than the shift count type, promote it.
2828 if (ShiftSize > Op2Size)
2829 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2831 // If the operand is larger than the shift count type but the shift
2832 // count type has enough bits to represent any shift value, truncate
2833 // it now. This is a common case and it exposes the truncate to
2834 // optimization early.
2835 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2836 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2837 // Otherwise we'll need to temporarily settle for some other convenient
2838 // type. Type legalization will make adjustments once the shiftee is split.
2840 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2847 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2849 if (const OverflowingBinaryOperator *OFBinOp =
2850 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2851 nuw = OFBinOp->hasNoUnsignedWrap();
2852 nsw = OFBinOp->hasNoSignedWrap();
2854 if (const PossiblyExactOperator *ExactOp =
2855 dyn_cast<const PossiblyExactOperator>(&I))
2856 exact = ExactOp->isExact();
2859 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2864 void SelectionDAGBuilder::visitSDiv(const User &I) {
2865 SDValue Op1 = getValue(I.getOperand(0));
2866 SDValue Op2 = getValue(I.getOperand(1));
2868 // Turn exact SDivs into multiplications.
2869 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2871 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2872 !isa<ConstantSDNode>(Op1) &&
2873 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2874 setValue(&I, TM.getSubtargetImpl()->getTargetLowering()->BuildExactSDIV(
2875 Op1, Op2, getCurSDLoc(), DAG));
2877 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2881 void SelectionDAGBuilder::visitICmp(const User &I) {
2882 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2883 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2884 predicate = IC->getPredicate();
2885 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2886 predicate = ICmpInst::Predicate(IC->getPredicate());
2887 SDValue Op1 = getValue(I.getOperand(0));
2888 SDValue Op2 = getValue(I.getOperand(1));
2889 ISD::CondCode Opcode = getICmpCondCode(predicate);
2892 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2893 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2896 void SelectionDAGBuilder::visitFCmp(const User &I) {
2897 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2898 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2899 predicate = FC->getPredicate();
2900 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2901 predicate = FCmpInst::Predicate(FC->getPredicate());
2902 SDValue Op1 = getValue(I.getOperand(0));
2903 SDValue Op2 = getValue(I.getOperand(1));
2904 ISD::CondCode Condition = getFCmpCondCode(predicate);
2905 if (TM.Options.NoNaNsFPMath)
2906 Condition = getFCmpCodeWithoutNaN(Condition);
2908 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2909 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2912 void SelectionDAGBuilder::visitSelect(const User &I) {
2913 SmallVector<EVT, 4> ValueVTs;
2914 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), I.getType(),
2916 unsigned NumValues = ValueVTs.size();
2917 if (NumValues == 0) return;
2919 SmallVector<SDValue, 4> Values(NumValues);
2920 SDValue Cond = getValue(I.getOperand(0));
2921 SDValue TrueVal = getValue(I.getOperand(1));
2922 SDValue FalseVal = getValue(I.getOperand(2));
2923 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2924 ISD::VSELECT : ISD::SELECT;
2926 for (unsigned i = 0; i != NumValues; ++i)
2927 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2928 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2930 SDValue(TrueVal.getNode(),
2931 TrueVal.getResNo() + i),
2932 SDValue(FalseVal.getNode(),
2933 FalseVal.getResNo() + i));
2935 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2936 DAG.getVTList(ValueVTs), Values));
2939 void SelectionDAGBuilder::visitTrunc(const User &I) {
2940 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2941 SDValue N = getValue(I.getOperand(0));
2943 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2944 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2947 void SelectionDAGBuilder::visitZExt(const User &I) {
2948 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2949 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2950 SDValue N = getValue(I.getOperand(0));
2952 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2953 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2956 void SelectionDAGBuilder::visitSExt(const User &I) {
2957 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2958 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2959 SDValue N = getValue(I.getOperand(0));
2961 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2962 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2965 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2966 // FPTrunc is never a no-op cast, no need to check
2967 SDValue N = getValue(I.getOperand(0));
2968 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
2969 EVT DestVT = TLI->getValueType(I.getType());
2970 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2972 DAG.getTargetConstant(0, TLI->getPointerTy())));
2975 void SelectionDAGBuilder::visitFPExt(const User &I) {
2976 // FPExt is never a no-op cast, no need to check
2977 SDValue N = getValue(I.getOperand(0));
2979 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2980 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2983 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2984 // FPToUI is never a no-op cast, no need to check
2985 SDValue N = getValue(I.getOperand(0));
2987 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2988 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2991 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2992 // FPToSI is never a no-op cast, no need to check
2993 SDValue N = getValue(I.getOperand(0));
2995 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
2996 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2999 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3000 // UIToFP is never a no-op cast, no need to check
3001 SDValue N = getValue(I.getOperand(0));
3003 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3004 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3007 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3008 // SIToFP is never a no-op cast, no need to check
3009 SDValue N = getValue(I.getOperand(0));
3011 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3012 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3015 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3016 // What to do depends on the size of the integer and the size of the pointer.
3017 // We can either truncate, zero extend, or no-op, accordingly.
3018 SDValue N = getValue(I.getOperand(0));
3020 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3021 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3024 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3025 // What to do depends on the size of the integer and the size of the pointer.
3026 // We can either truncate, zero extend, or no-op, accordingly.
3027 SDValue N = getValue(I.getOperand(0));
3029 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3030 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3033 void SelectionDAGBuilder::visitBitCast(const User &I) {
3034 SDValue N = getValue(I.getOperand(0));
3036 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3038 // BitCast assures us that source and destination are the same size so this is
3039 // either a BITCAST or a no-op.
3040 if (DestVT != N.getValueType())
3041 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3042 DestVT, N)); // convert types.
3043 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3044 // might fold any kind of constant expression to an integer constant and that
3045 // is not what we are looking for. Only regcognize a bitcast of a genuine
3046 // constant integer as an opaque constant.
3047 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3048 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3051 setValue(&I, N); // noop cast.
3054 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3055 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3056 const Value *SV = I.getOperand(0);
3057 SDValue N = getValue(SV);
3059 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
3061 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3062 unsigned DestAS = I.getType()->getPointerAddressSpace();
3064 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3065 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3070 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3071 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3072 SDValue InVec = getValue(I.getOperand(0));
3073 SDValue InVal = getValue(I.getOperand(1));
3074 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3075 getCurSDLoc(), TLI.getVectorIdxTy());
3077 DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3078 TM.getSubtargetImpl()->getTargetLowering()->getValueType(
3080 InVec, InVal, InIdx));
3083 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3085 SDValue InVec = getValue(I.getOperand(0));
3086 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3087 getCurSDLoc(), TLI.getVectorIdxTy());
3089 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3090 TM.getSubtargetImpl()->getTargetLowering()->getValueType(
3095 // Utility for visitShuffleVector - Return true if every element in Mask,
3096 // beginning from position Pos and ending in Pos+Size, falls within the
3097 // specified sequential range [L, L+Pos). or is undef.
3098 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3099 unsigned Pos, unsigned Size, int Low) {
3100 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3101 if (Mask[i] >= 0 && Mask[i] != Low)
3106 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3107 SDValue Src1 = getValue(I.getOperand(0));
3108 SDValue Src2 = getValue(I.getOperand(1));
3110 SmallVector<int, 8> Mask;
3111 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3112 unsigned MaskNumElts = Mask.size();
3114 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3115 EVT VT = TLI->getValueType(I.getType());
3116 EVT SrcVT = Src1.getValueType();
3117 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3119 if (SrcNumElts == MaskNumElts) {
3120 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3125 // Normalize the shuffle vector since mask and vector length don't match.
3126 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3127 // Mask is longer than the source vectors and is a multiple of the source
3128 // vectors. We can use concatenate vector to make the mask and vectors
3130 if (SrcNumElts*2 == MaskNumElts) {
3131 // First check for Src1 in low and Src2 in high
3132 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3133 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3134 // The shuffle is concatenating two vectors together.
3135 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3139 // Then check for Src2 in low and Src1 in high
3140 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3141 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3142 // The shuffle is concatenating two vectors together.
3143 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3149 // Pad both vectors with undefs to make them the same length as the mask.
3150 unsigned NumConcat = MaskNumElts / SrcNumElts;
3151 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3152 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3153 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3155 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3156 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3160 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3161 getCurSDLoc(), VT, MOps1);
3162 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3163 getCurSDLoc(), VT, MOps2);
3165 // Readjust mask for new input vector length.
3166 SmallVector<int, 8> MappedOps;
3167 for (unsigned i = 0; i != MaskNumElts; ++i) {
3169 if (Idx >= (int)SrcNumElts)
3170 Idx -= SrcNumElts - MaskNumElts;
3171 MappedOps.push_back(Idx);
3174 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3179 if (SrcNumElts > MaskNumElts) {
3180 // Analyze the access pattern of the vector to see if we can extract
3181 // two subvectors and do the shuffle. The analysis is done by calculating
3182 // the range of elements the mask access on both vectors.
3183 int MinRange[2] = { static_cast<int>(SrcNumElts),
3184 static_cast<int>(SrcNumElts)};
3185 int MaxRange[2] = {-1, -1};
3187 for (unsigned i = 0; i != MaskNumElts; ++i) {
3193 if (Idx >= (int)SrcNumElts) {
3197 if (Idx > MaxRange[Input])
3198 MaxRange[Input] = Idx;
3199 if (Idx < MinRange[Input])
3200 MinRange[Input] = Idx;
3203 // Check if the access is smaller than the vector size and can we find
3204 // a reasonable extract index.
3205 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3207 int StartIdx[2]; // StartIdx to extract from
3208 for (unsigned Input = 0; Input < 2; ++Input) {
3209 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3210 RangeUse[Input] = 0; // Unused
3211 StartIdx[Input] = 0;
3215 // Find a good start index that is a multiple of the mask length. Then
3216 // see if the rest of the elements are in range.
3217 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3218 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3219 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3220 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3223 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3224 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3227 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3228 // Extract appropriate subvector and generate a vector shuffle
3229 for (unsigned Input = 0; Input < 2; ++Input) {
3230 SDValue &Src = Input == 0 ? Src1 : Src2;
3231 if (RangeUse[Input] == 0)
3232 Src = DAG.getUNDEF(VT);
3234 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3235 Src, DAG.getConstant(StartIdx[Input],
3236 TLI->getVectorIdxTy()));
3239 // Calculate new mask.
3240 SmallVector<int, 8> MappedOps;
3241 for (unsigned i = 0; i != MaskNumElts; ++i) {
3244 if (Idx < (int)SrcNumElts)
3247 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3249 MappedOps.push_back(Idx);
3252 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3258 // We can't use either concat vectors or extract subvectors so fall back to
3259 // replacing the shuffle with extract and build vector.
3260 // to insert and build vector.
3261 EVT EltVT = VT.getVectorElementType();
3262 EVT IdxVT = TLI->getVectorIdxTy();
3263 SmallVector<SDValue,8> Ops;
3264 for (unsigned i = 0; i != MaskNumElts; ++i) {
3269 Res = DAG.getUNDEF(EltVT);
3271 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3272 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3274 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3275 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3281 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3284 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3285 const Value *Op0 = I.getOperand(0);
3286 const Value *Op1 = I.getOperand(1);
3287 Type *AggTy = I.getType();
3288 Type *ValTy = Op1->getType();
3289 bool IntoUndef = isa<UndefValue>(Op0);
3290 bool FromUndef = isa<UndefValue>(Op1);
3292 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3294 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3295 SmallVector<EVT, 4> AggValueVTs;
3296 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3297 SmallVector<EVT, 4> ValValueVTs;
3298 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3300 unsigned NumAggValues = AggValueVTs.size();
3301 unsigned NumValValues = ValValueVTs.size();
3302 SmallVector<SDValue, 4> Values(NumAggValues);
3304 SDValue Agg = getValue(Op0);
3306 // Copy the beginning value(s) from the original aggregate.
3307 for (; i != LinearIndex; ++i)
3308 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3309 SDValue(Agg.getNode(), Agg.getResNo() + i);
3310 // Copy values from the inserted value(s).
3312 SDValue Val = getValue(Op1);
3313 for (; i != LinearIndex + NumValValues; ++i)
3314 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3315 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3317 // Copy remaining value(s) from the original aggregate.
3318 for (; i != NumAggValues; ++i)
3319 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3320 SDValue(Agg.getNode(), Agg.getResNo() + i);
3322 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3323 DAG.getVTList(AggValueVTs), Values));
3326 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3327 const Value *Op0 = I.getOperand(0);
3328 Type *AggTy = Op0->getType();
3329 Type *ValTy = I.getType();
3330 bool OutOfUndef = isa<UndefValue>(Op0);
3332 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3334 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3335 SmallVector<EVT, 4> ValValueVTs;
3336 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3338 unsigned NumValValues = ValValueVTs.size();
3340 // Ignore a extractvalue that produces an empty object
3341 if (!NumValValues) {
3342 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3346 SmallVector<SDValue, 4> Values(NumValValues);
3348 SDValue Agg = getValue(Op0);
3349 // Copy out the selected value(s).
3350 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3351 Values[i - LinearIndex] =
3353 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3354 SDValue(Agg.getNode(), Agg.getResNo() + i);
3356 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3357 DAG.getVTList(ValValueVTs), Values));
3360 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3361 Value *Op0 = I.getOperand(0);
3362 // Note that the pointer operand may be a vector of pointers. Take the scalar
3363 // element which holds a pointer.
3364 Type *Ty = Op0->getType()->getScalarType();
3365 unsigned AS = Ty->getPointerAddressSpace();
3366 SDValue N = getValue(Op0);
3368 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3370 const Value *Idx = *OI;
3371 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3372 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3375 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3376 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3377 DAG.getConstant(Offset, N.getValueType()));
3380 Ty = StTy->getElementType(Field);
3382 Ty = cast<SequentialType>(Ty)->getElementType();
3384 // If this is a constant subscript, handle it quickly.
3385 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3386 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3387 if (CI->isZero()) continue;
3389 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3391 EVT PTy = TLI->getPointerTy(AS);
3392 unsigned PtrBits = PTy.getSizeInBits();
3394 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3395 DAG.getConstant(Offs, MVT::i64));
3397 OffsVal = DAG.getConstant(Offs, PTy);
3399 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3404 // N = N + Idx * ElementSize;
3405 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3406 DL->getTypeAllocSize(Ty));
3407 SDValue IdxN = getValue(Idx);
3409 // If the index is smaller or larger than intptr_t, truncate or extend
3411 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3413 // If this is a multiply by a power of two, turn it into a shl
3414 // immediately. This is a very common case.
3415 if (ElementSize != 1) {
3416 if (ElementSize.isPowerOf2()) {
3417 unsigned Amt = ElementSize.logBase2();
3418 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3419 N.getValueType(), IdxN,
3420 DAG.getConstant(Amt, IdxN.getValueType()));
3422 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3423 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3424 N.getValueType(), IdxN, Scale);
3428 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3429 N.getValueType(), N, IdxN);
3436 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3437 // If this is a fixed sized alloca in the entry block of the function,
3438 // allocate it statically on the stack.
3439 if (FuncInfo.StaticAllocaMap.count(&I))
3440 return; // getValue will auto-populate this.
3442 Type *Ty = I.getAllocatedType();
3443 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3444 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3446 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3449 SDValue AllocSize = getValue(I.getArraySize());
3451 EVT IntPtr = TLI->getPointerTy();
3452 if (AllocSize.getValueType() != IntPtr)
3453 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3455 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3457 DAG.getConstant(TySize, IntPtr));
3459 // Handle alignment. If the requested alignment is less than or equal to
3460 // the stack alignment, ignore it. If the size is greater than or equal to
3461 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3462 unsigned StackAlign =
3463 TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
3464 if (Align <= StackAlign)
3467 // Round the size of the allocation up to the stack alignment size
3468 // by add SA-1 to the size.
3469 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3470 AllocSize.getValueType(), AllocSize,
3471 DAG.getIntPtrConstant(StackAlign-1));
3473 // Mask out the low bits for alignment purposes.
3474 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3475 AllocSize.getValueType(), AllocSize,
3476 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3478 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3479 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3480 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3482 DAG.setRoot(DSA.getValue(1));
3484 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3487 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3489 return visitAtomicLoad(I);
3491 const Value *SV = I.getOperand(0);
3492 SDValue Ptr = getValue(SV);
3494 Type *Ty = I.getType();
3496 bool isVolatile = I.isVolatile();
3497 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3498 bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3499 unsigned Alignment = I.getAlignment();
3502 I.getAAMetadata(AAInfo);
3503 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3505 SmallVector<EVT, 4> ValueVTs;
3506 SmallVector<uint64_t, 4> Offsets;
3507 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), Ty, ValueVTs,
3509 unsigned NumValues = ValueVTs.size();
3514 bool ConstantMemory = false;
3515 if (isVolatile || NumValues > MaxParallelChains)
3516 // Serialize volatile loads with other side effects.
3518 else if (AA->pointsToConstantMemory(
3519 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3520 // Do not serialize (non-volatile) loads of constant memory with anything.
3521 Root = DAG.getEntryNode();
3522 ConstantMemory = true;
3524 // Do not serialize non-volatile loads against each other.
3525 Root = DAG.getRoot();
3528 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3530 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3532 SmallVector<SDValue, 4> Values(NumValues);
3533 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3535 EVT PtrVT = Ptr.getValueType();
3536 unsigned ChainI = 0;
3537 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3538 // Serializing loads here may result in excessive register pressure, and
3539 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3540 // could recover a bit by hoisting nodes upward in the chain by recognizing
3541 // they are side-effect free or do not alias. The optimizer should really
3542 // avoid this case by converting large object/array copies to llvm.memcpy
3543 // (MaxParallelChains should always remain as failsafe).
3544 if (ChainI == MaxParallelChains) {
3545 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3546 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3547 makeArrayRef(Chains.data(), ChainI));
3551 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3553 DAG.getConstant(Offsets[i], PtrVT));
3554 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3555 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3556 isNonTemporal, isInvariant, Alignment, AAInfo,
3560 Chains[ChainI] = L.getValue(1);
3563 if (!ConstantMemory) {
3564 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3565 makeArrayRef(Chains.data(), ChainI));
3569 PendingLoads.push_back(Chain);
3572 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3573 DAG.getVTList(ValueVTs), Values));
3576 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3578 return visitAtomicStore(I);
3580 const Value *SrcV = I.getOperand(0);
3581 const Value *PtrV = I.getOperand(1);
3583 SmallVector<EVT, 4> ValueVTs;
3584 SmallVector<uint64_t, 4> Offsets;
3585 ComputeValueVTs(*TM.getSubtargetImpl()->getTargetLowering(), SrcV->getType(),
3586 ValueVTs, &Offsets);
3587 unsigned NumValues = ValueVTs.size();
3591 // Get the lowered operands. Note that we do this after
3592 // checking if NumResults is zero, because with zero results
3593 // the operands won't have values in the map.
3594 SDValue Src = getValue(SrcV);
3595 SDValue Ptr = getValue(PtrV);
3597 SDValue Root = getRoot();
3598 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3600 EVT PtrVT = Ptr.getValueType();
3601 bool isVolatile = I.isVolatile();
3602 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3603 unsigned Alignment = I.getAlignment();
3606 I.getAAMetadata(AAInfo);
3608 unsigned ChainI = 0;
3609 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3610 // See visitLoad comments.
3611 if (ChainI == MaxParallelChains) {
3612 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3613 makeArrayRef(Chains.data(), ChainI));
3617 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3618 DAG.getConstant(Offsets[i], PtrVT));
3619 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3620 SDValue(Src.getNode(), Src.getResNo() + i),
3621 Add, MachinePointerInfo(PtrV, Offsets[i]),
3622 isVolatile, isNonTemporal, Alignment, AAInfo);
3623 Chains[ChainI] = St;
3626 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3627 makeArrayRef(Chains.data(), ChainI));
3628 DAG.setRoot(StoreNode);
3631 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3632 SynchronizationScope Scope,
3633 bool Before, SDLoc dl,
3635 const TargetLowering &TLI) {
3636 // Fence, if necessary
3638 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3640 else if (Order == Acquire || Order == Monotonic || Order == Unordered)
3643 if (Order == AcquireRelease)
3645 else if (Order == Release || Order == Monotonic || Order == Unordered)
3650 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3651 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3652 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops);
3655 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3656 SDLoc dl = getCurSDLoc();
3657 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3658 AtomicOrdering FailureOrder = I.getFailureOrdering();
3659 SynchronizationScope Scope = I.getSynchScope();
3661 SDValue InChain = getRoot();
3663 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3664 if (TLI->getInsertFencesForAtomic())
3665 InChain = InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl,
3668 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3669 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3670 SDValue L = DAG.getAtomicCmpSwap(
3671 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3672 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3673 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3675 TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3676 TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder, Scope);
3678 SDValue OutChain = L.getValue(2);
3680 if (TLI->getInsertFencesForAtomic())
3681 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3685 DAG.setRoot(OutChain);
3688 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3689 SDLoc dl = getCurSDLoc();
3691 switch (I.getOperation()) {
3692 default: llvm_unreachable("Unknown atomicrmw operation");
3693 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3694 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3695 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3696 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3697 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3698 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3699 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3700 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3701 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3702 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3703 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3705 AtomicOrdering Order = I.getOrdering();
3706 SynchronizationScope Scope = I.getSynchScope();
3708 SDValue InChain = getRoot();
3710 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3711 if (TLI->getInsertFencesForAtomic())
3712 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3716 DAG.getAtomic(NT, dl,
3717 getValue(I.getValOperand()).getSimpleValueType(),
3719 getValue(I.getPointerOperand()),
3720 getValue(I.getValOperand()),
3721 I.getPointerOperand(), 0 /* Alignment */,
3722 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3725 SDValue OutChain = L.getValue(1);
3727 if (TLI->getInsertFencesForAtomic())
3728 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3732 DAG.setRoot(OutChain);
3735 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3736 SDLoc dl = getCurSDLoc();
3737 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3740 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3741 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3742 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3745 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3746 SDLoc dl = getCurSDLoc();
3747 AtomicOrdering Order = I.getOrdering();
3748 SynchronizationScope Scope = I.getSynchScope();
3750 SDValue InChain = getRoot();
3752 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3753 EVT VT = TLI->getValueType(I.getType());
3755 if (I.getAlignment() < VT.getSizeInBits() / 8)
3756 report_fatal_error("Cannot generate unaligned atomic load");
3758 MachineMemOperand *MMO =
3759 DAG.getMachineFunction().
3760 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3761 MachineMemOperand::MOVolatile |
3762 MachineMemOperand::MOLoad,
3764 I.getAlignment() ? I.getAlignment() :
3765 DAG.getEVTAlignment(VT));
3767 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3769 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3770 getValue(I.getPointerOperand()), MMO,
3771 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3774 SDValue OutChain = L.getValue(1);
3776 if (TLI->getInsertFencesForAtomic())
3777 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3781 DAG.setRoot(OutChain);
3784 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3785 SDLoc dl = getCurSDLoc();
3787 AtomicOrdering Order = I.getOrdering();
3788 SynchronizationScope Scope = I.getSynchScope();
3790 SDValue InChain = getRoot();
3792 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3793 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3795 if (I.getAlignment() < VT.getSizeInBits() / 8)
3796 report_fatal_error("Cannot generate unaligned atomic store");
3798 if (TLI->getInsertFencesForAtomic())
3799 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3803 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3805 getValue(I.getPointerOperand()),
3806 getValue(I.getValueOperand()),
3807 I.getPointerOperand(), I.getAlignment(),
3808 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3811 if (TLI->getInsertFencesForAtomic())
3812 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3815 DAG.setRoot(OutChain);
3818 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3820 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3821 unsigned Intrinsic) {
3822 bool HasChain = !I.doesNotAccessMemory();
3823 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3825 // Build the operand list.
3826 SmallVector<SDValue, 8> Ops;
3827 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3829 // We don't need to serialize loads against other loads.
3830 Ops.push_back(DAG.getRoot());
3832 Ops.push_back(getRoot());
3836 // Info is set by getTgtMemInstrinsic
3837 TargetLowering::IntrinsicInfo Info;
3838 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
3839 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3841 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3842 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3843 Info.opc == ISD::INTRINSIC_W_CHAIN)
3844 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3846 // Add all operands of the call to the operand list.
3847 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3848 SDValue Op = getValue(I.getArgOperand(i));
3852 SmallVector<EVT, 4> ValueVTs;
3853 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3856 ValueVTs.push_back(MVT::Other);
3858 SDVTList VTs = DAG.getVTList(ValueVTs);
3862 if (IsTgtIntrinsic) {
3863 // This is target intrinsic that touches memory
3864 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3865 VTs, Ops, Info.memVT,
3866 MachinePointerInfo(Info.ptrVal, Info.offset),
3867 Info.align, Info.vol,
3868 Info.readMem, Info.writeMem);
3869 } else if (!HasChain) {
3870 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3871 } else if (!I.getType()->isVoidTy()) {
3872 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3874 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3878 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3880 PendingLoads.push_back(Chain);
3885 if (!I.getType()->isVoidTy()) {
3886 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3887 EVT VT = TLI->getValueType(PTy);
3888 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3891 setValue(&I, Result);
3895 /// GetSignificand - Get the significand and build it into a floating-point
3896 /// number with exponent of 1:
3898 /// Op = (Op & 0x007fffff) | 0x3f800000;
3900 /// where Op is the hexadecimal representation of floating point value.
3902 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3903 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3904 DAG.getConstant(0x007fffff, MVT::i32));
3905 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3906 DAG.getConstant(0x3f800000, MVT::i32));
3907 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3910 /// GetExponent - Get the exponent:
3912 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3914 /// where Op is the hexadecimal representation of floating point value.
3916 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3918 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3919 DAG.getConstant(0x7f800000, MVT::i32));
3920 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3921 DAG.getConstant(23, TLI.getPointerTy()));
3922 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3923 DAG.getConstant(127, MVT::i32));
3924 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3927 /// getF32Constant - Get 32-bit floating point constant.
3929 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3930 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3934 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3935 /// limited-precision mode.
3936 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3937 const TargetLowering &TLI) {
3938 if (Op.getValueType() == MVT::f32 &&
3939 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3941 // Put the exponent in the right bit position for later addition to the
3944 // #define LOG2OFe 1.4426950f
3945 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3946 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3947 getF32Constant(DAG, 0x3fb8aa3b));
3948 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3950 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3951 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3952 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3954 // IntegerPartOfX <<= 23;
3955 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3956 DAG.getConstant(23, TLI.getPointerTy()));
3958 SDValue TwoToFracPartOfX;
3959 if (LimitFloatPrecision <= 6) {
3960 // For floating-point precision of 6:
3962 // TwoToFractionalPartOfX =
3964 // (0.735607626f + 0.252464424f * x) * x;
3966 // error 0.0144103317, which is 6 bits
3967 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3968 getF32Constant(DAG, 0x3e814304));
3969 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3970 getF32Constant(DAG, 0x3f3c50c8));
3971 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3972 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3973 getF32Constant(DAG, 0x3f7f5e7e));
3974 } else if (LimitFloatPrecision <= 12) {
3975 // For floating-point precision of 12:
3977 // TwoToFractionalPartOfX =
3980 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3982 // 0.000107046256 error, which is 13 to 14 bits
3983 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3984 getF32Constant(DAG, 0x3da235e3));
3985 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3986 getF32Constant(DAG, 0x3e65b8f3));
3987 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3988 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3989 getF32Constant(DAG, 0x3f324b07));
3990 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3991 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3992 getF32Constant(DAG, 0x3f7ff8fd));
3993 } else { // LimitFloatPrecision <= 18
3994 // For floating-point precision of 18:
3996 // TwoToFractionalPartOfX =
4000 // (0.554906021e-1f +
4001 // (0.961591928e-2f +
4002 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4004 // error 2.47208000*10^(-7), which is better than 18 bits
4005 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4006 getF32Constant(DAG, 0x3924b03e));
4007 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4008 getF32Constant(DAG, 0x3ab24b87));
4009 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4010 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4011 getF32Constant(DAG, 0x3c1d8c17));
4012 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4013 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4014 getF32Constant(DAG, 0x3d634a1d));
4015 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4016 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4017 getF32Constant(DAG, 0x3e75fe14));
4018 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4019 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4020 getF32Constant(DAG, 0x3f317234));
4021 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4022 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4023 getF32Constant(DAG, 0x3f800000));
4026 // Add the exponent into the result in integer domain.
4027 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
4028 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4029 DAG.getNode(ISD::ADD, dl, MVT::i32,
4030 t13, IntegerPartOfX));
4033 // No special expansion.
4034 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4037 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4038 /// limited-precision mode.
4039 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4040 const TargetLowering &TLI) {
4041 if (Op.getValueType() == MVT::f32 &&
4042 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4043 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4045 // Scale the exponent by log(2) [0.69314718f].
4046 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4047 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4048 getF32Constant(DAG, 0x3f317218));
4050 // Get the significand and build it into a floating-point number with
4052 SDValue X = GetSignificand(DAG, Op1, dl);
4054 SDValue LogOfMantissa;
4055 if (LimitFloatPrecision <= 6) {
4056 // For floating-point precision of 6:
4060 // (1.4034025f - 0.23903021f * x) * x;
4062 // error 0.0034276066, which is better than 8 bits
4063 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4064 getF32Constant(DAG, 0xbe74c456));
4065 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4066 getF32Constant(DAG, 0x3fb3a2b1));
4067 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4068 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4069 getF32Constant(DAG, 0x3f949a29));
4070 } else if (LimitFloatPrecision <= 12) {
4071 // For floating-point precision of 12:
4077 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4079 // error 0.000061011436, which is 14 bits
4080 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4081 getF32Constant(DAG, 0xbd67b6d6));
4082 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4083 getF32Constant(DAG, 0x3ee4f4b8));
4084 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4085 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4086 getF32Constant(DAG, 0x3fbc278b));
4087 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4088 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4089 getF32Constant(DAG, 0x40348e95));
4090 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4091 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4092 getF32Constant(DAG, 0x3fdef31a));
4093 } else { // LimitFloatPrecision <= 18
4094 // For floating-point precision of 18:
4102 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4104 // error 0.0000023660568, which is better than 18 bits
4105 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4106 getF32Constant(DAG, 0xbc91e5ac));
4107 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4108 getF32Constant(DAG, 0x3e4350aa));
4109 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4110 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4111 getF32Constant(DAG, 0x3f60d3e3));
4112 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4113 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4114 getF32Constant(DAG, 0x4011cdf0));
4115 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4116 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4117 getF32Constant(DAG, 0x406cfd1c));
4118 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4119 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4120 getF32Constant(DAG, 0x408797cb));
4121 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4122 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4123 getF32Constant(DAG, 0x4006dcab));
4126 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4129 // No special expansion.
4130 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4133 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4134 /// limited-precision mode.
4135 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4136 const TargetLowering &TLI) {
4137 if (Op.getValueType() == MVT::f32 &&
4138 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4139 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4141 // Get the exponent.
4142 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4144 // Get the significand and build it into a floating-point number with
4146 SDValue X = GetSignificand(DAG, Op1, dl);
4148 // Different possible minimax approximations of significand in
4149 // floating-point for various degrees of accuracy over [1,2].
4150 SDValue Log2ofMantissa;
4151 if (LimitFloatPrecision <= 6) {
4152 // For floating-point precision of 6:
4154 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4156 // error 0.0049451742, which is more than 7 bits
4157 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4158 getF32Constant(DAG, 0xbeb08fe0));
4159 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4160 getF32Constant(DAG, 0x40019463));
4161 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4162 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4163 getF32Constant(DAG, 0x3fd6633d));
4164 } else if (LimitFloatPrecision <= 12) {
4165 // For floating-point precision of 12:
4171 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4173 // error 0.0000876136000, which is better than 13 bits
4174 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4175 getF32Constant(DAG, 0xbda7262e));
4176 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4177 getF32Constant(DAG, 0x3f25280b));
4178 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4179 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4180 getF32Constant(DAG, 0x4007b923));
4181 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4182 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4183 getF32Constant(DAG, 0x40823e2f));
4184 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4185 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4186 getF32Constant(DAG, 0x4020d29c));
4187 } else { // LimitFloatPrecision <= 18
4188 // For floating-point precision of 18:
4197 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4199 // error 0.0000018516, which is better than 18 bits
4200 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4201 getF32Constant(DAG, 0xbcd2769e));
4202 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4203 getF32Constant(DAG, 0x3e8ce0b9));
4204 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4205 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4206 getF32Constant(DAG, 0x3fa22ae7));
4207 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4208 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4209 getF32Constant(DAG, 0x40525723));
4210 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4211 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4212 getF32Constant(DAG, 0x40aaf200));
4213 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4214 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4215 getF32Constant(DAG, 0x40c39dad));
4216 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4217 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4218 getF32Constant(DAG, 0x4042902c));
4221 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4224 // No special expansion.
4225 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4228 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4229 /// limited-precision mode.
4230 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4231 const TargetLowering &TLI) {
4232 if (Op.getValueType() == MVT::f32 &&
4233 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4234 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4236 // Scale the exponent by log10(2) [0.30102999f].
4237 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4238 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4239 getF32Constant(DAG, 0x3e9a209a));
4241 // Get the significand and build it into a floating-point number with
4243 SDValue X = GetSignificand(DAG, Op1, dl);
4245 SDValue Log10ofMantissa;
4246 if (LimitFloatPrecision <= 6) {
4247 // For floating-point precision of 6:
4249 // Log10ofMantissa =
4251 // (0.60948995f - 0.10380950f * x) * x;
4253 // error 0.0014886165, which is 6 bits
4254 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4255 getF32Constant(DAG, 0xbdd49a13));
4256 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4257 getF32Constant(DAG, 0x3f1c0789));
4258 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4259 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4260 getF32Constant(DAG, 0x3f011300));
4261 } else if (LimitFloatPrecision <= 12) {
4262 // For floating-point precision of 12:
4264 // Log10ofMantissa =
4267 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4269 // error 0.00019228036, which is better than 12 bits
4270 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4271 getF32Constant(DAG, 0x3d431f31));
4272 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4273 getF32Constant(DAG, 0x3ea21fb2));
4274 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4275 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4276 getF32Constant(DAG, 0x3f6ae232));
4277 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4278 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4279 getF32Constant(DAG, 0x3f25f7c3));
4280 } else { // LimitFloatPrecision <= 18
4281 // For floating-point precision of 18:
4283 // Log10ofMantissa =
4288 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4290 // error 0.0000037995730, which is better than 18 bits
4291 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4292 getF32Constant(DAG, 0x3c5d51ce));
4293 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4294 getF32Constant(DAG, 0x3e00685a));
4295 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4296 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4297 getF32Constant(DAG, 0x3efb6798));
4298 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4299 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4300 getF32Constant(DAG, 0x3f88d192));
4301 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4302 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4303 getF32Constant(DAG, 0x3fc4316c));
4304 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4305 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4306 getF32Constant(DAG, 0x3f57ce70));
4309 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4312 // No special expansion.
4313 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4316 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4317 /// limited-precision mode.
4318 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4319 const TargetLowering &TLI) {
4320 if (Op.getValueType() == MVT::f32 &&
4321 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4322 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4324 // FractionalPartOfX = x - (float)IntegerPartOfX;
4325 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4326 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4328 // IntegerPartOfX <<= 23;
4329 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4330 DAG.getConstant(23, TLI.getPointerTy()));
4332 SDValue TwoToFractionalPartOfX;
4333 if (LimitFloatPrecision <= 6) {
4334 // For floating-point precision of 6:
4336 // TwoToFractionalPartOfX =
4338 // (0.735607626f + 0.252464424f * x) * x;
4340 // error 0.0144103317, which is 6 bits
4341 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4342 getF32Constant(DAG, 0x3e814304));
4343 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4344 getF32Constant(DAG, 0x3f3c50c8));
4345 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4346 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4347 getF32Constant(DAG, 0x3f7f5e7e));
4348 } else if (LimitFloatPrecision <= 12) {
4349 // For floating-point precision of 12:
4351 // TwoToFractionalPartOfX =
4354 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4356 // error 0.000107046256, which is 13 to 14 bits
4357 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4358 getF32Constant(DAG, 0x3da235e3));
4359 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4360 getF32Constant(DAG, 0x3e65b8f3));
4361 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4362 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4363 getF32Constant(DAG, 0x3f324b07));
4364 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4365 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4366 getF32Constant(DAG, 0x3f7ff8fd));
4367 } else { // LimitFloatPrecision <= 18
4368 // For floating-point precision of 18:
4370 // TwoToFractionalPartOfX =
4374 // (0.554906021e-1f +
4375 // (0.961591928e-2f +
4376 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4377 // error 2.47208000*10^(-7), which is better than 18 bits
4378 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4379 getF32Constant(DAG, 0x3924b03e));
4380 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4381 getF32Constant(DAG, 0x3ab24b87));
4382 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4383 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4384 getF32Constant(DAG, 0x3c1d8c17));
4385 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4386 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4387 getF32Constant(DAG, 0x3d634a1d));
4388 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4389 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4390 getF32Constant(DAG, 0x3e75fe14));
4391 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4392 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4393 getF32Constant(DAG, 0x3f317234));
4394 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4395 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4396 getF32Constant(DAG, 0x3f800000));
4399 // Add the exponent into the result in integer domain.
4400 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4401 TwoToFractionalPartOfX);
4402 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4403 DAG.getNode(ISD::ADD, dl, MVT::i32,
4404 t13, IntegerPartOfX));
4407 // No special expansion.
4408 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4411 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4412 /// limited-precision mode with x == 10.0f.
4413 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4414 SelectionDAG &DAG, const TargetLowering &TLI) {
4415 bool IsExp10 = false;
4416 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4417 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4418 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4420 IsExp10 = LHSC->isExactlyValue(Ten);
4425 // Put the exponent in the right bit position for later addition to the
4428 // #define LOG2OF10 3.3219281f
4429 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4430 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4431 getF32Constant(DAG, 0x40549a78));
4432 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4434 // FractionalPartOfX = x - (float)IntegerPartOfX;
4435 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4436 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4438 // IntegerPartOfX <<= 23;
4439 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4440 DAG.getConstant(23, TLI.getPointerTy()));
4442 SDValue TwoToFractionalPartOfX;
4443 if (LimitFloatPrecision <= 6) {
4444 // For floating-point precision of 6:
4446 // twoToFractionalPartOfX =
4448 // (0.735607626f + 0.252464424f * x) * x;
4450 // error 0.0144103317, which is 6 bits
4451 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4452 getF32Constant(DAG, 0x3e814304));
4453 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4454 getF32Constant(DAG, 0x3f3c50c8));
4455 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4456 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4457 getF32Constant(DAG, 0x3f7f5e7e));
4458 } else if (LimitFloatPrecision <= 12) {
4459 // For floating-point precision of 12:
4461 // TwoToFractionalPartOfX =
4464 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4466 // error 0.000107046256, which is 13 to 14 bits
4467 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4468 getF32Constant(DAG, 0x3da235e3));
4469 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4470 getF32Constant(DAG, 0x3e65b8f3));
4471 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4472 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4473 getF32Constant(DAG, 0x3f324b07));
4474 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4475 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4476 getF32Constant(DAG, 0x3f7ff8fd));
4477 } else { // LimitFloatPrecision <= 18
4478 // For floating-point precision of 18:
4480 // TwoToFractionalPartOfX =
4484 // (0.554906021e-1f +
4485 // (0.961591928e-2f +
4486 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4487 // error 2.47208000*10^(-7), which is better than 18 bits
4488 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4489 getF32Constant(DAG, 0x3924b03e));
4490 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4491 getF32Constant(DAG, 0x3ab24b87));
4492 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4493 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4494 getF32Constant(DAG, 0x3c1d8c17));
4495 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4496 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4497 getF32Constant(DAG, 0x3d634a1d));
4498 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4499 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4500 getF32Constant(DAG, 0x3e75fe14));
4501 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4502 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4503 getF32Constant(DAG, 0x3f317234));
4504 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4505 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4506 getF32Constant(DAG, 0x3f800000));
4509 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4510 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4511 DAG.getNode(ISD::ADD, dl, MVT::i32,
4512 t13, IntegerPartOfX));
4515 // No special expansion.
4516 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4520 /// ExpandPowI - Expand a llvm.powi intrinsic.
4521 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4522 SelectionDAG &DAG) {
4523 // If RHS is a constant, we can expand this out to a multiplication tree,
4524 // otherwise we end up lowering to a call to __powidf2 (for example). When
4525 // optimizing for size, we only want to do this if the expansion would produce
4526 // a small number of multiplies, otherwise we do the full expansion.
4527 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4528 // Get the exponent as a positive value.
4529 unsigned Val = RHSC->getSExtValue();
4530 if ((int)Val < 0) Val = -Val;
4532 // powi(x, 0) -> 1.0
4534 return DAG.getConstantFP(1.0, LHS.getValueType());
4536 const Function *F = DAG.getMachineFunction().getFunction();
4537 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4538 Attribute::OptimizeForSize) ||
4539 // If optimizing for size, don't insert too many multiplies. This
4540 // inserts up to 5 multiplies.
4541 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4542 // We use the simple binary decomposition method to generate the multiply
4543 // sequence. There are more optimal ways to do this (for example,
4544 // powi(x,15) generates one more multiply than it should), but this has
4545 // the benefit of being both really simple and much better than a libcall.
4546 SDValue Res; // Logically starts equal to 1.0
4547 SDValue CurSquare = LHS;
4551 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4553 Res = CurSquare; // 1.0*CurSquare.
4556 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4557 CurSquare, CurSquare);
4561 // If the original was negative, invert the result, producing 1/(x*x*x).
4562 if (RHSC->getSExtValue() < 0)
4563 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4564 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4569 // Otherwise, expand to a libcall.
4570 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4573 // getTruncatedArgReg - Find underlying register used for an truncated
4575 static unsigned getTruncatedArgReg(const SDValue &N) {
4576 if (N.getOpcode() != ISD::TRUNCATE)
4579 const SDValue &Ext = N.getOperand(0);
4580 if (Ext.getOpcode() == ISD::AssertZext ||
4581 Ext.getOpcode() == ISD::AssertSext) {
4582 const SDValue &CFR = Ext.getOperand(0);
4583 if (CFR.getOpcode() == ISD::CopyFromReg)
4584 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4585 if (CFR.getOpcode() == ISD::TRUNCATE)
4586 return getTruncatedArgReg(CFR);
4591 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4592 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4593 /// At the end of instruction selection, they will be inserted to the entry BB.
4595 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4596 int64_t Offset, bool IsIndirect,
4598 const Argument *Arg = dyn_cast<Argument>(V);
4602 MachineFunction &MF = DAG.getMachineFunction();
4603 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4605 // Ignore inlined function arguments here.
4606 DIVariable DV(Variable);
4607 if (DV.isInlinedFnArgument(MF.getFunction()))
4610 Optional<MachineOperand> Op;
4611 // Some arguments' frame index is recorded during argument lowering.
4612 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4613 Op = MachineOperand::CreateFI(FI);
4615 if (!Op && N.getNode()) {
4617 if (N.getOpcode() == ISD::CopyFromReg)
4618 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4620 Reg = getTruncatedArgReg(N);
4621 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4622 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4623 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4628 Op = MachineOperand::CreateReg(Reg, false);
4632 // Check if ValueMap has reg number.
4633 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4634 if (VMI != FuncInfo.ValueMap.end())
4635 Op = MachineOperand::CreateReg(VMI->second, false);
4638 if (!Op && N.getNode())
4639 // Check if frame index is available.
4640 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4641 if (FrameIndexSDNode *FINode =
4642 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4643 Op = MachineOperand::CreateFI(FINode->getIndex());
4649 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
4650 TII->get(TargetOpcode::DBG_VALUE),
4652 Op->getReg(), Offset, Variable));
4654 FuncInfo.ArgDbgValues.push_back(
4655 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4656 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4661 // VisualStudio defines setjmp as _setjmp
4662 #if defined(_MSC_VER) && defined(setjmp) && \
4663 !defined(setjmp_undefined_for_msvc)
4664 # pragma push_macro("setjmp")
4666 # define setjmp_undefined_for_msvc
4669 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4670 /// we want to emit this as a call to a named external function, return the name
4671 /// otherwise lower it and return null.
4673 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4674 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
4675 SDLoc sdl = getCurSDLoc();
4676 DebugLoc dl = getCurDebugLoc();
4679 switch (Intrinsic) {
4681 // By default, turn this into a target intrinsic node.
4682 visitTargetIntrinsic(I, Intrinsic);
4684 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4685 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4686 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4687 case Intrinsic::returnaddress:
4688 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4689 getValue(I.getArgOperand(0))));
4691 case Intrinsic::frameaddress:
4692 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4693 getValue(I.getArgOperand(0))));
4695 case Intrinsic::read_register: {
4696 Value *Reg = I.getArgOperand(0);
4697 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4699 TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType());
4700 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4703 case Intrinsic::write_register: {
4704 Value *Reg = I.getArgOperand(0);
4705 Value *RegValue = I.getArgOperand(1);
4706 SDValue Chain = getValue(RegValue).getOperand(0);
4707 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4708 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4709 RegName, getValue(RegValue)));
4712 case Intrinsic::setjmp:
4713 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4714 case Intrinsic::longjmp:
4715 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4716 case Intrinsic::memcpy: {
4717 // Assert for address < 256 since we support only user defined address
4719 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4721 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4723 "Unknown address space");
4724 SDValue Op1 = getValue(I.getArgOperand(0));
4725 SDValue Op2 = getValue(I.getArgOperand(1));
4726 SDValue Op3 = getValue(I.getArgOperand(2));
4727 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4729 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4730 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4731 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4732 MachinePointerInfo(I.getArgOperand(0)),
4733 MachinePointerInfo(I.getArgOperand(1))));
4736 case Intrinsic::memset: {
4737 // Assert for address < 256 since we support only user defined address
4739 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4741 "Unknown address space");
4742 SDValue Op1 = getValue(I.getArgOperand(0));
4743 SDValue Op2 = getValue(I.getArgOperand(1));
4744 SDValue Op3 = getValue(I.getArgOperand(2));
4745 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4747 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4748 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4749 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4750 MachinePointerInfo(I.getArgOperand(0))));
4753 case Intrinsic::memmove: {
4754 // Assert for address < 256 since we support only user defined address
4756 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4758 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4760 "Unknown address space");
4761 SDValue Op1 = getValue(I.getArgOperand(0));
4762 SDValue Op2 = getValue(I.getArgOperand(1));
4763 SDValue Op3 = getValue(I.getArgOperand(2));
4764 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4766 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4767 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4768 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4769 MachinePointerInfo(I.getArgOperand(0)),
4770 MachinePointerInfo(I.getArgOperand(1))));
4773 case Intrinsic::dbg_declare: {
4774 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4775 MDNode *Variable = DI.getVariable();
4776 const Value *Address = DI.getAddress();
4777 DIVariable DIVar(Variable);
4778 assert((!DIVar || DIVar.isVariable()) &&
4779 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4780 if (!Address || !DIVar) {
4781 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4785 // Check if address has undef value.
4786 if (isa<UndefValue>(Address) ||
4787 (Address->use_empty() && !isa<Argument>(Address))) {
4788 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4792 SDValue &N = NodeMap[Address];
4793 if (!N.getNode() && isa<Argument>(Address))
4794 // Check unused arguments map.
4795 N = UnusedArgNodeMap[Address];
4798 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4799 Address = BCI->getOperand(0);
4800 // Parameters are handled specially.
4802 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4803 isa<Argument>(Address));
4805 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4807 if (isParameter && !AI) {
4808 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4810 // Byval parameter. We have a frame index at this point.
4811 SDV = DAG.getFrameIndexDbgValue(Variable, FINode->getIndex(),
4812 0, dl, SDNodeOrder);
4814 // Address is an argument, so try to emit its dbg value using
4815 // virtual register info from the FuncInfo.ValueMap.
4816 EmitFuncArgumentDbgValue(Address, Variable, 0, false, N);
4820 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4821 true, 0, dl, SDNodeOrder);
4823 // Can't do anything with other non-AI cases yet.
4824 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4825 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4826 DEBUG(Address->dump());
4829 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4831 // If Address is an argument then try to emit its dbg value using
4832 // virtual register info from the FuncInfo.ValueMap.
4833 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, false, N)) {
4834 // If variable is pinned by a alloca in dominating bb then
4835 // use StaticAllocaMap.
4836 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4837 if (AI->getParent() != DI.getParent()) {
4838 DenseMap<const AllocaInst*, int>::iterator SI =
4839 FuncInfo.StaticAllocaMap.find(AI);
4840 if (SI != FuncInfo.StaticAllocaMap.end()) {
4841 SDV = DAG.getFrameIndexDbgValue(Variable, SI->second,
4842 0, dl, SDNodeOrder);
4843 DAG.AddDbgValue(SDV, nullptr, false);
4848 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4853 case Intrinsic::dbg_value: {
4854 const DbgValueInst &DI = cast<DbgValueInst>(I);
4855 DIVariable DIVar(DI.getVariable());
4856 assert((!DIVar || DIVar.isVariable()) &&
4857 "Variable in DbgValueInst should be either null or a DIVariable.");
4861 MDNode *Variable = DI.getVariable();
4862 uint64_t Offset = DI.getOffset();
4863 const Value *V = DI.getValue();
4868 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4869 SDV = DAG.getConstantDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4870 DAG.AddDbgValue(SDV, nullptr, false);
4872 // Do not use getValue() in here; we don't want to generate code at
4873 // this point if it hasn't been done yet.
4874 SDValue N = NodeMap[V];
4875 if (!N.getNode() && isa<Argument>(V))
4876 // Check unused arguments map.
4877 N = UnusedArgNodeMap[V];
4879 // A dbg.value for an alloca is always indirect.
4880 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4881 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, N)) {
4882 SDV = DAG.getDbgValue(Variable, N.getNode(),
4883 N.getResNo(), IsIndirect,
4884 Offset, dl, SDNodeOrder);
4885 DAG.AddDbgValue(SDV, N.getNode(), false);
4887 } else if (!V->use_empty() ) {
4888 // Do not call getValue(V) yet, as we don't want to generate code.
4889 // Remember it for later.
4890 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4891 DanglingDebugInfoMap[V] = DDI;
4893 // We may expand this to cover more cases. One case where we have no
4894 // data available is an unreferenced parameter.
4895 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4899 // Build a debug info table entry.
4900 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4901 V = BCI->getOperand(0);
4902 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4903 // Don't handle byval struct arguments or VLAs, for example.
4905 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4906 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4909 DenseMap<const AllocaInst*, int>::iterator SI =
4910 FuncInfo.StaticAllocaMap.find(AI);
4911 if (SI == FuncInfo.StaticAllocaMap.end())
4912 return nullptr; // VLAs.
4916 case Intrinsic::eh_typeid_for: {
4917 // Find the type id for the given typeinfo.
4918 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4919 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4920 Res = DAG.getConstant(TypeID, MVT::i32);
4925 case Intrinsic::eh_return_i32:
4926 case Intrinsic::eh_return_i64:
4927 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4928 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4931 getValue(I.getArgOperand(0)),
4932 getValue(I.getArgOperand(1))));
4934 case Intrinsic::eh_unwind_init:
4935 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4937 case Intrinsic::eh_dwarf_cfa: {
4938 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4939 TLI->getPointerTy());
4940 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4941 CfaArg.getValueType(),
4942 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4943 CfaArg.getValueType()),
4945 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4946 TLI->getPointerTy(),
4947 DAG.getConstant(0, TLI->getPointerTy()));
4948 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4952 case Intrinsic::eh_sjlj_callsite: {
4953 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4954 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4955 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4956 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4958 MMI.setCurrentCallSite(CI->getZExtValue());
4961 case Intrinsic::eh_sjlj_functioncontext: {
4962 // Get and store the index of the function context.
4963 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4965 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4966 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4967 MFI->setFunctionContextIndex(FI);
4970 case Intrinsic::eh_sjlj_setjmp: {
4973 Ops[1] = getValue(I.getArgOperand(0));
4974 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4975 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4976 setValue(&I, Op.getValue(0));
4977 DAG.setRoot(Op.getValue(1));
4980 case Intrinsic::eh_sjlj_longjmp: {
4981 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4982 getRoot(), getValue(I.getArgOperand(0))));
4986 case Intrinsic::x86_mmx_pslli_w:
4987 case Intrinsic::x86_mmx_pslli_d:
4988 case Intrinsic::x86_mmx_pslli_q:
4989 case Intrinsic::x86_mmx_psrli_w:
4990 case Intrinsic::x86_mmx_psrli_d:
4991 case Intrinsic::x86_mmx_psrli_q:
4992 case Intrinsic::x86_mmx_psrai_w:
4993 case Intrinsic::x86_mmx_psrai_d: {
4994 SDValue ShAmt = getValue(I.getArgOperand(1));
4995 if (isa<ConstantSDNode>(ShAmt)) {
4996 visitTargetIntrinsic(I, Intrinsic);
4999 unsigned NewIntrinsic = 0;
5000 EVT ShAmtVT = MVT::v2i32;
5001 switch (Intrinsic) {
5002 case Intrinsic::x86_mmx_pslli_w:
5003 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5005 case Intrinsic::x86_mmx_pslli_d:
5006 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5008 case Intrinsic::x86_mmx_pslli_q:
5009 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5011 case Intrinsic::x86_mmx_psrli_w:
5012 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5014 case Intrinsic::x86_mmx_psrli_d:
5015 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5017 case Intrinsic::x86_mmx_psrli_q:
5018 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5020 case Intrinsic::x86_mmx_psrai_w:
5021 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5023 case Intrinsic::x86_mmx_psrai_d:
5024 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5026 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5029 // The vector shift intrinsics with scalars uses 32b shift amounts but
5030 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5032 // We must do this early because v2i32 is not a legal type.
5035 ShOps[1] = DAG.getConstant(0, MVT::i32);
5036 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5037 EVT DestVT = TLI->getValueType(I.getType());
5038 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5039 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5040 DAG.getConstant(NewIntrinsic, MVT::i32),
5041 getValue(I.getArgOperand(0)), ShAmt);
5045 case Intrinsic::x86_avx_vinsertf128_pd_256:
5046 case Intrinsic::x86_avx_vinsertf128_ps_256:
5047 case Intrinsic::x86_avx_vinsertf128_si_256:
5048 case Intrinsic::x86_avx2_vinserti128: {
5049 EVT DestVT = TLI->getValueType(I.getType());
5050 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
5051 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5052 ElVT.getVectorNumElements();
5053 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5054 getValue(I.getArgOperand(0)),
5055 getValue(I.getArgOperand(1)),
5056 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5060 case Intrinsic::x86_avx_vextractf128_pd_256:
5061 case Intrinsic::x86_avx_vextractf128_ps_256:
5062 case Intrinsic::x86_avx_vextractf128_si_256:
5063 case Intrinsic::x86_avx2_vextracti128: {
5064 EVT DestVT = TLI->getValueType(I.getType());
5065 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5066 DestVT.getVectorNumElements();
5067 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5068 getValue(I.getArgOperand(0)),
5069 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5073 case Intrinsic::convertff:
5074 case Intrinsic::convertfsi:
5075 case Intrinsic::convertfui:
5076 case Intrinsic::convertsif:
5077 case Intrinsic::convertuif:
5078 case Intrinsic::convertss:
5079 case Intrinsic::convertsu:
5080 case Intrinsic::convertus:
5081 case Intrinsic::convertuu: {
5082 ISD::CvtCode Code = ISD::CVT_INVALID;
5083 switch (Intrinsic) {
5084 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5085 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5086 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5087 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5088 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5089 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5090 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5091 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5092 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5093 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5095 EVT DestVT = TLI->getValueType(I.getType());
5096 const Value *Op1 = I.getArgOperand(0);
5097 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5098 DAG.getValueType(DestVT),
5099 DAG.getValueType(getValue(Op1).getValueType()),
5100 getValue(I.getArgOperand(1)),
5101 getValue(I.getArgOperand(2)),
5106 case Intrinsic::powi:
5107 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5108 getValue(I.getArgOperand(1)), DAG));
5110 case Intrinsic::log:
5111 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5113 case Intrinsic::log2:
5114 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5116 case Intrinsic::log10:
5117 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5119 case Intrinsic::exp:
5120 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5122 case Intrinsic::exp2:
5123 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5125 case Intrinsic::pow:
5126 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5127 getValue(I.getArgOperand(1)), DAG, *TLI));
5129 case Intrinsic::sqrt:
5130 case Intrinsic::fabs:
5131 case Intrinsic::sin:
5132 case Intrinsic::cos:
5133 case Intrinsic::floor:
5134 case Intrinsic::ceil:
5135 case Intrinsic::trunc:
5136 case Intrinsic::rint:
5137 case Intrinsic::nearbyint:
5138 case Intrinsic::round: {
5140 switch (Intrinsic) {
5141 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5142 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5143 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5144 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5145 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5146 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5147 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5148 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5149 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5150 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5151 case Intrinsic::round: Opcode = ISD::FROUND; break;
5154 setValue(&I, DAG.getNode(Opcode, sdl,
5155 getValue(I.getArgOperand(0)).getValueType(),
5156 getValue(I.getArgOperand(0))));
5159 case Intrinsic::copysign:
5160 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5161 getValue(I.getArgOperand(0)).getValueType(),
5162 getValue(I.getArgOperand(0)),
5163 getValue(I.getArgOperand(1))));
5165 case Intrinsic::fma:
5166 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5167 getValue(I.getArgOperand(0)).getValueType(),
5168 getValue(I.getArgOperand(0)),
5169 getValue(I.getArgOperand(1)),
5170 getValue(I.getArgOperand(2))));
5172 case Intrinsic::fmuladd: {
5173 EVT VT = TLI->getValueType(I.getType());
5174 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5175 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5176 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5177 getValue(I.getArgOperand(0)).getValueType(),
5178 getValue(I.getArgOperand(0)),
5179 getValue(I.getArgOperand(1)),
5180 getValue(I.getArgOperand(2))));
5182 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5183 getValue(I.getArgOperand(0)).getValueType(),
5184 getValue(I.getArgOperand(0)),
5185 getValue(I.getArgOperand(1)));
5186 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5187 getValue(I.getArgOperand(0)).getValueType(),
5189 getValue(I.getArgOperand(2)));
5194 case Intrinsic::convert_to_fp16:
5195 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5196 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5197 getValue(I.getArgOperand(0)),
5198 DAG.getTargetConstant(0, MVT::i32))));
5200 case Intrinsic::convert_from_fp16:
5202 DAG.getNode(ISD::FP_EXTEND, sdl, TLI->getValueType(I.getType()),
5203 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5204 getValue(I.getArgOperand(0)))));
5206 case Intrinsic::pcmarker: {
5207 SDValue Tmp = getValue(I.getArgOperand(0));
5208 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5211 case Intrinsic::readcyclecounter: {
5212 SDValue Op = getRoot();
5213 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5214 DAG.getVTList(MVT::i64, MVT::Other), Op);
5216 DAG.setRoot(Res.getValue(1));
5219 case Intrinsic::bswap:
5220 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5221 getValue(I.getArgOperand(0)).getValueType(),
5222 getValue(I.getArgOperand(0))));
5224 case Intrinsic::cttz: {
5225 SDValue Arg = getValue(I.getArgOperand(0));
5226 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5227 EVT Ty = Arg.getValueType();
5228 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5232 case Intrinsic::ctlz: {
5233 SDValue Arg = getValue(I.getArgOperand(0));
5234 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5235 EVT Ty = Arg.getValueType();
5236 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5240 case Intrinsic::ctpop: {
5241 SDValue Arg = getValue(I.getArgOperand(0));
5242 EVT Ty = Arg.getValueType();
5243 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5246 case Intrinsic::stacksave: {
5247 SDValue Op = getRoot();
5248 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5249 DAG.getVTList(TLI->getPointerTy(), MVT::Other), Op);
5251 DAG.setRoot(Res.getValue(1));
5254 case Intrinsic::stackrestore: {
5255 Res = getValue(I.getArgOperand(0));
5256 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5259 case Intrinsic::stackprotector: {
5260 // Emit code into the DAG to store the stack guard onto the stack.
5261 MachineFunction &MF = DAG.getMachineFunction();
5262 MachineFrameInfo *MFI = MF.getFrameInfo();
5263 EVT PtrTy = TLI->getPointerTy();
5264 SDValue Src, Chain = getRoot();
5266 if (TLI->useLoadStackGuardNode()) {
5267 // Emit a LOAD_STACK_GUARD node.
5268 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5270 LoadInst *LI = cast<LoadInst>(I.getArgOperand(0));
5271 MachinePointerInfo MPInfo(LI->getPointerOperand());
5272 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5273 unsigned Flags = MachineMemOperand::MOLoad |
5274 MachineMemOperand::MOInvariant;
5275 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5276 PtrTy.getSizeInBits() / 8,
5277 DAG.getEVTAlignment(PtrTy));
5278 Node->setMemRefs(MemRefs, MemRefs + 1);
5280 // Copy the guard value to a virtual register so that it can be
5281 // retrieved in the epilogue.
5282 Src = SDValue(Node, 0);
5283 const TargetRegisterClass *RC =
5284 TLI->getRegClassFor(Src.getSimpleValueType());
5285 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5287 SPDescriptor.setGuardReg(Reg);
5288 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5290 Src = getValue(I.getArgOperand(0)); // The guard's value.
5293 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5295 int FI = FuncInfo.StaticAllocaMap[Slot];
5296 MFI->setStackProtectorIndex(FI);
5298 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5300 // Store the stack protector onto the stack.
5301 Res = DAG.getStore(Chain, sdl, Src, FIN,
5302 MachinePointerInfo::getFixedStack(FI),
5308 case Intrinsic::objectsize: {
5309 // If we don't know by now, we're never going to know.
5310 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5312 assert(CI && "Non-constant type in __builtin_object_size?");
5314 SDValue Arg = getValue(I.getCalledValue());
5315 EVT Ty = Arg.getValueType();
5318 Res = DAG.getConstant(-1ULL, Ty);
5320 Res = DAG.getConstant(0, Ty);
5325 case Intrinsic::annotation:
5326 case Intrinsic::ptr_annotation:
5327 // Drop the intrinsic, but forward the value
5328 setValue(&I, getValue(I.getOperand(0)));
5330 case Intrinsic::assume:
5331 case Intrinsic::var_annotation:
5332 // Discard annotate attributes and assumptions
5335 case Intrinsic::init_trampoline: {
5336 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5340 Ops[1] = getValue(I.getArgOperand(0));
5341 Ops[2] = getValue(I.getArgOperand(1));
5342 Ops[3] = getValue(I.getArgOperand(2));
5343 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5344 Ops[5] = DAG.getSrcValue(F);
5346 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5351 case Intrinsic::adjust_trampoline: {
5352 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5353 TLI->getPointerTy(),
5354 getValue(I.getArgOperand(0))));
5357 case Intrinsic::gcroot:
5359 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5360 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5362 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5363 GFI->addStackRoot(FI->getIndex(), TypeMap);
5366 case Intrinsic::gcread:
5367 case Intrinsic::gcwrite:
5368 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5369 case Intrinsic::flt_rounds:
5370 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5373 case Intrinsic::expect: {
5374 // Just replace __builtin_expect(exp, c) with EXP.
5375 setValue(&I, getValue(I.getArgOperand(0)));
5379 case Intrinsic::debugtrap:
5380 case Intrinsic::trap: {
5381 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5382 if (TrapFuncName.empty()) {
5383 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5384 ISD::TRAP : ISD::DEBUGTRAP;
5385 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5388 TargetLowering::ArgListTy Args;
5390 TargetLowering::CallLoweringInfo CLI(DAG);
5391 CLI.setDebugLoc(sdl).setChain(getRoot())
5392 .setCallee(CallingConv::C, I.getType(),
5393 DAG.getExternalSymbol(TrapFuncName.data(), TLI->getPointerTy()),
5394 std::move(Args), 0);
5396 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5397 DAG.setRoot(Result.second);
5401 case Intrinsic::uadd_with_overflow:
5402 case Intrinsic::sadd_with_overflow:
5403 case Intrinsic::usub_with_overflow:
5404 case Intrinsic::ssub_with_overflow:
5405 case Intrinsic::umul_with_overflow:
5406 case Intrinsic::smul_with_overflow: {
5408 switch (Intrinsic) {
5409 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5410 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5411 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5412 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5413 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5414 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5415 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5417 SDValue Op1 = getValue(I.getArgOperand(0));
5418 SDValue Op2 = getValue(I.getArgOperand(1));
5420 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5421 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5424 case Intrinsic::prefetch: {
5426 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5428 Ops[1] = getValue(I.getArgOperand(0));
5429 Ops[2] = getValue(I.getArgOperand(1));
5430 Ops[3] = getValue(I.getArgOperand(2));
5431 Ops[4] = getValue(I.getArgOperand(3));
5432 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5433 DAG.getVTList(MVT::Other), Ops,
5434 EVT::getIntegerVT(*Context, 8),
5435 MachinePointerInfo(I.getArgOperand(0)),
5437 false, /* volatile */
5439 rw==1)); /* write */
5442 case Intrinsic::lifetime_start:
5443 case Intrinsic::lifetime_end: {
5444 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5445 // Stack coloring is not enabled in O0, discard region information.
5446 if (TM.getOptLevel() == CodeGenOpt::None)
5449 SmallVector<Value *, 4> Allocas;
5450 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5452 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5453 E = Allocas.end(); Object != E; ++Object) {
5454 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5456 // Could not find an Alloca.
5457 if (!LifetimeObject)
5460 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5464 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5465 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5467 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5472 case Intrinsic::invariant_start:
5473 // Discard region information.
5474 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5476 case Intrinsic::invariant_end:
5477 // Discard region information.
5479 case Intrinsic::stackprotectorcheck: {
5480 // Do not actually emit anything for this basic block. Instead we initialize
5481 // the stack protector descriptor and export the guard variable so we can
5482 // access it in FinishBasicBlock.
5483 const BasicBlock *BB = I.getParent();
5484 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5485 ExportFromCurrentBlock(SPDescriptor.getGuard());
5487 // Flush our exports since we are going to process a terminator.
5488 (void)getControlRoot();
5491 case Intrinsic::clear_cache:
5492 return TLI->getClearCacheBuiltinName();
5493 case Intrinsic::donothing:
5496 case Intrinsic::experimental_stackmap: {
5500 case Intrinsic::experimental_patchpoint_void:
5501 case Intrinsic::experimental_patchpoint_i64: {
5508 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5510 MachineBasicBlock *LandingPad) {
5511 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5512 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5513 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5514 Type *RetTy = FTy->getReturnType();
5515 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5516 MCSymbol *BeginLabel = nullptr;
5518 TargetLowering::ArgListTy Args;
5519 TargetLowering::ArgListEntry Entry;
5520 Args.reserve(CS.arg_size());
5522 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5524 const Value *V = *i;
5527 if (V->getType()->isEmptyTy())
5530 SDValue ArgNode = getValue(V);
5531 Entry.Node = ArgNode; Entry.Ty = V->getType();
5533 // Skip the first return-type Attribute to get to params.
5534 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5535 Args.push_back(Entry);
5539 // Insert a label before the invoke call to mark the try range. This can be
5540 // used to detect deletion of the invoke via the MachineModuleInfo.
5541 BeginLabel = MMI.getContext().CreateTempSymbol();
5543 // For SjLj, keep track of which landing pads go with which invokes
5544 // so as to maintain the ordering of pads in the LSDA.
5545 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5546 if (CallSiteIndex) {
5547 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5548 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5550 // Now that the call site is handled, stop tracking it.
5551 MMI.setCurrentCallSite(0);
5554 // Both PendingLoads and PendingExports must be flushed here;
5555 // this call might not return.
5557 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5560 // Check if target-independent constraints permit a tail call here.
5561 // Target-dependent constraints are checked within TLI->LowerCallTo.
5562 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5565 TargetLowering::CallLoweringInfo CLI(DAG);
5566 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5567 .setCallee(RetTy, FTy, Callee, std::move(Args), CS).setTailCall(isTailCall);
5569 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5570 assert((isTailCall || Result.second.getNode()) &&
5571 "Non-null chain expected with non-tail call!");
5572 assert((Result.second.getNode() || !Result.first.getNode()) &&
5573 "Null value expected with tail call!");
5574 if (Result.first.getNode())
5575 setValue(CS.getInstruction(), Result.first);
5577 if (!Result.second.getNode()) {
5578 // As a special case, a null chain means that a tail call has been emitted
5579 // and the DAG root is already updated.
5582 // Since there's no actual continuation from this block, nothing can be
5583 // relying on us setting vregs for them.
5584 PendingExports.clear();
5586 DAG.setRoot(Result.second);
5590 // Insert a label at the end of the invoke call to mark the try range. This
5591 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5592 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5593 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5595 // Inform MachineModuleInfo of range.
5596 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5600 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5601 /// value is equal or not-equal to zero.
5602 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5603 for (const User *U : V->users()) {
5604 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5605 if (IC->isEquality())
5606 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5607 if (C->isNullValue())
5609 // Unknown instruction.
5615 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5617 SelectionDAGBuilder &Builder) {
5619 // Check to see if this load can be trivially constant folded, e.g. if the
5620 // input is from a string literal.
5621 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5622 // Cast pointer to the type we really want to load.
5623 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5624 PointerType::getUnqual(LoadTy));
5626 if (const Constant *LoadCst =
5627 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5629 return Builder.getValue(LoadCst);
5632 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5633 // still constant memory, the input chain can be the entry node.
5635 bool ConstantMemory = false;
5637 // Do not serialize (non-volatile) loads of constant memory with anything.
5638 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5639 Root = Builder.DAG.getEntryNode();
5640 ConstantMemory = true;
5642 // Do not serialize non-volatile loads against each other.
5643 Root = Builder.DAG.getRoot();
5646 SDValue Ptr = Builder.getValue(PtrVal);
5647 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5648 Ptr, MachinePointerInfo(PtrVal),
5650 false /*nontemporal*/,
5651 false /*isinvariant*/, 1 /* align=1 */);
5653 if (!ConstantMemory)
5654 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5658 /// processIntegerCallValue - Record the value for an instruction that
5659 /// produces an integer result, converting the type where necessary.
5660 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5663 EVT VT = TM.getSubtargetImpl()->getTargetLowering()->getValueType(I.getType(),
5666 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5668 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5669 setValue(&I, Value);
5672 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5673 /// If so, return true and lower it, otherwise return false and it will be
5674 /// lowered like a normal call.
5675 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5676 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5677 if (I.getNumArgOperands() != 3)
5680 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5681 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5682 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5683 !I.getType()->isIntegerTy())
5686 const Value *Size = I.getArgOperand(2);
5687 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5688 if (CSize && CSize->getZExtValue() == 0) {
5689 EVT CallVT = TM.getSubtargetImpl()->getTargetLowering()->getValueType(
5691 setValue(&I, DAG.getConstant(0, CallVT));
5695 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5696 std::pair<SDValue, SDValue> Res =
5697 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5698 getValue(LHS), getValue(RHS), getValue(Size),
5699 MachinePointerInfo(LHS),
5700 MachinePointerInfo(RHS));
5701 if (Res.first.getNode()) {
5702 processIntegerCallValue(I, Res.first, true);
5703 PendingLoads.push_back(Res.second);
5707 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5708 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5709 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5710 bool ActuallyDoIt = true;
5713 switch (CSize->getZExtValue()) {
5715 LoadVT = MVT::Other;
5717 ActuallyDoIt = false;
5721 LoadTy = Type::getInt16Ty(CSize->getContext());
5725 LoadTy = Type::getInt32Ty(CSize->getContext());
5729 LoadTy = Type::getInt64Ty(CSize->getContext());
5733 LoadVT = MVT::v4i32;
5734 LoadTy = Type::getInt32Ty(CSize->getContext());
5735 LoadTy = VectorType::get(LoadTy, 4);
5740 // This turns into unaligned loads. We only do this if the target natively
5741 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5742 // we'll only produce a small number of byte loads.
5744 // Require that we can find a legal MVT, and only do this if the target
5745 // supports unaligned loads of that type. Expanding into byte loads would
5747 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5748 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5749 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5750 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5751 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5752 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5753 // TODO: Check alignment of src and dest ptrs.
5754 if (!TLI->isTypeLegal(LoadVT) ||
5755 !TLI->allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5756 !TLI->allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5757 ActuallyDoIt = false;
5761 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5762 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5764 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5766 processIntegerCallValue(I, Res, false);
5775 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5776 /// form. If so, return true and lower it, otherwise return false and it
5777 /// will be lowered like a normal call.
5778 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5779 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5780 if (I.getNumArgOperands() != 3)
5783 const Value *Src = I.getArgOperand(0);
5784 const Value *Char = I.getArgOperand(1);
5785 const Value *Length = I.getArgOperand(2);
5786 if (!Src->getType()->isPointerTy() ||
5787 !Char->getType()->isIntegerTy() ||
5788 !Length->getType()->isIntegerTy() ||
5789 !I.getType()->isPointerTy())
5792 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5793 std::pair<SDValue, SDValue> Res =
5794 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5795 getValue(Src), getValue(Char), getValue(Length),
5796 MachinePointerInfo(Src));
5797 if (Res.first.getNode()) {
5798 setValue(&I, Res.first);
5799 PendingLoads.push_back(Res.second);
5806 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5807 /// optimized form. If so, return true and lower it, otherwise return false
5808 /// and it will be lowered like a normal call.
5809 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5810 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5811 if (I.getNumArgOperands() != 2)
5814 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5815 if (!Arg0->getType()->isPointerTy() ||
5816 !Arg1->getType()->isPointerTy() ||
5817 !I.getType()->isPointerTy())
5820 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5821 std::pair<SDValue, SDValue> Res =
5822 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5823 getValue(Arg0), getValue(Arg1),
5824 MachinePointerInfo(Arg0),
5825 MachinePointerInfo(Arg1), isStpcpy);
5826 if (Res.first.getNode()) {
5827 setValue(&I, Res.first);
5828 DAG.setRoot(Res.second);
5835 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5836 /// If so, return true and lower it, otherwise return false and it will be
5837 /// lowered like a normal call.
5838 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5839 // Verify that the prototype makes sense. int strcmp(void*,void*)
5840 if (I.getNumArgOperands() != 2)
5843 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5844 if (!Arg0->getType()->isPointerTy() ||
5845 !Arg1->getType()->isPointerTy() ||
5846 !I.getType()->isIntegerTy())
5849 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5850 std::pair<SDValue, SDValue> Res =
5851 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5852 getValue(Arg0), getValue(Arg1),
5853 MachinePointerInfo(Arg0),
5854 MachinePointerInfo(Arg1));
5855 if (Res.first.getNode()) {
5856 processIntegerCallValue(I, Res.first, true);
5857 PendingLoads.push_back(Res.second);
5864 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5865 /// form. If so, return true and lower it, otherwise return false and it
5866 /// will be lowered like a normal call.
5867 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5868 // Verify that the prototype makes sense. size_t strlen(char *)
5869 if (I.getNumArgOperands() != 1)
5872 const Value *Arg0 = I.getArgOperand(0);
5873 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5876 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5877 std::pair<SDValue, SDValue> Res =
5878 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5879 getValue(Arg0), MachinePointerInfo(Arg0));
5880 if (Res.first.getNode()) {
5881 processIntegerCallValue(I, Res.first, false);
5882 PendingLoads.push_back(Res.second);
5889 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5890 /// form. If so, return true and lower it, otherwise return false and it
5891 /// will be lowered like a normal call.
5892 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5893 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5894 if (I.getNumArgOperands() != 2)
5897 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5898 if (!Arg0->getType()->isPointerTy() ||
5899 !Arg1->getType()->isIntegerTy() ||
5900 !I.getType()->isIntegerTy())
5903 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5904 std::pair<SDValue, SDValue> Res =
5905 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5906 getValue(Arg0), getValue(Arg1),
5907 MachinePointerInfo(Arg0));
5908 if (Res.first.getNode()) {
5909 processIntegerCallValue(I, Res.first, false);
5910 PendingLoads.push_back(Res.second);
5917 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5918 /// operation (as expected), translate it to an SDNode with the specified opcode
5919 /// and return true.
5920 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5922 // Sanity check that it really is a unary floating-point call.
5923 if (I.getNumArgOperands() != 1 ||
5924 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5925 I.getType() != I.getArgOperand(0)->getType() ||
5926 !I.onlyReadsMemory())
5929 SDValue Tmp = getValue(I.getArgOperand(0));
5930 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5934 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5935 // Handle inline assembly differently.
5936 if (isa<InlineAsm>(I.getCalledValue())) {
5941 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5942 ComputeUsesVAFloatArgument(I, &MMI);
5944 const char *RenameFn = nullptr;
5945 if (Function *F = I.getCalledFunction()) {
5946 if (F->isDeclaration()) {
5947 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5948 if (unsigned IID = II->getIntrinsicID(F)) {
5949 RenameFn = visitIntrinsicCall(I, IID);
5954 if (unsigned IID = F->getIntrinsicID()) {
5955 RenameFn = visitIntrinsicCall(I, IID);
5961 // Check for well-known libc/libm calls. If the function is internal, it
5962 // can't be a library call.
5964 if (!F->hasLocalLinkage() && F->hasName() &&
5965 LibInfo->getLibFunc(F->getName(), Func) &&
5966 LibInfo->hasOptimizedCodeGen(Func)) {
5969 case LibFunc::copysign:
5970 case LibFunc::copysignf:
5971 case LibFunc::copysignl:
5972 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5973 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5974 I.getType() == I.getArgOperand(0)->getType() &&
5975 I.getType() == I.getArgOperand(1)->getType() &&
5976 I.onlyReadsMemory()) {
5977 SDValue LHS = getValue(I.getArgOperand(0));
5978 SDValue RHS = getValue(I.getArgOperand(1));
5979 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5980 LHS.getValueType(), LHS, RHS));
5985 case LibFunc::fabsf:
5986 case LibFunc::fabsl:
5987 if (visitUnaryFloatCall(I, ISD::FABS))
5993 if (visitUnaryFloatCall(I, ISD::FSIN))
5999 if (visitUnaryFloatCall(I, ISD::FCOS))
6003 case LibFunc::sqrtf:
6004 case LibFunc::sqrtl:
6005 case LibFunc::sqrt_finite:
6006 case LibFunc::sqrtf_finite:
6007 case LibFunc::sqrtl_finite:
6008 if (visitUnaryFloatCall(I, ISD::FSQRT))
6011 case LibFunc::floor:
6012 case LibFunc::floorf:
6013 case LibFunc::floorl:
6014 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6017 case LibFunc::nearbyint:
6018 case LibFunc::nearbyintf:
6019 case LibFunc::nearbyintl:
6020 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6024 case LibFunc::ceilf:
6025 case LibFunc::ceill:
6026 if (visitUnaryFloatCall(I, ISD::FCEIL))
6030 case LibFunc::rintf:
6031 case LibFunc::rintl:
6032 if (visitUnaryFloatCall(I, ISD::FRINT))
6035 case LibFunc::round:
6036 case LibFunc::roundf:
6037 case LibFunc::roundl:
6038 if (visitUnaryFloatCall(I, ISD::FROUND))
6041 case LibFunc::trunc:
6042 case LibFunc::truncf:
6043 case LibFunc::truncl:
6044 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6048 case LibFunc::log2f:
6049 case LibFunc::log2l:
6050 if (visitUnaryFloatCall(I, ISD::FLOG2))
6054 case LibFunc::exp2f:
6055 case LibFunc::exp2l:
6056 if (visitUnaryFloatCall(I, ISD::FEXP2))
6059 case LibFunc::memcmp:
6060 if (visitMemCmpCall(I))
6063 case LibFunc::memchr:
6064 if (visitMemChrCall(I))
6067 case LibFunc::strcpy:
6068 if (visitStrCpyCall(I, false))
6071 case LibFunc::stpcpy:
6072 if (visitStrCpyCall(I, true))
6075 case LibFunc::strcmp:
6076 if (visitStrCmpCall(I))
6079 case LibFunc::strlen:
6080 if (visitStrLenCall(I))
6083 case LibFunc::strnlen:
6084 if (visitStrNLenCall(I))
6093 Callee = getValue(I.getCalledValue());
6095 Callee = DAG.getExternalSymbol(
6096 RenameFn, TM.getSubtargetImpl()->getTargetLowering()->getPointerTy());
6098 // Check if we can potentially perform a tail call. More detailed checking is
6099 // be done within LowerCallTo, after more information about the call is known.
6100 LowerCallTo(&I, Callee, I.isTailCall());
6105 /// AsmOperandInfo - This contains information for each constraint that we are
6107 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6109 /// CallOperand - If this is the result output operand or a clobber
6110 /// this is null, otherwise it is the incoming operand to the CallInst.
6111 /// This gets modified as the asm is processed.
6112 SDValue CallOperand;
6114 /// AssignedRegs - If this is a register or register class operand, this
6115 /// contains the set of register corresponding to the operand.
6116 RegsForValue AssignedRegs;
6118 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6119 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6122 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6123 /// corresponds to. If there is no Value* for this operand, it returns
6125 EVT getCallOperandValEVT(LLVMContext &Context,
6126 const TargetLowering &TLI,
6127 const DataLayout *DL) const {
6128 if (!CallOperandVal) return MVT::Other;
6130 if (isa<BasicBlock>(CallOperandVal))
6131 return TLI.getPointerTy();
6133 llvm::Type *OpTy = CallOperandVal->getType();
6135 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6136 // If this is an indirect operand, the operand is a pointer to the
6139 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6141 report_fatal_error("Indirect operand for inline asm not a pointer!");
6142 OpTy = PtrTy->getElementType();
6145 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6146 if (StructType *STy = dyn_cast<StructType>(OpTy))
6147 if (STy->getNumElements() == 1)
6148 OpTy = STy->getElementType(0);
6150 // If OpTy is not a single value, it may be a struct/union that we
6151 // can tile with integers.
6152 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6153 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6162 OpTy = IntegerType::get(Context, BitSize);
6167 return TLI.getValueType(OpTy, true);
6171 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6173 } // end anonymous namespace
6175 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6176 /// specified operand. We prefer to assign virtual registers, to allow the
6177 /// register allocator to handle the assignment process. However, if the asm
6178 /// uses features that we can't model on machineinstrs, we have SDISel do the
6179 /// allocation. This produces generally horrible, but correct, code.
6181 /// OpInfo describes the operand.
6183 static void GetRegistersForValue(SelectionDAG &DAG,
6184 const TargetLowering &TLI,
6186 SDISelAsmOperandInfo &OpInfo) {
6187 LLVMContext &Context = *DAG.getContext();
6189 MachineFunction &MF = DAG.getMachineFunction();
6190 SmallVector<unsigned, 4> Regs;
6192 // If this is a constraint for a single physreg, or a constraint for a
6193 // register class, find it.
6194 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6195 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6196 OpInfo.ConstraintVT);
6198 unsigned NumRegs = 1;
6199 if (OpInfo.ConstraintVT != MVT::Other) {
6200 // If this is a FP input in an integer register (or visa versa) insert a bit
6201 // cast of the input value. More generally, handle any case where the input
6202 // value disagrees with the register class we plan to stick this in.
6203 if (OpInfo.Type == InlineAsm::isInput &&
6204 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6205 // Try to convert to the first EVT that the reg class contains. If the
6206 // types are identical size, use a bitcast to convert (e.g. two differing
6208 MVT RegVT = *PhysReg.second->vt_begin();
6209 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6210 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6211 RegVT, OpInfo.CallOperand);
6212 OpInfo.ConstraintVT = RegVT;
6213 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6214 // If the input is a FP value and we want it in FP registers, do a
6215 // bitcast to the corresponding integer type. This turns an f64 value
6216 // into i64, which can be passed with two i32 values on a 32-bit
6218 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6219 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6220 RegVT, OpInfo.CallOperand);
6221 OpInfo.ConstraintVT = RegVT;
6225 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6229 EVT ValueVT = OpInfo.ConstraintVT;
6231 // If this is a constraint for a specific physical register, like {r17},
6233 if (unsigned AssignedReg = PhysReg.first) {
6234 const TargetRegisterClass *RC = PhysReg.second;
6235 if (OpInfo.ConstraintVT == MVT::Other)
6236 ValueVT = *RC->vt_begin();
6238 // Get the actual register value type. This is important, because the user
6239 // may have asked for (e.g.) the AX register in i32 type. We need to
6240 // remember that AX is actually i16 to get the right extension.
6241 RegVT = *RC->vt_begin();
6243 // This is a explicit reference to a physical register.
6244 Regs.push_back(AssignedReg);
6246 // If this is an expanded reference, add the rest of the regs to Regs.
6248 TargetRegisterClass::iterator I = RC->begin();
6249 for (; *I != AssignedReg; ++I)
6250 assert(I != RC->end() && "Didn't find reg!");
6252 // Already added the first reg.
6254 for (; NumRegs; --NumRegs, ++I) {
6255 assert(I != RC->end() && "Ran out of registers to allocate!");
6260 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6264 // Otherwise, if this was a reference to an LLVM register class, create vregs
6265 // for this reference.
6266 if (const TargetRegisterClass *RC = PhysReg.second) {
6267 RegVT = *RC->vt_begin();
6268 if (OpInfo.ConstraintVT == MVT::Other)
6271 // Create the appropriate number of virtual registers.
6272 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6273 for (; NumRegs; --NumRegs)
6274 Regs.push_back(RegInfo.createVirtualRegister(RC));
6276 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6280 // Otherwise, we couldn't allocate enough registers for this.
6283 /// visitInlineAsm - Handle a call to an InlineAsm object.
6285 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6286 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6288 /// ConstraintOperands - Information about all of the constraints.
6289 SDISelAsmOperandInfoVector ConstraintOperands;
6291 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6292 TargetLowering::AsmOperandInfoVector
6293 TargetConstraints = TLI->ParseConstraints(CS);
6295 bool hasMemory = false;
6297 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6298 unsigned ResNo = 0; // ResNo - The result number of the next output.
6299 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6300 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6301 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6303 MVT OpVT = MVT::Other;
6305 // Compute the value type for each operand.
6306 switch (OpInfo.Type) {
6307 case InlineAsm::isOutput:
6308 // Indirect outputs just consume an argument.
6309 if (OpInfo.isIndirect) {
6310 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6314 // The return value of the call is this value. As such, there is no
6315 // corresponding argument.
6316 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6317 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6318 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6320 assert(ResNo == 0 && "Asm only has one result!");
6321 OpVT = TLI->getSimpleValueType(CS.getType());
6325 case InlineAsm::isInput:
6326 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6328 case InlineAsm::isClobber:
6333 // If this is an input or an indirect output, process the call argument.
6334 // BasicBlocks are labels, currently appearing only in asm's.
6335 if (OpInfo.CallOperandVal) {
6336 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6337 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6339 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6342 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, DL).
6346 OpInfo.ConstraintVT = OpVT;
6348 // Indirect operand accesses access memory.
6349 if (OpInfo.isIndirect)
6352 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6353 TargetLowering::ConstraintType
6354 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6355 if (CType == TargetLowering::C_Memory) {
6363 SDValue Chain, Flag;
6365 // We won't need to flush pending loads if this asm doesn't touch
6366 // memory and is nonvolatile.
6367 if (hasMemory || IA->hasSideEffects())
6370 Chain = DAG.getRoot();
6372 // Second pass over the constraints: compute which constraint option to use
6373 // and assign registers to constraints that want a specific physreg.
6374 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6375 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6377 // If this is an output operand with a matching input operand, look up the
6378 // matching input. If their types mismatch, e.g. one is an integer, the
6379 // other is floating point, or their sizes are different, flag it as an
6381 if (OpInfo.hasMatchingInput()) {
6382 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6384 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6385 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6386 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6387 OpInfo.ConstraintVT);
6388 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6389 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6390 Input.ConstraintVT);
6391 if ((OpInfo.ConstraintVT.isInteger() !=
6392 Input.ConstraintVT.isInteger()) ||
6393 (MatchRC.second != InputRC.second)) {
6394 report_fatal_error("Unsupported asm: input constraint"
6395 " with a matching output constraint of"
6396 " incompatible type!");
6398 Input.ConstraintVT = OpInfo.ConstraintVT;
6402 // Compute the constraint code and ConstraintType to use.
6403 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6405 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6406 OpInfo.Type == InlineAsm::isClobber)
6409 // If this is a memory input, and if the operand is not indirect, do what we
6410 // need to to provide an address for the memory input.
6411 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6412 !OpInfo.isIndirect) {
6413 assert((OpInfo.isMultipleAlternative ||
6414 (OpInfo.Type == InlineAsm::isInput)) &&
6415 "Can only indirectify direct input operands!");
6417 // Memory operands really want the address of the value. If we don't have
6418 // an indirect input, put it in the constpool if we can, otherwise spill
6419 // it to a stack slot.
6420 // TODO: This isn't quite right. We need to handle these according to
6421 // the addressing mode that the constraint wants. Also, this may take
6422 // an additional register for the computation and we don't want that
6425 // If the operand is a float, integer, or vector constant, spill to a
6426 // constant pool entry to get its address.
6427 const Value *OpVal = OpInfo.CallOperandVal;
6428 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6429 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6430 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6431 TLI->getPointerTy());
6433 // Otherwise, create a stack slot and emit a store to it before the
6435 Type *Ty = OpVal->getType();
6436 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6437 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6438 MachineFunction &MF = DAG.getMachineFunction();
6439 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6440 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6441 Chain = DAG.getStore(Chain, getCurSDLoc(),
6442 OpInfo.CallOperand, StackSlot,
6443 MachinePointerInfo::getFixedStack(SSFI),
6445 OpInfo.CallOperand = StackSlot;
6448 // There is no longer a Value* corresponding to this operand.
6449 OpInfo.CallOperandVal = nullptr;
6451 // It is now an indirect operand.
6452 OpInfo.isIndirect = true;
6455 // If this constraint is for a specific register, allocate it before
6457 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6458 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6461 // Second pass - Loop over all of the operands, assigning virtual or physregs
6462 // to register class operands.
6463 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6464 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6466 // C_Register operands have already been allocated, Other/Memory don't need
6468 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6469 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6472 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6473 std::vector<SDValue> AsmNodeOperands;
6474 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6475 AsmNodeOperands.push_back(
6476 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6477 TLI->getPointerTy()));
6479 // If we have a !srcloc metadata node associated with it, we want to attach
6480 // this to the ultimately generated inline asm machineinstr. To do this, we
6481 // pass in the third operand as this (potentially null) inline asm MDNode.
6482 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6483 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6485 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6486 // bits as operand 3.
6487 unsigned ExtraInfo = 0;
6488 if (IA->hasSideEffects())
6489 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6490 if (IA->isAlignStack())
6491 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6492 // Set the asm dialect.
6493 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6495 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6496 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6497 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6499 // Compute the constraint code and ConstraintType to use.
6500 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6502 // Ideally, we would only check against memory constraints. However, the
6503 // meaning of an other constraint can be target-specific and we can't easily
6504 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6505 // for other constriants as well.
6506 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6507 OpInfo.ConstraintType == TargetLowering::C_Other) {
6508 if (OpInfo.Type == InlineAsm::isInput)
6509 ExtraInfo |= InlineAsm::Extra_MayLoad;
6510 else if (OpInfo.Type == InlineAsm::isOutput)
6511 ExtraInfo |= InlineAsm::Extra_MayStore;
6512 else if (OpInfo.Type == InlineAsm::isClobber)
6513 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6517 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6518 TLI->getPointerTy()));
6520 // Loop over all of the inputs, copying the operand values into the
6521 // appropriate registers and processing the output regs.
6522 RegsForValue RetValRegs;
6524 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6525 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6527 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6528 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6530 switch (OpInfo.Type) {
6531 case InlineAsm::isOutput: {
6532 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6533 OpInfo.ConstraintType != TargetLowering::C_Register) {
6534 // Memory output, or 'other' output (e.g. 'X' constraint).
6535 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6537 // Add information to the INLINEASM node to know about this output.
6538 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6539 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6540 TLI->getPointerTy()));
6541 AsmNodeOperands.push_back(OpInfo.CallOperand);
6545 // Otherwise, this is a register or register class output.
6547 // Copy the output from the appropriate register. Find a register that
6549 if (OpInfo.AssignedRegs.Regs.empty()) {
6550 LLVMContext &Ctx = *DAG.getContext();
6551 Ctx.emitError(CS.getInstruction(),
6552 "couldn't allocate output register for constraint '" +
6553 Twine(OpInfo.ConstraintCode) + "'");
6557 // If this is an indirect operand, store through the pointer after the
6559 if (OpInfo.isIndirect) {
6560 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6561 OpInfo.CallOperandVal));
6563 // This is the result value of the call.
6564 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6565 // Concatenate this output onto the outputs list.
6566 RetValRegs.append(OpInfo.AssignedRegs);
6569 // Add information to the INLINEASM node to know that this register is
6572 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6573 ? InlineAsm::Kind_RegDefEarlyClobber
6574 : InlineAsm::Kind_RegDef,
6575 false, 0, DAG, AsmNodeOperands);
6578 case InlineAsm::isInput: {
6579 SDValue InOperandVal = OpInfo.CallOperand;
6581 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6582 // If this is required to match an output register we have already set,
6583 // just use its register.
6584 unsigned OperandNo = OpInfo.getMatchedOperand();
6586 // Scan until we find the definition we already emitted of this operand.
6587 // When we find it, create a RegsForValue operand.
6588 unsigned CurOp = InlineAsm::Op_FirstOperand;
6589 for (; OperandNo; --OperandNo) {
6590 // Advance to the next operand.
6592 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6593 assert((InlineAsm::isRegDefKind(OpFlag) ||
6594 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6595 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6596 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6600 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6601 if (InlineAsm::isRegDefKind(OpFlag) ||
6602 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6603 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6604 if (OpInfo.isIndirect) {
6605 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6606 LLVMContext &Ctx = *DAG.getContext();
6607 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6608 " don't know how to handle tied "
6609 "indirect register inputs");
6613 RegsForValue MatchedRegs;
6614 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6615 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6616 MatchedRegs.RegVTs.push_back(RegVT);
6617 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6618 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6620 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6621 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6623 LLVMContext &Ctx = *DAG.getContext();
6624 Ctx.emitError(CS.getInstruction(),
6625 "inline asm error: This value"
6626 " type register class is not natively supported!");
6630 // Use the produced MatchedRegs object to
6631 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6632 Chain, &Flag, CS.getInstruction());
6633 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6634 true, OpInfo.getMatchedOperand(),
6635 DAG, AsmNodeOperands);
6639 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6640 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6641 "Unexpected number of operands");
6642 // Add information to the INLINEASM node to know about this input.
6643 // See InlineAsm.h isUseOperandTiedToDef.
6644 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6645 OpInfo.getMatchedOperand());
6646 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6647 TLI->getPointerTy()));
6648 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6652 // Treat indirect 'X' constraint as memory.
6653 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6655 OpInfo.ConstraintType = TargetLowering::C_Memory;
6657 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6658 std::vector<SDValue> Ops;
6659 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6662 LLVMContext &Ctx = *DAG.getContext();
6663 Ctx.emitError(CS.getInstruction(),
6664 "invalid operand for inline asm constraint '" +
6665 Twine(OpInfo.ConstraintCode) + "'");
6669 // Add information to the INLINEASM node to know about this input.
6670 unsigned ResOpType =
6671 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6672 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6673 TLI->getPointerTy()));
6674 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6678 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6679 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6680 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6681 "Memory operands expect pointer values");
6683 // Add information to the INLINEASM node to know about this input.
6684 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6685 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6686 TLI->getPointerTy()));
6687 AsmNodeOperands.push_back(InOperandVal);
6691 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6692 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6693 "Unknown constraint type!");
6695 // TODO: Support this.
6696 if (OpInfo.isIndirect) {
6697 LLVMContext &Ctx = *DAG.getContext();
6698 Ctx.emitError(CS.getInstruction(),
6699 "Don't know how to handle indirect register inputs yet "
6700 "for constraint '" +
6701 Twine(OpInfo.ConstraintCode) + "'");
6705 // Copy the input into the appropriate registers.
6706 if (OpInfo.AssignedRegs.Regs.empty()) {
6707 LLVMContext &Ctx = *DAG.getContext();
6708 Ctx.emitError(CS.getInstruction(),
6709 "couldn't allocate input reg for constraint '" +
6710 Twine(OpInfo.ConstraintCode) + "'");
6714 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6715 Chain, &Flag, CS.getInstruction());
6717 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6718 DAG, AsmNodeOperands);
6721 case InlineAsm::isClobber: {
6722 // Add the clobbered value to the operand list, so that the register
6723 // allocator is aware that the physreg got clobbered.
6724 if (!OpInfo.AssignedRegs.Regs.empty())
6725 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6733 // Finish up input operands. Set the input chain and add the flag last.
6734 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6735 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6737 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6738 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6739 Flag = Chain.getValue(1);
6741 // If this asm returns a register value, copy the result from that register
6742 // and set it as the value of the call.
6743 if (!RetValRegs.Regs.empty()) {
6744 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6745 Chain, &Flag, CS.getInstruction());
6747 // FIXME: Why don't we do this for inline asms with MRVs?
6748 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6749 EVT ResultType = TLI->getValueType(CS.getType());
6751 // If any of the results of the inline asm is a vector, it may have the
6752 // wrong width/num elts. This can happen for register classes that can
6753 // contain multiple different value types. The preg or vreg allocated may
6754 // not have the same VT as was expected. Convert it to the right type
6755 // with bit_convert.
6756 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6757 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6760 } else if (ResultType != Val.getValueType() &&
6761 ResultType.isInteger() && Val.getValueType().isInteger()) {
6762 // If a result value was tied to an input value, the computed result may
6763 // have a wider width than the expected result. Extract the relevant
6765 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6768 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6771 setValue(CS.getInstruction(), Val);
6772 // Don't need to use this as a chain in this case.
6773 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6777 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6779 // Process indirect outputs, first output all of the flagged copies out of
6781 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6782 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6783 const Value *Ptr = IndirectStoresToEmit[i].second;
6784 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6786 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6789 // Emit the non-flagged stores from the physregs.
6790 SmallVector<SDValue, 8> OutChains;
6791 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6792 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6793 StoresToEmit[i].first,
6794 getValue(StoresToEmit[i].second),
6795 MachinePointerInfo(StoresToEmit[i].second),
6797 OutChains.push_back(Val);
6800 if (!OutChains.empty())
6801 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6806 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6807 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6808 MVT::Other, getRoot(),
6809 getValue(I.getArgOperand(0)),
6810 DAG.getSrcValue(I.getArgOperand(0))));
6813 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6814 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6815 const DataLayout &DL = *TLI->getDataLayout();
6816 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6817 getRoot(), getValue(I.getOperand(0)),
6818 DAG.getSrcValue(I.getOperand(0)),
6819 DL.getABITypeAlignment(I.getType()));
6821 DAG.setRoot(V.getValue(1));
6824 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6825 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6826 MVT::Other, getRoot(),
6827 getValue(I.getArgOperand(0)),
6828 DAG.getSrcValue(I.getArgOperand(0))));
6831 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6832 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6833 MVT::Other, getRoot(),
6834 getValue(I.getArgOperand(0)),
6835 getValue(I.getArgOperand(1)),
6836 DAG.getSrcValue(I.getArgOperand(0)),
6837 DAG.getSrcValue(I.getArgOperand(1))));
6840 /// \brief Lower an argument list according to the target calling convention.
6842 /// \return A tuple of <return-value, token-chain>
6844 /// This is a helper for lowering intrinsics that follow a target calling
6845 /// convention or require stack pointer adjustment. Only a subset of the
6846 /// intrinsic's operands need to participate in the calling convention.
6847 std::pair<SDValue, SDValue>
6848 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6849 unsigned NumArgs, SDValue Callee,
6851 TargetLowering::ArgListTy Args;
6852 Args.reserve(NumArgs);
6854 // Populate the argument list.
6855 // Attributes for args start at offset 1, after the return attribute.
6856 ImmutableCallSite CS(&CI);
6857 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6858 ArgI != ArgE; ++ArgI) {
6859 const Value *V = CI.getOperand(ArgI);
6861 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6863 TargetLowering::ArgListEntry Entry;
6864 Entry.Node = getValue(V);
6865 Entry.Ty = V->getType();
6866 Entry.setAttributes(&CS, AttrI);
6867 Args.push_back(Entry);
6870 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6871 TargetLowering::CallLoweringInfo CLI(DAG);
6872 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6873 .setCallee(CI.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6874 .setDiscardResult(!CI.use_empty());
6876 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
6877 return TLI->LowerCallTo(CLI);
6880 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6881 /// or patchpoint target node's operand list.
6883 /// Constants are converted to TargetConstants purely as an optimization to
6884 /// avoid constant materialization and register allocation.
6886 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6887 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6888 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6889 /// address materialization and register allocation, but may also be required
6890 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6891 /// alloca in the entry block, then the runtime may assume that the alloca's
6892 /// StackMap location can be read immediately after compilation and that the
6893 /// location is valid at any point during execution (this is similar to the
6894 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6895 /// only available in a register, then the runtime would need to trap when
6896 /// execution reaches the StackMap in order to read the alloca's location.
6897 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6898 SmallVectorImpl<SDValue> &Ops,
6899 SelectionDAGBuilder &Builder) {
6900 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6901 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6902 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6904 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6906 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6907 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6908 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6910 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6912 Ops.push_back(OpVal);
6916 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6917 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6918 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6919 // [live variables...])
6921 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6923 SDValue Chain, InFlag, Callee, NullPtr;
6924 SmallVector<SDValue, 32> Ops;
6926 SDLoc DL = getCurSDLoc();
6927 Callee = getValue(CI.getCalledValue());
6928 NullPtr = DAG.getIntPtrConstant(0, true);
6930 // The stackmap intrinsic only records the live variables (the arguemnts
6931 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6932 // intrinsic, this won't be lowered to a function call. This means we don't
6933 // have to worry about calling conventions and target specific lowering code.
6934 // Instead we perform the call lowering right here.
6936 // chain, flag = CALLSEQ_START(chain, 0)
6937 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6938 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6940 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6941 InFlag = Chain.getValue(1);
6943 // Add the <id> and <numBytes> constants.
6944 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6945 Ops.push_back(DAG.getTargetConstant(
6946 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6947 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6948 Ops.push_back(DAG.getTargetConstant(
6949 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6951 // Push live variables for the stack map.
6952 addStackMapLiveVars(CI, 2, Ops, *this);
6954 // We are not pushing any register mask info here on the operands list,
6955 // because the stackmap doesn't clobber anything.
6957 // Push the chain and the glue flag.
6958 Ops.push_back(Chain);
6959 Ops.push_back(InFlag);
6961 // Create the STACKMAP node.
6962 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6963 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6964 Chain = SDValue(SM, 0);
6965 InFlag = Chain.getValue(1);
6967 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6969 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6971 // Set the root to the target-lowered call chain.
6974 // Inform the Frame Information that we have a stackmap in this function.
6975 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6978 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6979 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6980 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6985 // [live variables...])
6987 CallingConv::ID CC = CI.getCallingConv();
6988 bool isAnyRegCC = CC == CallingConv::AnyReg;
6989 bool hasDef = !CI.getType()->isVoidTy();
6990 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6992 // Get the real number of arguments participating in the call <numArgs>
6993 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6994 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6996 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6997 // Intrinsics include all meta-operands up to but not including CC.
6998 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6999 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
7000 "Not enough arguments provided to the patchpoint intrinsic");
7002 // For AnyRegCC the arguments are lowered later on manually.
7003 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
7004 std::pair<SDValue, SDValue> Result =
7005 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
7007 // Set the root to the target-lowered call chain.
7008 SDValue Chain = Result.second;
7011 SDNode *CallEnd = Chain.getNode();
7012 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7013 CallEnd = CallEnd->getOperand(0).getNode();
7015 /// Get a call instruction from the call sequence chain.
7016 /// Tail calls are not allowed.
7017 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7018 "Expected a callseq node.");
7019 SDNode *Call = CallEnd->getOperand(0).getNode();
7020 bool hasGlue = Call->getGluedNode();
7022 // Replace the target specific call node with the patchable intrinsic.
7023 SmallVector<SDValue, 8> Ops;
7025 // Add the <id> and <numBytes> constants.
7026 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7027 Ops.push_back(DAG.getTargetConstant(
7028 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7029 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7030 Ops.push_back(DAG.getTargetConstant(
7031 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7033 // Assume that the Callee is a constant address.
7034 // FIXME: handle function symbols in the future.
7036 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7037 /*isTarget=*/true));
7039 // Adjust <numArgs> to account for any arguments that have been passed on the
7041 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7042 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7043 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7044 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7046 // Add the calling convention
7047 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7049 // Add the arguments we omitted previously. The register allocator should
7050 // place these in any free register.
7052 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7053 Ops.push_back(getValue(CI.getArgOperand(i)));
7055 // Push the arguments from the call instruction up to the register mask.
7056 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7057 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7060 // Push live variables for the stack map.
7061 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7063 // Push the register mask info.
7065 Ops.push_back(*(Call->op_end()-2));
7067 Ops.push_back(*(Call->op_end()-1));
7069 // Push the chain (this is originally the first operand of the call, but
7070 // becomes now the last or second to last operand).
7071 Ops.push_back(*(Call->op_begin()));
7073 // Push the glue flag (last operand).
7075 Ops.push_back(*(Call->op_end()-1));
7078 if (isAnyRegCC && hasDef) {
7079 // Create the return types based on the intrinsic definition
7080 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7081 SmallVector<EVT, 3> ValueVTs;
7082 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7083 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7085 // There is always a chain and a glue type at the end
7086 ValueVTs.push_back(MVT::Other);
7087 ValueVTs.push_back(MVT::Glue);
7088 NodeTys = DAG.getVTList(ValueVTs);
7090 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7092 // Replace the target specific call node with a PATCHPOINT node.
7093 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7094 getCurSDLoc(), NodeTys, Ops);
7096 // Update the NodeMap.
7099 setValue(&CI, SDValue(MN, 0));
7101 setValue(&CI, Result.first);
7104 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7105 // call sequence. Furthermore the location of the chain and glue can change
7106 // when the AnyReg calling convention is used and the intrinsic returns a
7108 if (isAnyRegCC && hasDef) {
7109 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7110 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7111 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7113 DAG.ReplaceAllUsesWith(Call, MN);
7114 DAG.DeleteNode(Call);
7116 // Inform the Frame Information that we have a patchpoint in this function.
7117 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7120 /// Returns an AttributeSet representing the attributes applied to the return
7121 /// value of the given call.
7122 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7123 SmallVector<Attribute::AttrKind, 2> Attrs;
7125 Attrs.push_back(Attribute::SExt);
7127 Attrs.push_back(Attribute::ZExt);
7129 Attrs.push_back(Attribute::InReg);
7131 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7135 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7136 /// implementation, which just calls LowerCall.
7137 /// FIXME: When all targets are
7138 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7139 std::pair<SDValue, SDValue>
7140 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7141 // Handle the incoming return values from the call.
7143 Type *OrigRetTy = CLI.RetTy;
7144 SmallVector<EVT, 4> RetTys;
7145 SmallVector<uint64_t, 4> Offsets;
7146 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7148 SmallVector<ISD::OutputArg, 4> Outs;
7149 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7151 bool CanLowerReturn =
7152 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7153 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7155 SDValue DemoteStackSlot;
7156 int DemoteStackIdx = -100;
7157 if (!CanLowerReturn) {
7158 // FIXME: equivalent assert?
7159 // assert(!CS.hasInAllocaArgument() &&
7160 // "sret demotion is incompatible with inalloca");
7161 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7162 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7163 MachineFunction &MF = CLI.DAG.getMachineFunction();
7164 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7165 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7167 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7169 Entry.Node = DemoteStackSlot;
7170 Entry.Ty = StackSlotPtrType;
7171 Entry.isSExt = false;
7172 Entry.isZExt = false;
7173 Entry.isInReg = false;
7174 Entry.isSRet = true;
7175 Entry.isNest = false;
7176 Entry.isByVal = false;
7177 Entry.isReturned = false;
7178 Entry.Alignment = Align;
7179 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7180 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7182 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7184 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7185 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7186 for (unsigned i = 0; i != NumRegs; ++i) {
7187 ISD::InputArg MyFlags;
7188 MyFlags.VT = RegisterVT;
7190 MyFlags.Used = CLI.IsReturnValueUsed;
7192 MyFlags.Flags.setSExt();
7194 MyFlags.Flags.setZExt();
7196 MyFlags.Flags.setInReg();
7197 CLI.Ins.push_back(MyFlags);
7202 // Handle all of the outgoing arguments.
7204 CLI.OutVals.clear();
7205 ArgListTy &Args = CLI.getArgs();
7206 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7207 SmallVector<EVT, 4> ValueVTs;
7208 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7209 Type *FinalType = Args[i].Ty;
7210 if (Args[i].isByVal)
7211 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7212 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7213 FinalType, CLI.CallConv, CLI.IsVarArg);
7214 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7216 EVT VT = ValueVTs[Value];
7217 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7218 SDValue Op = SDValue(Args[i].Node.getNode(),
7219 Args[i].Node.getResNo() + Value);
7220 ISD::ArgFlagsTy Flags;
7221 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7227 if (Args[i].isInReg)
7231 if (Args[i].isByVal)
7233 if (Args[i].isInAlloca) {
7234 Flags.setInAlloca();
7235 // Set the byval flag for CCAssignFn callbacks that don't know about
7236 // inalloca. This way we can know how many bytes we should've allocated
7237 // and how many bytes a callee cleanup function will pop. If we port
7238 // inalloca to more targets, we'll have to add custom inalloca handling
7239 // in the various CC lowering callbacks.
7242 if (Args[i].isByVal || Args[i].isInAlloca) {
7243 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7244 Type *ElementTy = Ty->getElementType();
7245 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7246 // For ByVal, alignment should come from FE. BE will guess if this
7247 // info is not there but there are cases it cannot get right.
7248 unsigned FrameAlign;
7249 if (Args[i].Alignment)
7250 FrameAlign = Args[i].Alignment;
7252 FrameAlign = getByValTypeAlignment(ElementTy);
7253 Flags.setByValAlign(FrameAlign);
7258 Flags.setInConsecutiveRegs();
7259 Flags.setOrigAlign(OriginalAlignment);
7261 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7262 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7263 SmallVector<SDValue, 4> Parts(NumParts);
7264 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7267 ExtendKind = ISD::SIGN_EXTEND;
7268 else if (Args[i].isZExt)
7269 ExtendKind = ISD::ZERO_EXTEND;
7271 // Conservatively only handle 'returned' on non-vectors for now
7272 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7273 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7274 "unexpected use of 'returned'");
7275 // Before passing 'returned' to the target lowering code, ensure that
7276 // either the register MVT and the actual EVT are the same size or that
7277 // the return value and argument are extended in the same way; in these
7278 // cases it's safe to pass the argument register value unchanged as the
7279 // return register value (although it's at the target's option whether
7281 // TODO: allow code generation to take advantage of partially preserved
7282 // registers rather than clobbering the entire register when the
7283 // parameter extension method is not compatible with the return
7285 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7286 (ExtendKind != ISD::ANY_EXTEND &&
7287 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7288 Flags.setReturned();
7291 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7292 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7294 for (unsigned j = 0; j != NumParts; ++j) {
7295 // if it isn't first piece, alignment must be 1
7296 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7297 i < CLI.NumFixedArgs,
7298 i, j*Parts[j].getValueType().getStoreSize());
7299 if (NumParts > 1 && j == 0)
7300 MyFlags.Flags.setSplit();
7302 MyFlags.Flags.setOrigAlign(1);
7304 // Only mark the end at the last register of the last value.
7305 if (NeedsRegBlock && Value == NumValues - 1 && j == NumParts - 1)
7306 MyFlags.Flags.setInConsecutiveRegsLast();
7308 CLI.Outs.push_back(MyFlags);
7309 CLI.OutVals.push_back(Parts[j]);
7314 SmallVector<SDValue, 4> InVals;
7315 CLI.Chain = LowerCall(CLI, InVals);
7317 // Verify that the target's LowerCall behaved as expected.
7318 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7319 "LowerCall didn't return a valid chain!");
7320 assert((!CLI.IsTailCall || InVals.empty()) &&
7321 "LowerCall emitted a return value for a tail call!");
7322 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7323 "LowerCall didn't emit the correct number of values!");
7325 // For a tail call, the return value is merely live-out and there aren't
7326 // any nodes in the DAG representing it. Return a special value to
7327 // indicate that a tail call has been emitted and no more Instructions
7328 // should be processed in the current block.
7329 if (CLI.IsTailCall) {
7330 CLI.DAG.setRoot(CLI.Chain);
7331 return std::make_pair(SDValue(), SDValue());
7334 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7335 assert(InVals[i].getNode() &&
7336 "LowerCall emitted a null value!");
7337 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7338 "LowerCall emitted a value with the wrong type!");
7341 SmallVector<SDValue, 4> ReturnValues;
7342 if (!CanLowerReturn) {
7343 // The instruction result is the result of loading from the
7344 // hidden sret parameter.
7345 SmallVector<EVT, 1> PVTs;
7346 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7348 ComputeValueVTs(*this, PtrRetTy, PVTs);
7349 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7350 EVT PtrVT = PVTs[0];
7352 unsigned NumValues = RetTys.size();
7353 ReturnValues.resize(NumValues);
7354 SmallVector<SDValue, 4> Chains(NumValues);
7356 for (unsigned i = 0; i < NumValues; ++i) {
7357 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7358 CLI.DAG.getConstant(Offsets[i], PtrVT));
7359 SDValue L = CLI.DAG.getLoad(
7360 RetTys[i], CLI.DL, CLI.Chain, Add,
7361 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7363 ReturnValues[i] = L;
7364 Chains[i] = L.getValue(1);
7367 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7369 // Collect the legal value parts into potentially illegal values
7370 // that correspond to the original function's return values.
7371 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7373 AssertOp = ISD::AssertSext;
7374 else if (CLI.RetZExt)
7375 AssertOp = ISD::AssertZext;
7376 unsigned CurReg = 0;
7377 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7379 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7380 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7382 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7383 NumRegs, RegisterVT, VT, nullptr,
7388 // For a function returning void, there is no return value. We can't create
7389 // such a node, so we just return a null return value in that case. In
7390 // that case, nothing will actually look at the value.
7391 if (ReturnValues.empty())
7392 return std::make_pair(SDValue(), CLI.Chain);
7395 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7396 CLI.DAG.getVTList(RetTys), ReturnValues);
7397 return std::make_pair(Res, CLI.Chain);
7400 void TargetLowering::LowerOperationWrapper(SDNode *N,
7401 SmallVectorImpl<SDValue> &Results,
7402 SelectionDAG &DAG) const {
7403 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7405 Results.push_back(Res);
7408 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7409 llvm_unreachable("LowerOperation not implemented for this target!");
7413 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7414 SDValue Op = getNonRegisterValue(V);
7415 assert((Op.getOpcode() != ISD::CopyFromReg ||
7416 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7417 "Copy from a reg to the same reg!");
7418 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7420 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
7421 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7422 SDValue Chain = DAG.getEntryNode();
7423 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V);
7424 PendingExports.push_back(Chain);
7427 #include "llvm/CodeGen/SelectionDAGISel.h"
7429 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7430 /// entry block, return true. This includes arguments used by switches, since
7431 /// the switch may expand into multiple basic blocks.
7432 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7433 // With FastISel active, we may be splitting blocks, so force creation
7434 // of virtual registers for all non-dead arguments.
7436 return A->use_empty();
7438 const BasicBlock *Entry = A->getParent()->begin();
7439 for (const User *U : A->users())
7440 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7441 return false; // Use not in entry block.
7446 void SelectionDAGISel::LowerArguments(const Function &F) {
7447 SelectionDAG &DAG = SDB->DAG;
7448 SDLoc dl = SDB->getCurSDLoc();
7449 const TargetLowering *TLI = getTargetLowering();
7450 const DataLayout *DL = TLI->getDataLayout();
7451 SmallVector<ISD::InputArg, 16> Ins;
7453 if (!FuncInfo->CanLowerReturn) {
7454 // Put in an sret pointer parameter before all the other parameters.
7455 SmallVector<EVT, 1> ValueVTs;
7456 ComputeValueVTs(*getTargetLowering(),
7457 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7459 // NOTE: Assuming that a pointer will never break down to more than one VT
7461 ISD::ArgFlagsTy Flags;
7463 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7464 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7465 Ins.push_back(RetArg);
7468 // Set up the incoming argument description vector.
7470 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7471 I != E; ++I, ++Idx) {
7472 SmallVector<EVT, 4> ValueVTs;
7473 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7474 bool isArgValueUsed = !I->use_empty();
7475 unsigned PartBase = 0;
7476 Type *FinalType = I->getType();
7477 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7478 FinalType = cast<PointerType>(FinalType)->getElementType();
7479 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7480 FinalType, F.getCallingConv(), F.isVarArg());
7481 for (unsigned Value = 0, NumValues = ValueVTs.size();
7482 Value != NumValues; ++Value) {
7483 EVT VT = ValueVTs[Value];
7484 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7485 ISD::ArgFlagsTy Flags;
7486 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7488 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7490 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7492 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7494 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7496 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7498 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7499 Flags.setInAlloca();
7500 // Set the byval flag for CCAssignFn callbacks that don't know about
7501 // inalloca. This way we can know how many bytes we should've allocated
7502 // and how many bytes a callee cleanup function will pop. If we port
7503 // inalloca to more targets, we'll have to add custom inalloca handling
7504 // in the various CC lowering callbacks.
7507 if (Flags.isByVal() || Flags.isInAlloca()) {
7508 PointerType *Ty = cast<PointerType>(I->getType());
7509 Type *ElementTy = Ty->getElementType();
7510 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7511 // For ByVal, alignment should be passed from FE. BE will guess if
7512 // this info is not there but there are cases it cannot get right.
7513 unsigned FrameAlign;
7514 if (F.getParamAlignment(Idx))
7515 FrameAlign = F.getParamAlignment(Idx);
7517 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7518 Flags.setByValAlign(FrameAlign);
7520 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7523 Flags.setInConsecutiveRegs();
7524 Flags.setOrigAlign(OriginalAlignment);
7526 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7527 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7528 for (unsigned i = 0; i != NumRegs; ++i) {
7529 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7530 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7531 if (NumRegs > 1 && i == 0)
7532 MyFlags.Flags.setSplit();
7533 // if it isn't first piece, alignment must be 1
7535 MyFlags.Flags.setOrigAlign(1);
7537 // Only mark the end at the last register of the last value.
7538 if (NeedsRegBlock && Value == NumValues - 1 && i == NumRegs - 1)
7539 MyFlags.Flags.setInConsecutiveRegsLast();
7541 Ins.push_back(MyFlags);
7543 PartBase += VT.getStoreSize();
7547 // Call the target to set up the argument values.
7548 SmallVector<SDValue, 8> InVals;
7549 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7553 // Verify that the target's LowerFormalArguments behaved as expected.
7554 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7555 "LowerFormalArguments didn't return a valid chain!");
7556 assert(InVals.size() == Ins.size() &&
7557 "LowerFormalArguments didn't emit the correct number of values!");
7559 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7560 assert(InVals[i].getNode() &&
7561 "LowerFormalArguments emitted a null value!");
7562 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7563 "LowerFormalArguments emitted a value with the wrong type!");
7567 // Update the DAG with the new chain value resulting from argument lowering.
7568 DAG.setRoot(NewRoot);
7570 // Set up the argument values.
7573 if (!FuncInfo->CanLowerReturn) {
7574 // Create a virtual register for the sret pointer, and put in a copy
7575 // from the sret argument into it.
7576 SmallVector<EVT, 1> ValueVTs;
7577 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7578 MVT VT = ValueVTs[0].getSimpleVT();
7579 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7580 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7581 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7582 RegVT, VT, nullptr, AssertOp);
7584 MachineFunction& MF = SDB->DAG.getMachineFunction();
7585 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7586 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7587 FuncInfo->DemoteRegister = SRetReg;
7588 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7590 DAG.setRoot(NewRoot);
7592 // i indexes lowered arguments. Bump it past the hidden sret argument.
7593 // Idx indexes LLVM arguments. Don't touch it.
7597 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7599 SmallVector<SDValue, 4> ArgValues;
7600 SmallVector<EVT, 4> ValueVTs;
7601 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7602 unsigned NumValues = ValueVTs.size();
7604 // If this argument is unused then remember its value. It is used to generate
7605 // debugging information.
7606 if (I->use_empty() && NumValues) {
7607 SDB->setUnusedArgValue(I, InVals[i]);
7609 // Also remember any frame index for use in FastISel.
7610 if (FrameIndexSDNode *FI =
7611 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7612 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7615 for (unsigned Val = 0; Val != NumValues; ++Val) {
7616 EVT VT = ValueVTs[Val];
7617 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7618 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7620 if (!I->use_empty()) {
7621 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7622 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7623 AssertOp = ISD::AssertSext;
7624 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7625 AssertOp = ISD::AssertZext;
7627 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7628 NumParts, PartVT, VT,
7629 nullptr, AssertOp));
7635 // We don't need to do anything else for unused arguments.
7636 if (ArgValues.empty())
7639 // Note down frame index.
7640 if (FrameIndexSDNode *FI =
7641 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7642 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7644 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7645 SDB->getCurSDLoc());
7647 SDB->setValue(I, Res);
7648 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7649 if (LoadSDNode *LNode =
7650 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7651 if (FrameIndexSDNode *FI =
7652 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7653 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7656 // If this argument is live outside of the entry block, insert a copy from
7657 // wherever we got it to the vreg that other BB's will reference it as.
7658 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7659 // If we can, though, try to skip creating an unnecessary vreg.
7660 // FIXME: This isn't very clean... it would be nice to make this more
7661 // general. It's also subtly incompatible with the hacks FastISel
7663 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7664 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7665 FuncInfo->ValueMap[I] = Reg;
7669 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7670 FuncInfo->InitializeRegForValue(I);
7671 SDB->CopyToExportRegsIfNeeded(I);
7675 assert(i == InVals.size() && "Argument register count mismatch!");
7677 // Finally, if the target has anything special to do, allow it to do so.
7678 // FIXME: this should insert code into the DAG!
7679 EmitFunctionEntryCode();
7682 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7683 /// ensure constants are generated when needed. Remember the virtual registers
7684 /// that need to be added to the Machine PHI nodes as input. We cannot just
7685 /// directly add them, because expansion might result in multiple MBB's for one
7686 /// BB. As such, the start of the BB might correspond to a different MBB than
7690 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7691 const TerminatorInst *TI = LLVMBB->getTerminator();
7693 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7695 // Check successor nodes' PHI nodes that expect a constant to be available
7697 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7698 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7699 if (!isa<PHINode>(SuccBB->begin())) continue;
7700 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7702 // If this terminator has multiple identical successors (common for
7703 // switches), only handle each succ once.
7704 if (!SuccsHandled.insert(SuccMBB)) continue;
7706 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7708 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7709 // nodes and Machine PHI nodes, but the incoming operands have not been
7711 for (BasicBlock::const_iterator I = SuccBB->begin();
7712 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7713 // Ignore dead phi's.
7714 if (PN->use_empty()) continue;
7717 if (PN->getType()->isEmptyTy())
7721 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7723 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7724 unsigned &RegOut = ConstantsOut[C];
7726 RegOut = FuncInfo.CreateRegs(C->getType());
7727 CopyValueToVirtualRegister(C, RegOut);
7731 DenseMap<const Value *, unsigned>::iterator I =
7732 FuncInfo.ValueMap.find(PHIOp);
7733 if (I != FuncInfo.ValueMap.end())
7736 assert(isa<AllocaInst>(PHIOp) &&
7737 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7738 "Didn't codegen value into a register!??");
7739 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7740 CopyValueToVirtualRegister(PHIOp, Reg);
7744 // Remember that this register needs to added to the machine PHI node as
7745 // the input for this MBB.
7746 SmallVector<EVT, 4> ValueVTs;
7747 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
7748 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7749 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7750 EVT VT = ValueVTs[vti];
7751 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7752 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7753 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7754 Reg += NumRegisters;
7759 ConstantsOut.clear();
7762 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7765 SelectionDAGBuilder::StackProtectorDescriptor::
7766 AddSuccessorMBB(const BasicBlock *BB,
7767 MachineBasicBlock *ParentMBB,
7768 MachineBasicBlock *SuccMBB) {
7769 // If SuccBB has not been created yet, create it.
7771 MachineFunction *MF = ParentMBB->getParent();
7772 MachineFunction::iterator BBI = ParentMBB;
7773 SuccMBB = MF->CreateMachineBasicBlock(BB);
7774 MF->insert(++BBI, SuccMBB);
7776 // Add it as a successor of ParentMBB.
7777 ParentMBB->addSuccessor(SuccMBB);