1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
82 // Limit the width of DAG chains. This is important in general to prevent
83 // prevent DAG-based analysis from blowing up. For example, alias analysis and
84 // load clustering may not complete in reasonable time. It is difficult to
85 // recognize and avoid this situation within each individual analysis, and
86 // future analyses are likely to have the same behavior. Limiting DAG width is
87 // the safe approach, and will be especially important with global DAGs.
89 // MaxParallelChains default is arbitrarily high to avoid affecting
90 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
91 // sequence over this should have been converted to llvm.memcpy by the
92 // frontend. It easy to induce this behavior with .ll code such as:
93 // %buffer = alloca [4096 x i8]
94 // %data = load [4096 x i8]* %argPtr
95 // store [4096 x i8] %data, [4096 x i8]* %buffer
96 static const unsigned MaxParallelChains = 64;
98 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
99 const SDValue *Parts, unsigned NumParts,
100 MVT PartVT, EVT ValueVT, const Value *V);
102 /// getCopyFromParts - Create a value that contains the specified legal parts
103 /// combined into the value they represent. If the parts combine to a type
104 /// larger then ValueVT then AssertOp can be used to specify whether the extra
105 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
106 /// (ISD::AssertSext).
107 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
108 const SDValue *Parts,
109 unsigned NumParts, MVT PartVT, EVT ValueVT,
111 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
112 if (ValueVT.isVector())
113 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
116 assert(NumParts > 0 && "No parts to assemble!");
117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
118 SDValue Val = Parts[0];
121 // Assemble the value from multiple parts.
122 if (ValueVT.isInteger()) {
123 unsigned PartBits = PartVT.getSizeInBits();
124 unsigned ValueBits = ValueVT.getSizeInBits();
126 // Assemble the power of 2 part.
127 unsigned RoundParts = NumParts & (NumParts - 1) ?
128 1 << Log2_32(NumParts) : NumParts;
129 unsigned RoundBits = PartBits * RoundParts;
130 EVT RoundVT = RoundBits == ValueBits ?
131 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
134 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
136 if (RoundParts > 2) {
137 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
139 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
140 RoundParts / 2, PartVT, HalfVT, V);
142 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
143 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
146 if (TLI.isBigEndian())
149 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
151 if (RoundParts < NumParts) {
152 // Assemble the trailing non-power-of-2 part.
153 unsigned OddParts = NumParts - RoundParts;
154 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
155 Hi = getCopyFromParts(DAG, DL,
156 Parts + RoundParts, OddParts, PartVT, OddVT, V);
158 // Combine the round and odd parts.
160 if (TLI.isBigEndian())
162 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
163 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
164 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
165 DAG.getConstant(Lo.getValueType().getSizeInBits(),
166 TLI.getPointerTy()));
167 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
168 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
170 } else if (PartVT.isFloatingPoint()) {
171 // FP split into multiple FP parts (for ppcf128)
172 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
175 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
176 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
177 if (TLI.hasBigEndianPartOrdering(ValueVT))
179 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
181 // FP split into integer parts (soft fp)
182 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
183 !PartVT.isVector() && "Unexpected split");
184 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
185 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
189 // There is now one part, held in Val. Correct it to match ValueVT.
190 EVT PartEVT = Val.getValueType();
192 if (PartEVT == ValueVT)
195 if (PartEVT.isInteger() && ValueVT.isInteger()) {
196 if (ValueVT.bitsLT(PartEVT)) {
197 // For a truncate, see if we have any information to
198 // indicate whether the truncated bits will always be
199 // zero or sign-extension.
200 if (AssertOp != ISD::DELETED_NODE)
201 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
202 DAG.getValueType(ValueVT));
203 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
205 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
208 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
209 // FP_ROUND's are always exact here.
210 if (ValueVT.bitsLT(Val.getValueType()))
211 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
212 DAG.getTargetConstant(1, TLI.getPointerTy()));
214 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
217 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
218 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
220 llvm_unreachable("Unknown mismatch!");
223 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
224 const Twine &ErrMsg) {
225 const Instruction *I = dyn_cast_or_null<Instruction>(V);
227 return Ctx.emitError(ErrMsg);
229 const char *AsmError = ", possible invalid constraint for vector type";
230 if (const CallInst *CI = dyn_cast<CallInst>(I))
231 if (isa<InlineAsm>(CI->getCalledValue()))
232 return Ctx.emitError(I, ErrMsg + AsmError);
234 return Ctx.emitError(I, ErrMsg);
237 /// getCopyFromPartsVector - Create a value that contains the specified legal
238 /// parts combined into the value they represent. If the parts combine to a
239 /// type larger then ValueVT then AssertOp can be used to specify whether the
240 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
241 /// ValueVT (ISD::AssertSext).
242 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
243 const SDValue *Parts, unsigned NumParts,
244 MVT PartVT, EVT ValueVT, const Value *V) {
245 assert(ValueVT.isVector() && "Not a vector value");
246 assert(NumParts > 0 && "No parts to assemble!");
247 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
248 SDValue Val = Parts[0];
250 // Handle a multi-element vector.
254 unsigned NumIntermediates;
256 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
257 NumIntermediates, RegisterVT);
258 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
259 NumParts = NumRegs; // Silence a compiler warning.
260 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
261 assert(RegisterVT == Parts[0].getSimpleValueType() &&
262 "Part type doesn't match part!");
264 // Assemble the parts into intermediate operands.
265 SmallVector<SDValue, 8> Ops(NumIntermediates);
266 if (NumIntermediates == NumParts) {
267 // If the register was not expanded, truncate or copy the value,
269 for (unsigned i = 0; i != NumParts; ++i)
270 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
271 PartVT, IntermediateVT, V);
272 } else if (NumParts > 0) {
273 // If the intermediate type was expanded, build the intermediate
274 // operands from the parts.
275 assert(NumParts % NumIntermediates == 0 &&
276 "Must expand into a divisible number of parts!");
277 unsigned Factor = NumParts / NumIntermediates;
278 for (unsigned i = 0; i != NumIntermediates; ++i)
279 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
280 PartVT, IntermediateVT, V);
283 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
284 // intermediate operands.
285 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
290 // There is now one part, held in Val. Correct it to match ValueVT.
291 EVT PartEVT = Val.getValueType();
293 if (PartEVT == ValueVT)
296 if (PartEVT.isVector()) {
297 // If the element type of the source/dest vectors are the same, but the
298 // parts vector has more elements than the value vector, then we have a
299 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
301 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
302 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
303 "Cannot narrow, it would be a lossy transformation");
304 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
305 DAG.getConstant(0, TLI.getVectorIdxTy()));
308 // Vector/Vector bitcast.
309 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
310 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
312 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
313 "Cannot handle this kind of promotion");
314 // Promoted vector extract
315 bool Smaller = ValueVT.bitsLE(PartEVT);
316 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
321 // Trivial bitcast if the types are the same size and the destination
322 // vector type is legal.
323 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
324 TLI.isTypeLegal(ValueVT))
325 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
327 // Handle cases such as i8 -> <1 x i1>
328 if (ValueVT.getVectorNumElements() != 1) {
329 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
330 "non-trivial scalar-to-vector conversion");
331 return DAG.getUNDEF(ValueVT);
334 if (ValueVT.getVectorNumElements() == 1 &&
335 ValueVT.getVectorElementType() != PartEVT) {
336 bool Smaller = ValueVT.bitsLE(PartEVT);
337 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
338 DL, ValueVT.getScalarType(), Val);
341 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
344 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
345 SDValue Val, SDValue *Parts, unsigned NumParts,
346 MVT PartVT, const Value *V);
348 /// getCopyToParts - Create a series of nodes that contain the specified value
349 /// split into legal parts. If the parts contain more bits than Val, then, for
350 /// integers, ExtendKind can be used to specify how to generate the extra bits.
351 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
352 SDValue Val, SDValue *Parts, unsigned NumParts,
353 MVT PartVT, const Value *V,
354 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
355 EVT ValueVT = Val.getValueType();
357 // Handle the vector case separately.
358 if (ValueVT.isVector())
359 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
362 unsigned PartBits = PartVT.getSizeInBits();
363 unsigned OrigNumParts = NumParts;
364 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
369 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
370 EVT PartEVT = PartVT;
371 if (PartEVT == ValueVT) {
372 assert(NumParts == 1 && "No-op copy with multiple parts!");
377 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
378 // If the parts cover more bits than the value has, promote the value.
379 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
380 assert(NumParts == 1 && "Do not know what to promote to!");
381 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
384 ValueVT.isInteger() &&
385 "Unknown mismatch!");
386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
387 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
388 if (PartVT == MVT::x86mmx)
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (PartBits == ValueVT.getSizeInBits()) {
392 // Different types of the same size.
393 assert(NumParts == 1 && PartEVT != ValueVT);
394 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
395 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
396 // If the parts cover less bits than value has, truncate the value.
397 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
398 ValueVT.isInteger() &&
399 "Unknown mismatch!");
400 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
401 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
402 if (PartVT == MVT::x86mmx)
403 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
406 // The value may have changed - recompute ValueVT.
407 ValueVT = Val.getValueType();
408 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
409 "Failed to tile the value with PartVT!");
412 if (PartEVT != ValueVT)
413 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
414 "scalar-to-vector conversion failed");
420 // Expand the value into multiple parts.
421 if (NumParts & (NumParts - 1)) {
422 // The number of parts is not a power of 2. Split off and copy the tail.
423 assert(PartVT.isInteger() && ValueVT.isInteger() &&
424 "Do not know what to expand to!");
425 unsigned RoundParts = 1 << Log2_32(NumParts);
426 unsigned RoundBits = RoundParts * PartBits;
427 unsigned OddParts = NumParts - RoundParts;
428 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
429 DAG.getIntPtrConstant(RoundBits));
430 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
432 if (TLI.isBigEndian())
433 // The odd parts were reversed by getCopyToParts - unreverse them.
434 std::reverse(Parts + RoundParts, Parts + NumParts);
436 NumParts = RoundParts;
437 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
438 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
441 // The number of parts is a power of 2. Repeatedly bisect the value using
443 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
444 EVT::getIntegerVT(*DAG.getContext(),
445 ValueVT.getSizeInBits()),
448 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
449 for (unsigned i = 0; i < NumParts; i += StepSize) {
450 unsigned ThisBits = StepSize * PartBits / 2;
451 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
452 SDValue &Part0 = Parts[i];
453 SDValue &Part1 = Parts[i+StepSize/2];
455 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
456 ThisVT, Part0, DAG.getIntPtrConstant(1));
457 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
458 ThisVT, Part0, DAG.getIntPtrConstant(0));
460 if (ThisBits == PartBits && ThisVT != PartVT) {
461 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
462 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
467 if (TLI.isBigEndian())
468 std::reverse(Parts, Parts + OrigNumParts);
472 /// getCopyToPartsVector - Create a series of nodes that contain the specified
473 /// value split into legal parts.
474 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
475 SDValue Val, SDValue *Parts, unsigned NumParts,
476 MVT PartVT, const Value *V) {
477 EVT ValueVT = Val.getValueType();
478 assert(ValueVT.isVector() && "Not a vector");
479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
482 EVT PartEVT = PartVT;
483 if (PartEVT == ValueVT) {
485 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
486 // Bitconvert vector->vector case.
487 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
488 } else if (PartVT.isVector() &&
489 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
490 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
491 EVT ElementVT = PartVT.getVectorElementType();
492 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
494 SmallVector<SDValue, 16> Ops;
495 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
497 ElementVT, Val, DAG.getConstant(i,
498 TLI.getVectorIdxTy())));
500 for (unsigned i = ValueVT.getVectorNumElements(),
501 e = PartVT.getVectorNumElements(); i != e; ++i)
502 Ops.push_back(DAG.getUNDEF(ElementVT));
504 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
506 // FIXME: Use CONCAT for 2x -> 4x.
508 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
509 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
510 } else if (PartVT.isVector() &&
511 PartEVT.getVectorElementType().bitsGE(
512 ValueVT.getVectorElementType()) &&
513 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
515 // Promoted vector extract
516 bool Smaller = PartEVT.bitsLE(ValueVT);
517 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
520 // Vector -> scalar conversion.
521 assert(ValueVT.getVectorNumElements() == 1 &&
522 "Only trivial vector-to-scalar conversions should get here!");
523 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
526 bool Smaller = ValueVT.bitsLE(PartVT);
527 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
552 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
554 DAG.getConstant(i * (NumElements / NumIntermediates),
555 TLI.getVectorIdxTy()));
557 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
559 DAG.getConstant(i, TLI.getVectorIdxTy()));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
581 /// RegsForValue - This struct represents the registers (physical or virtual)
582 /// that a particular set of values is assigned, and the type information
583 /// about the value. The most common situation is to represent one value at a
584 /// time, but struct or array values are handled element-wise as multiple
585 /// values. The splitting of aggregates is performed recursively, so that we
586 /// never have aggregate-typed registers. The values at this point do not
587 /// necessarily have legal types, so each value may require one or more
588 /// registers of some legal type.
590 struct RegsForValue {
591 /// ValueVTs - The value types of the values, which may not be legal, and
592 /// may need be promoted or synthesized from one or more registers.
594 SmallVector<EVT, 4> ValueVTs;
596 /// RegVTs - The value types of the registers. This is the same size as
597 /// ValueVTs and it records, for each value, what the type of the assigned
598 /// register or registers are. (Individual values are never synthesized
599 /// from more than one type of register.)
601 /// With virtual registers, the contents of RegVTs is redundant with TLI's
602 /// getRegisterType member function, however when with physical registers
603 /// it is necessary to have a separate record of the types.
605 SmallVector<MVT, 4> RegVTs;
607 /// Regs - This list holds the registers assigned to the values.
608 /// Each legal or promoted value requires one register, and each
609 /// expanded value requires multiple registers.
611 SmallVector<unsigned, 4> Regs;
615 RegsForValue(const SmallVector<unsigned, 4> ®s,
616 MVT regvt, EVT valuevt)
617 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
619 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
620 unsigned Reg, Type *Ty) {
621 ComputeValueVTs(tli, Ty, ValueVTs);
623 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
624 EVT ValueVT = ValueVTs[Value];
625 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
626 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
627 for (unsigned i = 0; i != NumRegs; ++i)
628 Regs.push_back(Reg + i);
629 RegVTs.push_back(RegisterVT);
634 /// append - Add the specified values to this one.
635 void append(const RegsForValue &RHS) {
636 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
637 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
638 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
641 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
642 /// this value and returns the result as a ValueVTs value. This uses
643 /// Chain/Flag as the input and updates them for the output Chain/Flag.
644 /// If the Flag pointer is NULL, no flag is used.
645 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
647 SDValue &Chain, SDValue *Flag,
648 const Value *V = nullptr) const;
650 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
651 /// specified value into the registers specified by this object. This uses
652 /// Chain/Flag as the input and updates them for the output Chain/Flag.
653 /// If the Flag pointer is NULL, no flag is used.
655 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
656 SDValue *Flag, const Value *V,
657 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
659 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
660 /// operand list. This adds the code marker, matching input operand index
661 /// (if applicable), and includes the number of values added into it.
662 void AddInlineAsmOperands(unsigned Kind,
663 bool HasMatching, unsigned MatchingIdx,
665 std::vector<SDValue> &Ops) const;
669 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
670 /// this value and returns the result as a ValueVT value. This uses
671 /// Chain/Flag as the input and updates them for the output Chain/Flag.
672 /// If the Flag pointer is NULL, no flag is used.
673 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
674 FunctionLoweringInfo &FuncInfo,
676 SDValue &Chain, SDValue *Flag,
677 const Value *V) const {
678 // A Value with type {} or [0 x %t] needs no registers.
679 if (ValueVTs.empty())
682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
684 // Assemble the legal parts into the final values.
685 SmallVector<SDValue, 4> Values(ValueVTs.size());
686 SmallVector<SDValue, 8> Parts;
687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
688 // Copy the legal parts from the registers.
689 EVT ValueVT = ValueVTs[Value];
690 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
691 MVT RegisterVT = RegVTs[Value];
693 Parts.resize(NumRegs);
694 for (unsigned i = 0; i != NumRegs; ++i) {
697 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
699 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
700 *Flag = P.getValue(2);
703 Chain = P.getValue(1);
706 // If the source register was virtual and if we know something about it,
707 // add an assert node.
708 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
709 !RegisterVT.isInteger() || RegisterVT.isVector())
712 const FunctionLoweringInfo::LiveOutInfo *LOI =
713 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
717 unsigned RegSize = RegisterVT.getSizeInBits();
718 unsigned NumSignBits = LOI->NumSignBits;
719 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
721 if (NumZeroBits == RegSize) {
722 // The current value is a zero.
723 // Explicitly express that as it would be easier for
724 // optimizations to kick in.
725 Parts[i] = DAG.getConstant(0, RegisterVT);
729 // FIXME: We capture more information than the dag can represent. For
730 // now, just use the tightest assertzext/assertsext possible.
732 EVT FromVT(MVT::Other);
733 if (NumSignBits == RegSize)
734 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
735 else if (NumZeroBits >= RegSize-1)
736 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
737 else if (NumSignBits > RegSize-8)
738 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
739 else if (NumZeroBits >= RegSize-8)
740 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
741 else if (NumSignBits > RegSize-16)
742 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
743 else if (NumZeroBits >= RegSize-16)
744 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
745 else if (NumSignBits > RegSize-32)
746 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
747 else if (NumZeroBits >= RegSize-32)
748 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
752 // Add an assertion node.
753 assert(FromVT != MVT::Other);
754 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
755 RegisterVT, P, DAG.getValueType(FromVT));
758 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
759 NumRegs, RegisterVT, ValueVT, V);
764 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
767 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
768 /// specified value into the registers specified by this object. This uses
769 /// Chain/Flag as the input and updates them for the output Chain/Flag.
770 /// If the Flag pointer is NULL, no flag is used.
771 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
772 SDValue &Chain, SDValue *Flag, const Value *V,
773 ISD::NodeType PreferredExtendType) const {
774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
775 ISD::NodeType ExtendKind = PreferredExtendType;
777 // Get the list of the values's legal parts.
778 unsigned NumRegs = Regs.size();
779 SmallVector<SDValue, 8> Parts(NumRegs);
780 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
781 EVT ValueVT = ValueVTs[Value];
782 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
783 MVT RegisterVT = RegVTs[Value];
785 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
786 ExtendKind = ISD::ZERO_EXTEND;
788 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
789 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
793 // Copy the parts into the registers.
794 SmallVector<SDValue, 8> Chains(NumRegs);
795 for (unsigned i = 0; i != NumRegs; ++i) {
798 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
800 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
801 *Flag = Part.getValue(1);
804 Chains[i] = Part.getValue(0);
807 if (NumRegs == 1 || Flag)
808 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
809 // flagged to it. That is the CopyToReg nodes and the user are considered
810 // a single scheduling unit. If we create a TokenFactor and return it as
811 // chain, then the TokenFactor is both a predecessor (operand) of the
812 // user as well as a successor (the TF operands are flagged to the user).
813 // c1, f1 = CopyToReg
814 // c2, f2 = CopyToReg
815 // c3 = TokenFactor c1, c2
818 Chain = Chains[NumRegs-1];
820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
823 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
824 /// operand list. This adds the code marker and includes the number of
825 /// values added into it.
826 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
827 unsigned MatchingIdx,
829 std::vector<SDValue> &Ops) const {
830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
832 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
834 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
835 else if (!Regs.empty() &&
836 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
837 // Put the register class of the virtual registers in the flag word. That
838 // way, later passes can recompute register class constraints for inline
839 // assembly as well as normal instructions.
840 // Don't do this for tied operands that can use the regclass information
842 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
843 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
844 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
847 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
850 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
851 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
852 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
853 MVT RegisterVT = RegVTs[Value];
854 for (unsigned i = 0; i != NumRegs; ++i) {
855 assert(Reg < Regs.size() && "Mismatch in # registers expected");
856 unsigned TheReg = Regs[Reg++];
857 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
859 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
860 // If we clobbered the stack pointer, MFI should know about it.
861 assert(DAG.getMachineFunction().getFrameInfo()->
862 hasInlineAsmWithSPAdjust());
868 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
869 const TargetLibraryInfo *li) {
873 DL = DAG.getTarget().getDataLayout();
874 Context = DAG.getContext();
875 LPadToCallSiteMap.clear();
878 /// clear - Clear out the current SelectionDAG and the associated
879 /// state and prepare this SelectionDAGBuilder object to be used
880 /// for a new block. This doesn't clear out information about
881 /// additional blocks that are needed to complete switch lowering
882 /// or PHI node updating; that information is cleared out as it is
884 void SelectionDAGBuilder::clear() {
886 UnusedArgNodeMap.clear();
887 PendingLoads.clear();
888 PendingExports.clear();
891 SDNodeOrder = LowestSDNodeOrder;
892 StatepointLowering.clear();
895 /// clearDanglingDebugInfo - Clear the dangling debug information
896 /// map. This function is separated from the clear so that debug
897 /// information that is dangling in a basic block can be properly
898 /// resolved in a different basic block. This allows the
899 /// SelectionDAG to resolve dangling debug information attached
901 void SelectionDAGBuilder::clearDanglingDebugInfo() {
902 DanglingDebugInfoMap.clear();
905 /// getRoot - Return the current virtual root of the Selection DAG,
906 /// flushing any PendingLoad items. This must be done before emitting
907 /// a store or any other node that may need to be ordered after any
908 /// prior load instructions.
910 SDValue SelectionDAGBuilder::getRoot() {
911 if (PendingLoads.empty())
912 return DAG.getRoot();
914 if (PendingLoads.size() == 1) {
915 SDValue Root = PendingLoads[0];
917 PendingLoads.clear();
921 // Otherwise, we have to make a token factor node.
922 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
924 PendingLoads.clear();
929 /// getControlRoot - Similar to getRoot, but instead of flushing all the
930 /// PendingLoad items, flush all the PendingExports items. It is necessary
931 /// to do this before emitting a terminator instruction.
933 SDValue SelectionDAGBuilder::getControlRoot() {
934 SDValue Root = DAG.getRoot();
936 if (PendingExports.empty())
939 // Turn all of the CopyToReg chains into one factored node.
940 if (Root.getOpcode() != ISD::EntryToken) {
941 unsigned i = 0, e = PendingExports.size();
942 for (; i != e; ++i) {
943 assert(PendingExports[i].getNode()->getNumOperands() > 1);
944 if (PendingExports[i].getNode()->getOperand(0) == Root)
945 break; // Don't add the root if we already indirectly depend on it.
949 PendingExports.push_back(Root);
952 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
954 PendingExports.clear();
959 void SelectionDAGBuilder::visit(const Instruction &I) {
960 // Set up outgoing PHI node register values before emitting the terminator.
961 if (isa<TerminatorInst>(&I))
962 HandlePHINodesInSuccessorBlocks(I.getParent());
968 visit(I.getOpcode(), I);
970 if (!isa<TerminatorInst>(&I) && !HasTailCall)
971 CopyToExportRegsIfNeeded(&I);
976 void SelectionDAGBuilder::visitPHI(const PHINode &) {
977 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
980 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
981 // Note: this doesn't use InstVisitor, because it has to work with
982 // ConstantExpr's in addition to instructions.
984 default: llvm_unreachable("Unknown instruction type encountered!");
985 // Build the switch statement using the Instruction.def file.
986 #define HANDLE_INST(NUM, OPCODE, CLASS) \
987 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
988 #include "llvm/IR/Instruction.def"
992 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
993 // generate the debug data structures now that we've seen its definition.
994 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
996 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
998 const DbgValueInst *DI = DDI.getDI();
999 DebugLoc dl = DDI.getdl();
1000 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1001 MDLocalVariable *Variable = DI->getVariable();
1002 MDExpression *Expr = DI->getExpression();
1003 assert(Variable->isValidLocationForIntrinsic(dl) &&
1004 "Expected inlined-at fields to agree");
1005 uint64_t Offset = DI->getOffset();
1006 // A dbg.value for an alloca is always indirect.
1007 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1009 if (Val.getNode()) {
1010 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
1012 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1013 IsIndirect, Offset, dl, DbgSDNodeOrder);
1014 DAG.AddDbgValue(SDV, Val.getNode(), false);
1017 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1018 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1022 /// getCopyFromRegs - If there was virtual register allocated for the value V
1023 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1024 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1025 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1028 if (It != FuncInfo.ValueMap.end()) {
1029 unsigned InReg = It->second;
1030 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1032 SDValue Chain = DAG.getEntryNode();
1033 res = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1034 resolveDanglingDebugInfo(V, res);
1040 /// getValue - Return an SDValue for the given Value.
1041 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1042 // If we already have an SDValue for this value, use it. It's important
1043 // to do this first, so that we don't create a CopyFromReg if we already
1044 // have a regular SDValue.
1045 SDValue &N = NodeMap[V];
1046 if (N.getNode()) return N;
1048 // If there's a virtual register allocated and initialized for this
1050 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
1051 if (copyFromReg.getNode()) {
1055 // Otherwise create a new SDValue and remember it.
1056 SDValue Val = getValueImpl(V);
1058 resolveDanglingDebugInfo(V, Val);
1062 /// getNonRegisterValue - Return an SDValue for the given Value, but
1063 /// don't look in FuncInfo.ValueMap for a virtual register.
1064 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1065 // If we already have an SDValue for this value, use it.
1066 SDValue &N = NodeMap[V];
1067 if (N.getNode()) return N;
1069 // Otherwise create a new SDValue and remember it.
1070 SDValue Val = getValueImpl(V);
1072 resolveDanglingDebugInfo(V, Val);
1076 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1077 /// Create an SDValue for the given value.
1078 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1081 if (const Constant *C = dyn_cast<Constant>(V)) {
1082 EVT VT = TLI.getValueType(V->getType(), true);
1084 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1085 return DAG.getConstant(*CI, VT);
1087 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1088 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1090 if (isa<ConstantPointerNull>(C)) {
1091 unsigned AS = V->getType()->getPointerAddressSpace();
1092 return DAG.getConstant(0, TLI.getPointerTy(AS));
1095 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1096 return DAG.getConstantFP(*CFP, VT);
1098 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1099 return DAG.getUNDEF(VT);
1101 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1102 visit(CE->getOpcode(), *CE);
1103 SDValue N1 = NodeMap[V];
1104 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1108 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1109 SmallVector<SDValue, 4> Constants;
1110 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1112 SDNode *Val = getValue(*OI).getNode();
1113 // If the operand is an empty aggregate, there are no values.
1115 // Add each leaf value from the operand to the Constants list
1116 // to form a flattened list of all the values.
1117 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1118 Constants.push_back(SDValue(Val, i));
1121 return DAG.getMergeValues(Constants, getCurSDLoc());
1124 if (const ConstantDataSequential *CDS =
1125 dyn_cast<ConstantDataSequential>(C)) {
1126 SmallVector<SDValue, 4> Ops;
1127 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1128 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1129 // Add each leaf value from the operand to the Constants list
1130 // to form a flattened list of all the values.
1131 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1132 Ops.push_back(SDValue(Val, i));
1135 if (isa<ArrayType>(CDS->getType()))
1136 return DAG.getMergeValues(Ops, getCurSDLoc());
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1141 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1142 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1143 "Unknown struct or array constant!");
1145 SmallVector<EVT, 4> ValueVTs;
1146 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1147 unsigned NumElts = ValueVTs.size();
1149 return SDValue(); // empty struct
1150 SmallVector<SDValue, 4> Constants(NumElts);
1151 for (unsigned i = 0; i != NumElts; ++i) {
1152 EVT EltVT = ValueVTs[i];
1153 if (isa<UndefValue>(C))
1154 Constants[i] = DAG.getUNDEF(EltVT);
1155 else if (EltVT.isFloatingPoint())
1156 Constants[i] = DAG.getConstantFP(0, EltVT);
1158 Constants[i] = DAG.getConstant(0, EltVT);
1161 return DAG.getMergeValues(Constants, getCurSDLoc());
1164 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1165 return DAG.getBlockAddress(BA, VT);
1167 VectorType *VecTy = cast<VectorType>(V->getType());
1168 unsigned NumElements = VecTy->getNumElements();
1170 // Now that we know the number and type of the elements, get that number of
1171 // elements into the Ops array based on what kind of constant it is.
1172 SmallVector<SDValue, 16> Ops;
1173 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1174 for (unsigned i = 0; i != NumElements; ++i)
1175 Ops.push_back(getValue(CV->getOperand(i)));
1177 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1178 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1181 if (EltVT.isFloatingPoint())
1182 Op = DAG.getConstantFP(0, EltVT);
1184 Op = DAG.getConstant(0, EltVT);
1185 Ops.assign(NumElements, Op);
1188 // Create a BUILD_VECTOR node.
1189 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1192 // If this is a static alloca, generate it as the frameindex instead of
1194 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1195 DenseMap<const AllocaInst*, int>::iterator SI =
1196 FuncInfo.StaticAllocaMap.find(AI);
1197 if (SI != FuncInfo.StaticAllocaMap.end())
1198 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1201 // If this is an instruction which fast-isel has deferred, select it now.
1202 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1203 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1204 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1205 SDValue Chain = DAG.getEntryNode();
1206 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1209 llvm_unreachable("Can't get register for value!");
1212 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1213 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1214 SDValue Chain = getControlRoot();
1215 SmallVector<ISD::OutputArg, 8> Outs;
1216 SmallVector<SDValue, 8> OutVals;
1218 if (!FuncInfo.CanLowerReturn) {
1219 unsigned DemoteReg = FuncInfo.DemoteRegister;
1220 const Function *F = I.getParent()->getParent();
1222 // Emit a store of the return value through the virtual register.
1223 // Leave Outs empty so that LowerReturn won't try to load return
1224 // registers the usual way.
1225 SmallVector<EVT, 1> PtrValueVTs;
1226 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1229 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1230 SDValue RetOp = getValue(I.getOperand(0));
1232 SmallVector<EVT, 4> ValueVTs;
1233 SmallVector<uint64_t, 4> Offsets;
1234 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1235 unsigned NumValues = ValueVTs.size();
1237 SmallVector<SDValue, 4> Chains(NumValues);
1238 for (unsigned i = 0; i != NumValues; ++i) {
1239 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1240 RetPtr.getValueType(), RetPtr,
1241 DAG.getIntPtrConstant(Offsets[i]));
1243 DAG.getStore(Chain, getCurSDLoc(),
1244 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1245 // FIXME: better loc info would be nice.
1246 Add, MachinePointerInfo(), false, false, 0);
1249 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1250 MVT::Other, Chains);
1251 } else if (I.getNumOperands() != 0) {
1252 SmallVector<EVT, 4> ValueVTs;
1253 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1254 unsigned NumValues = ValueVTs.size();
1256 SDValue RetOp = getValue(I.getOperand(0));
1258 const Function *F = I.getParent()->getParent();
1260 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1261 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1263 ExtendKind = ISD::SIGN_EXTEND;
1264 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1266 ExtendKind = ISD::ZERO_EXTEND;
1268 LLVMContext &Context = F->getContext();
1269 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1272 for (unsigned j = 0; j != NumValues; ++j) {
1273 EVT VT = ValueVTs[j];
1275 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1276 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1278 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1279 MVT PartVT = TLI.getRegisterType(Context, VT);
1280 SmallVector<SDValue, 4> Parts(NumParts);
1281 getCopyToParts(DAG, getCurSDLoc(),
1282 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1283 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1285 // 'inreg' on function refers to return value
1286 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1290 // Propagate extension type if any
1291 if (ExtendKind == ISD::SIGN_EXTEND)
1293 else if (ExtendKind == ISD::ZERO_EXTEND)
1296 for (unsigned i = 0; i < NumParts; ++i) {
1297 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1298 VT, /*isfixed=*/true, 0, 0));
1299 OutVals.push_back(Parts[i]);
1305 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1306 CallingConv::ID CallConv =
1307 DAG.getMachineFunction().getFunction()->getCallingConv();
1308 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1309 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1311 // Verify that the target's LowerReturn behaved as expected.
1312 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1313 "LowerReturn didn't return a valid chain!");
1315 // Update the DAG with the new chain value resulting from return lowering.
1319 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1320 /// created for it, emit nodes to copy the value into the virtual
1322 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1324 if (V->getType()->isEmptyTy())
1327 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1328 if (VMI != FuncInfo.ValueMap.end()) {
1329 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1330 CopyValueToVirtualRegister(V, VMI->second);
1334 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1335 /// the current basic block, add it to ValueMap now so that we'll get a
1337 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1338 // No need to export constants.
1339 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1341 // Already exported?
1342 if (FuncInfo.isExportedInst(V)) return;
1344 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1345 CopyValueToVirtualRegister(V, Reg);
1348 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1349 const BasicBlock *FromBB) {
1350 // The operands of the setcc have to be in this block. We don't know
1351 // how to export them from some other block.
1352 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1353 // Can export from current BB.
1354 if (VI->getParent() == FromBB)
1357 // Is already exported, noop.
1358 return FuncInfo.isExportedInst(V);
1361 // If this is an argument, we can export it if the BB is the entry block or
1362 // if it is already exported.
1363 if (isa<Argument>(V)) {
1364 if (FromBB == &FromBB->getParent()->getEntryBlock())
1367 // Otherwise, can only export this if it is already exported.
1368 return FuncInfo.isExportedInst(V);
1371 // Otherwise, constants can always be exported.
1375 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1376 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1377 const MachineBasicBlock *Dst) const {
1378 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1381 const BasicBlock *SrcBB = Src->getBasicBlock();
1382 const BasicBlock *DstBB = Dst->getBasicBlock();
1383 return BPI->getEdgeWeight(SrcBB, DstBB);
1386 void SelectionDAGBuilder::
1387 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1388 uint32_t Weight /* = 0 */) {
1390 Weight = getEdgeWeight(Src, Dst);
1391 Src->addSuccessor(Dst, Weight);
1395 static bool InBlock(const Value *V, const BasicBlock *BB) {
1396 if (const Instruction *I = dyn_cast<Instruction>(V))
1397 return I->getParent() == BB;
1401 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1402 /// This function emits a branch and is used at the leaves of an OR or an
1403 /// AND operator tree.
1406 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1407 MachineBasicBlock *TBB,
1408 MachineBasicBlock *FBB,
1409 MachineBasicBlock *CurBB,
1410 MachineBasicBlock *SwitchBB,
1413 const BasicBlock *BB = CurBB->getBasicBlock();
1415 // If the leaf of the tree is a comparison, merge the condition into
1417 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1418 // The operands of the cmp have to be in this block. We don't know
1419 // how to export them from some other block. If this is the first block
1420 // of the sequence, no exporting is needed.
1421 if (CurBB == SwitchBB ||
1422 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1423 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1424 ISD::CondCode Condition;
1425 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1426 Condition = getICmpCondCode(IC->getPredicate());
1427 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1428 Condition = getFCmpCondCode(FC->getPredicate());
1429 if (TM.Options.NoNaNsFPMath)
1430 Condition = getFCmpCodeWithoutNaN(Condition);
1432 (void)Condition; // silence warning.
1433 llvm_unreachable("Unknown compare instruction");
1436 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1437 TBB, FBB, CurBB, TWeight, FWeight);
1438 SwitchCases.push_back(CB);
1443 // Create a CaseBlock record representing this branch.
1444 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1445 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1446 SwitchCases.push_back(CB);
1449 /// Scale down both weights to fit into uint32_t.
1450 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1451 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1452 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1453 NewTrue = NewTrue / Scale;
1454 NewFalse = NewFalse / Scale;
1457 /// FindMergedConditions - If Cond is an expression like
1458 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1459 MachineBasicBlock *TBB,
1460 MachineBasicBlock *FBB,
1461 MachineBasicBlock *CurBB,
1462 MachineBasicBlock *SwitchBB,
1463 unsigned Opc, uint32_t TWeight,
1465 // If this node is not part of the or/and tree, emit it as a branch.
1466 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1467 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1468 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1469 BOp->getParent() != CurBB->getBasicBlock() ||
1470 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1471 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1472 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1477 // Create TmpBB after CurBB.
1478 MachineFunction::iterator BBI = CurBB;
1479 MachineFunction &MF = DAG.getMachineFunction();
1480 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1481 CurBB->getParent()->insert(++BBI, TmpBB);
1483 if (Opc == Instruction::Or) {
1484 // Codegen X | Y as:
1493 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1494 // The requirement is that
1495 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1496 // = TrueProb for orignal BB.
1497 // Assuming the orignal weights are A and B, one choice is to set BB1's
1498 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1500 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1501 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1502 // TmpBB, but the math is more complicated.
1504 uint64_t NewTrueWeight = TWeight;
1505 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1506 ScaleWeights(NewTrueWeight, NewFalseWeight);
1507 // Emit the LHS condition.
1508 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1509 NewTrueWeight, NewFalseWeight);
1511 NewTrueWeight = TWeight;
1512 NewFalseWeight = 2 * (uint64_t)FWeight;
1513 ScaleWeights(NewTrueWeight, NewFalseWeight);
1514 // Emit the RHS condition into TmpBB.
1515 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1516 NewTrueWeight, NewFalseWeight);
1518 assert(Opc == Instruction::And && "Unknown merge op!");
1519 // Codegen X & Y as:
1527 // This requires creation of TmpBB after CurBB.
1529 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1530 // The requirement is that
1531 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1532 // = FalseProb for orignal BB.
1533 // Assuming the orignal weights are A and B, one choice is to set BB1's
1534 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1536 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1538 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1539 uint64_t NewFalseWeight = FWeight;
1540 ScaleWeights(NewTrueWeight, NewFalseWeight);
1541 // Emit the LHS condition.
1542 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1543 NewTrueWeight, NewFalseWeight);
1545 NewTrueWeight = 2 * (uint64_t)TWeight;
1546 NewFalseWeight = FWeight;
1547 ScaleWeights(NewTrueWeight, NewFalseWeight);
1548 // Emit the RHS condition into TmpBB.
1549 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1550 NewTrueWeight, NewFalseWeight);
1554 /// If the set of cases should be emitted as a series of branches, return true.
1555 /// If we should emit this as a bunch of and/or'd together conditions, return
1558 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1559 if (Cases.size() != 2) return true;
1561 // If this is two comparisons of the same values or'd or and'd together, they
1562 // will get folded into a single comparison, so don't emit two blocks.
1563 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1564 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1565 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1566 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1570 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1571 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1572 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1573 Cases[0].CC == Cases[1].CC &&
1574 isa<Constant>(Cases[0].CmpRHS) &&
1575 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1576 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1578 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1585 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1586 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1588 // Update machine-CFG edges.
1589 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1591 if (I.isUnconditional()) {
1592 // Update machine-CFG edges.
1593 BrMBB->addSuccessor(Succ0MBB);
1595 // If this is not a fall-through branch or optimizations are switched off,
1597 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1598 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1599 MVT::Other, getControlRoot(),
1600 DAG.getBasicBlock(Succ0MBB)));
1605 // If this condition is one of the special cases we handle, do special stuff
1607 const Value *CondVal = I.getCondition();
1608 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1610 // If this is a series of conditions that are or'd or and'd together, emit
1611 // this as a sequence of branches instead of setcc's with and/or operations.
1612 // As long as jumps are not expensive, this should improve performance.
1613 // For example, instead of something like:
1626 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1627 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1628 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1629 BOp->getOpcode() == Instruction::Or)) {
1630 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1631 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1632 getEdgeWeight(BrMBB, Succ1MBB));
1633 // If the compares in later blocks need to use values not currently
1634 // exported from this block, export them now. This block should always
1635 // be the first entry.
1636 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1638 // Allow some cases to be rejected.
1639 if (ShouldEmitAsBranches(SwitchCases)) {
1640 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1641 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1642 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1645 // Emit the branch for this block.
1646 visitSwitchCase(SwitchCases[0], BrMBB);
1647 SwitchCases.erase(SwitchCases.begin());
1651 // Okay, we decided not to do this, remove any inserted MBB's and clear
1653 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1654 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1656 SwitchCases.clear();
1660 // Create a CaseBlock record representing this branch.
1661 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1662 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1664 // Use visitSwitchCase to actually insert the fast branch sequence for this
1666 visitSwitchCase(CB, BrMBB);
1669 /// visitSwitchCase - Emits the necessary code to represent a single node in
1670 /// the binary search tree resulting from lowering a switch instruction.
1671 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1672 MachineBasicBlock *SwitchBB) {
1674 SDValue CondLHS = getValue(CB.CmpLHS);
1675 SDLoc dl = getCurSDLoc();
1677 // Build the setcc now.
1679 // Fold "(X == true)" to X and "(X == false)" to !X to
1680 // handle common cases produced by branch lowering.
1681 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1682 CB.CC == ISD::SETEQ)
1684 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1685 CB.CC == ISD::SETEQ) {
1686 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1687 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1689 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1691 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1693 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1694 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1696 SDValue CmpOp = getValue(CB.CmpMHS);
1697 EVT VT = CmpOp.getValueType();
1699 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1700 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1703 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1704 VT, CmpOp, DAG.getConstant(Low, VT));
1705 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1706 DAG.getConstant(High-Low, VT), ISD::SETULE);
1710 // Update successor info
1711 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1712 // TrueBB and FalseBB are always different unless the incoming IR is
1713 // degenerate. This only happens when running llc on weird IR.
1714 if (CB.TrueBB != CB.FalseBB)
1715 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1717 // If the lhs block is the next block, invert the condition so that we can
1718 // fall through to the lhs instead of the rhs block.
1719 if (CB.TrueBB == NextBlock(SwitchBB)) {
1720 std::swap(CB.TrueBB, CB.FalseBB);
1721 SDValue True = DAG.getConstant(1, Cond.getValueType());
1722 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1725 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1726 MVT::Other, getControlRoot(), Cond,
1727 DAG.getBasicBlock(CB.TrueBB));
1729 // Insert the false branch. Do this even if it's a fall through branch,
1730 // this makes it easier to do DAG optimizations which require inverting
1731 // the branch condition.
1732 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1733 DAG.getBasicBlock(CB.FalseBB));
1735 DAG.setRoot(BrCond);
1738 /// visitJumpTable - Emit JumpTable node in the current MBB
1739 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1740 // Emit the code for the jump table
1741 assert(JT.Reg != -1U && "Should lower JT Header first!");
1742 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1743 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1745 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1746 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1747 MVT::Other, Index.getValue(1),
1749 DAG.setRoot(BrJumpTable);
1752 /// visitJumpTableHeader - This function emits necessary code to produce index
1753 /// in the JumpTable from switch case.
1754 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1755 JumpTableHeader &JTH,
1756 MachineBasicBlock *SwitchBB) {
1757 // Subtract the lowest switch case value from the value being switched on and
1758 // conditional branch to default mbb if the result is greater than the
1759 // difference between smallest and largest cases.
1760 SDValue SwitchOp = getValue(JTH.SValue);
1761 EVT VT = SwitchOp.getValueType();
1762 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1763 DAG.getConstant(JTH.First, VT));
1765 // The SDNode we just created, which holds the value being switched on minus
1766 // the smallest case value, needs to be copied to a virtual register so it
1767 // can be used as an index into the jump table in a subsequent basic block.
1768 // This value may be smaller or larger than the target's pointer type, and
1769 // therefore require extension or truncating.
1770 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1771 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1773 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1774 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1775 JumpTableReg, SwitchOp);
1776 JT.Reg = JumpTableReg;
1778 // Emit the range check for the jump table, and branch to the default block
1779 // for the switch statement if the value being switched on exceeds the largest
1780 // case in the switch.
1782 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1783 Sub.getValueType()),
1784 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1786 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1787 MVT::Other, CopyTo, CMP,
1788 DAG.getBasicBlock(JT.Default));
1790 // Avoid emitting unnecessary branches to the next block.
1791 if (JT.MBB != NextBlock(SwitchBB))
1792 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1793 DAG.getBasicBlock(JT.MBB));
1795 DAG.setRoot(BrCond);
1798 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1799 /// tail spliced into a stack protector check success bb.
1801 /// For a high level explanation of how this fits into the stack protector
1802 /// generation see the comment on the declaration of class
1803 /// StackProtectorDescriptor.
1804 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1805 MachineBasicBlock *ParentBB) {
1807 // First create the loads to the guard/stack slot for the comparison.
1808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1809 EVT PtrTy = TLI.getPointerTy();
1811 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1812 int FI = MFI->getStackProtectorIndex();
1814 const Value *IRGuard = SPD.getGuard();
1815 SDValue GuardPtr = getValue(IRGuard);
1816 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1819 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1823 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1824 // guard value from the virtual register holding the value. Otherwise, emit a
1825 // volatile load to retrieve the stack guard value.
1826 unsigned GuardReg = SPD.getGuardReg();
1828 if (GuardReg && TLI.useLoadStackGuardNode())
1829 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1832 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1833 GuardPtr, MachinePointerInfo(IRGuard, 0),
1834 true, false, false, Align);
1836 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1838 MachinePointerInfo::getFixedStack(FI),
1839 true, false, false, Align);
1841 // Perform the comparison via a subtract/getsetcc.
1842 EVT VT = Guard.getValueType();
1843 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1846 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1847 Sub.getValueType()),
1848 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1850 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1851 // branch to failure MBB.
1852 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1853 MVT::Other, StackSlot.getOperand(0),
1854 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1855 // Otherwise branch to success MBB.
1856 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1858 DAG.getBasicBlock(SPD.getSuccessMBB()));
1863 /// Codegen the failure basic block for a stack protector check.
1865 /// A failure stack protector machine basic block consists simply of a call to
1866 /// __stack_chk_fail().
1868 /// For a high level explanation of how this fits into the stack protector
1869 /// generation see the comment on the declaration of class
1870 /// StackProtectorDescriptor.
1872 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1873 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1875 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1876 nullptr, 0, false, getCurSDLoc(), false, false).second;
1880 /// visitBitTestHeader - This function emits necessary code to produce value
1881 /// suitable for "bit tests"
1882 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1883 MachineBasicBlock *SwitchBB) {
1884 // Subtract the minimum value
1885 SDValue SwitchOp = getValue(B.SValue);
1886 EVT VT = SwitchOp.getValueType();
1887 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1888 DAG.getConstant(B.First, VT));
1891 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1893 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1894 Sub.getValueType()),
1895 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1897 // Determine the type of the test operands.
1898 bool UsePtrType = false;
1899 if (!TLI.isTypeLegal(VT))
1902 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1903 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1904 // Switch table case range are encoded into series of masks.
1905 // Just use pointer type, it's guaranteed to fit.
1911 VT = TLI.getPointerTy();
1912 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1915 B.RegVT = VT.getSimpleVT();
1916 B.Reg = FuncInfo.CreateReg(B.RegVT);
1917 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1920 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1922 addSuccessorWithWeight(SwitchBB, B.Default);
1923 addSuccessorWithWeight(SwitchBB, MBB);
1925 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1926 MVT::Other, CopyTo, RangeCmp,
1927 DAG.getBasicBlock(B.Default));
1929 // Avoid emitting unnecessary branches to the next block.
1930 if (MBB != NextBlock(SwitchBB))
1931 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrRange,
1932 DAG.getBasicBlock(MBB));
1934 DAG.setRoot(BrRange);
1937 /// visitBitTestCase - this function produces one "bit test"
1938 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1939 MachineBasicBlock* NextMBB,
1940 uint32_t BranchWeightToNext,
1943 MachineBasicBlock *SwitchBB) {
1945 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1948 unsigned PopCount = countPopulation(B.Mask);
1949 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1950 if (PopCount == 1) {
1951 // Testing for a single bit; just compare the shift count with what it
1952 // would need to be to shift a 1 bit in that position.
1954 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1955 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1956 } else if (PopCount == BB.Range) {
1957 // There is only one zero bit in the range, test for it directly.
1959 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1960 DAG.getConstant(countTrailingOnes(B.Mask), VT), ISD::SETNE);
1962 // Make desired shift
1963 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1964 DAG.getConstant(1, VT), ShiftOp);
1966 // Emit bit tests and jumps
1967 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1968 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1969 Cmp = DAG.getSetCC(getCurSDLoc(),
1970 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1971 DAG.getConstant(0, VT), ISD::SETNE);
1974 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1975 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1976 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1977 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1979 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1980 MVT::Other, getControlRoot(),
1981 Cmp, DAG.getBasicBlock(B.TargetBB));
1983 // Avoid emitting unnecessary branches to the next block.
1984 if (NextMBB != NextBlock(SwitchBB))
1985 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1986 DAG.getBasicBlock(NextMBB));
1991 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1992 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1994 // Retrieve successors.
1995 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1996 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1998 const Value *Callee(I.getCalledValue());
1999 const Function *Fn = dyn_cast<Function>(Callee);
2000 if (isa<InlineAsm>(Callee))
2002 else if (Fn && Fn->isIntrinsic()) {
2003 switch (Fn->getIntrinsicID()) {
2005 llvm_unreachable("Cannot invoke this intrinsic");
2006 case Intrinsic::donothing:
2007 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2009 case Intrinsic::experimental_patchpoint_void:
2010 case Intrinsic::experimental_patchpoint_i64:
2011 visitPatchpoint(&I, LandingPad);
2013 case Intrinsic::experimental_gc_statepoint:
2014 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2018 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2020 // If the value of the invoke is used outside of its defining block, make it
2021 // available as a virtual register.
2022 // We already took care of the exported value for the statepoint instruction
2023 // during call to the LowerStatepoint.
2024 if (!isStatepoint(I)) {
2025 CopyToExportRegsIfNeeded(&I);
2028 // Update successor info
2029 addSuccessorWithWeight(InvokeMBB, Return);
2030 addSuccessorWithWeight(InvokeMBB, LandingPad);
2032 // Drop into normal successor.
2033 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2034 MVT::Other, getControlRoot(),
2035 DAG.getBasicBlock(Return)));
2038 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2039 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2042 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2043 assert(FuncInfo.MBB->isLandingPad() &&
2044 "Call to landingpad not in landing pad!");
2046 MachineBasicBlock *MBB = FuncInfo.MBB;
2047 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2048 AddLandingPadInfo(LP, MMI, MBB);
2050 // If there aren't registers to copy the values into (e.g., during SjLj
2051 // exceptions), then don't bother to create these DAG nodes.
2052 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2053 if (TLI.getExceptionPointerRegister() == 0 &&
2054 TLI.getExceptionSelectorRegister() == 0)
2057 SmallVector<EVT, 2> ValueVTs;
2058 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2059 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2061 // Get the two live-in registers as SDValues. The physregs have already been
2062 // copied into virtual registers.
2064 if (FuncInfo.ExceptionPointerVirtReg) {
2065 Ops[0] = DAG.getZExtOrTrunc(
2066 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2067 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2068 getCurSDLoc(), ValueVTs[0]);
2070 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2072 Ops[1] = DAG.getZExtOrTrunc(
2073 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2074 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2075 getCurSDLoc(), ValueVTs[1]);
2078 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2079 DAG.getVTList(ValueVTs), Ops);
2084 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2085 MachineBasicBlock *LPadBB) {
2086 SDValue Chain = getControlRoot();
2088 // Get the typeid that we will dispatch on later.
2089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2090 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2091 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2092 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2093 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2094 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2096 // Branch to the main landing pad block.
2097 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2098 ClauseMBB->addSuccessor(LPadBB);
2099 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2100 DAG.getBasicBlock(LPadBB)));
2104 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2106 for (const CaseCluster &CC : Clusters)
2107 assert(CC.Low == CC.High && "Input clusters must be single-case");
2110 std::sort(Clusters.begin(), Clusters.end(),
2111 [](const CaseCluster &a, const CaseCluster &b) {
2112 return a.Low->getValue().slt(b.Low->getValue());
2115 // Merge adjacent clusters with the same destination.
2116 const unsigned N = Clusters.size();
2117 unsigned DstIndex = 0;
2118 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2119 CaseCluster &CC = Clusters[SrcIndex];
2120 const ConstantInt *CaseVal = CC.Low;
2121 MachineBasicBlock *Succ = CC.MBB;
2123 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2124 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2125 // If this case has the same successor and is a neighbour, merge it into
2126 // the previous cluster.
2127 Clusters[DstIndex - 1].High = CaseVal;
2128 Clusters[DstIndex - 1].Weight += CC.Weight;
2130 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2131 sizeof(Clusters[SrcIndex]));
2134 Clusters.resize(DstIndex);
2137 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2138 MachineBasicBlock *Last) {
2140 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2141 if (JTCases[i].first.HeaderBB == First)
2142 JTCases[i].first.HeaderBB = Last;
2144 // Update BitTestCases.
2145 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2146 if (BitTestCases[i].Parent == First)
2147 BitTestCases[i].Parent = Last;
2150 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2151 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2153 // Update machine-CFG edges with unique successors.
2154 SmallSet<BasicBlock*, 32> Done;
2155 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2156 BasicBlock *BB = I.getSuccessor(i);
2157 bool Inserted = Done.insert(BB).second;
2161 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2162 addSuccessorWithWeight(IndirectBrMBB, Succ);
2165 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2166 MVT::Other, getControlRoot(),
2167 getValue(I.getAddress())));
2170 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2171 if (DAG.getTarget().Options.TrapUnreachable)
2172 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2175 void SelectionDAGBuilder::visitFSub(const User &I) {
2176 // -0.0 - X --> fneg
2177 Type *Ty = I.getType();
2178 if (isa<Constant>(I.getOperand(0)) &&
2179 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2180 SDValue Op2 = getValue(I.getOperand(1));
2181 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2182 Op2.getValueType(), Op2));
2186 visitBinary(I, ISD::FSUB);
2189 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2190 SDValue Op1 = getValue(I.getOperand(0));
2191 SDValue Op2 = getValue(I.getOperand(1));
2196 if (const OverflowingBinaryOperator *OFBinOp =
2197 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2198 nuw = OFBinOp->hasNoUnsignedWrap();
2199 nsw = OFBinOp->hasNoSignedWrap();
2201 if (const PossiblyExactOperator *ExactOp =
2202 dyn_cast<const PossiblyExactOperator>(&I))
2203 exact = ExactOp->isExact();
2205 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2206 Op1, Op2, nuw, nsw, exact);
2207 setValue(&I, BinNodeValue);
2210 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2211 SDValue Op1 = getValue(I.getOperand(0));
2212 SDValue Op2 = getValue(I.getOperand(1));
2215 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2217 // Coerce the shift amount to the right type if we can.
2218 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2219 unsigned ShiftSize = ShiftTy.getSizeInBits();
2220 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2221 SDLoc DL = getCurSDLoc();
2223 // If the operand is smaller than the shift count type, promote it.
2224 if (ShiftSize > Op2Size)
2225 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2227 // If the operand is larger than the shift count type but the shift
2228 // count type has enough bits to represent any shift value, truncate
2229 // it now. This is a common case and it exposes the truncate to
2230 // optimization early.
2231 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2232 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2233 // Otherwise we'll need to temporarily settle for some other convenient
2234 // type. Type legalization will make adjustments once the shiftee is split.
2236 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2243 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2245 if (const OverflowingBinaryOperator *OFBinOp =
2246 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2247 nuw = OFBinOp->hasNoUnsignedWrap();
2248 nsw = OFBinOp->hasNoSignedWrap();
2250 if (const PossiblyExactOperator *ExactOp =
2251 dyn_cast<const PossiblyExactOperator>(&I))
2252 exact = ExactOp->isExact();
2255 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2260 void SelectionDAGBuilder::visitSDiv(const User &I) {
2261 SDValue Op1 = getValue(I.getOperand(0));
2262 SDValue Op2 = getValue(I.getOperand(1));
2264 // Turn exact SDivs into multiplications.
2265 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2267 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2268 !isa<ConstantSDNode>(Op1) &&
2269 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2270 setValue(&I, DAG.getTargetLoweringInfo()
2271 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2273 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2277 void SelectionDAGBuilder::visitICmp(const User &I) {
2278 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2279 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2280 predicate = IC->getPredicate();
2281 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2282 predicate = ICmpInst::Predicate(IC->getPredicate());
2283 SDValue Op1 = getValue(I.getOperand(0));
2284 SDValue Op2 = getValue(I.getOperand(1));
2285 ISD::CondCode Opcode = getICmpCondCode(predicate);
2287 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2288 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2291 void SelectionDAGBuilder::visitFCmp(const User &I) {
2292 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2293 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2294 predicate = FC->getPredicate();
2295 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2296 predicate = FCmpInst::Predicate(FC->getPredicate());
2297 SDValue Op1 = getValue(I.getOperand(0));
2298 SDValue Op2 = getValue(I.getOperand(1));
2299 ISD::CondCode Condition = getFCmpCondCode(predicate);
2300 if (TM.Options.NoNaNsFPMath)
2301 Condition = getFCmpCodeWithoutNaN(Condition);
2302 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2303 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2306 void SelectionDAGBuilder::visitSelect(const User &I) {
2307 SmallVector<EVT, 4> ValueVTs;
2308 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2309 unsigned NumValues = ValueVTs.size();
2310 if (NumValues == 0) return;
2312 SmallVector<SDValue, 4> Values(NumValues);
2313 SDValue Cond = getValue(I.getOperand(0));
2314 SDValue TrueVal = getValue(I.getOperand(1));
2315 SDValue FalseVal = getValue(I.getOperand(2));
2316 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2317 ISD::VSELECT : ISD::SELECT;
2319 for (unsigned i = 0; i != NumValues; ++i)
2320 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2321 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2323 SDValue(TrueVal.getNode(),
2324 TrueVal.getResNo() + i),
2325 SDValue(FalseVal.getNode(),
2326 FalseVal.getResNo() + i));
2328 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2329 DAG.getVTList(ValueVTs), Values));
2332 void SelectionDAGBuilder::visitTrunc(const User &I) {
2333 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2334 SDValue N = getValue(I.getOperand(0));
2335 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2336 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2339 void SelectionDAGBuilder::visitZExt(const User &I) {
2340 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2341 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2342 SDValue N = getValue(I.getOperand(0));
2343 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2344 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2347 void SelectionDAGBuilder::visitSExt(const User &I) {
2348 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2349 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2350 SDValue N = getValue(I.getOperand(0));
2351 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2352 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2355 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2356 // FPTrunc is never a no-op cast, no need to check
2357 SDValue N = getValue(I.getOperand(0));
2358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2359 EVT DestVT = TLI.getValueType(I.getType());
2360 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
2361 DAG.getTargetConstant(0, TLI.getPointerTy())));
2364 void SelectionDAGBuilder::visitFPExt(const User &I) {
2365 // FPExt is never a no-op cast, no need to check
2366 SDValue N = getValue(I.getOperand(0));
2367 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2368 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2371 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2372 // FPToUI is never a no-op cast, no need to check
2373 SDValue N = getValue(I.getOperand(0));
2374 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2375 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2378 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2379 // FPToSI is never a no-op cast, no need to check
2380 SDValue N = getValue(I.getOperand(0));
2381 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2382 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2385 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2386 // UIToFP is never a no-op cast, no need to check
2387 SDValue N = getValue(I.getOperand(0));
2388 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2389 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2392 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2393 // SIToFP is never a no-op cast, no need to check
2394 SDValue N = getValue(I.getOperand(0));
2395 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2396 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2399 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2400 // What to do depends on the size of the integer and the size of the pointer.
2401 // We can either truncate, zero extend, or no-op, accordingly.
2402 SDValue N = getValue(I.getOperand(0));
2403 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2404 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2407 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2408 // What to do depends on the size of the integer and the size of the pointer.
2409 // We can either truncate, zero extend, or no-op, accordingly.
2410 SDValue N = getValue(I.getOperand(0));
2411 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2412 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2415 void SelectionDAGBuilder::visitBitCast(const User &I) {
2416 SDValue N = getValue(I.getOperand(0));
2417 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2419 // BitCast assures us that source and destination are the same size so this is
2420 // either a BITCAST or a no-op.
2421 if (DestVT != N.getValueType())
2422 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2423 DestVT, N)); // convert types.
2424 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2425 // might fold any kind of constant expression to an integer constant and that
2426 // is not what we are looking for. Only regcognize a bitcast of a genuine
2427 // constant integer as an opaque constant.
2428 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2429 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
2432 setValue(&I, N); // noop cast.
2435 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2437 const Value *SV = I.getOperand(0);
2438 SDValue N = getValue(SV);
2439 EVT DestVT = TLI.getValueType(I.getType());
2441 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2442 unsigned DestAS = I.getType()->getPointerAddressSpace();
2444 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2445 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2450 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2452 SDValue InVec = getValue(I.getOperand(0));
2453 SDValue InVal = getValue(I.getOperand(1));
2454 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2455 getCurSDLoc(), TLI.getVectorIdxTy());
2456 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2457 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
2460 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2461 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2462 SDValue InVec = getValue(I.getOperand(0));
2463 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2464 getCurSDLoc(), TLI.getVectorIdxTy());
2465 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2466 TLI.getValueType(I.getType()), InVec, InIdx));
2469 // Utility for visitShuffleVector - Return true if every element in Mask,
2470 // beginning from position Pos and ending in Pos+Size, falls within the
2471 // specified sequential range [L, L+Pos). or is undef.
2472 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2473 unsigned Pos, unsigned Size, int Low) {
2474 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2475 if (Mask[i] >= 0 && Mask[i] != Low)
2480 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2481 SDValue Src1 = getValue(I.getOperand(0));
2482 SDValue Src2 = getValue(I.getOperand(1));
2484 SmallVector<int, 8> Mask;
2485 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2486 unsigned MaskNumElts = Mask.size();
2488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2489 EVT VT = TLI.getValueType(I.getType());
2490 EVT SrcVT = Src1.getValueType();
2491 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2493 if (SrcNumElts == MaskNumElts) {
2494 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2499 // Normalize the shuffle vector since mask and vector length don't match.
2500 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2501 // Mask is longer than the source vectors and is a multiple of the source
2502 // vectors. We can use concatenate vector to make the mask and vectors
2504 if (SrcNumElts*2 == MaskNumElts) {
2505 // First check for Src1 in low and Src2 in high
2506 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2507 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2508 // The shuffle is concatenating two vectors together.
2509 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2513 // Then check for Src2 in low and Src1 in high
2514 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2515 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2516 // The shuffle is concatenating two vectors together.
2517 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2523 // Pad both vectors with undefs to make them the same length as the mask.
2524 unsigned NumConcat = MaskNumElts / SrcNumElts;
2525 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2526 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2527 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2529 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2530 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2534 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2535 getCurSDLoc(), VT, MOps1);
2536 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2537 getCurSDLoc(), VT, MOps2);
2539 // Readjust mask for new input vector length.
2540 SmallVector<int, 8> MappedOps;
2541 for (unsigned i = 0; i != MaskNumElts; ++i) {
2543 if (Idx >= (int)SrcNumElts)
2544 Idx -= SrcNumElts - MaskNumElts;
2545 MappedOps.push_back(Idx);
2548 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2553 if (SrcNumElts > MaskNumElts) {
2554 // Analyze the access pattern of the vector to see if we can extract
2555 // two subvectors and do the shuffle. The analysis is done by calculating
2556 // the range of elements the mask access on both vectors.
2557 int MinRange[2] = { static_cast<int>(SrcNumElts),
2558 static_cast<int>(SrcNumElts)};
2559 int MaxRange[2] = {-1, -1};
2561 for (unsigned i = 0; i != MaskNumElts; ++i) {
2567 if (Idx >= (int)SrcNumElts) {
2571 if (Idx > MaxRange[Input])
2572 MaxRange[Input] = Idx;
2573 if (Idx < MinRange[Input])
2574 MinRange[Input] = Idx;
2577 // Check if the access is smaller than the vector size and can we find
2578 // a reasonable extract index.
2579 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2581 int StartIdx[2]; // StartIdx to extract from
2582 for (unsigned Input = 0; Input < 2; ++Input) {
2583 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2584 RangeUse[Input] = 0; // Unused
2585 StartIdx[Input] = 0;
2589 // Find a good start index that is a multiple of the mask length. Then
2590 // see if the rest of the elements are in range.
2591 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2592 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2593 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2594 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2597 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2598 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2601 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2602 // Extract appropriate subvector and generate a vector shuffle
2603 for (unsigned Input = 0; Input < 2; ++Input) {
2604 SDValue &Src = Input == 0 ? Src1 : Src2;
2605 if (RangeUse[Input] == 0)
2606 Src = DAG.getUNDEF(VT);
2609 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
2610 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
2613 // Calculate new mask.
2614 SmallVector<int, 8> MappedOps;
2615 for (unsigned i = 0; i != MaskNumElts; ++i) {
2618 if (Idx < (int)SrcNumElts)
2621 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2623 MappedOps.push_back(Idx);
2626 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2632 // We can't use either concat vectors or extract subvectors so fall back to
2633 // replacing the shuffle with extract and build vector.
2634 // to insert and build vector.
2635 EVT EltVT = VT.getVectorElementType();
2636 EVT IdxVT = TLI.getVectorIdxTy();
2637 SmallVector<SDValue,8> Ops;
2638 for (unsigned i = 0; i != MaskNumElts; ++i) {
2643 Res = DAG.getUNDEF(EltVT);
2645 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2646 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2648 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2649 EltVT, Src, DAG.getConstant(Idx, IdxVT));
2655 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
2658 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2659 const Value *Op0 = I.getOperand(0);
2660 const Value *Op1 = I.getOperand(1);
2661 Type *AggTy = I.getType();
2662 Type *ValTy = Op1->getType();
2663 bool IntoUndef = isa<UndefValue>(Op0);
2664 bool FromUndef = isa<UndefValue>(Op1);
2666 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2668 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2669 SmallVector<EVT, 4> AggValueVTs;
2670 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2671 SmallVector<EVT, 4> ValValueVTs;
2672 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2674 unsigned NumAggValues = AggValueVTs.size();
2675 unsigned NumValValues = ValValueVTs.size();
2676 SmallVector<SDValue, 4> Values(NumAggValues);
2678 // Ignore an insertvalue that produces an empty object
2679 if (!NumAggValues) {
2680 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2684 SDValue Agg = getValue(Op0);
2686 // Copy the beginning value(s) from the original aggregate.
2687 for (; i != LinearIndex; ++i)
2688 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2689 SDValue(Agg.getNode(), Agg.getResNo() + i);
2690 // Copy values from the inserted value(s).
2692 SDValue Val = getValue(Op1);
2693 for (; i != LinearIndex + NumValValues; ++i)
2694 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2695 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2697 // Copy remaining value(s) from the original aggregate.
2698 for (; i != NumAggValues; ++i)
2699 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2700 SDValue(Agg.getNode(), Agg.getResNo() + i);
2702 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2703 DAG.getVTList(AggValueVTs), Values));
2706 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2707 const Value *Op0 = I.getOperand(0);
2708 Type *AggTy = Op0->getType();
2709 Type *ValTy = I.getType();
2710 bool OutOfUndef = isa<UndefValue>(Op0);
2712 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2714 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2715 SmallVector<EVT, 4> ValValueVTs;
2716 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2718 unsigned NumValValues = ValValueVTs.size();
2720 // Ignore a extractvalue that produces an empty object
2721 if (!NumValValues) {
2722 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2726 SmallVector<SDValue, 4> Values(NumValValues);
2728 SDValue Agg = getValue(Op0);
2729 // Copy out the selected value(s).
2730 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2731 Values[i - LinearIndex] =
2733 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2734 SDValue(Agg.getNode(), Agg.getResNo() + i);
2736 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2737 DAG.getVTList(ValValueVTs), Values));
2740 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2741 Value *Op0 = I.getOperand(0);
2742 // Note that the pointer operand may be a vector of pointers. Take the scalar
2743 // element which holds a pointer.
2744 Type *Ty = Op0->getType()->getScalarType();
2745 unsigned AS = Ty->getPointerAddressSpace();
2746 SDValue N = getValue(Op0);
2748 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2750 const Value *Idx = *OI;
2751 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2752 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2755 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2756 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
2757 DAG.getConstant(Offset, N.getValueType()));
2760 Ty = StTy->getElementType(Field);
2762 Ty = cast<SequentialType>(Ty)->getElementType();
2763 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
2764 unsigned PtrSize = PtrTy.getSizeInBits();
2765 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2767 // If this is a constant subscript, handle it quickly.
2768 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
2771 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2772 SDValue OffsVal = DAG.getConstant(Offs, PtrTy);
2773 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, OffsVal);
2777 // N = N + Idx * ElementSize;
2778 SDValue IdxN = getValue(Idx);
2780 // If the index is smaller or larger than intptr_t, truncate or extend
2782 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
2784 // If this is a multiply by a power of two, turn it into a shl
2785 // immediately. This is a very common case.
2786 if (ElementSize != 1) {
2787 if (ElementSize.isPowerOf2()) {
2788 unsigned Amt = ElementSize.logBase2();
2789 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
2790 N.getValueType(), IdxN,
2791 DAG.getConstant(Amt, IdxN.getValueType()));
2793 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
2794 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
2795 N.getValueType(), IdxN, Scale);
2799 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
2800 N.getValueType(), N, IdxN);
2807 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2808 // If this is a fixed sized alloca in the entry block of the function,
2809 // allocate it statically on the stack.
2810 if (FuncInfo.StaticAllocaMap.count(&I))
2811 return; // getValue will auto-populate this.
2813 Type *Ty = I.getAllocatedType();
2814 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2815 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
2817 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
2820 SDValue AllocSize = getValue(I.getArraySize());
2822 EVT IntPtr = TLI.getPointerTy();
2823 if (AllocSize.getValueType() != IntPtr)
2824 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
2826 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
2828 DAG.getConstant(TySize, IntPtr));
2830 // Handle alignment. If the requested alignment is less than or equal to
2831 // the stack alignment, ignore it. If the size is greater than or equal to
2832 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2833 unsigned StackAlign =
2834 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2835 if (Align <= StackAlign)
2838 // Round the size of the allocation up to the stack alignment size
2839 // by add SA-1 to the size.
2840 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
2841 AllocSize.getValueType(), AllocSize,
2842 DAG.getIntPtrConstant(StackAlign-1));
2844 // Mask out the low bits for alignment purposes.
2845 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
2846 AllocSize.getValueType(), AllocSize,
2847 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2849 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2850 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2851 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
2853 DAG.setRoot(DSA.getValue(1));
2855 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2858 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2860 return visitAtomicLoad(I);
2862 const Value *SV = I.getOperand(0);
2863 SDValue Ptr = getValue(SV);
2865 Type *Ty = I.getType();
2867 bool isVolatile = I.isVolatile();
2868 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2869 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
2870 unsigned Alignment = I.getAlignment();
2873 I.getAAMetadata(AAInfo);
2874 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2876 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2877 SmallVector<EVT, 4> ValueVTs;
2878 SmallVector<uint64_t, 4> Offsets;
2879 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2880 unsigned NumValues = ValueVTs.size();
2885 bool ConstantMemory = false;
2886 if (isVolatile || NumValues > MaxParallelChains)
2887 // Serialize volatile loads with other side effects.
2889 else if (AA->pointsToConstantMemory(
2890 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2891 // Do not serialize (non-volatile) loads of constant memory with anything.
2892 Root = DAG.getEntryNode();
2893 ConstantMemory = true;
2895 // Do not serialize non-volatile loads against each other.
2896 Root = DAG.getRoot();
2900 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
2902 SmallVector<SDValue, 4> Values(NumValues);
2903 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2905 EVT PtrVT = Ptr.getValueType();
2906 unsigned ChainI = 0;
2907 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2908 // Serializing loads here may result in excessive register pressure, and
2909 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2910 // could recover a bit by hoisting nodes upward in the chain by recognizing
2911 // they are side-effect free or do not alias. The optimizer should really
2912 // avoid this case by converting large object/array copies to llvm.memcpy
2913 // (MaxParallelChains should always remain as failsafe).
2914 if (ChainI == MaxParallelChains) {
2915 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2916 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
2917 makeArrayRef(Chains.data(), ChainI));
2921 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
2923 DAG.getConstant(Offsets[i], PtrVT));
2924 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
2925 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2926 isNonTemporal, isInvariant, Alignment, AAInfo,
2930 Chains[ChainI] = L.getValue(1);
2933 if (!ConstantMemory) {
2934 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
2935 makeArrayRef(Chains.data(), ChainI));
2939 PendingLoads.push_back(Chain);
2942 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2943 DAG.getVTList(ValueVTs), Values));
2946 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2948 return visitAtomicStore(I);
2950 const Value *SrcV = I.getOperand(0);
2951 const Value *PtrV = I.getOperand(1);
2953 SmallVector<EVT, 4> ValueVTs;
2954 SmallVector<uint64_t, 4> Offsets;
2955 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
2956 ValueVTs, &Offsets);
2957 unsigned NumValues = ValueVTs.size();
2961 // Get the lowered operands. Note that we do this after
2962 // checking if NumResults is zero, because with zero results
2963 // the operands won't have values in the map.
2964 SDValue Src = getValue(SrcV);
2965 SDValue Ptr = getValue(PtrV);
2967 SDValue Root = getRoot();
2968 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2970 EVT PtrVT = Ptr.getValueType();
2971 bool isVolatile = I.isVolatile();
2972 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2973 unsigned Alignment = I.getAlignment();
2976 I.getAAMetadata(AAInfo);
2978 unsigned ChainI = 0;
2979 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2980 // See visitLoad comments.
2981 if (ChainI == MaxParallelChains) {
2982 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
2983 makeArrayRef(Chains.data(), ChainI));
2987 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
2988 DAG.getConstant(Offsets[i], PtrVT));
2989 SDValue St = DAG.getStore(Root, getCurSDLoc(),
2990 SDValue(Src.getNode(), Src.getResNo() + i),
2991 Add, MachinePointerInfo(PtrV, Offsets[i]),
2992 isVolatile, isNonTemporal, Alignment, AAInfo);
2993 Chains[ChainI] = St;
2996 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
2997 makeArrayRef(Chains.data(), ChainI));
2998 DAG.setRoot(StoreNode);
3001 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3002 SDLoc sdl = getCurSDLoc();
3004 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3005 Value *PtrOperand = I.getArgOperand(1);
3006 SDValue Ptr = getValue(PtrOperand);
3007 SDValue Src0 = getValue(I.getArgOperand(0));
3008 SDValue Mask = getValue(I.getArgOperand(3));
3009 EVT VT = Src0.getValueType();
3010 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3012 Alignment = DAG.getEVTAlignment(VT);
3015 I.getAAMetadata(AAInfo);
3017 MachineMemOperand *MMO =
3018 DAG.getMachineFunction().
3019 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3020 MachineMemOperand::MOStore, VT.getStoreSize(),
3022 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3024 DAG.setRoot(StoreNode);
3025 setValue(&I, StoreNode);
3028 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3029 SDLoc sdl = getCurSDLoc();
3031 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3032 Value *PtrOperand = I.getArgOperand(0);
3033 SDValue Ptr = getValue(PtrOperand);
3034 SDValue Src0 = getValue(I.getArgOperand(3));
3035 SDValue Mask = getValue(I.getArgOperand(2));
3037 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3038 EVT VT = TLI.getValueType(I.getType());
3039 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3041 Alignment = DAG.getEVTAlignment(VT);
3044 I.getAAMetadata(AAInfo);
3045 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3047 SDValue InChain = DAG.getRoot();
3048 if (AA->pointsToConstantMemory(
3049 AliasAnalysis::Location(PtrOperand,
3050 AA->getTypeStoreSize(I.getType()),
3052 // Do not serialize (non-volatile) loads of constant memory with anything.
3053 InChain = DAG.getEntryNode();
3056 MachineMemOperand *MMO =
3057 DAG.getMachineFunction().
3058 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3059 MachineMemOperand::MOLoad, VT.getStoreSize(),
3060 Alignment, AAInfo, Ranges);
3062 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3064 SDValue OutChain = Load.getValue(1);
3065 DAG.setRoot(OutChain);
3069 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3070 SDLoc dl = getCurSDLoc();
3071 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3072 AtomicOrdering FailureOrder = I.getFailureOrdering();
3073 SynchronizationScope Scope = I.getSynchScope();
3075 SDValue InChain = getRoot();
3077 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3078 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3079 SDValue L = DAG.getAtomicCmpSwap(
3080 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3081 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3082 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3083 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3085 SDValue OutChain = L.getValue(2);
3088 DAG.setRoot(OutChain);
3091 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3092 SDLoc dl = getCurSDLoc();
3094 switch (I.getOperation()) {
3095 default: llvm_unreachable("Unknown atomicrmw operation");
3096 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3097 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3098 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3099 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3100 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3101 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3102 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3103 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3104 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3105 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3106 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3108 AtomicOrdering Order = I.getOrdering();
3109 SynchronizationScope Scope = I.getSynchScope();
3111 SDValue InChain = getRoot();
3114 DAG.getAtomic(NT, dl,
3115 getValue(I.getValOperand()).getSimpleValueType(),
3117 getValue(I.getPointerOperand()),
3118 getValue(I.getValOperand()),
3119 I.getPointerOperand(),
3120 /* Alignment=*/ 0, Order, Scope);
3122 SDValue OutChain = L.getValue(1);
3125 DAG.setRoot(OutChain);
3128 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3129 SDLoc dl = getCurSDLoc();
3130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3133 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3134 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3135 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3138 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3139 SDLoc dl = getCurSDLoc();
3140 AtomicOrdering Order = I.getOrdering();
3141 SynchronizationScope Scope = I.getSynchScope();
3143 SDValue InChain = getRoot();
3145 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3146 EVT VT = TLI.getValueType(I.getType());
3148 if (I.getAlignment() < VT.getSizeInBits() / 8)
3149 report_fatal_error("Cannot generate unaligned atomic load");
3151 MachineMemOperand *MMO =
3152 DAG.getMachineFunction().
3153 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3154 MachineMemOperand::MOVolatile |
3155 MachineMemOperand::MOLoad,
3157 I.getAlignment() ? I.getAlignment() :
3158 DAG.getEVTAlignment(VT));
3160 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3162 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3163 getValue(I.getPointerOperand()), MMO,
3166 SDValue OutChain = L.getValue(1);
3169 DAG.setRoot(OutChain);
3172 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3173 SDLoc dl = getCurSDLoc();
3175 AtomicOrdering Order = I.getOrdering();
3176 SynchronizationScope Scope = I.getSynchScope();
3178 SDValue InChain = getRoot();
3180 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3181 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3183 if (I.getAlignment() < VT.getSizeInBits() / 8)
3184 report_fatal_error("Cannot generate unaligned atomic store");
3187 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3189 getValue(I.getPointerOperand()),
3190 getValue(I.getValueOperand()),
3191 I.getPointerOperand(), I.getAlignment(),
3194 DAG.setRoot(OutChain);
3197 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3199 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3200 unsigned Intrinsic) {
3201 bool HasChain = !I.doesNotAccessMemory();
3202 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3204 // Build the operand list.
3205 SmallVector<SDValue, 8> Ops;
3206 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3208 // We don't need to serialize loads against other loads.
3209 Ops.push_back(DAG.getRoot());
3211 Ops.push_back(getRoot());
3215 // Info is set by getTgtMemInstrinsic
3216 TargetLowering::IntrinsicInfo Info;
3217 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3218 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3220 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3221 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3222 Info.opc == ISD::INTRINSIC_W_CHAIN)
3223 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3225 // Add all operands of the call to the operand list.
3226 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3227 SDValue Op = getValue(I.getArgOperand(i));
3231 SmallVector<EVT, 4> ValueVTs;
3232 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3235 ValueVTs.push_back(MVT::Other);
3237 SDVTList VTs = DAG.getVTList(ValueVTs);
3241 if (IsTgtIntrinsic) {
3242 // This is target intrinsic that touches memory
3243 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3244 VTs, Ops, Info.memVT,
3245 MachinePointerInfo(Info.ptrVal, Info.offset),
3246 Info.align, Info.vol,
3247 Info.readMem, Info.writeMem, Info.size);
3248 } else if (!HasChain) {
3249 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3250 } else if (!I.getType()->isVoidTy()) {
3251 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3253 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3257 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3259 PendingLoads.push_back(Chain);
3264 if (!I.getType()->isVoidTy()) {
3265 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3266 EVT VT = TLI.getValueType(PTy);
3267 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3270 setValue(&I, Result);
3274 /// GetSignificand - Get the significand and build it into a floating-point
3275 /// number with exponent of 1:
3277 /// Op = (Op & 0x007fffff) | 0x3f800000;
3279 /// where Op is the hexadecimal representation of floating point value.
3281 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3282 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3283 DAG.getConstant(0x007fffff, MVT::i32));
3284 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3285 DAG.getConstant(0x3f800000, MVT::i32));
3286 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3289 /// GetExponent - Get the exponent:
3291 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3293 /// where Op is the hexadecimal representation of floating point value.
3295 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3297 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3298 DAG.getConstant(0x7f800000, MVT::i32));
3299 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3300 DAG.getConstant(23, TLI.getPointerTy()));
3301 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3302 DAG.getConstant(127, MVT::i32));
3303 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3306 /// getF32Constant - Get 32-bit floating point constant.
3308 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3309 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3313 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3314 SelectionDAG &DAG) {
3315 // IntegerPartOfX = ((int32_t)(t0);
3316 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3318 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3319 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3320 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3322 // IntegerPartOfX <<= 23;
3323 IntegerPartOfX = DAG.getNode(
3324 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3325 DAG.getConstant(23, DAG.getTargetLoweringInfo().getPointerTy()));
3327 SDValue TwoToFractionalPartOfX;
3328 if (LimitFloatPrecision <= 6) {
3329 // For floating-point precision of 6:
3331 // TwoToFractionalPartOfX =
3333 // (0.735607626f + 0.252464424f * x) * x;
3335 // error 0.0144103317, which is 6 bits
3336 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3337 getF32Constant(DAG, 0x3e814304));
3338 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3339 getF32Constant(DAG, 0x3f3c50c8));
3340 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3341 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3342 getF32Constant(DAG, 0x3f7f5e7e));
3343 } else if (LimitFloatPrecision <= 12) {
3344 // For floating-point precision of 12:
3346 // TwoToFractionalPartOfX =
3349 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3351 // error 0.000107046256, which is 13 to 14 bits
3352 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3353 getF32Constant(DAG, 0x3da235e3));
3354 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3355 getF32Constant(DAG, 0x3e65b8f3));
3356 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3357 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3358 getF32Constant(DAG, 0x3f324b07));
3359 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3360 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3361 getF32Constant(DAG, 0x3f7ff8fd));
3362 } else { // LimitFloatPrecision <= 18
3363 // For floating-point precision of 18:
3365 // TwoToFractionalPartOfX =
3369 // (0.554906021e-1f +
3370 // (0.961591928e-2f +
3371 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3372 // error 2.47208000*10^(-7), which is better than 18 bits
3373 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3374 getF32Constant(DAG, 0x3924b03e));
3375 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3376 getF32Constant(DAG, 0x3ab24b87));
3377 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3378 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3379 getF32Constant(DAG, 0x3c1d8c17));
3380 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3381 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3382 getF32Constant(DAG, 0x3d634a1d));
3383 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3384 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3385 getF32Constant(DAG, 0x3e75fe14));
3386 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3387 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3388 getF32Constant(DAG, 0x3f317234));
3389 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3390 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3391 getF32Constant(DAG, 0x3f800000));
3394 // Add the exponent into the result in integer domain.
3395 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3396 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3397 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3400 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3401 /// limited-precision mode.
3402 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3403 const TargetLowering &TLI) {
3404 if (Op.getValueType() == MVT::f32 &&
3405 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3407 // Put the exponent in the right bit position for later addition to the
3410 // #define LOG2OFe 1.4426950f
3411 // t0 = Op * LOG2OFe
3412 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3413 getF32Constant(DAG, 0x3fb8aa3b));
3414 return getLimitedPrecisionExp2(t0, dl, DAG);
3417 // No special expansion.
3418 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3421 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3422 /// limited-precision mode.
3423 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3424 const TargetLowering &TLI) {
3425 if (Op.getValueType() == MVT::f32 &&
3426 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3427 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3429 // Scale the exponent by log(2) [0.69314718f].
3430 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3431 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3432 getF32Constant(DAG, 0x3f317218));
3434 // Get the significand and build it into a floating-point number with
3436 SDValue X = GetSignificand(DAG, Op1, dl);
3438 SDValue LogOfMantissa;
3439 if (LimitFloatPrecision <= 6) {
3440 // For floating-point precision of 6:
3444 // (1.4034025f - 0.23903021f * x) * x;
3446 // error 0.0034276066, which is better than 8 bits
3447 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3448 getF32Constant(DAG, 0xbe74c456));
3449 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3450 getF32Constant(DAG, 0x3fb3a2b1));
3451 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3452 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3453 getF32Constant(DAG, 0x3f949a29));
3454 } else if (LimitFloatPrecision <= 12) {
3455 // For floating-point precision of 12:
3461 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3463 // error 0.000061011436, which is 14 bits
3464 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3465 getF32Constant(DAG, 0xbd67b6d6));
3466 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3467 getF32Constant(DAG, 0x3ee4f4b8));
3468 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3469 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3470 getF32Constant(DAG, 0x3fbc278b));
3471 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3472 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3473 getF32Constant(DAG, 0x40348e95));
3474 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3475 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3476 getF32Constant(DAG, 0x3fdef31a));
3477 } else { // LimitFloatPrecision <= 18
3478 // For floating-point precision of 18:
3486 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3488 // error 0.0000023660568, which is better than 18 bits
3489 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3490 getF32Constant(DAG, 0xbc91e5ac));
3491 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3492 getF32Constant(DAG, 0x3e4350aa));
3493 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3494 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3495 getF32Constant(DAG, 0x3f60d3e3));
3496 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3497 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3498 getF32Constant(DAG, 0x4011cdf0));
3499 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3500 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3501 getF32Constant(DAG, 0x406cfd1c));
3502 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3503 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3504 getF32Constant(DAG, 0x408797cb));
3505 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3506 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3507 getF32Constant(DAG, 0x4006dcab));
3510 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3513 // No special expansion.
3514 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3517 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3518 /// limited-precision mode.
3519 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3520 const TargetLowering &TLI) {
3521 if (Op.getValueType() == MVT::f32 &&
3522 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3523 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3525 // Get the exponent.
3526 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3528 // Get the significand and build it into a floating-point number with
3530 SDValue X = GetSignificand(DAG, Op1, dl);
3532 // Different possible minimax approximations of significand in
3533 // floating-point for various degrees of accuracy over [1,2].
3534 SDValue Log2ofMantissa;
3535 if (LimitFloatPrecision <= 6) {
3536 // For floating-point precision of 6:
3538 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3540 // error 0.0049451742, which is more than 7 bits
3541 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3542 getF32Constant(DAG, 0xbeb08fe0));
3543 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3544 getF32Constant(DAG, 0x40019463));
3545 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3546 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3547 getF32Constant(DAG, 0x3fd6633d));
3548 } else if (LimitFloatPrecision <= 12) {
3549 // For floating-point precision of 12:
3555 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3557 // error 0.0000876136000, which is better than 13 bits
3558 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3559 getF32Constant(DAG, 0xbda7262e));
3560 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3561 getF32Constant(DAG, 0x3f25280b));
3562 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3563 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3564 getF32Constant(DAG, 0x4007b923));
3565 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3566 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3567 getF32Constant(DAG, 0x40823e2f));
3568 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3569 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3570 getF32Constant(DAG, 0x4020d29c));
3571 } else { // LimitFloatPrecision <= 18
3572 // For floating-point precision of 18:
3581 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3583 // error 0.0000018516, which is better than 18 bits
3584 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3585 getF32Constant(DAG, 0xbcd2769e));
3586 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3587 getF32Constant(DAG, 0x3e8ce0b9));
3588 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3589 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3590 getF32Constant(DAG, 0x3fa22ae7));
3591 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3592 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3593 getF32Constant(DAG, 0x40525723));
3594 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3595 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3596 getF32Constant(DAG, 0x40aaf200));
3597 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3598 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3599 getF32Constant(DAG, 0x40c39dad));
3600 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3601 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3602 getF32Constant(DAG, 0x4042902c));
3605 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3608 // No special expansion.
3609 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3612 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3613 /// limited-precision mode.
3614 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3615 const TargetLowering &TLI) {
3616 if (Op.getValueType() == MVT::f32 &&
3617 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3618 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3620 // Scale the exponent by log10(2) [0.30102999f].
3621 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3622 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3623 getF32Constant(DAG, 0x3e9a209a));
3625 // Get the significand and build it into a floating-point number with
3627 SDValue X = GetSignificand(DAG, Op1, dl);
3629 SDValue Log10ofMantissa;
3630 if (LimitFloatPrecision <= 6) {
3631 // For floating-point precision of 6:
3633 // Log10ofMantissa =
3635 // (0.60948995f - 0.10380950f * x) * x;
3637 // error 0.0014886165, which is 6 bits
3638 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3639 getF32Constant(DAG, 0xbdd49a13));
3640 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3641 getF32Constant(DAG, 0x3f1c0789));
3642 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3643 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3644 getF32Constant(DAG, 0x3f011300));
3645 } else if (LimitFloatPrecision <= 12) {
3646 // For floating-point precision of 12:
3648 // Log10ofMantissa =
3651 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3653 // error 0.00019228036, which is better than 12 bits
3654 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3655 getF32Constant(DAG, 0x3d431f31));
3656 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3657 getF32Constant(DAG, 0x3ea21fb2));
3658 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3659 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3660 getF32Constant(DAG, 0x3f6ae232));
3661 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3662 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3663 getF32Constant(DAG, 0x3f25f7c3));
3664 } else { // LimitFloatPrecision <= 18
3665 // For floating-point precision of 18:
3667 // Log10ofMantissa =
3672 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3674 // error 0.0000037995730, which is better than 18 bits
3675 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3676 getF32Constant(DAG, 0x3c5d51ce));
3677 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3678 getF32Constant(DAG, 0x3e00685a));
3679 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3680 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3681 getF32Constant(DAG, 0x3efb6798));
3682 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3683 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3684 getF32Constant(DAG, 0x3f88d192));
3685 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3686 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3687 getF32Constant(DAG, 0x3fc4316c));
3688 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3689 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3690 getF32Constant(DAG, 0x3f57ce70));
3693 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3696 // No special expansion.
3697 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3700 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3701 /// limited-precision mode.
3702 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3703 const TargetLowering &TLI) {
3704 if (Op.getValueType() == MVT::f32 &&
3705 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3706 return getLimitedPrecisionExp2(Op, dl, DAG);
3708 // No special expansion.
3709 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3712 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3713 /// limited-precision mode with x == 10.0f.
3714 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3715 SelectionDAG &DAG, const TargetLowering &TLI) {
3716 bool IsExp10 = false;
3717 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3718 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3719 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3721 IsExp10 = LHSC->isExactlyValue(Ten);
3726 // Put the exponent in the right bit position for later addition to the
3729 // #define LOG2OF10 3.3219281f
3730 // t0 = Op * LOG2OF10;
3731 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3732 getF32Constant(DAG, 0x40549a78));
3733 return getLimitedPrecisionExp2(t0, dl, DAG);
3736 // No special expansion.
3737 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3741 /// ExpandPowI - Expand a llvm.powi intrinsic.
3742 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3743 SelectionDAG &DAG) {
3744 // If RHS is a constant, we can expand this out to a multiplication tree,
3745 // otherwise we end up lowering to a call to __powidf2 (for example). When
3746 // optimizing for size, we only want to do this if the expansion would produce
3747 // a small number of multiplies, otherwise we do the full expansion.
3748 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3749 // Get the exponent as a positive value.
3750 unsigned Val = RHSC->getSExtValue();
3751 if ((int)Val < 0) Val = -Val;
3753 // powi(x, 0) -> 1.0
3755 return DAG.getConstantFP(1.0, LHS.getValueType());
3757 const Function *F = DAG.getMachineFunction().getFunction();
3758 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3759 // If optimizing for size, don't insert too many multiplies. This
3760 // inserts up to 5 multiplies.
3761 countPopulation(Val) + Log2_32(Val) < 7) {
3762 // We use the simple binary decomposition method to generate the multiply
3763 // sequence. There are more optimal ways to do this (for example,
3764 // powi(x,15) generates one more multiply than it should), but this has
3765 // the benefit of being both really simple and much better than a libcall.
3766 SDValue Res; // Logically starts equal to 1.0
3767 SDValue CurSquare = LHS;
3771 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3773 Res = CurSquare; // 1.0*CurSquare.
3776 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3777 CurSquare, CurSquare);
3781 // If the original was negative, invert the result, producing 1/(x*x*x).
3782 if (RHSC->getSExtValue() < 0)
3783 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3784 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3789 // Otherwise, expand to a libcall.
3790 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3793 // getTruncatedArgReg - Find underlying register used for an truncated
3795 static unsigned getTruncatedArgReg(const SDValue &N) {
3796 if (N.getOpcode() != ISD::TRUNCATE)
3799 const SDValue &Ext = N.getOperand(0);
3800 if (Ext.getOpcode() == ISD::AssertZext ||
3801 Ext.getOpcode() == ISD::AssertSext) {
3802 const SDValue &CFR = Ext.getOperand(0);
3803 if (CFR.getOpcode() == ISD::CopyFromReg)
3804 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3805 if (CFR.getOpcode() == ISD::TRUNCATE)
3806 return getTruncatedArgReg(CFR);
3811 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3812 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3813 /// At the end of instruction selection, they will be inserted to the entry BB.
3814 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
3815 const Value *V, MDLocalVariable *Variable, MDExpression *Expr,
3816 MDLocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
3817 const Argument *Arg = dyn_cast<Argument>(V);
3821 MachineFunction &MF = DAG.getMachineFunction();
3822 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
3824 // Ignore inlined function arguments here.
3826 // FIXME: Should we be checking DL->inlinedAt() to determine this?
3827 DIVariable DV(Variable);
3828 if (!DV->getScope()->getSubprogram()->describes(MF.getFunction()))
3831 Optional<MachineOperand> Op;
3832 // Some arguments' frame index is recorded during argument lowering.
3833 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
3834 Op = MachineOperand::CreateFI(FI);
3836 if (!Op && N.getNode()) {
3838 if (N.getOpcode() == ISD::CopyFromReg)
3839 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3841 Reg = getTruncatedArgReg(N);
3842 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3843 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3844 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3849 Op = MachineOperand::CreateReg(Reg, false);
3853 // Check if ValueMap has reg number.
3854 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
3855 if (VMI != FuncInfo.ValueMap.end())
3856 Op = MachineOperand::CreateReg(VMI->second, false);
3859 if (!Op && N.getNode())
3860 // Check if frame index is available.
3861 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
3862 if (FrameIndexSDNode *FINode =
3863 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
3864 Op = MachineOperand::CreateFI(FINode->getIndex());
3869 assert(Variable->isValidLocationForIntrinsic(DL) &&
3870 "Expected inlined-at fields to agree");
3872 FuncInfo.ArgDbgValues.push_back(
3873 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
3874 Op->getReg(), Offset, Variable, Expr));
3876 FuncInfo.ArgDbgValues.push_back(
3877 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
3880 .addMetadata(Variable)
3881 .addMetadata(Expr));
3886 // VisualStudio defines setjmp as _setjmp
3887 #if defined(_MSC_VER) && defined(setjmp) && \
3888 !defined(setjmp_undefined_for_msvc)
3889 # pragma push_macro("setjmp")
3891 # define setjmp_undefined_for_msvc
3894 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3895 /// we want to emit this as a call to a named external function, return the name
3896 /// otherwise lower it and return null.
3898 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
3899 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3900 SDLoc sdl = getCurSDLoc();
3901 DebugLoc dl = getCurDebugLoc();
3904 switch (Intrinsic) {
3906 // By default, turn this into a target intrinsic node.
3907 visitTargetIntrinsic(I, Intrinsic);
3909 case Intrinsic::vastart: visitVAStart(I); return nullptr;
3910 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
3911 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
3912 case Intrinsic::returnaddress:
3913 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
3914 getValue(I.getArgOperand(0))));
3916 case Intrinsic::frameaddress:
3917 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
3918 getValue(I.getArgOperand(0))));
3920 case Intrinsic::read_register: {
3921 Value *Reg = I.getArgOperand(0);
3923 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
3924 EVT VT = TLI.getValueType(I.getType());
3925 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
3928 case Intrinsic::write_register: {
3929 Value *Reg = I.getArgOperand(0);
3930 Value *RegValue = I.getArgOperand(1);
3931 SDValue Chain = getValue(RegValue).getOperand(0);
3933 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
3934 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
3935 RegName, getValue(RegValue)));
3938 case Intrinsic::setjmp:
3939 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
3940 case Intrinsic::longjmp:
3941 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
3942 case Intrinsic::memcpy: {
3943 // FIXME: this definition of "user defined address space" is x86-specific
3944 // Assert for address < 256 since we support only user defined address
3946 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
3948 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
3950 "Unknown address space");
3951 SDValue Op1 = getValue(I.getArgOperand(0));
3952 SDValue Op2 = getValue(I.getArgOperand(1));
3953 SDValue Op3 = getValue(I.getArgOperand(2));
3954 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
3956 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
3957 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
3958 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
3959 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
3961 MachinePointerInfo(I.getArgOperand(0)),
3962 MachinePointerInfo(I.getArgOperand(1)));
3963 updateDAGForMaybeTailCall(MC);
3966 case Intrinsic::memset: {
3967 // FIXME: this definition of "user defined address space" is x86-specific
3968 // Assert for address < 256 since we support only user defined address
3970 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
3972 "Unknown address space");
3973 SDValue Op1 = getValue(I.getArgOperand(0));
3974 SDValue Op2 = getValue(I.getArgOperand(1));
3975 SDValue Op3 = getValue(I.getArgOperand(2));
3976 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
3978 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
3979 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
3980 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
3981 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
3982 isTC, MachinePointerInfo(I.getArgOperand(0)));
3983 updateDAGForMaybeTailCall(MS);
3986 case Intrinsic::memmove: {
3987 // FIXME: this definition of "user defined address space" is x86-specific
3988 // Assert for address < 256 since we support only user defined address
3990 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
3992 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
3994 "Unknown address space");
3995 SDValue Op1 = getValue(I.getArgOperand(0));
3996 SDValue Op2 = getValue(I.getArgOperand(1));
3997 SDValue Op3 = getValue(I.getArgOperand(2));
3998 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4000 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4001 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4002 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4003 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4004 isTC, MachinePointerInfo(I.getArgOperand(0)),
4005 MachinePointerInfo(I.getArgOperand(1)));
4006 updateDAGForMaybeTailCall(MM);
4009 case Intrinsic::dbg_declare: {
4010 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4011 MDLocalVariable *Variable = DI.getVariable();
4012 MDExpression *Expression = DI.getExpression();
4013 const Value *Address = DI.getAddress();
4014 DIVariable DIVar = Variable;
4015 if (!Address || !DIVar) {
4016 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4020 // Check if address has undef value.
4021 if (isa<UndefValue>(Address) ||
4022 (Address->use_empty() && !isa<Argument>(Address))) {
4023 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4027 SDValue &N = NodeMap[Address];
4028 if (!N.getNode() && isa<Argument>(Address))
4029 // Check unused arguments map.
4030 N = UnusedArgNodeMap[Address];
4033 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4034 Address = BCI->getOperand(0);
4035 // Parameters are handled specially.
4037 (DIVariable(Variable)->getTag() == dwarf::DW_TAG_arg_variable ||
4038 isa<Argument>(Address));
4040 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4042 if (isParameter && !AI) {
4043 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4045 // Byval parameter. We have a frame index at this point.
4046 SDV = DAG.getFrameIndexDbgValue(
4047 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4049 // Address is an argument, so try to emit its dbg value using
4050 // virtual register info from the FuncInfo.ValueMap.
4051 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4056 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4057 true, 0, dl, SDNodeOrder);
4059 // Can't do anything with other non-AI cases yet.
4060 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4061 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4062 DEBUG(Address->dump());
4065 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4067 // If Address is an argument then try to emit its dbg value using
4068 // virtual register info from the FuncInfo.ValueMap.
4069 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4071 // If variable is pinned by a alloca in dominating bb then
4072 // use StaticAllocaMap.
4073 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4074 if (AI->getParent() != DI.getParent()) {
4075 DenseMap<const AllocaInst*, int>::iterator SI =
4076 FuncInfo.StaticAllocaMap.find(AI);
4077 if (SI != FuncInfo.StaticAllocaMap.end()) {
4078 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4079 0, dl, SDNodeOrder);
4080 DAG.AddDbgValue(SDV, nullptr, false);
4085 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4090 case Intrinsic::dbg_value: {
4091 const DbgValueInst &DI = cast<DbgValueInst>(I);
4092 DIVariable DIVar = DI.getVariable();
4096 MDLocalVariable *Variable = DI.getVariable();
4097 MDExpression *Expression = DI.getExpression();
4098 uint64_t Offset = DI.getOffset();
4099 const Value *V = DI.getValue();
4104 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4105 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4107 DAG.AddDbgValue(SDV, nullptr, false);
4109 // Do not use getValue() in here; we don't want to generate code at
4110 // this point if it hasn't been done yet.
4111 SDValue N = NodeMap[V];
4112 if (!N.getNode() && isa<Argument>(V))
4113 // Check unused arguments map.
4114 N = UnusedArgNodeMap[V];
4116 // A dbg.value for an alloca is always indirect.
4117 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4118 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4120 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4121 IsIndirect, Offset, dl, SDNodeOrder);
4122 DAG.AddDbgValue(SDV, N.getNode(), false);
4124 } else if (!V->use_empty() ) {
4125 // Do not call getValue(V) yet, as we don't want to generate code.
4126 // Remember it for later.
4127 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4128 DanglingDebugInfoMap[V] = DDI;
4130 // We may expand this to cover more cases. One case where we have no
4131 // data available is an unreferenced parameter.
4132 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4136 // Build a debug info table entry.
4137 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4138 V = BCI->getOperand(0);
4139 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4140 // Don't handle byval struct arguments or VLAs, for example.
4142 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4143 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4146 DenseMap<const AllocaInst*, int>::iterator SI =
4147 FuncInfo.StaticAllocaMap.find(AI);
4148 if (SI == FuncInfo.StaticAllocaMap.end())
4149 return nullptr; // VLAs.
4153 case Intrinsic::eh_typeid_for: {
4154 // Find the type id for the given typeinfo.
4155 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4156 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4157 Res = DAG.getConstant(TypeID, MVT::i32);
4162 case Intrinsic::eh_return_i32:
4163 case Intrinsic::eh_return_i64:
4164 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4165 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4168 getValue(I.getArgOperand(0)),
4169 getValue(I.getArgOperand(1))));
4171 case Intrinsic::eh_unwind_init:
4172 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4174 case Intrinsic::eh_dwarf_cfa: {
4175 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4176 TLI.getPointerTy());
4177 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4178 CfaArg.getValueType(),
4179 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4180 CfaArg.getValueType()),
4182 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4183 DAG.getConstant(0, TLI.getPointerTy()));
4184 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4188 case Intrinsic::eh_sjlj_callsite: {
4189 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4190 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4191 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4192 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4194 MMI.setCurrentCallSite(CI->getZExtValue());
4197 case Intrinsic::eh_sjlj_functioncontext: {
4198 // Get and store the index of the function context.
4199 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4201 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4202 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4203 MFI->setFunctionContextIndex(FI);
4206 case Intrinsic::eh_sjlj_setjmp: {
4209 Ops[1] = getValue(I.getArgOperand(0));
4210 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4211 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4212 setValue(&I, Op.getValue(0));
4213 DAG.setRoot(Op.getValue(1));
4216 case Intrinsic::eh_sjlj_longjmp: {
4217 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4218 getRoot(), getValue(I.getArgOperand(0))));
4222 case Intrinsic::masked_load:
4225 case Intrinsic::masked_store:
4226 visitMaskedStore(I);
4228 case Intrinsic::x86_mmx_pslli_w:
4229 case Intrinsic::x86_mmx_pslli_d:
4230 case Intrinsic::x86_mmx_pslli_q:
4231 case Intrinsic::x86_mmx_psrli_w:
4232 case Intrinsic::x86_mmx_psrli_d:
4233 case Intrinsic::x86_mmx_psrli_q:
4234 case Intrinsic::x86_mmx_psrai_w:
4235 case Intrinsic::x86_mmx_psrai_d: {
4236 SDValue ShAmt = getValue(I.getArgOperand(1));
4237 if (isa<ConstantSDNode>(ShAmt)) {
4238 visitTargetIntrinsic(I, Intrinsic);
4241 unsigned NewIntrinsic = 0;
4242 EVT ShAmtVT = MVT::v2i32;
4243 switch (Intrinsic) {
4244 case Intrinsic::x86_mmx_pslli_w:
4245 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4247 case Intrinsic::x86_mmx_pslli_d:
4248 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4250 case Intrinsic::x86_mmx_pslli_q:
4251 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4253 case Intrinsic::x86_mmx_psrli_w:
4254 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4256 case Intrinsic::x86_mmx_psrli_d:
4257 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4259 case Intrinsic::x86_mmx_psrli_q:
4260 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4262 case Intrinsic::x86_mmx_psrai_w:
4263 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4265 case Intrinsic::x86_mmx_psrai_d:
4266 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4268 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4271 // The vector shift intrinsics with scalars uses 32b shift amounts but
4272 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4274 // We must do this early because v2i32 is not a legal type.
4277 ShOps[1] = DAG.getConstant(0, MVT::i32);
4278 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4279 EVT DestVT = TLI.getValueType(I.getType());
4280 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4281 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4282 DAG.getConstant(NewIntrinsic, MVT::i32),
4283 getValue(I.getArgOperand(0)), ShAmt);
4287 case Intrinsic::convertff:
4288 case Intrinsic::convertfsi:
4289 case Intrinsic::convertfui:
4290 case Intrinsic::convertsif:
4291 case Intrinsic::convertuif:
4292 case Intrinsic::convertss:
4293 case Intrinsic::convertsu:
4294 case Intrinsic::convertus:
4295 case Intrinsic::convertuu: {
4296 ISD::CvtCode Code = ISD::CVT_INVALID;
4297 switch (Intrinsic) {
4298 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4299 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4300 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4301 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4302 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4303 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4304 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4305 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4306 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4307 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4309 EVT DestVT = TLI.getValueType(I.getType());
4310 const Value *Op1 = I.getArgOperand(0);
4311 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4312 DAG.getValueType(DestVT),
4313 DAG.getValueType(getValue(Op1).getValueType()),
4314 getValue(I.getArgOperand(1)),
4315 getValue(I.getArgOperand(2)),
4320 case Intrinsic::powi:
4321 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4322 getValue(I.getArgOperand(1)), DAG));
4324 case Intrinsic::log:
4325 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4327 case Intrinsic::log2:
4328 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4330 case Intrinsic::log10:
4331 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4333 case Intrinsic::exp:
4334 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4336 case Intrinsic::exp2:
4337 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4339 case Intrinsic::pow:
4340 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4341 getValue(I.getArgOperand(1)), DAG, TLI));
4343 case Intrinsic::sqrt:
4344 case Intrinsic::fabs:
4345 case Intrinsic::sin:
4346 case Intrinsic::cos:
4347 case Intrinsic::floor:
4348 case Intrinsic::ceil:
4349 case Intrinsic::trunc:
4350 case Intrinsic::rint:
4351 case Intrinsic::nearbyint:
4352 case Intrinsic::round: {
4354 switch (Intrinsic) {
4355 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4356 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4357 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4358 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4359 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4360 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4361 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4362 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4363 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4364 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4365 case Intrinsic::round: Opcode = ISD::FROUND; break;
4368 setValue(&I, DAG.getNode(Opcode, sdl,
4369 getValue(I.getArgOperand(0)).getValueType(),
4370 getValue(I.getArgOperand(0))));
4373 case Intrinsic::minnum:
4374 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4375 getValue(I.getArgOperand(0)).getValueType(),
4376 getValue(I.getArgOperand(0)),
4377 getValue(I.getArgOperand(1))));
4379 case Intrinsic::maxnum:
4380 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4381 getValue(I.getArgOperand(0)).getValueType(),
4382 getValue(I.getArgOperand(0)),
4383 getValue(I.getArgOperand(1))));
4385 case Intrinsic::copysign:
4386 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4387 getValue(I.getArgOperand(0)).getValueType(),
4388 getValue(I.getArgOperand(0)),
4389 getValue(I.getArgOperand(1))));
4391 case Intrinsic::fma:
4392 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4393 getValue(I.getArgOperand(0)).getValueType(),
4394 getValue(I.getArgOperand(0)),
4395 getValue(I.getArgOperand(1)),
4396 getValue(I.getArgOperand(2))));
4398 case Intrinsic::fmuladd: {
4399 EVT VT = TLI.getValueType(I.getType());
4400 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4401 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4402 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4403 getValue(I.getArgOperand(0)).getValueType(),
4404 getValue(I.getArgOperand(0)),
4405 getValue(I.getArgOperand(1)),
4406 getValue(I.getArgOperand(2))));
4408 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4409 getValue(I.getArgOperand(0)).getValueType(),
4410 getValue(I.getArgOperand(0)),
4411 getValue(I.getArgOperand(1)));
4412 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4413 getValue(I.getArgOperand(0)).getValueType(),
4415 getValue(I.getArgOperand(2)));
4420 case Intrinsic::convert_to_fp16:
4421 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4422 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4423 getValue(I.getArgOperand(0)),
4424 DAG.getTargetConstant(0, MVT::i32))));
4426 case Intrinsic::convert_from_fp16:
4428 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
4429 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4430 getValue(I.getArgOperand(0)))));
4432 case Intrinsic::pcmarker: {
4433 SDValue Tmp = getValue(I.getArgOperand(0));
4434 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4437 case Intrinsic::readcyclecounter: {
4438 SDValue Op = getRoot();
4439 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4440 DAG.getVTList(MVT::i64, MVT::Other), Op);
4442 DAG.setRoot(Res.getValue(1));
4445 case Intrinsic::bswap:
4446 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4447 getValue(I.getArgOperand(0)).getValueType(),
4448 getValue(I.getArgOperand(0))));
4450 case Intrinsic::cttz: {
4451 SDValue Arg = getValue(I.getArgOperand(0));
4452 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4453 EVT Ty = Arg.getValueType();
4454 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4458 case Intrinsic::ctlz: {
4459 SDValue Arg = getValue(I.getArgOperand(0));
4460 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4461 EVT Ty = Arg.getValueType();
4462 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4466 case Intrinsic::ctpop: {
4467 SDValue Arg = getValue(I.getArgOperand(0));
4468 EVT Ty = Arg.getValueType();
4469 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4472 case Intrinsic::stacksave: {
4473 SDValue Op = getRoot();
4474 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4475 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
4477 DAG.setRoot(Res.getValue(1));
4480 case Intrinsic::stackrestore: {
4481 Res = getValue(I.getArgOperand(0));
4482 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4485 case Intrinsic::stackprotector: {
4486 // Emit code into the DAG to store the stack guard onto the stack.
4487 MachineFunction &MF = DAG.getMachineFunction();
4488 MachineFrameInfo *MFI = MF.getFrameInfo();
4489 EVT PtrTy = TLI.getPointerTy();
4490 SDValue Src, Chain = getRoot();
4491 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4492 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4494 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4495 // global variable __stack_chk_guard.
4497 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4498 if (BC->getOpcode() == Instruction::BitCast)
4499 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4501 if (GV && TLI.useLoadStackGuardNode()) {
4502 // Emit a LOAD_STACK_GUARD node.
4503 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4505 MachinePointerInfo MPInfo(GV);
4506 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4507 unsigned Flags = MachineMemOperand::MOLoad |
4508 MachineMemOperand::MOInvariant;
4509 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4510 PtrTy.getSizeInBits() / 8,
4511 DAG.getEVTAlignment(PtrTy));
4512 Node->setMemRefs(MemRefs, MemRefs + 1);
4514 // Copy the guard value to a virtual register so that it can be
4515 // retrieved in the epilogue.
4516 Src = SDValue(Node, 0);
4517 const TargetRegisterClass *RC =
4518 TLI.getRegClassFor(Src.getSimpleValueType());
4519 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4521 SPDescriptor.setGuardReg(Reg);
4522 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4524 Src = getValue(I.getArgOperand(0)); // The guard's value.
4527 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4529 int FI = FuncInfo.StaticAllocaMap[Slot];
4530 MFI->setStackProtectorIndex(FI);
4532 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4534 // Store the stack protector onto the stack.
4535 Res = DAG.getStore(Chain, sdl, Src, FIN,
4536 MachinePointerInfo::getFixedStack(FI),
4542 case Intrinsic::objectsize: {
4543 // If we don't know by now, we're never going to know.
4544 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4546 assert(CI && "Non-constant type in __builtin_object_size?");
4548 SDValue Arg = getValue(I.getCalledValue());
4549 EVT Ty = Arg.getValueType();
4552 Res = DAG.getConstant(-1ULL, Ty);
4554 Res = DAG.getConstant(0, Ty);
4559 case Intrinsic::annotation:
4560 case Intrinsic::ptr_annotation:
4561 // Drop the intrinsic, but forward the value
4562 setValue(&I, getValue(I.getOperand(0)));
4564 case Intrinsic::assume:
4565 case Intrinsic::var_annotation:
4566 // Discard annotate attributes and assumptions
4569 case Intrinsic::init_trampoline: {
4570 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4574 Ops[1] = getValue(I.getArgOperand(0));
4575 Ops[2] = getValue(I.getArgOperand(1));
4576 Ops[3] = getValue(I.getArgOperand(2));
4577 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4578 Ops[5] = DAG.getSrcValue(F);
4580 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4585 case Intrinsic::adjust_trampoline: {
4586 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4588 getValue(I.getArgOperand(0))));
4591 case Intrinsic::gcroot:
4593 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4594 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4596 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4597 GFI->addStackRoot(FI->getIndex(), TypeMap);
4600 case Intrinsic::gcread:
4601 case Intrinsic::gcwrite:
4602 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4603 case Intrinsic::flt_rounds:
4604 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4607 case Intrinsic::expect: {
4608 // Just replace __builtin_expect(exp, c) with EXP.
4609 setValue(&I, getValue(I.getArgOperand(0)));
4613 case Intrinsic::debugtrap:
4614 case Intrinsic::trap: {
4615 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
4616 if (TrapFuncName.empty()) {
4617 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4618 ISD::TRAP : ISD::DEBUGTRAP;
4619 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4622 TargetLowering::ArgListTy Args;
4624 TargetLowering::CallLoweringInfo CLI(DAG);
4625 CLI.setDebugLoc(sdl).setChain(getRoot())
4626 .setCallee(CallingConv::C, I.getType(),
4627 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4628 std::move(Args), 0);
4630 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4631 DAG.setRoot(Result.second);
4635 case Intrinsic::uadd_with_overflow:
4636 case Intrinsic::sadd_with_overflow:
4637 case Intrinsic::usub_with_overflow:
4638 case Intrinsic::ssub_with_overflow:
4639 case Intrinsic::umul_with_overflow:
4640 case Intrinsic::smul_with_overflow: {
4642 switch (Intrinsic) {
4643 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4644 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4645 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4646 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4647 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4648 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4649 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4651 SDValue Op1 = getValue(I.getArgOperand(0));
4652 SDValue Op2 = getValue(I.getArgOperand(1));
4654 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4655 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4658 case Intrinsic::prefetch: {
4660 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4662 Ops[1] = getValue(I.getArgOperand(0));
4663 Ops[2] = getValue(I.getArgOperand(1));
4664 Ops[3] = getValue(I.getArgOperand(2));
4665 Ops[4] = getValue(I.getArgOperand(3));
4666 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4667 DAG.getVTList(MVT::Other), Ops,
4668 EVT::getIntegerVT(*Context, 8),
4669 MachinePointerInfo(I.getArgOperand(0)),
4671 false, /* volatile */
4673 rw==1)); /* write */
4676 case Intrinsic::lifetime_start:
4677 case Intrinsic::lifetime_end: {
4678 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4679 // Stack coloring is not enabled in O0, discard region information.
4680 if (TM.getOptLevel() == CodeGenOpt::None)
4683 SmallVector<Value *, 4> Allocas;
4684 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4686 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4687 E = Allocas.end(); Object != E; ++Object) {
4688 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4690 // Could not find an Alloca.
4691 if (!LifetimeObject)
4694 // First check that the Alloca is static, otherwise it won't have a
4695 // valid frame index.
4696 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4697 if (SI == FuncInfo.StaticAllocaMap.end())
4700 int FI = SI->second;
4704 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
4705 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4707 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4712 case Intrinsic::invariant_start:
4713 // Discard region information.
4714 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4716 case Intrinsic::invariant_end:
4717 // Discard region information.
4719 case Intrinsic::stackprotectorcheck: {
4720 // Do not actually emit anything for this basic block. Instead we initialize
4721 // the stack protector descriptor and export the guard variable so we can
4722 // access it in FinishBasicBlock.
4723 const BasicBlock *BB = I.getParent();
4724 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4725 ExportFromCurrentBlock(SPDescriptor.getGuard());
4727 // Flush our exports since we are going to process a terminator.
4728 (void)getControlRoot();
4731 case Intrinsic::clear_cache:
4732 return TLI.getClearCacheBuiltinName();
4733 case Intrinsic::eh_actions:
4734 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4736 case Intrinsic::donothing:
4739 case Intrinsic::experimental_stackmap: {
4743 case Intrinsic::experimental_patchpoint_void:
4744 case Intrinsic::experimental_patchpoint_i64: {
4745 visitPatchpoint(&I);
4748 case Intrinsic::experimental_gc_statepoint: {
4752 case Intrinsic::experimental_gc_result_int:
4753 case Intrinsic::experimental_gc_result_float:
4754 case Intrinsic::experimental_gc_result_ptr:
4755 case Intrinsic::experimental_gc_result: {
4759 case Intrinsic::experimental_gc_relocate: {
4763 case Intrinsic::instrprof_increment:
4764 llvm_unreachable("instrprof failed to lower an increment");
4766 case Intrinsic::frameescape: {
4767 MachineFunction &MF = DAG.getMachineFunction();
4768 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4770 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
4771 // is the same on all targets.
4772 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4773 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4774 if (isa<ConstantPointerNull>(Arg))
4775 continue; // Skip null pointers. They represent a hole in index space.
4776 AllocaInst *Slot = cast<AllocaInst>(Arg);
4777 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4778 "can only escape static allocas");
4779 int FI = FuncInfo.StaticAllocaMap[Slot];
4780 MCSymbol *FrameAllocSym =
4781 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4782 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4783 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4784 TII->get(TargetOpcode::FRAME_ALLOC))
4785 .addSym(FrameAllocSym)
4792 case Intrinsic::framerecover: {
4793 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
4794 MachineFunction &MF = DAG.getMachineFunction();
4795 MVT PtrVT = TLI.getPointerTy(0);
4797 // Get the symbol that defines the frame offset.
4798 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
4799 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
4800 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
4801 MCSymbol *FrameAllocSym =
4802 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4803 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
4805 // Create a TargetExternalSymbol for the label to avoid any target lowering
4806 // that would make this PC relative.
4807 StringRef Name = FrameAllocSym->getName();
4808 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
4809 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
4811 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
4813 // Add the offset to the FP.
4814 Value *FP = I.getArgOperand(1);
4815 SDValue FPVal = getValue(FP);
4816 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
4821 case Intrinsic::eh_begincatch:
4822 case Intrinsic::eh_endcatch:
4823 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
4827 std::pair<SDValue, SDValue>
4828 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
4829 MachineBasicBlock *LandingPad) {
4830 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4831 MCSymbol *BeginLabel = nullptr;
4834 // Insert a label before the invoke call to mark the try range. This can be
4835 // used to detect deletion of the invoke via the MachineModuleInfo.
4836 BeginLabel = MMI.getContext().CreateTempSymbol();
4838 // For SjLj, keep track of which landing pads go with which invokes
4839 // so as to maintain the ordering of pads in the LSDA.
4840 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4841 if (CallSiteIndex) {
4842 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4843 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
4845 // Now that the call site is handled, stop tracking it.
4846 MMI.setCurrentCallSite(0);
4849 // Both PendingLoads and PendingExports must be flushed here;
4850 // this call might not return.
4852 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
4854 CLI.setChain(getRoot());
4856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4857 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4859 assert((CLI.IsTailCall || Result.second.getNode()) &&
4860 "Non-null chain expected with non-tail call!");
4861 assert((Result.second.getNode() || !Result.first.getNode()) &&
4862 "Null value expected with tail call!");
4864 if (!Result.second.getNode()) {
4865 // As a special case, a null chain means that a tail call has been emitted
4866 // and the DAG root is already updated.
4869 // Since there's no actual continuation from this block, nothing can be
4870 // relying on us setting vregs for them.
4871 PendingExports.clear();
4873 DAG.setRoot(Result.second);
4877 // Insert a label at the end of the invoke call to mark the try range. This
4878 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4879 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4880 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
4882 // Inform MachineModuleInfo of range.
4883 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4889 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4891 MachineBasicBlock *LandingPad) {
4892 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4893 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4894 Type *RetTy = FTy->getReturnType();
4896 TargetLowering::ArgListTy Args;
4897 TargetLowering::ArgListEntry Entry;
4898 Args.reserve(CS.arg_size());
4900 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4902 const Value *V = *i;
4905 if (V->getType()->isEmptyTy())
4908 SDValue ArgNode = getValue(V);
4909 Entry.Node = ArgNode; Entry.Ty = V->getType();
4911 // Skip the first return-type Attribute to get to params.
4912 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
4913 Args.push_back(Entry);
4915 // If we have an explicit sret argument that is an Instruction, (i.e., it
4916 // might point to function-local memory), we can't meaningfully tail-call.
4917 if (Entry.isSRet && isa<Instruction>(V))
4921 // Check if target-independent constraints permit a tail call here.
4922 // Target-dependent constraints are checked within TLI->LowerCallTo.
4923 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
4926 TargetLowering::CallLoweringInfo CLI(DAG);
4927 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
4928 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
4929 .setTailCall(isTailCall);
4930 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
4932 if (Result.first.getNode())
4933 setValue(CS.getInstruction(), Result.first);
4936 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4937 /// value is equal or not-equal to zero.
4938 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4939 for (const User *U : V->users()) {
4940 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
4941 if (IC->isEquality())
4942 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4943 if (C->isNullValue())
4945 // Unknown instruction.
4951 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4953 SelectionDAGBuilder &Builder) {
4955 // Check to see if this load can be trivially constant folded, e.g. if the
4956 // input is from a string literal.
4957 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4958 // Cast pointer to the type we really want to load.
4959 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4960 PointerType::getUnqual(LoadTy));
4962 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
4963 const_cast<Constant *>(LoadInput), *Builder.DL))
4964 return Builder.getValue(LoadCst);
4967 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4968 // still constant memory, the input chain can be the entry node.
4970 bool ConstantMemory = false;
4972 // Do not serialize (non-volatile) loads of constant memory with anything.
4973 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4974 Root = Builder.DAG.getEntryNode();
4975 ConstantMemory = true;
4977 // Do not serialize non-volatile loads against each other.
4978 Root = Builder.DAG.getRoot();
4981 SDValue Ptr = Builder.getValue(PtrVal);
4982 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
4983 Ptr, MachinePointerInfo(PtrVal),
4985 false /*nontemporal*/,
4986 false /*isinvariant*/, 1 /* align=1 */);
4988 if (!ConstantMemory)
4989 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4993 /// processIntegerCallValue - Record the value for an instruction that
4994 /// produces an integer result, converting the type where necessary.
4995 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
4998 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5000 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5002 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5003 setValue(&I, Value);
5006 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5007 /// If so, return true and lower it, otherwise return false and it will be
5008 /// lowered like a normal call.
5009 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5010 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5011 if (I.getNumArgOperands() != 3)
5014 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5015 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5016 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5017 !I.getType()->isIntegerTy())
5020 const Value *Size = I.getArgOperand(2);
5021 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5022 if (CSize && CSize->getZExtValue() == 0) {
5023 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5024 setValue(&I, DAG.getConstant(0, CallVT));
5028 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5029 std::pair<SDValue, SDValue> Res =
5030 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5031 getValue(LHS), getValue(RHS), getValue(Size),
5032 MachinePointerInfo(LHS),
5033 MachinePointerInfo(RHS));
5034 if (Res.first.getNode()) {
5035 processIntegerCallValue(I, Res.first, true);
5036 PendingLoads.push_back(Res.second);
5040 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5041 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5042 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5043 bool ActuallyDoIt = true;
5046 switch (CSize->getZExtValue()) {
5048 LoadVT = MVT::Other;
5050 ActuallyDoIt = false;
5054 LoadTy = Type::getInt16Ty(CSize->getContext());
5058 LoadTy = Type::getInt32Ty(CSize->getContext());
5062 LoadTy = Type::getInt64Ty(CSize->getContext());
5066 LoadVT = MVT::v4i32;
5067 LoadTy = Type::getInt32Ty(CSize->getContext());
5068 LoadTy = VectorType::get(LoadTy, 4);
5073 // This turns into unaligned loads. We only do this if the target natively
5074 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5075 // we'll only produce a small number of byte loads.
5077 // Require that we can find a legal MVT, and only do this if the target
5078 // supports unaligned loads of that type. Expanding into byte loads would
5080 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5081 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5082 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5083 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5084 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5085 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5086 // TODO: Check alignment of src and dest ptrs.
5087 if (!TLI.isTypeLegal(LoadVT) ||
5088 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5089 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5090 ActuallyDoIt = false;
5094 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5095 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5097 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5099 processIntegerCallValue(I, Res, false);
5108 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5109 /// form. If so, return true and lower it, otherwise return false and it
5110 /// will be lowered like a normal call.
5111 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5112 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5113 if (I.getNumArgOperands() != 3)
5116 const Value *Src = I.getArgOperand(0);
5117 const Value *Char = I.getArgOperand(1);
5118 const Value *Length = I.getArgOperand(2);
5119 if (!Src->getType()->isPointerTy() ||
5120 !Char->getType()->isIntegerTy() ||
5121 !Length->getType()->isIntegerTy() ||
5122 !I.getType()->isPointerTy())
5125 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5126 std::pair<SDValue, SDValue> Res =
5127 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5128 getValue(Src), getValue(Char), getValue(Length),
5129 MachinePointerInfo(Src));
5130 if (Res.first.getNode()) {
5131 setValue(&I, Res.first);
5132 PendingLoads.push_back(Res.second);
5139 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5140 /// optimized form. If so, return true and lower it, otherwise return false
5141 /// and it will be lowered like a normal call.
5142 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5143 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5144 if (I.getNumArgOperands() != 2)
5147 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5148 if (!Arg0->getType()->isPointerTy() ||
5149 !Arg1->getType()->isPointerTy() ||
5150 !I.getType()->isPointerTy())
5153 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5154 std::pair<SDValue, SDValue> Res =
5155 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5156 getValue(Arg0), getValue(Arg1),
5157 MachinePointerInfo(Arg0),
5158 MachinePointerInfo(Arg1), isStpcpy);
5159 if (Res.first.getNode()) {
5160 setValue(&I, Res.first);
5161 DAG.setRoot(Res.second);
5168 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5169 /// If so, return true and lower it, otherwise return false and it will be
5170 /// lowered like a normal call.
5171 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5172 // Verify that the prototype makes sense. int strcmp(void*,void*)
5173 if (I.getNumArgOperands() != 2)
5176 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5177 if (!Arg0->getType()->isPointerTy() ||
5178 !Arg1->getType()->isPointerTy() ||
5179 !I.getType()->isIntegerTy())
5182 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5183 std::pair<SDValue, SDValue> Res =
5184 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5185 getValue(Arg0), getValue(Arg1),
5186 MachinePointerInfo(Arg0),
5187 MachinePointerInfo(Arg1));
5188 if (Res.first.getNode()) {
5189 processIntegerCallValue(I, Res.first, true);
5190 PendingLoads.push_back(Res.second);
5197 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5198 /// form. If so, return true and lower it, otherwise return false and it
5199 /// will be lowered like a normal call.
5200 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5201 // Verify that the prototype makes sense. size_t strlen(char *)
5202 if (I.getNumArgOperands() != 1)
5205 const Value *Arg0 = I.getArgOperand(0);
5206 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5209 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5210 std::pair<SDValue, SDValue> Res =
5211 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5212 getValue(Arg0), MachinePointerInfo(Arg0));
5213 if (Res.first.getNode()) {
5214 processIntegerCallValue(I, Res.first, false);
5215 PendingLoads.push_back(Res.second);
5222 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5223 /// form. If so, return true and lower it, otherwise return false and it
5224 /// will be lowered like a normal call.
5225 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5226 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5227 if (I.getNumArgOperands() != 2)
5230 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5231 if (!Arg0->getType()->isPointerTy() ||
5232 !Arg1->getType()->isIntegerTy() ||
5233 !I.getType()->isIntegerTy())
5236 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5237 std::pair<SDValue, SDValue> Res =
5238 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5239 getValue(Arg0), getValue(Arg1),
5240 MachinePointerInfo(Arg0));
5241 if (Res.first.getNode()) {
5242 processIntegerCallValue(I, Res.first, false);
5243 PendingLoads.push_back(Res.second);
5250 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5251 /// operation (as expected), translate it to an SDNode with the specified opcode
5252 /// and return true.
5253 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5255 // Sanity check that it really is a unary floating-point call.
5256 if (I.getNumArgOperands() != 1 ||
5257 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5258 I.getType() != I.getArgOperand(0)->getType() ||
5259 !I.onlyReadsMemory())
5262 SDValue Tmp = getValue(I.getArgOperand(0));
5263 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5267 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5268 /// operation (as expected), translate it to an SDNode with the specified opcode
5269 /// and return true.
5270 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5272 // Sanity check that it really is a binary floating-point call.
5273 if (I.getNumArgOperands() != 2 ||
5274 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5275 I.getType() != I.getArgOperand(0)->getType() ||
5276 I.getType() != I.getArgOperand(1)->getType() ||
5277 !I.onlyReadsMemory())
5280 SDValue Tmp0 = getValue(I.getArgOperand(0));
5281 SDValue Tmp1 = getValue(I.getArgOperand(1));
5282 EVT VT = Tmp0.getValueType();
5283 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5287 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5288 // Handle inline assembly differently.
5289 if (isa<InlineAsm>(I.getCalledValue())) {
5294 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5295 ComputeUsesVAFloatArgument(I, &MMI);
5297 const char *RenameFn = nullptr;
5298 if (Function *F = I.getCalledFunction()) {
5299 if (F->isDeclaration()) {
5300 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5301 if (unsigned IID = II->getIntrinsicID(F)) {
5302 RenameFn = visitIntrinsicCall(I, IID);
5307 if (unsigned IID = F->getIntrinsicID()) {
5308 RenameFn = visitIntrinsicCall(I, IID);
5314 // Check for well-known libc/libm calls. If the function is internal, it
5315 // can't be a library call.
5317 if (!F->hasLocalLinkage() && F->hasName() &&
5318 LibInfo->getLibFunc(F->getName(), Func) &&
5319 LibInfo->hasOptimizedCodeGen(Func)) {
5322 case LibFunc::copysign:
5323 case LibFunc::copysignf:
5324 case LibFunc::copysignl:
5325 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5326 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5327 I.getType() == I.getArgOperand(0)->getType() &&
5328 I.getType() == I.getArgOperand(1)->getType() &&
5329 I.onlyReadsMemory()) {
5330 SDValue LHS = getValue(I.getArgOperand(0));
5331 SDValue RHS = getValue(I.getArgOperand(1));
5332 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5333 LHS.getValueType(), LHS, RHS));
5338 case LibFunc::fabsf:
5339 case LibFunc::fabsl:
5340 if (visitUnaryFloatCall(I, ISD::FABS))
5344 case LibFunc::fminf:
5345 case LibFunc::fminl:
5346 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5350 case LibFunc::fmaxf:
5351 case LibFunc::fmaxl:
5352 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5358 if (visitUnaryFloatCall(I, ISD::FSIN))
5364 if (visitUnaryFloatCall(I, ISD::FCOS))
5368 case LibFunc::sqrtf:
5369 case LibFunc::sqrtl:
5370 case LibFunc::sqrt_finite:
5371 case LibFunc::sqrtf_finite:
5372 case LibFunc::sqrtl_finite:
5373 if (visitUnaryFloatCall(I, ISD::FSQRT))
5376 case LibFunc::floor:
5377 case LibFunc::floorf:
5378 case LibFunc::floorl:
5379 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5382 case LibFunc::nearbyint:
5383 case LibFunc::nearbyintf:
5384 case LibFunc::nearbyintl:
5385 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5389 case LibFunc::ceilf:
5390 case LibFunc::ceill:
5391 if (visitUnaryFloatCall(I, ISD::FCEIL))
5395 case LibFunc::rintf:
5396 case LibFunc::rintl:
5397 if (visitUnaryFloatCall(I, ISD::FRINT))
5400 case LibFunc::round:
5401 case LibFunc::roundf:
5402 case LibFunc::roundl:
5403 if (visitUnaryFloatCall(I, ISD::FROUND))
5406 case LibFunc::trunc:
5407 case LibFunc::truncf:
5408 case LibFunc::truncl:
5409 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5413 case LibFunc::log2f:
5414 case LibFunc::log2l:
5415 if (visitUnaryFloatCall(I, ISD::FLOG2))
5419 case LibFunc::exp2f:
5420 case LibFunc::exp2l:
5421 if (visitUnaryFloatCall(I, ISD::FEXP2))
5424 case LibFunc::memcmp:
5425 if (visitMemCmpCall(I))
5428 case LibFunc::memchr:
5429 if (visitMemChrCall(I))
5432 case LibFunc::strcpy:
5433 if (visitStrCpyCall(I, false))
5436 case LibFunc::stpcpy:
5437 if (visitStrCpyCall(I, true))
5440 case LibFunc::strcmp:
5441 if (visitStrCmpCall(I))
5444 case LibFunc::strlen:
5445 if (visitStrLenCall(I))
5448 case LibFunc::strnlen:
5449 if (visitStrNLenCall(I))
5458 Callee = getValue(I.getCalledValue());
5460 Callee = DAG.getExternalSymbol(RenameFn,
5461 DAG.getTargetLoweringInfo().getPointerTy());
5463 // Check if we can potentially perform a tail call. More detailed checking is
5464 // be done within LowerCallTo, after more information about the call is known.
5465 LowerCallTo(&I, Callee, I.isTailCall());
5470 /// AsmOperandInfo - This contains information for each constraint that we are
5472 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5474 /// CallOperand - If this is the result output operand or a clobber
5475 /// this is null, otherwise it is the incoming operand to the CallInst.
5476 /// This gets modified as the asm is processed.
5477 SDValue CallOperand;
5479 /// AssignedRegs - If this is a register or register class operand, this
5480 /// contains the set of register corresponding to the operand.
5481 RegsForValue AssignedRegs;
5483 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5484 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5487 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5488 /// corresponds to. If there is no Value* for this operand, it returns
5490 EVT getCallOperandValEVT(LLVMContext &Context,
5491 const TargetLowering &TLI,
5492 const DataLayout *DL) const {
5493 if (!CallOperandVal) return MVT::Other;
5495 if (isa<BasicBlock>(CallOperandVal))
5496 return TLI.getPointerTy();
5498 llvm::Type *OpTy = CallOperandVal->getType();
5500 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5501 // If this is an indirect operand, the operand is a pointer to the
5504 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5506 report_fatal_error("Indirect operand for inline asm not a pointer!");
5507 OpTy = PtrTy->getElementType();
5510 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5511 if (StructType *STy = dyn_cast<StructType>(OpTy))
5512 if (STy->getNumElements() == 1)
5513 OpTy = STy->getElementType(0);
5515 // If OpTy is not a single value, it may be a struct/union that we
5516 // can tile with integers.
5517 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5518 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
5527 OpTy = IntegerType::get(Context, BitSize);
5532 return TLI.getValueType(OpTy, true);
5536 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5538 } // end anonymous namespace
5540 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5541 /// specified operand. We prefer to assign virtual registers, to allow the
5542 /// register allocator to handle the assignment process. However, if the asm
5543 /// uses features that we can't model on machineinstrs, we have SDISel do the
5544 /// allocation. This produces generally horrible, but correct, code.
5546 /// OpInfo describes the operand.
5548 static void GetRegistersForValue(SelectionDAG &DAG,
5549 const TargetLowering &TLI,
5551 SDISelAsmOperandInfo &OpInfo) {
5552 LLVMContext &Context = *DAG.getContext();
5554 MachineFunction &MF = DAG.getMachineFunction();
5555 SmallVector<unsigned, 4> Regs;
5557 // If this is a constraint for a single physreg, or a constraint for a
5558 // register class, find it.
5559 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5560 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5561 OpInfo.ConstraintCode,
5562 OpInfo.ConstraintVT);
5564 unsigned NumRegs = 1;
5565 if (OpInfo.ConstraintVT != MVT::Other) {
5566 // If this is a FP input in an integer register (or visa versa) insert a bit
5567 // cast of the input value. More generally, handle any case where the input
5568 // value disagrees with the register class we plan to stick this in.
5569 if (OpInfo.Type == InlineAsm::isInput &&
5570 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5571 // Try to convert to the first EVT that the reg class contains. If the
5572 // types are identical size, use a bitcast to convert (e.g. two differing
5574 MVT RegVT = *PhysReg.second->vt_begin();
5575 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5576 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5577 RegVT, OpInfo.CallOperand);
5578 OpInfo.ConstraintVT = RegVT;
5579 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5580 // If the input is a FP value and we want it in FP registers, do a
5581 // bitcast to the corresponding integer type. This turns an f64 value
5582 // into i64, which can be passed with two i32 values on a 32-bit
5584 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5585 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5586 RegVT, OpInfo.CallOperand);
5587 OpInfo.ConstraintVT = RegVT;
5591 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5595 EVT ValueVT = OpInfo.ConstraintVT;
5597 // If this is a constraint for a specific physical register, like {r17},
5599 if (unsigned AssignedReg = PhysReg.first) {
5600 const TargetRegisterClass *RC = PhysReg.second;
5601 if (OpInfo.ConstraintVT == MVT::Other)
5602 ValueVT = *RC->vt_begin();
5604 // Get the actual register value type. This is important, because the user
5605 // may have asked for (e.g.) the AX register in i32 type. We need to
5606 // remember that AX is actually i16 to get the right extension.
5607 RegVT = *RC->vt_begin();
5609 // This is a explicit reference to a physical register.
5610 Regs.push_back(AssignedReg);
5612 // If this is an expanded reference, add the rest of the regs to Regs.
5614 TargetRegisterClass::iterator I = RC->begin();
5615 for (; *I != AssignedReg; ++I)
5616 assert(I != RC->end() && "Didn't find reg!");
5618 // Already added the first reg.
5620 for (; NumRegs; --NumRegs, ++I) {
5621 assert(I != RC->end() && "Ran out of registers to allocate!");
5626 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5630 // Otherwise, if this was a reference to an LLVM register class, create vregs
5631 // for this reference.
5632 if (const TargetRegisterClass *RC = PhysReg.second) {
5633 RegVT = *RC->vt_begin();
5634 if (OpInfo.ConstraintVT == MVT::Other)
5637 // Create the appropriate number of virtual registers.
5638 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5639 for (; NumRegs; --NumRegs)
5640 Regs.push_back(RegInfo.createVirtualRegister(RC));
5642 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5646 // Otherwise, we couldn't allocate enough registers for this.
5649 /// visitInlineAsm - Handle a call to an InlineAsm object.
5651 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5652 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5654 /// ConstraintOperands - Information about all of the constraints.
5655 SDISelAsmOperandInfoVector ConstraintOperands;
5657 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5658 TargetLowering::AsmOperandInfoVector TargetConstraints =
5659 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
5661 bool hasMemory = false;
5663 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5664 unsigned ResNo = 0; // ResNo - The result number of the next output.
5665 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5666 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5667 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5669 MVT OpVT = MVT::Other;
5671 // Compute the value type for each operand.
5672 switch (OpInfo.Type) {
5673 case InlineAsm::isOutput:
5674 // Indirect outputs just consume an argument.
5675 if (OpInfo.isIndirect) {
5676 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5680 // The return value of the call is this value. As such, there is no
5681 // corresponding argument.
5682 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5683 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5684 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5686 assert(ResNo == 0 && "Asm only has one result!");
5687 OpVT = TLI.getSimpleValueType(CS.getType());
5691 case InlineAsm::isInput:
5692 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5694 case InlineAsm::isClobber:
5699 // If this is an input or an indirect output, process the call argument.
5700 // BasicBlocks are labels, currently appearing only in asm's.
5701 if (OpInfo.CallOperandVal) {
5702 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5703 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5705 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5709 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
5712 OpInfo.ConstraintVT = OpVT;
5714 // Indirect operand accesses access memory.
5715 if (OpInfo.isIndirect)
5718 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5719 TargetLowering::ConstraintType
5720 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5721 if (CType == TargetLowering::C_Memory) {
5729 SDValue Chain, Flag;
5731 // We won't need to flush pending loads if this asm doesn't touch
5732 // memory and is nonvolatile.
5733 if (hasMemory || IA->hasSideEffects())
5736 Chain = DAG.getRoot();
5738 // Second pass over the constraints: compute which constraint option to use
5739 // and assign registers to constraints that want a specific physreg.
5740 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5741 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5743 // If this is an output operand with a matching input operand, look up the
5744 // matching input. If their types mismatch, e.g. one is an integer, the
5745 // other is floating point, or their sizes are different, flag it as an
5747 if (OpInfo.hasMatchingInput()) {
5748 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5750 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5751 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5752 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5753 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5754 OpInfo.ConstraintVT);
5755 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5756 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5757 Input.ConstraintVT);
5758 if ((OpInfo.ConstraintVT.isInteger() !=
5759 Input.ConstraintVT.isInteger()) ||
5760 (MatchRC.second != InputRC.second)) {
5761 report_fatal_error("Unsupported asm: input constraint"
5762 " with a matching output constraint of"
5763 " incompatible type!");
5765 Input.ConstraintVT = OpInfo.ConstraintVT;
5769 // Compute the constraint code and ConstraintType to use.
5770 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5772 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5773 OpInfo.Type == InlineAsm::isClobber)
5776 // If this is a memory input, and if the operand is not indirect, do what we
5777 // need to to provide an address for the memory input.
5778 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5779 !OpInfo.isIndirect) {
5780 assert((OpInfo.isMultipleAlternative ||
5781 (OpInfo.Type == InlineAsm::isInput)) &&
5782 "Can only indirectify direct input operands!");
5784 // Memory operands really want the address of the value. If we don't have
5785 // an indirect input, put it in the constpool if we can, otherwise spill
5786 // it to a stack slot.
5787 // TODO: This isn't quite right. We need to handle these according to
5788 // the addressing mode that the constraint wants. Also, this may take
5789 // an additional register for the computation and we don't want that
5792 // If the operand is a float, integer, or vector constant, spill to a
5793 // constant pool entry to get its address.
5794 const Value *OpVal = OpInfo.CallOperandVal;
5795 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5796 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5797 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5798 TLI.getPointerTy());
5800 // Otherwise, create a stack slot and emit a store to it before the
5802 Type *Ty = OpVal->getType();
5803 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5804 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5805 MachineFunction &MF = DAG.getMachineFunction();
5806 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5807 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5808 Chain = DAG.getStore(Chain, getCurSDLoc(),
5809 OpInfo.CallOperand, StackSlot,
5810 MachinePointerInfo::getFixedStack(SSFI),
5812 OpInfo.CallOperand = StackSlot;
5815 // There is no longer a Value* corresponding to this operand.
5816 OpInfo.CallOperandVal = nullptr;
5818 // It is now an indirect operand.
5819 OpInfo.isIndirect = true;
5822 // If this constraint is for a specific register, allocate it before
5824 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5825 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5828 // Second pass - Loop over all of the operands, assigning virtual or physregs
5829 // to register class operands.
5830 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5831 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5833 // C_Register operands have already been allocated, Other/Memory don't need
5835 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5836 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5839 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5840 std::vector<SDValue> AsmNodeOperands;
5841 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5842 AsmNodeOperands.push_back(
5843 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5844 TLI.getPointerTy()));
5846 // If we have a !srcloc metadata node associated with it, we want to attach
5847 // this to the ultimately generated inline asm machineinstr. To do this, we
5848 // pass in the third operand as this (potentially null) inline asm MDNode.
5849 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5850 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5852 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
5853 // bits as operand 3.
5854 unsigned ExtraInfo = 0;
5855 if (IA->hasSideEffects())
5856 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5857 if (IA->isAlignStack())
5858 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5859 // Set the asm dialect.
5860 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
5862 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
5863 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5864 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
5866 // Compute the constraint code and ConstraintType to use.
5867 TLI.ComputeConstraintToUse(OpInfo, SDValue());
5869 // Ideally, we would only check against memory constraints. However, the
5870 // meaning of an other constraint can be target-specific and we can't easily
5871 // reason about it. Therefore, be conservative and set MayLoad/MayStore
5872 // for other constriants as well.
5873 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
5874 OpInfo.ConstraintType == TargetLowering::C_Other) {
5875 if (OpInfo.Type == InlineAsm::isInput)
5876 ExtraInfo |= InlineAsm::Extra_MayLoad;
5877 else if (OpInfo.Type == InlineAsm::isOutput)
5878 ExtraInfo |= InlineAsm::Extra_MayStore;
5879 else if (OpInfo.Type == InlineAsm::isClobber)
5880 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
5884 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5885 TLI.getPointerTy()));
5887 // Loop over all of the inputs, copying the operand values into the
5888 // appropriate registers and processing the output regs.
5889 RegsForValue RetValRegs;
5891 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5892 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5894 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5895 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5897 switch (OpInfo.Type) {
5898 case InlineAsm::isOutput: {
5899 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5900 OpInfo.ConstraintType != TargetLowering::C_Register) {
5901 // Memory output, or 'other' output (e.g. 'X' constraint).
5902 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5904 unsigned ConstraintID =
5905 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
5906 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
5907 "Failed to convert memory constraint code to constraint id.");
5909 // Add information to the INLINEASM node to know about this output.
5910 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5911 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
5912 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32));
5913 AsmNodeOperands.push_back(OpInfo.CallOperand);
5917 // Otherwise, this is a register or register class output.
5919 // Copy the output from the appropriate register. Find a register that
5921 if (OpInfo.AssignedRegs.Regs.empty()) {
5922 LLVMContext &Ctx = *DAG.getContext();
5923 Ctx.emitError(CS.getInstruction(),
5924 "couldn't allocate output register for constraint '" +
5925 Twine(OpInfo.ConstraintCode) + "'");
5929 // If this is an indirect operand, store through the pointer after the
5931 if (OpInfo.isIndirect) {
5932 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5933 OpInfo.CallOperandVal));
5935 // This is the result value of the call.
5936 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5937 // Concatenate this output onto the outputs list.
5938 RetValRegs.append(OpInfo.AssignedRegs);
5941 // Add information to the INLINEASM node to know that this register is
5944 .AddInlineAsmOperands(OpInfo.isEarlyClobber
5945 ? InlineAsm::Kind_RegDefEarlyClobber
5946 : InlineAsm::Kind_RegDef,
5947 false, 0, DAG, AsmNodeOperands);
5950 case InlineAsm::isInput: {
5951 SDValue InOperandVal = OpInfo.CallOperand;
5953 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5954 // If this is required to match an output register we have already set,
5955 // just use its register.
5956 unsigned OperandNo = OpInfo.getMatchedOperand();
5958 // Scan until we find the definition we already emitted of this operand.
5959 // When we find it, create a RegsForValue operand.
5960 unsigned CurOp = InlineAsm::Op_FirstOperand;
5961 for (; OperandNo; --OperandNo) {
5962 // Advance to the next operand.
5964 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5965 assert((InlineAsm::isRegDefKind(OpFlag) ||
5966 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5967 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5968 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5972 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5973 if (InlineAsm::isRegDefKind(OpFlag) ||
5974 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5975 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5976 if (OpInfo.isIndirect) {
5977 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5978 LLVMContext &Ctx = *DAG.getContext();
5979 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5980 " don't know how to handle tied "
5981 "indirect register inputs");
5985 RegsForValue MatchedRegs;
5986 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5987 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
5988 MatchedRegs.RegVTs.push_back(RegVT);
5989 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5990 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5992 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
5993 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
5995 LLVMContext &Ctx = *DAG.getContext();
5996 Ctx.emitError(CS.getInstruction(),
5997 "inline asm error: This value"
5998 " type register class is not natively supported!");
6002 // Use the produced MatchedRegs object to
6003 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6004 Chain, &Flag, CS.getInstruction());
6005 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6006 true, OpInfo.getMatchedOperand(),
6007 DAG, AsmNodeOperands);
6011 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6012 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6013 "Unexpected number of operands");
6014 // Add information to the INLINEASM node to know about this input.
6015 // See InlineAsm.h isUseOperandTiedToDef.
6016 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6017 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6018 OpInfo.getMatchedOperand());
6019 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6020 TLI.getPointerTy()));
6021 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6025 // Treat indirect 'X' constraint as memory.
6026 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6028 OpInfo.ConstraintType = TargetLowering::C_Memory;
6030 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6031 std::vector<SDValue> Ops;
6032 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6035 LLVMContext &Ctx = *DAG.getContext();
6036 Ctx.emitError(CS.getInstruction(),
6037 "invalid operand for inline asm constraint '" +
6038 Twine(OpInfo.ConstraintCode) + "'");
6042 // Add information to the INLINEASM node to know about this input.
6043 unsigned ResOpType =
6044 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6045 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6046 TLI.getPointerTy()));
6047 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6051 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6052 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6053 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6054 "Memory operands expect pointer values");
6056 unsigned ConstraintID =
6057 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6058 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6059 "Failed to convert memory constraint code to constraint id.");
6061 // Add information to the INLINEASM node to know about this input.
6062 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6063 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6064 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32));
6065 AsmNodeOperands.push_back(InOperandVal);
6069 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6070 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6071 "Unknown constraint type!");
6073 // TODO: Support this.
6074 if (OpInfo.isIndirect) {
6075 LLVMContext &Ctx = *DAG.getContext();
6076 Ctx.emitError(CS.getInstruction(),
6077 "Don't know how to handle indirect register inputs yet "
6078 "for constraint '" +
6079 Twine(OpInfo.ConstraintCode) + "'");
6083 // Copy the input into the appropriate registers.
6084 if (OpInfo.AssignedRegs.Regs.empty()) {
6085 LLVMContext &Ctx = *DAG.getContext();
6086 Ctx.emitError(CS.getInstruction(),
6087 "couldn't allocate input reg for constraint '" +
6088 Twine(OpInfo.ConstraintCode) + "'");
6092 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6093 Chain, &Flag, CS.getInstruction());
6095 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6096 DAG, AsmNodeOperands);
6099 case InlineAsm::isClobber: {
6100 // Add the clobbered value to the operand list, so that the register
6101 // allocator is aware that the physreg got clobbered.
6102 if (!OpInfo.AssignedRegs.Regs.empty())
6103 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6111 // Finish up input operands. Set the input chain and add the flag last.
6112 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6113 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6115 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6116 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6117 Flag = Chain.getValue(1);
6119 // If this asm returns a register value, copy the result from that register
6120 // and set it as the value of the call.
6121 if (!RetValRegs.Regs.empty()) {
6122 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6123 Chain, &Flag, CS.getInstruction());
6125 // FIXME: Why don't we do this for inline asms with MRVs?
6126 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6127 EVT ResultType = TLI.getValueType(CS.getType());
6129 // If any of the results of the inline asm is a vector, it may have the
6130 // wrong width/num elts. This can happen for register classes that can
6131 // contain multiple different value types. The preg or vreg allocated may
6132 // not have the same VT as was expected. Convert it to the right type
6133 // with bit_convert.
6134 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6135 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6138 } else if (ResultType != Val.getValueType() &&
6139 ResultType.isInteger() && Val.getValueType().isInteger()) {
6140 // If a result value was tied to an input value, the computed result may
6141 // have a wider width than the expected result. Extract the relevant
6143 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6146 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6149 setValue(CS.getInstruction(), Val);
6150 // Don't need to use this as a chain in this case.
6151 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6155 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6157 // Process indirect outputs, first output all of the flagged copies out of
6159 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6160 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6161 const Value *Ptr = IndirectStoresToEmit[i].second;
6162 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6164 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6167 // Emit the non-flagged stores from the physregs.
6168 SmallVector<SDValue, 8> OutChains;
6169 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6170 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6171 StoresToEmit[i].first,
6172 getValue(StoresToEmit[i].second),
6173 MachinePointerInfo(StoresToEmit[i].second),
6175 OutChains.push_back(Val);
6178 if (!OutChains.empty())
6179 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6184 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6185 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6186 MVT::Other, getRoot(),
6187 getValue(I.getArgOperand(0)),
6188 DAG.getSrcValue(I.getArgOperand(0))));
6191 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6192 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6193 const DataLayout &DL = *TLI.getDataLayout();
6194 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6195 getRoot(), getValue(I.getOperand(0)),
6196 DAG.getSrcValue(I.getOperand(0)),
6197 DL.getABITypeAlignment(I.getType()));
6199 DAG.setRoot(V.getValue(1));
6202 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6203 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6204 MVT::Other, getRoot(),
6205 getValue(I.getArgOperand(0)),
6206 DAG.getSrcValue(I.getArgOperand(0))));
6209 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6210 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6211 MVT::Other, getRoot(),
6212 getValue(I.getArgOperand(0)),
6213 getValue(I.getArgOperand(1)),
6214 DAG.getSrcValue(I.getArgOperand(0)),
6215 DAG.getSrcValue(I.getArgOperand(1))));
6218 /// \brief Lower an argument list according to the target calling convention.
6220 /// \return A tuple of <return-value, token-chain>
6222 /// This is a helper for lowering intrinsics that follow a target calling
6223 /// convention or require stack pointer adjustment. Only a subset of the
6224 /// intrinsic's operands need to participate in the calling convention.
6225 std::pair<SDValue, SDValue>
6226 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6227 unsigned NumArgs, SDValue Callee,
6229 MachineBasicBlock *LandingPad,
6230 bool IsPatchPoint) {
6231 TargetLowering::ArgListTy Args;
6232 Args.reserve(NumArgs);
6234 // Populate the argument list.
6235 // Attributes for args start at offset 1, after the return attribute.
6236 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6237 ArgI != ArgE; ++ArgI) {
6238 const Value *V = CS->getOperand(ArgI);
6240 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6242 TargetLowering::ArgListEntry Entry;
6243 Entry.Node = getValue(V);
6244 Entry.Ty = V->getType();
6245 Entry.setAttributes(&CS, AttrI);
6246 Args.push_back(Entry);
6249 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6250 TargetLowering::CallLoweringInfo CLI(DAG);
6251 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6252 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6253 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6255 return lowerInvokable(CLI, LandingPad);
6258 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6259 /// or patchpoint target node's operand list.
6261 /// Constants are converted to TargetConstants purely as an optimization to
6262 /// avoid constant materialization and register allocation.
6264 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6265 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6266 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6267 /// address materialization and register allocation, but may also be required
6268 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6269 /// alloca in the entry block, then the runtime may assume that the alloca's
6270 /// StackMap location can be read immediately after compilation and that the
6271 /// location is valid at any point during execution (this is similar to the
6272 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6273 /// only available in a register, then the runtime would need to trap when
6274 /// execution reaches the StackMap in order to read the alloca's location.
6275 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6276 SmallVectorImpl<SDValue> &Ops,
6277 SelectionDAGBuilder &Builder) {
6278 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6279 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6280 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6282 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6284 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6285 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6286 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6288 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6290 Ops.push_back(OpVal);
6294 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6295 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6296 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6297 // [live variables...])
6299 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6301 SDValue Chain, InFlag, Callee, NullPtr;
6302 SmallVector<SDValue, 32> Ops;
6304 SDLoc DL = getCurSDLoc();
6305 Callee = getValue(CI.getCalledValue());
6306 NullPtr = DAG.getIntPtrConstant(0, true);
6308 // The stackmap intrinsic only records the live variables (the arguemnts
6309 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6310 // intrinsic, this won't be lowered to a function call. This means we don't
6311 // have to worry about calling conventions and target specific lowering code.
6312 // Instead we perform the call lowering right here.
6314 // chain, flag = CALLSEQ_START(chain, 0)
6315 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6316 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6318 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6319 InFlag = Chain.getValue(1);
6321 // Add the <id> and <numBytes> constants.
6322 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6323 Ops.push_back(DAG.getTargetConstant(
6324 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6325 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6326 Ops.push_back(DAG.getTargetConstant(
6327 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6329 // Push live variables for the stack map.
6330 addStackMapLiveVars(&CI, 2, Ops, *this);
6332 // We are not pushing any register mask info here on the operands list,
6333 // because the stackmap doesn't clobber anything.
6335 // Push the chain and the glue flag.
6336 Ops.push_back(Chain);
6337 Ops.push_back(InFlag);
6339 // Create the STACKMAP node.
6340 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6341 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6342 Chain = SDValue(SM, 0);
6343 InFlag = Chain.getValue(1);
6345 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6347 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6349 // Set the root to the target-lowered call chain.
6352 // Inform the Frame Information that we have a stackmap in this function.
6353 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6356 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6357 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6358 MachineBasicBlock *LandingPad) {
6359 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6364 // [live variables...])
6366 CallingConv::ID CC = CS.getCallingConv();
6367 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6368 bool HasDef = !CS->getType()->isVoidTy();
6369 SDValue Callee = getValue(CS->getOperand(2)); // <target>
6371 // Get the real number of arguments participating in the call <numArgs>
6372 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6373 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6375 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6376 // Intrinsics include all meta-operands up to but not including CC.
6377 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6378 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6379 "Not enough arguments provided to the patchpoint intrinsic");
6381 // For AnyRegCC the arguments are lowered later on manually.
6382 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6383 std::pair<SDValue, SDValue> Result =
6384 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
6387 SDNode *CallEnd = Result.second.getNode();
6388 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6389 CallEnd = CallEnd->getOperand(0).getNode();
6391 /// Get a call instruction from the call sequence chain.
6392 /// Tail calls are not allowed.
6393 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6394 "Expected a callseq node.");
6395 SDNode *Call = CallEnd->getOperand(0).getNode();
6396 bool HasGlue = Call->getGluedNode();
6398 // Replace the target specific call node with the patchable intrinsic.
6399 SmallVector<SDValue, 8> Ops;
6401 // Add the <id> and <numBytes> constants.
6402 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6403 Ops.push_back(DAG.getTargetConstant(
6404 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6405 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6406 Ops.push_back(DAG.getTargetConstant(
6407 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6409 // Assume that the Callee is a constant address.
6410 // FIXME: handle function symbols in the future.
6412 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
6413 /*isTarget=*/true));
6415 // Adjust <numArgs> to account for any arguments that have been passed on the
6417 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6418 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6419 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6420 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
6422 // Add the calling convention
6423 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
6425 // Add the arguments we omitted previously. The register allocator should
6426 // place these in any free register.
6428 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6429 Ops.push_back(getValue(CS.getArgument(i)));
6431 // Push the arguments from the call instruction up to the register mask.
6432 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6433 Ops.append(Call->op_begin() + 2, e);
6435 // Push live variables for the stack map.
6436 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
6438 // Push the register mask info.
6440 Ops.push_back(*(Call->op_end()-2));
6442 Ops.push_back(*(Call->op_end()-1));
6444 // Push the chain (this is originally the first operand of the call, but
6445 // becomes now the last or second to last operand).
6446 Ops.push_back(*(Call->op_begin()));
6448 // Push the glue flag (last operand).
6450 Ops.push_back(*(Call->op_end()-1));
6453 if (IsAnyRegCC && HasDef) {
6454 // Create the return types based on the intrinsic definition
6455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6456 SmallVector<EVT, 3> ValueVTs;
6457 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
6458 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6460 // There is always a chain and a glue type at the end
6461 ValueVTs.push_back(MVT::Other);
6462 ValueVTs.push_back(MVT::Glue);
6463 NodeTys = DAG.getVTList(ValueVTs);
6465 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6467 // Replace the target specific call node with a PATCHPOINT node.
6468 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6469 getCurSDLoc(), NodeTys, Ops);
6471 // Update the NodeMap.
6474 setValue(CS.getInstruction(), SDValue(MN, 0));
6476 setValue(CS.getInstruction(), Result.first);
6479 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6480 // call sequence. Furthermore the location of the chain and glue can change
6481 // when the AnyReg calling convention is used and the intrinsic returns a
6483 if (IsAnyRegCC && HasDef) {
6484 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6485 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6486 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6488 DAG.ReplaceAllUsesWith(Call, MN);
6489 DAG.DeleteNode(Call);
6491 // Inform the Frame Information that we have a patchpoint in this function.
6492 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6495 /// Returns an AttributeSet representing the attributes applied to the return
6496 /// value of the given call.
6497 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6498 SmallVector<Attribute::AttrKind, 2> Attrs;
6500 Attrs.push_back(Attribute::SExt);
6502 Attrs.push_back(Attribute::ZExt);
6504 Attrs.push_back(Attribute::InReg);
6506 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6510 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6511 /// implementation, which just calls LowerCall.
6512 /// FIXME: When all targets are
6513 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6514 std::pair<SDValue, SDValue>
6515 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6516 // Handle the incoming return values from the call.
6518 Type *OrigRetTy = CLI.RetTy;
6519 SmallVector<EVT, 4> RetTys;
6520 SmallVector<uint64_t, 4> Offsets;
6521 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
6523 SmallVector<ISD::OutputArg, 4> Outs;
6524 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
6526 bool CanLowerReturn =
6527 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6528 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6530 SDValue DemoteStackSlot;
6531 int DemoteStackIdx = -100;
6532 if (!CanLowerReturn) {
6533 // FIXME: equivalent assert?
6534 // assert(!CS.hasInAllocaArgument() &&
6535 // "sret demotion is incompatible with inalloca");
6536 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
6537 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
6538 MachineFunction &MF = CLI.DAG.getMachineFunction();
6539 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6540 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6542 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
6544 Entry.Node = DemoteStackSlot;
6545 Entry.Ty = StackSlotPtrType;
6546 Entry.isSExt = false;
6547 Entry.isZExt = false;
6548 Entry.isInReg = false;
6549 Entry.isSRet = true;
6550 Entry.isNest = false;
6551 Entry.isByVal = false;
6552 Entry.isReturned = false;
6553 Entry.Alignment = Align;
6554 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6555 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6557 // sret demotion isn't compatible with tail-calls, since the sret argument
6558 // points into the callers stack frame.
6559 CLI.IsTailCall = false;
6561 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6563 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6564 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6565 for (unsigned i = 0; i != NumRegs; ++i) {
6566 ISD::InputArg MyFlags;
6567 MyFlags.VT = RegisterVT;
6569 MyFlags.Used = CLI.IsReturnValueUsed;
6571 MyFlags.Flags.setSExt();
6573 MyFlags.Flags.setZExt();
6575 MyFlags.Flags.setInReg();
6576 CLI.Ins.push_back(MyFlags);
6581 // Handle all of the outgoing arguments.
6583 CLI.OutVals.clear();
6584 ArgListTy &Args = CLI.getArgs();
6585 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6586 SmallVector<EVT, 4> ValueVTs;
6587 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6588 Type *FinalType = Args[i].Ty;
6589 if (Args[i].isByVal)
6590 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6591 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6592 FinalType, CLI.CallConv, CLI.IsVarArg);
6593 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6595 EVT VT = ValueVTs[Value];
6596 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6597 SDValue Op = SDValue(Args[i].Node.getNode(),
6598 Args[i].Node.getResNo() + Value);
6599 ISD::ArgFlagsTy Flags;
6600 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
6606 if (Args[i].isInReg)
6610 if (Args[i].isByVal)
6612 if (Args[i].isInAlloca) {
6613 Flags.setInAlloca();
6614 // Set the byval flag for CCAssignFn callbacks that don't know about
6615 // inalloca. This way we can know how many bytes we should've allocated
6616 // and how many bytes a callee cleanup function will pop. If we port
6617 // inalloca to more targets, we'll have to add custom inalloca handling
6618 // in the various CC lowering callbacks.
6621 if (Args[i].isByVal || Args[i].isInAlloca) {
6622 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6623 Type *ElementTy = Ty->getElementType();
6624 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6625 // For ByVal, alignment should come from FE. BE will guess if this
6626 // info is not there but there are cases it cannot get right.
6627 unsigned FrameAlign;
6628 if (Args[i].Alignment)
6629 FrameAlign = Args[i].Alignment;
6631 FrameAlign = getByValTypeAlignment(ElementTy);
6632 Flags.setByValAlign(FrameAlign);
6637 Flags.setInConsecutiveRegs();
6638 Flags.setOrigAlign(OriginalAlignment);
6640 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6641 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6642 SmallVector<SDValue, 4> Parts(NumParts);
6643 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6646 ExtendKind = ISD::SIGN_EXTEND;
6647 else if (Args[i].isZExt)
6648 ExtendKind = ISD::ZERO_EXTEND;
6650 // Conservatively only handle 'returned' on non-vectors for now
6651 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6652 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6653 "unexpected use of 'returned'");
6654 // Before passing 'returned' to the target lowering code, ensure that
6655 // either the register MVT and the actual EVT are the same size or that
6656 // the return value and argument are extended in the same way; in these
6657 // cases it's safe to pass the argument register value unchanged as the
6658 // return register value (although it's at the target's option whether
6660 // TODO: allow code generation to take advantage of partially preserved
6661 // registers rather than clobbering the entire register when the
6662 // parameter extension method is not compatible with the return
6664 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6665 (ExtendKind != ISD::ANY_EXTEND &&
6666 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6667 Flags.setReturned();
6670 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6671 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6673 for (unsigned j = 0; j != NumParts; ++j) {
6674 // if it isn't first piece, alignment must be 1
6675 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6676 i < CLI.NumFixedArgs,
6677 i, j*Parts[j].getValueType().getStoreSize());
6678 if (NumParts > 1 && j == 0)
6679 MyFlags.Flags.setSplit();
6681 MyFlags.Flags.setOrigAlign(1);
6683 CLI.Outs.push_back(MyFlags);
6684 CLI.OutVals.push_back(Parts[j]);
6687 if (NeedsRegBlock && Value == NumValues - 1)
6688 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6692 SmallVector<SDValue, 4> InVals;
6693 CLI.Chain = LowerCall(CLI, InVals);
6695 // Verify that the target's LowerCall behaved as expected.
6696 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6697 "LowerCall didn't return a valid chain!");
6698 assert((!CLI.IsTailCall || InVals.empty()) &&
6699 "LowerCall emitted a return value for a tail call!");
6700 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6701 "LowerCall didn't emit the correct number of values!");
6703 // For a tail call, the return value is merely live-out and there aren't
6704 // any nodes in the DAG representing it. Return a special value to
6705 // indicate that a tail call has been emitted and no more Instructions
6706 // should be processed in the current block.
6707 if (CLI.IsTailCall) {
6708 CLI.DAG.setRoot(CLI.Chain);
6709 return std::make_pair(SDValue(), SDValue());
6712 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6713 assert(InVals[i].getNode() &&
6714 "LowerCall emitted a null value!");
6715 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6716 "LowerCall emitted a value with the wrong type!");
6719 SmallVector<SDValue, 4> ReturnValues;
6720 if (!CanLowerReturn) {
6721 // The instruction result is the result of loading from the
6722 // hidden sret parameter.
6723 SmallVector<EVT, 1> PVTs;
6724 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6726 ComputeValueVTs(*this, PtrRetTy, PVTs);
6727 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6728 EVT PtrVT = PVTs[0];
6730 unsigned NumValues = RetTys.size();
6731 ReturnValues.resize(NumValues);
6732 SmallVector<SDValue, 4> Chains(NumValues);
6734 for (unsigned i = 0; i < NumValues; ++i) {
6735 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6736 CLI.DAG.getConstant(Offsets[i], PtrVT));
6737 SDValue L = CLI.DAG.getLoad(
6738 RetTys[i], CLI.DL, CLI.Chain, Add,
6739 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6741 ReturnValues[i] = L;
6742 Chains[i] = L.getValue(1);
6745 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6747 // Collect the legal value parts into potentially illegal values
6748 // that correspond to the original function's return values.
6749 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6751 AssertOp = ISD::AssertSext;
6752 else if (CLI.RetZExt)
6753 AssertOp = ISD::AssertZext;
6754 unsigned CurReg = 0;
6755 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6757 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6758 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6760 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6761 NumRegs, RegisterVT, VT, nullptr,
6766 // For a function returning void, there is no return value. We can't create
6767 // such a node, so we just return a null return value in that case. In
6768 // that case, nothing will actually look at the value.
6769 if (ReturnValues.empty())
6770 return std::make_pair(SDValue(), CLI.Chain);
6773 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6774 CLI.DAG.getVTList(RetTys), ReturnValues);
6775 return std::make_pair(Res, CLI.Chain);
6778 void TargetLowering::LowerOperationWrapper(SDNode *N,
6779 SmallVectorImpl<SDValue> &Results,
6780 SelectionDAG &DAG) const {
6781 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6783 Results.push_back(Res);
6786 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6787 llvm_unreachable("LowerOperation not implemented for this target!");
6791 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6792 SDValue Op = getNonRegisterValue(V);
6793 assert((Op.getOpcode() != ISD::CopyFromReg ||
6794 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6795 "Copy from a reg to the same reg!");
6796 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6798 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6799 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6800 SDValue Chain = DAG.getEntryNode();
6802 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
6803 FuncInfo.PreferredExtendType.end())
6805 : FuncInfo.PreferredExtendType[V];
6806 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
6807 PendingExports.push_back(Chain);
6810 #include "llvm/CodeGen/SelectionDAGISel.h"
6812 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6813 /// entry block, return true. This includes arguments used by switches, since
6814 /// the switch may expand into multiple basic blocks.
6815 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6816 // With FastISel active, we may be splitting blocks, so force creation
6817 // of virtual registers for all non-dead arguments.
6819 return A->use_empty();
6821 const BasicBlock *Entry = A->getParent()->begin();
6822 for (const User *U : A->users())
6823 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6824 return false; // Use not in entry block.
6829 void SelectionDAGISel::LowerArguments(const Function &F) {
6830 SelectionDAG &DAG = SDB->DAG;
6831 SDLoc dl = SDB->getCurSDLoc();
6832 const DataLayout *DL = TLI->getDataLayout();
6833 SmallVector<ISD::InputArg, 16> Ins;
6835 if (!FuncInfo->CanLowerReturn) {
6836 // Put in an sret pointer parameter before all the other parameters.
6837 SmallVector<EVT, 1> ValueVTs;
6838 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6840 // NOTE: Assuming that a pointer will never break down to more than one VT
6842 ISD::ArgFlagsTy Flags;
6844 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
6845 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
6846 ISD::InputArg::NoArgIndex, 0);
6847 Ins.push_back(RetArg);
6850 // Set up the incoming argument description vector.
6852 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6853 I != E; ++I, ++Idx) {
6854 SmallVector<EVT, 4> ValueVTs;
6855 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
6856 bool isArgValueUsed = !I->use_empty();
6857 unsigned PartBase = 0;
6858 Type *FinalType = I->getType();
6859 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
6860 FinalType = cast<PointerType>(FinalType)->getElementType();
6861 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
6862 FinalType, F.getCallingConv(), F.isVarArg());
6863 for (unsigned Value = 0, NumValues = ValueVTs.size();
6864 Value != NumValues; ++Value) {
6865 EVT VT = ValueVTs[Value];
6866 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6867 ISD::ArgFlagsTy Flags;
6868 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
6870 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6872 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6874 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
6876 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
6878 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
6880 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
6881 Flags.setInAlloca();
6882 // Set the byval flag for CCAssignFn callbacks that don't know about
6883 // inalloca. This way we can know how many bytes we should've allocated
6884 // and how many bytes a callee cleanup function will pop. If we port
6885 // inalloca to more targets, we'll have to add custom inalloca handling
6886 // in the various CC lowering callbacks.
6889 if (Flags.isByVal() || Flags.isInAlloca()) {
6890 PointerType *Ty = cast<PointerType>(I->getType());
6891 Type *ElementTy = Ty->getElementType();
6892 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
6893 // For ByVal, alignment should be passed from FE. BE will guess if
6894 // this info is not there but there are cases it cannot get right.
6895 unsigned FrameAlign;
6896 if (F.getParamAlignment(Idx))
6897 FrameAlign = F.getParamAlignment(Idx);
6899 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
6900 Flags.setByValAlign(FrameAlign);
6902 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
6905 Flags.setInConsecutiveRegs();
6906 Flags.setOrigAlign(OriginalAlignment);
6908 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6909 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
6910 for (unsigned i = 0; i != NumRegs; ++i) {
6911 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
6912 Idx-1, PartBase+i*RegisterVT.getStoreSize());
6913 if (NumRegs > 1 && i == 0)
6914 MyFlags.Flags.setSplit();
6915 // if it isn't first piece, alignment must be 1
6917 MyFlags.Flags.setOrigAlign(1);
6918 Ins.push_back(MyFlags);
6920 if (NeedsRegBlock && Value == NumValues - 1)
6921 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
6922 PartBase += VT.getStoreSize();
6926 // Call the target to set up the argument values.
6927 SmallVector<SDValue, 8> InVals;
6928 SDValue NewRoot = TLI->LowerFormalArguments(
6929 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
6931 // Verify that the target's LowerFormalArguments behaved as expected.
6932 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6933 "LowerFormalArguments didn't return a valid chain!");
6934 assert(InVals.size() == Ins.size() &&
6935 "LowerFormalArguments didn't emit the correct number of values!");
6937 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6938 assert(InVals[i].getNode() &&
6939 "LowerFormalArguments emitted a null value!");
6940 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6941 "LowerFormalArguments emitted a value with the wrong type!");
6945 // Update the DAG with the new chain value resulting from argument lowering.
6946 DAG.setRoot(NewRoot);
6948 // Set up the argument values.
6951 if (!FuncInfo->CanLowerReturn) {
6952 // Create a virtual register for the sret pointer, and put in a copy
6953 // from the sret argument into it.
6954 SmallVector<EVT, 1> ValueVTs;
6955 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6956 MVT VT = ValueVTs[0].getSimpleVT();
6957 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6958 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6959 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6960 RegVT, VT, nullptr, AssertOp);
6962 MachineFunction& MF = SDB->DAG.getMachineFunction();
6963 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6964 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
6965 FuncInfo->DemoteRegister = SRetReg;
6967 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
6968 DAG.setRoot(NewRoot);
6970 // i indexes lowered arguments. Bump it past the hidden sret argument.
6971 // Idx indexes LLVM arguments. Don't touch it.
6975 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6977 SmallVector<SDValue, 4> ArgValues;
6978 SmallVector<EVT, 4> ValueVTs;
6979 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
6980 unsigned NumValues = ValueVTs.size();
6982 // If this argument is unused then remember its value. It is used to generate
6983 // debugging information.
6984 if (I->use_empty() && NumValues) {
6985 SDB->setUnusedArgValue(I, InVals[i]);
6987 // Also remember any frame index for use in FastISel.
6988 if (FrameIndexSDNode *FI =
6989 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
6990 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6993 for (unsigned Val = 0; Val != NumValues; ++Val) {
6994 EVT VT = ValueVTs[Val];
6995 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6996 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
6998 if (!I->use_empty()) {
6999 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7000 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7001 AssertOp = ISD::AssertSext;
7002 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7003 AssertOp = ISD::AssertZext;
7005 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7006 NumParts, PartVT, VT,
7007 nullptr, AssertOp));
7013 // We don't need to do anything else for unused arguments.
7014 if (ArgValues.empty())
7017 // Note down frame index.
7018 if (FrameIndexSDNode *FI =
7019 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7020 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7022 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7023 SDB->getCurSDLoc());
7025 SDB->setValue(I, Res);
7026 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7027 if (LoadSDNode *LNode =
7028 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7029 if (FrameIndexSDNode *FI =
7030 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7031 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7034 // If this argument is live outside of the entry block, insert a copy from
7035 // wherever we got it to the vreg that other BB's will reference it as.
7036 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7037 // If we can, though, try to skip creating an unnecessary vreg.
7038 // FIXME: This isn't very clean... it would be nice to make this more
7039 // general. It's also subtly incompatible with the hacks FastISel
7041 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7042 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7043 FuncInfo->ValueMap[I] = Reg;
7047 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7048 FuncInfo->InitializeRegForValue(I);
7049 SDB->CopyToExportRegsIfNeeded(I);
7053 assert(i == InVals.size() && "Argument register count mismatch!");
7055 // Finally, if the target has anything special to do, allow it to do so.
7056 EmitFunctionEntryCode();
7059 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7060 /// ensure constants are generated when needed. Remember the virtual registers
7061 /// that need to be added to the Machine PHI nodes as input. We cannot just
7062 /// directly add them, because expansion might result in multiple MBB's for one
7063 /// BB. As such, the start of the BB might correspond to a different MBB than
7067 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7068 const TerminatorInst *TI = LLVMBB->getTerminator();
7070 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7072 // Check PHI nodes in successors that expect a value to be available from this
7074 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7075 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7076 if (!isa<PHINode>(SuccBB->begin())) continue;
7077 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7079 // If this terminator has multiple identical successors (common for
7080 // switches), only handle each succ once.
7081 if (!SuccsHandled.insert(SuccMBB).second)
7084 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7086 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7087 // nodes and Machine PHI nodes, but the incoming operands have not been
7089 for (BasicBlock::const_iterator I = SuccBB->begin();
7090 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7091 // Ignore dead phi's.
7092 if (PN->use_empty()) continue;
7095 if (PN->getType()->isEmptyTy())
7099 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7101 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7102 unsigned &RegOut = ConstantsOut[C];
7104 RegOut = FuncInfo.CreateRegs(C->getType());
7105 CopyValueToVirtualRegister(C, RegOut);
7109 DenseMap<const Value *, unsigned>::iterator I =
7110 FuncInfo.ValueMap.find(PHIOp);
7111 if (I != FuncInfo.ValueMap.end())
7114 assert(isa<AllocaInst>(PHIOp) &&
7115 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7116 "Didn't codegen value into a register!??");
7117 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7118 CopyValueToVirtualRegister(PHIOp, Reg);
7122 // Remember that this register needs to added to the machine PHI node as
7123 // the input for this MBB.
7124 SmallVector<EVT, 4> ValueVTs;
7125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7126 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7127 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7128 EVT VT = ValueVTs[vti];
7129 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7130 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7131 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7132 Reg += NumRegisters;
7137 ConstantsOut.clear();
7140 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7143 SelectionDAGBuilder::StackProtectorDescriptor::
7144 AddSuccessorMBB(const BasicBlock *BB,
7145 MachineBasicBlock *ParentMBB,
7147 MachineBasicBlock *SuccMBB) {
7148 // If SuccBB has not been created yet, create it.
7150 MachineFunction *MF = ParentMBB->getParent();
7151 MachineFunction::iterator BBI = ParentMBB;
7152 SuccMBB = MF->CreateMachineBasicBlock(BB);
7153 MF->insert(++BBI, SuccMBB);
7155 // Add it as a successor of ParentMBB.
7156 ParentMBB->addSuccessor(
7157 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7161 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7162 MachineFunction::iterator I = MBB;
7163 if (++I == FuncInfo.MF->end())
7168 /// During lowering new call nodes can be created (such as memset, etc.).
7169 /// Those will become new roots of the current DAG, but complications arise
7170 /// when they are tail calls. In such cases, the call lowering will update
7171 /// the root, but the builder still needs to know that a tail call has been
7172 /// lowered in order to avoid generating an additional return.
7173 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7174 // If the node is null, we do have a tail call.
7175 if (MaybeTC.getNode() != nullptr)
7176 DAG.setRoot(MaybeTC);
7181 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7182 unsigned *TotalCases, unsigned First,
7184 assert(Last >= First);
7185 assert(TotalCases[Last] >= TotalCases[First]);
7187 APInt LowCase = Clusters[First].Low->getValue();
7188 APInt HighCase = Clusters[Last].High->getValue();
7189 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7191 // FIXME: A range of consecutive cases has 100% density, but only requires one
7192 // comparison to lower. We should discriminate against such consecutive ranges
7195 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7196 uint64_t Range = Diff + 1;
7199 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7201 assert(NumCases < UINT64_MAX / 100);
7202 assert(Range >= NumCases);
7204 return NumCases * 100 >= Range * MinJumpTableDensity;
7207 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7208 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7209 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7212 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7213 unsigned First, unsigned Last,
7214 const SwitchInst *SI,
7215 MachineBasicBlock *DefaultMBB,
7216 CaseCluster &JTCluster) {
7217 assert(First <= Last);
7219 uint64_t Weight = 0;
7220 unsigned NumCmps = 0;
7221 std::vector<MachineBasicBlock*> Table;
7222 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7223 for (unsigned I = First; I <= Last; ++I) {
7224 assert(Clusters[I].Kind == CC_Range);
7225 Weight += Clusters[I].Weight;
7226 APInt Low = Clusters[I].Low->getValue();
7227 APInt High = Clusters[I].High->getValue();
7228 NumCmps += (Low == High) ? 1 : 2;
7230 // Fill the gap between this and the previous cluster.
7231 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7232 assert(PreviousHigh.slt(Low));
7233 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7234 for (uint64_t J = 0; J < Gap; J++)
7235 Table.push_back(DefaultMBB);
7237 for (APInt X = Low; X.sle(High); ++X)
7238 Table.push_back(Clusters[I].MBB);
7239 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7242 unsigned NumDests = JTWeights.size();
7243 if (isSuitableForBitTests(NumDests, NumCmps,
7244 Clusters[First].Low->getValue(),
7245 Clusters[Last].High->getValue())) {
7246 // Clusters[First..Last] should be lowered as bit tests instead.
7250 // Create the MBB that will load from and jump through the table.
7251 // Note: We create it here, but it's not inserted into the function yet.
7252 MachineFunction *CurMF = FuncInfo.MF;
7253 MachineBasicBlock *JumpTableMBB =
7254 CurMF->CreateMachineBasicBlock(SI->getParent());
7256 // Add successors. Note: use table order for determinism.
7257 SmallPtrSet<MachineBasicBlock *, 8> Done;
7258 for (MachineBasicBlock *Succ : Table) {
7259 if (Done.count(Succ))
7261 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7265 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7266 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7267 ->createJumpTableIndex(Table);
7269 // Set up the jump table info.
7270 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7271 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7272 Clusters[Last].High->getValue(), SI->getCondition(),
7274 JTCases.push_back(JumpTableBlock(JTH, JT));
7276 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7277 JTCases.size() - 1, Weight);
7281 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7282 const SwitchInst *SI,
7283 MachineBasicBlock *DefaultMBB) {
7285 // Clusters must be non-empty, sorted, and only contain Range clusters.
7286 assert(!Clusters.empty());
7287 for (CaseCluster &C : Clusters)
7288 assert(C.Kind == CC_Range);
7289 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7290 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7293 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7294 if (!areJTsAllowed(TLI))
7297 const int64_t N = Clusters.size();
7298 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7300 // Split Clusters into minimum number of dense partitions. The algorithm uses
7301 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7302 // for the Case Statement'" (1994), but builds the MinPartitions array in
7303 // reverse order to make it easier to reconstruct the partitions in ascending
7304 // order. In the choice between two optimal partitionings, it picks the one
7305 // which yields more jump tables.
7307 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7308 SmallVector<unsigned, 8> MinPartitions(N);
7309 // LastElement[i] is the last element of the partition starting at i.
7310 SmallVector<unsigned, 8> LastElement(N);
7311 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7312 SmallVector<unsigned, 8> NumTables(N);
7313 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7314 SmallVector<unsigned, 8> TotalCases(N);
7316 for (unsigned i = 0; i < N; ++i) {
7317 APInt Hi = Clusters[i].High->getValue();
7318 APInt Lo = Clusters[i].Low->getValue();
7319 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7321 TotalCases[i] += TotalCases[i - 1];
7324 // Base case: There is only one way to partition Clusters[N-1].
7325 MinPartitions[N - 1] = 1;
7326 LastElement[N - 1] = N - 1;
7327 assert(MinJumpTableSize > 1);
7328 NumTables[N - 1] = 0;
7330 // Note: loop indexes are signed to avoid underflow.
7331 for (int64_t i = N - 2; i >= 0; i--) {
7332 // Find optimal partitioning of Clusters[i..N-1].
7333 // Baseline: Put Clusters[i] into a partition on its own.
7334 MinPartitions[i] = MinPartitions[i + 1] + 1;
7336 NumTables[i] = NumTables[i + 1];
7338 // Search for a solution that results in fewer partitions.
7339 for (int64_t j = N - 1; j > i; j--) {
7340 // Try building a partition from Clusters[i..j].
7341 if (isDense(Clusters, &TotalCases[0], i, j)) {
7342 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7343 bool IsTable = j - i + 1 >= MinJumpTableSize;
7344 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7346 // If this j leads to fewer partitions, or same number of partitions
7347 // with more lookup tables, it is a better partitioning.
7348 if (NumPartitions < MinPartitions[i] ||
7349 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7350 MinPartitions[i] = NumPartitions;
7352 NumTables[i] = Tables;
7358 // Iterate over the partitions, replacing some with jump tables in-place.
7359 unsigned DstIndex = 0;
7360 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7361 Last = LastElement[First];
7362 assert(Last >= First);
7363 assert(DstIndex <= First);
7364 unsigned NumClusters = Last - First + 1;
7366 CaseCluster JTCluster;
7367 if (NumClusters >= MinJumpTableSize &&
7368 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7369 Clusters[DstIndex++] = JTCluster;
7371 for (unsigned I = First; I <= Last; ++I)
7372 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7375 Clusters.resize(DstIndex);
7378 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7379 // FIXME: Using the pointer type doesn't seem ideal.
7380 uint64_t BW = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7381 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7385 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7388 const APInt &High) {
7389 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7390 // range of cases both require only one branch to lower. Just looking at the
7391 // number of clusters and destinations should be enough to decide whether to
7394 // To lower a range with bit tests, the range must fit the bitwidth of a
7396 if (!rangeFitsInWord(Low, High))
7399 // Decide whether it's profitable to lower this range with bit tests. Each
7400 // destination requires a bit test and branch, and there is an overall range
7401 // check branch. For a small number of clusters, separate comparisons might be
7402 // cheaper, and for many destinations, splitting the range might be better.
7403 return (NumDests == 1 && NumCmps >= 3) ||
7404 (NumDests == 2 && NumCmps >= 5) ||
7405 (NumDests == 3 && NumCmps >= 6);
7408 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7409 unsigned First, unsigned Last,
7410 const SwitchInst *SI,
7411 CaseCluster &BTCluster) {
7412 assert(First <= Last);
7416 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7417 unsigned NumCmps = 0;
7418 for (int64_t I = First; I <= Last; ++I) {
7419 assert(Clusters[I].Kind == CC_Range);
7420 Dests.set(Clusters[I].MBB->getNumber());
7421 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7423 unsigned NumDests = Dests.count();
7425 APInt Low = Clusters[First].Low->getValue();
7426 APInt High = Clusters[Last].High->getValue();
7427 assert(Low.slt(High));
7429 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7435 const int BitWidth =
7436 DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7437 assert((High - Low + 1).sle(BitWidth) && "Case range must fit in bit mask!");
7439 if (Low.isNonNegative() && High.slt(BitWidth)) {
7440 // Optimize the case where all the case values fit in a
7441 // word without having to subtract minValue. In this case,
7442 // we can optimize away the subtraction.
7443 LowBound = APInt::getNullValue(Low.getBitWidth());
7447 CmpRange = High - Low;
7451 uint64_t TotalWeight = 0;
7452 for (unsigned i = First; i <= Last; ++i) {
7453 // Find the CaseBits for this destination.
7455 for (j = 0; j < CBV.size(); ++j)
7456 if (CBV[j].BB == Clusters[i].MBB)
7458 if (j == CBV.size())
7459 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7460 CaseBits *CB = &CBV[j];
7462 // Update Mask, Bits and ExtraWeight.
7463 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7464 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7465 for (uint64_t j = Lo; j <= Hi; ++j) {
7466 CB->Mask |= 1ULL << j;
7469 CB->ExtraWeight += Clusters[i].Weight;
7470 TotalWeight += Clusters[i].Weight;
7474 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7475 // FIXME: Sort by weight.
7476 return a.Bits > b.Bits;
7479 for (auto &CB : CBV) {
7480 MachineBasicBlock *BitTestBB =
7481 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7482 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7484 BitTestCases.push_back(BitTestBlock(LowBound, CmpRange, SI->getCondition(),
7485 -1U, MVT::Other, false, nullptr,
7486 nullptr, std::move(BTI)));
7488 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7489 BitTestCases.size() - 1, TotalWeight);
7493 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7494 const SwitchInst *SI) {
7495 // Partition Clusters into as few subsets as possible, where each subset has a
7496 // range that fits in a machine word and has <= 3 unique destinations.
7499 // Clusters must be sorted and contain Range or JumpTable clusters.
7500 assert(!Clusters.empty());
7501 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7502 for (const CaseCluster &C : Clusters)
7503 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7504 for (unsigned i = 1; i < Clusters.size(); ++i)
7505 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7508 // If target does not have legal shift left, do not emit bit tests at all.
7509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7510 EVT PTy = TLI.getPointerTy();
7511 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7514 int BitWidth = PTy.getSizeInBits();
7515 const int64_t N = Clusters.size();
7517 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7518 SmallVector<unsigned, 8> MinPartitions(N);
7519 // LastElement[i] is the last element of the partition starting at i.
7520 SmallVector<unsigned, 8> LastElement(N);
7522 // FIXME: This might not be the best algorithm for finding bit test clusters.
7524 // Base case: There is only one way to partition Clusters[N-1].
7525 MinPartitions[N - 1] = 1;
7526 LastElement[N - 1] = N - 1;
7528 // Note: loop indexes are signed to avoid underflow.
7529 for (int64_t i = N - 2; i >= 0; --i) {
7530 // Find optimal partitioning of Clusters[i..N-1].
7531 // Baseline: Put Clusters[i] into a partition on its own.
7532 MinPartitions[i] = MinPartitions[i + 1] + 1;
7535 // Search for a solution that results in fewer partitions.
7536 // Note: the search is limited by BitWidth, reducing time complexity.
7537 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7538 // Try building a partition from Clusters[i..j].
7541 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7542 Clusters[j].High->getValue()))
7545 // Check nbr of destinations and cluster types.
7546 // FIXME: This works, but doesn't seem very efficient.
7547 bool RangesOnly = true;
7548 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7549 for (int64_t k = i; k <= j; k++) {
7550 if (Clusters[k].Kind != CC_Range) {
7554 Dests.set(Clusters[k].MBB->getNumber());
7556 if (!RangesOnly || Dests.count() > 3)
7559 // Check if it's a better partition.
7560 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7561 if (NumPartitions < MinPartitions[i]) {
7562 // Found a better partition.
7563 MinPartitions[i] = NumPartitions;
7569 // Iterate over the partitions, replacing with bit-test clusters in-place.
7570 unsigned DstIndex = 0;
7571 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7572 Last = LastElement[First];
7573 assert(First <= Last);
7574 assert(DstIndex <= First);
7576 CaseCluster BitTestCluster;
7577 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7578 Clusters[DstIndex++] = BitTestCluster;
7580 for (unsigned I = First; I <= Last; ++I)
7581 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7584 Clusters.resize(DstIndex);
7587 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7588 MachineBasicBlock *SwitchMBB,
7589 MachineBasicBlock *DefaultMBB) {
7590 MachineFunction *CurMF = FuncInfo.MF;
7591 MachineBasicBlock *NextMBB = nullptr;
7592 MachineFunction::iterator BBI = W.MBB;
7593 if (++BBI != FuncInfo.MF->end())
7596 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7598 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7600 if (Size == 2 && W.MBB == SwitchMBB) {
7601 // If any two of the cases has the same destination, and if one value
7602 // is the same as the other, but has one bit unset that the other has set,
7603 // use bit manipulation to do two compares at once. For example:
7604 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7605 // TODO: This could be extended to merge any 2 cases in switches with 3
7607 // TODO: Handle cases where W.CaseBB != SwitchBB.
7608 CaseCluster &Small = *W.FirstCluster;
7609 CaseCluster &Big = *W.LastCluster;
7611 if (Small.Low == Small.High && Big.Low == Big.High &&
7612 Small.MBB == Big.MBB) {
7613 const APInt &SmallValue = Small.Low->getValue();
7614 const APInt &BigValue = Big.Low->getValue();
7616 // Check that there is only one bit different.
7617 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
7618 (SmallValue | BigValue) == BigValue) {
7619 // Isolate the common bit.
7620 APInt CommonBit = BigValue & ~SmallValue;
7621 assert((SmallValue | CommonBit) == BigValue &&
7622 CommonBit.countPopulation() == 1 && "Not a common bit?");
7624 SDValue CondLHS = getValue(Cond);
7625 EVT VT = CondLHS.getValueType();
7626 SDLoc DL = getCurSDLoc();
7628 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7629 DAG.getConstant(CommonBit, VT));
7630 SDValue Cond = DAG.getSetCC(DL, MVT::i1, Or,
7631 DAG.getConstant(BigValue, VT), ISD::SETEQ);
7633 // Update successor info.
7634 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7635 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7636 addSuccessorWithWeight(
7637 SwitchMBB, DefaultMBB,
7638 // The default destination is the first successor in IR.
7639 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7642 // Insert the true branch.
7644 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7645 DAG.getBasicBlock(Small.MBB));
7646 // Insert the false branch.
7647 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7648 DAG.getBasicBlock(DefaultMBB));
7650 DAG.setRoot(BrCond);
7656 if (TM.getOptLevel() != CodeGenOpt::None) {
7657 // Order cases by weight so the most likely case will be checked first.
7658 std::sort(W.FirstCluster, W.LastCluster + 1,
7659 [](const CaseCluster &a, const CaseCluster &b) {
7660 return a.Weight > b.Weight;
7663 // Rearrange the case blocks so that the last one falls through if possible.
7664 // Start at the bottom as that's the case with the lowest weight.
7665 // FIXME: Take branch probability into account.
7666 for (CaseClusterIt I = W.LastCluster - 1; I >= W.FirstCluster; --I) {
7667 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7668 std::swap(*I, *W.LastCluster);
7674 // Compute total weight.
7675 uint32_t UnhandledWeights = 0;
7676 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
7677 UnhandledWeights += I->Weight;
7679 MachineBasicBlock *CurMBB = W.MBB;
7680 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7681 MachineBasicBlock *Fallthrough;
7682 if (I == W.LastCluster) {
7683 // For the last cluster, fall through to the default destination.
7684 Fallthrough = DefaultMBB;
7686 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7687 CurMF->insert(BBI, Fallthrough);
7688 // Put Cond in a virtual register to make it available from the new blocks.
7689 ExportFromCurrentBlock(Cond);
7693 case CC_JumpTable: {
7694 // FIXME: Optimize away range check based on pivot comparisons.
7695 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7696 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7698 // The jump block hasn't been inserted yet; insert it here.
7699 MachineBasicBlock *JumpMBB = JT->MBB;
7700 CurMF->insert(BBI, JumpMBB);
7701 addSuccessorWithWeight(CurMBB, Fallthrough);
7702 addSuccessorWithWeight(CurMBB, JumpMBB);
7704 // The jump table header will be inserted in our current block, do the
7705 // range check, and fall through to our fallthrough block.
7706 JTH->HeaderBB = CurMBB;
7707 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7709 // If we're in the right place, emit the jump table header right now.
7710 if (CurMBB == SwitchMBB) {
7711 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7712 JTH->Emitted = true;
7717 // FIXME: Optimize away range check based on pivot comparisons.
7718 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7720 // The bit test blocks haven't been inserted yet; insert them here.
7721 for (BitTestCase &BTC : BTB->Cases)
7722 CurMF->insert(BBI, BTC.ThisBB);
7724 // Fill in fields of the BitTestBlock.
7725 BTB->Parent = CurMBB;
7726 BTB->Default = Fallthrough;
7728 // If we're in the right place, emit the bit test header header right now.
7729 if (CurMBB ==SwitchMBB) {
7730 visitBitTestHeader(*BTB, SwitchMBB);
7731 BTB->Emitted = true;
7736 const Value *RHS, *LHS, *MHS;
7738 if (I->Low == I->High) {
7739 // Check Cond == I->Low.
7745 // Check I->Low <= Cond <= I->High.
7752 // The false weight is the sum of all unhandled cases.
7753 UnhandledWeights -= I->Weight;
7754 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
7757 if (CurMBB == SwitchMBB)
7758 visitSwitchCase(CB, SwitchMBB);
7760 SwitchCases.push_back(CB);
7765 CurMBB = Fallthrough;
7769 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
7770 const SwitchWorkListItem &W,
7772 MachineBasicBlock *SwitchMBB) {
7773 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
7774 "Clusters not sorted?");
7776 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
7777 assert(NumClusters >= 2 && "Too small to split!");
7779 // FIXME: When we have profile info, we might want to balance the tree based
7780 // on weights instead of node count.
7782 CaseClusterIt PivotCluster = W.FirstCluster + NumClusters / 2;
7783 CaseClusterIt FirstLeft = W.FirstCluster;
7784 CaseClusterIt LastLeft = PivotCluster - 1;
7785 CaseClusterIt FirstRight = PivotCluster;
7786 CaseClusterIt LastRight = W.LastCluster;
7787 const ConstantInt *Pivot = PivotCluster->Low;
7789 // New blocks will be inserted immediately after the current one.
7790 MachineFunction::iterator BBI = W.MBB;
7793 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
7794 // we can branch to its destination directly if it's squeezed exactly in
7795 // between the known lower bound and Pivot - 1.
7796 MachineBasicBlock *LeftMBB;
7797 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
7798 FirstLeft->Low == W.GE &&
7799 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
7800 LeftMBB = FirstLeft->MBB;
7802 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
7803 FuncInfo.MF->insert(BBI, LeftMBB);
7804 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
7805 // Put Cond in a virtual register to make it available from the new blocks.
7806 ExportFromCurrentBlock(Cond);
7809 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
7810 // single cluster, RHS.Low == Pivot, and we can branch to its destination
7811 // directly if RHS.High equals the current upper bound.
7812 MachineBasicBlock *RightMBB;
7813 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
7814 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
7815 RightMBB = FirstRight->MBB;
7817 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
7818 FuncInfo.MF->insert(BBI, RightMBB);
7819 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
7820 // Put Cond in a virtual register to make it available from the new blocks.
7821 ExportFromCurrentBlock(Cond);
7824 // Create the CaseBlock record that will be used to lower the branch.
7825 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB);
7827 if (W.MBB == SwitchMBB)
7828 visitSwitchCase(CB, SwitchMBB);
7830 SwitchCases.push_back(CB);
7833 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
7834 // Extract cases from the switch.
7835 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7836 CaseClusterVector Clusters;
7837 Clusters.reserve(SI.getNumCases());
7838 for (auto I : SI.cases()) {
7839 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
7840 const ConstantInt *CaseVal = I.getCaseValue();
7841 uint32_t Weight = 0; // FIXME: Use 1 instead?
7843 Weight = BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex());
7844 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
7847 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
7849 if (TM.getOptLevel() != CodeGenOpt::None) {
7850 // Cluster adjacent cases with the same destination.
7851 sortAndRangeify(Clusters);
7853 // Replace an unreachable default with the most popular destination.
7854 // FIXME: Exploit unreachable default more aggressively.
7855 bool UnreachableDefault =
7856 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
7857 if (UnreachableDefault && !Clusters.empty()) {
7858 DenseMap<const BasicBlock *, unsigned> Popularity;
7859 unsigned MaxPop = 0;
7860 const BasicBlock *MaxBB = nullptr;
7861 for (auto I : SI.cases()) {
7862 const BasicBlock *BB = I.getCaseSuccessor();
7863 if (++Popularity[BB] > MaxPop) {
7864 MaxPop = Popularity[BB];
7869 assert(MaxPop > 0 && MaxBB);
7870 DefaultMBB = FuncInfo.MBBMap[MaxBB];
7872 // Remove cases that were pointing to the destination that is now the
7874 CaseClusterVector New;
7875 New.reserve(Clusters.size());
7876 for (CaseCluster &CC : Clusters) {
7877 if (CC.MBB != DefaultMBB)
7880 Clusters = std::move(New);
7884 // If there is only the default destination, jump there directly.
7885 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
7886 if (Clusters.empty()) {
7887 SwitchMBB->addSuccessor(DefaultMBB);
7888 if (DefaultMBB != NextBlock(SwitchMBB)) {
7889 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
7890 getControlRoot(), DAG.getBasicBlock(SwitchMBB)));
7895 if (TM.getOptLevel() != CodeGenOpt::None) {
7896 findJumpTables(Clusters, &SI, DefaultMBB);
7897 findBitTestClusters(Clusters, &SI);
7902 dbgs() << "Case clusters: ";
7903 for (const CaseCluster &C : Clusters) {
7904 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
7905 if (C.Kind == CC_BitTests) dbgs() << "BT:";
7907 C.Low->getValue().print(dbgs(), true);
7908 if (C.Low != C.High) {
7910 C.High->getValue().print(dbgs(), true);
7917 assert(!Clusters.empty());
7918 SwitchWorkList WorkList;
7919 CaseClusterIt First = Clusters.begin();
7920 CaseClusterIt Last = Clusters.end() - 1;
7921 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
7923 while (!WorkList.empty()) {
7924 SwitchWorkListItem W = WorkList.back();
7925 WorkList.pop_back();
7926 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
7928 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
7929 // For optimized builds, lower large range as a balanced binary tree.
7930 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
7934 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);