1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
126 R = ScalarizeVecRes_BinOp(N);
129 R = ScalarizeVecRes_TernaryOp(N);
133 // If R is null, the sub-method took care of registering the result.
135 SetScalarizedVector(SDValue(N, ResNo), R);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
139 SDValue LHS = GetScalarizedVector(N->getOperand(0));
140 SDValue RHS = GetScalarizedVector(N->getOperand(1));
141 return DAG.getNode(N->getOpcode(), SDLoc(N),
142 LHS.getValueType(), LHS, RHS);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
148 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
149 return DAG.getNode(N->getOpcode(), SDLoc(N),
150 Op0.getValueType(), Op0, Op1, Op2);
153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
156 return GetScalarizedVector(Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
160 EVT NewVT = N->getValueType(0).getVectorElementType();
161 return DAG.getNode(ISD::BITCAST, SDLoc(N),
162 NewVT, N->getOperand(0));
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
166 EVT EltVT = N->getValueType(0).getVectorElementType();
167 SDValue InOp = N->getOperand(0);
168 // The BUILD_VECTOR operands may be of wider element types and
169 // we may need to truncate them back to the requested return type.
170 if (EltVT.isInteger())
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 EVT NewVT = N->getValueType(0).getVectorElementType();
177 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
178 return DAG.getConvertRndSat(NewVT, SDLoc(N),
179 Op0, DAG.getValueType(NewVT),
180 DAG.getValueType(Op0.getValueType()),
183 cast<CvtRndSatSDNode>(N)->getCvtCode());
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
188 N->getValueType(0).getVectorElementType(),
189 N->getOperand(0), N->getOperand(1));
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
193 EVT NewVT = N->getValueType(0).getVectorElementType();
194 SDValue Op = GetScalarizedVector(N->getOperand(0));
195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
196 NewVT, Op, N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
200 SDValue Op = GetScalarizedVector(N->getOperand(0));
201 return DAG.getNode(ISD::FPOWI, SDLoc(N),
202 Op.getValueType(), Op, N->getOperand(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
206 // The value to insert may have a wider type than the vector element type,
207 // so be sure to truncate it to the element type if necessary.
208 SDValue Op = N->getOperand(1);
209 EVT EltVT = N->getValueType(0).getVectorElementType();
210 if (Op.getValueType() != EltVT)
211 // FIXME: Can this happen for floating point types?
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
216 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
217 assert(N->isUnindexed() && "Indexed vector load?");
219 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
220 N->getExtensionType(),
221 N->getValueType(0).getVectorElementType(),
223 N->getChain(), N->getBasePtr(),
224 DAG.getUNDEF(N->getBasePtr().getValueType()),
226 N->getMemoryVT().getVectorElementType(),
227 N->isVolatile(), N->isNonTemporal(),
228 N->isInvariant(), N->getOriginalAlignment(),
231 // Legalized the chain result - switch anything that used the old chain to
233 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
238 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
239 EVT DestVT = N->getValueType(0).getVectorElementType();
240 SDValue Op = N->getOperand(0);
241 EVT OpVT = Op.getValueType();
243 // The result needs scalarizing, but it's not a given that the source does.
244 // This is a workaround for targets where it's impossible to scalarize the
245 // result of a conversion, because the source type is legal.
246 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
247 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
248 // legal and was not scalarized.
249 // See the similar logic in ScalarizeVecRes_VSETCC
250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
251 Op = GetScalarizedVector(Op);
253 EVT VT = OpVT.getVectorElementType();
254 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
255 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
260 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
261 EVT EltVT = N->getValueType(0).getVectorElementType();
262 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
263 SDValue LHS = GetScalarizedVector(N->getOperand(0));
264 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
265 LHS, DAG.getValueType(ExtVT));
268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
269 // If the operand is wider than the vector element type then it is implicitly
270 // truncated. Make that explicit here.
271 EVT EltVT = N->getValueType(0).getVectorElementType();
272 SDValue InOp = N->getOperand(0);
273 if (InOp.getValueType() != EltVT)
274 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
278 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
279 SDValue Cond = GetScalarizedVector(N->getOperand(0));
280 SDValue LHS = GetScalarizedVector(N->getOperand(1));
281 TargetLowering::BooleanContent ScalarBool =
282 TLI.getBooleanContents(false, false);
283 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
285 // If integer and float booleans have different contents then we can't
286 // reliably optimize in all cases. There is a full explanation for this in
287 // DAGCombiner::visitSELECT() where the same issue affects folding
288 // (select C, 0, 1) to (xor C, 1).
289 if (TLI.getBooleanContents(false, false) !=
290 TLI.getBooleanContents(false, true)) {
291 // At least try the common case where the boolean is generated by a
293 if (Cond->getOpcode() == ISD::SETCC) {
294 EVT OpVT = Cond->getOperand(0)->getValueType(0);
295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
296 VecBool = TLI.getBooleanContents(OpVT);
298 ScalarBool = TargetLowering::UndefinedBooleanContent;
301 if (ScalarBool != VecBool) {
302 EVT CondVT = Cond.getValueType();
303 switch (ScalarBool) {
304 case TargetLowering::UndefinedBooleanContent:
306 case TargetLowering::ZeroOrOneBooleanContent:
307 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
308 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
309 // Vector read from all ones, scalar expects a single 1 so mask.
310 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
311 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
313 case TargetLowering::ZeroOrNegativeOneBooleanContent:
314 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
315 VecBool == TargetLowering::ZeroOrOneBooleanContent);
316 // Vector reads from a one, scalar from all ones so sign extend.
317 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
318 Cond, DAG.getValueType(MVT::i1));
323 return DAG.getSelect(SDLoc(N),
324 LHS.getValueType(), Cond, LHS,
325 GetScalarizedVector(N->getOperand(2)));
328 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
329 SDValue LHS = GetScalarizedVector(N->getOperand(1));
330 return DAG.getSelect(SDLoc(N),
331 LHS.getValueType(), N->getOperand(0), LHS,
332 GetScalarizedVector(N->getOperand(2)));
335 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
336 SDValue LHS = GetScalarizedVector(N->getOperand(2));
337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
338 N->getOperand(0), N->getOperand(1),
339 LHS, GetScalarizedVector(N->getOperand(3)),
343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
344 assert(N->getValueType(0).isVector() ==
345 N->getOperand(0).getValueType().isVector() &&
346 "Scalar/Vector type mismatch");
348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
350 SDValue LHS = GetScalarizedVector(N->getOperand(0));
351 SDValue RHS = GetScalarizedVector(N->getOperand(1));
354 // Turn it into a scalar SETCC.
355 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
359 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
363 // Figure out if the scalar is the LHS or RHS and return it.
364 SDValue Arg = N->getOperand(2).getOperand(0);
365 if (Arg.getOpcode() == ISD::UNDEF)
366 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
367 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
368 return GetScalarizedVector(N->getOperand(Op));
371 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
372 assert(N->getValueType(0).isVector() &&
373 N->getOperand(0).getValueType().isVector() &&
374 "Operand types must be vectors");
375 SDValue LHS = N->getOperand(0);
376 SDValue RHS = N->getOperand(1);
377 EVT OpVT = LHS.getValueType();
378 EVT NVT = N->getValueType(0).getVectorElementType();
381 // The result needs scalarizing, but it's not a given that the source does.
382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
383 LHS = GetScalarizedVector(LHS);
384 RHS = GetScalarizedVector(RHS);
386 EVT VT = OpVT.getVectorElementType();
387 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
388 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
389 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
390 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
393 // Turn it into a scalar SETCC.
394 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
396 // Vectors may have a different boolean contents to scalars. Promote the
397 // value appropriately.
398 ISD::NodeType ExtendCode =
399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
400 return DAG.getNode(ExtendCode, DL, NVT, Res);
404 //===----------------------------------------------------------------------===//
405 // Operand Vector Scalarization <1 x ty> -> ty.
406 //===----------------------------------------------------------------------===//
408 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
409 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
412 SDValue Res = SDValue();
414 if (!Res.getNode()) {
415 switch (N->getOpcode()) {
418 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
422 llvm_unreachable("Do not know how to scalarize this operator's operand!");
424 Res = ScalarizeVecOp_BITCAST(N);
426 case ISD::ANY_EXTEND:
427 case ISD::ZERO_EXTEND:
428 case ISD::SIGN_EXTEND:
430 case ISD::FP_TO_SINT:
431 case ISD::FP_TO_UINT:
432 case ISD::SINT_TO_FP:
433 case ISD::UINT_TO_FP:
434 Res = ScalarizeVecOp_UnaryOp(N);
436 case ISD::CONCAT_VECTORS:
437 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
439 case ISD::EXTRACT_VECTOR_ELT:
440 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
443 Res = ScalarizeVecOp_VSELECT(N);
446 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
449 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
454 // If the result is null, the sub-method took care of registering results etc.
455 if (!Res.getNode()) return false;
457 // If the result is N, the sub-method updated N in place. Tell the legalizer
459 if (Res.getNode() == N)
462 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
463 "Invalid operand expansion");
465 ReplaceValueWith(SDValue(N, 0), Res);
469 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
470 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
471 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
472 SDValue Elt = GetScalarizedVector(N->getOperand(0));
473 return DAG.getNode(ISD::BITCAST, SDLoc(N),
474 N->getValueType(0), Elt);
477 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
478 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
479 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
480 assert(N->getValueType(0).getVectorNumElements() == 1 &&
481 "Unexpected vector type!");
482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
483 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
484 N->getValueType(0).getScalarType(), Elt);
485 // Revectorize the result so the types line up with what the uses of this
486 // expression expect.
487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
490 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
491 /// use a BUILD_VECTOR instead.
492 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
493 SmallVector<SDValue, 8> Ops(N->getNumOperands());
494 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
495 Ops[i] = GetScalarizedVector(N->getOperand(i));
496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
499 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
500 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
503 SDValue Res = GetScalarizedVector(N->getOperand(0));
504 if (Res.getValueType() != N->getValueType(0))
505 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
511 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
512 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
513 /// (still with vector output type since that was acceptable if we got here).
514 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
515 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
516 EVT VT = N->getValueType(0);
518 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
522 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
523 /// scalarized, it must be <1 x ty>. Just store the element.
524 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
525 assert(N->isUnindexed() && "Indexed store of one-element vector?");
526 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
529 if (N->isTruncatingStore())
530 return DAG.getTruncStore(N->getChain(), dl,
531 GetScalarizedVector(N->getOperand(1)),
532 N->getBasePtr(), N->getPointerInfo(),
533 N->getMemoryVT().getVectorElementType(),
534 N->isVolatile(), N->isNonTemporal(),
535 N->getAlignment(), N->getAAInfo());
537 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getOriginalAlignment(), N->getAAInfo());
543 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
544 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
545 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
546 SDValue Elt = GetScalarizedVector(N->getOperand(0));
547 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
548 N->getValueType(0).getVectorElementType(), Elt,
550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
553 //===----------------------------------------------------------------------===//
554 // Result Vector Splitting
555 //===----------------------------------------------------------------------===//
557 /// SplitVectorResult - This method is called when the specified result of the
558 /// specified node is found to need vector splitting. At this point, the node
559 /// may also have invalid operands or may have other results that need
560 /// legalization, we just know that (at least) one result needs vector
562 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
563 DEBUG(dbgs() << "Split node result: ";
568 // See if the target wants to custom expand this node.
569 if (CustomLowerNode(N, N->getValueType(ResNo), true))
572 switch (N->getOpcode()) {
575 dbgs() << "SplitVectorResult #" << ResNo << ": ";
579 report_fatal_error("Do not know how to split the result of this "
582 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
584 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
586 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
587 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
589 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
590 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
591 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
592 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
593 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
595 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
596 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
601 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
604 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
607 SplitVecRes_SETCC(N, Lo, Hi);
609 case ISD::VECTOR_SHUFFLE:
610 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
614 case ISD::CONVERT_RNDSAT:
617 case ISD::CTLZ_ZERO_UNDEF:
618 case ISD::CTTZ_ZERO_UNDEF:
629 case ISD::FNEARBYINT:
633 case ISD::FP_TO_SINT:
634 case ISD::FP_TO_UINT:
640 case ISD::SINT_TO_FP:
642 case ISD::UINT_TO_FP:
643 SplitVecRes_UnaryOp(N, Lo, Hi);
646 case ISD::ANY_EXTEND:
647 case ISD::SIGN_EXTEND:
648 case ISD::ZERO_EXTEND:
649 SplitVecRes_ExtendOp(N, Lo, Hi);
678 SplitVecRes_BinOp(N, Lo, Hi);
681 SplitVecRes_TernaryOp(N, Lo, Hi);
685 // If Lo/Hi is null, the sub-method took care of registering results etc.
687 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
690 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
692 SDValue LHSLo, LHSHi;
693 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
694 SDValue RHSLo, RHSHi;
695 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
698 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
699 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
702 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
704 SDValue Op0Lo, Op0Hi;
705 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
706 SDValue Op1Lo, Op1Hi;
707 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
708 SDValue Op2Lo, Op2Hi;
709 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
712 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
713 Op0Lo, Op1Lo, Op2Lo);
714 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
715 Op0Hi, Op1Hi, Op2Hi);
718 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
720 // We know the result is a vector. The input may be either a vector or a
723 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
726 SDValue InOp = N->getOperand(0);
727 EVT InVT = InOp.getValueType();
729 // Handle some special cases efficiently.
730 switch (getTypeAction(InVT)) {
731 case TargetLowering::TypeLegal:
732 case TargetLowering::TypePromoteInteger:
733 case TargetLowering::TypePromoteFloat:
734 case TargetLowering::TypeSoftenFloat:
735 case TargetLowering::TypeScalarizeVector:
736 case TargetLowering::TypeWidenVector:
738 case TargetLowering::TypeExpandInteger:
739 case TargetLowering::TypeExpandFloat:
740 // A scalar to vector conversion, where the scalar needs expansion.
741 // If the vector is being split in two then we can just convert the
744 GetExpandedOp(InOp, Lo, Hi);
745 if (DAG.getDataLayout().isBigEndian())
747 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
748 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
752 case TargetLowering::TypeSplitVector:
753 // If the input is a vector that needs to be split, convert each split
754 // piece of the input now.
755 GetSplitVector(InOp, Lo, Hi);
756 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
757 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
761 // In the general case, convert the input to an integer and split it by hand.
762 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
763 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
764 if (DAG.getDataLayout().isBigEndian())
765 std::swap(LoIntVT, HiIntVT);
767 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
769 if (DAG.getDataLayout().isBigEndian())
771 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
772 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
775 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
779 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
780 unsigned LoNumElts = LoVT.getVectorNumElements();
781 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
782 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
784 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
785 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
788 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
790 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
792 unsigned NumSubvectors = N->getNumOperands() / 2;
793 if (NumSubvectors == 1) {
794 Lo = N->getOperand(0);
795 Hi = N->getOperand(1);
800 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
802 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
803 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
805 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
806 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
809 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
811 SDValue Vec = N->getOperand(0);
812 SDValue Idx = N->getOperand(1);
816 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
818 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
819 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
820 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
821 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
822 TLI.getVectorIdxTy()));
825 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
827 SDValue Vec = N->getOperand(0);
828 SDValue SubVec = N->getOperand(1);
829 SDValue Idx = N->getOperand(2);
831 GetSplitVector(Vec, Lo, Hi);
833 // Spill the vector to the stack.
834 EVT VecVT = Vec.getValueType();
835 EVT SubVecVT = VecVT.getVectorElementType();
836 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
837 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
838 MachinePointerInfo(), false, false, 0);
840 // Store the new subvector into the specified index.
841 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
842 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
843 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
844 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
847 // Load the Lo part from the stack slot.
848 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
849 false, false, false, 0);
851 // Increment the pointer to the other part.
852 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
854 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
855 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
857 // Load the Hi part from the stack slot.
858 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
859 false, false, false, MinAlign(Alignment, IncrementSize));
862 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
865 GetSplitVector(N->getOperand(0), Lo, Hi);
866 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
867 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
870 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
872 SDValue LHSLo, LHSHi;
873 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
877 std::tie(LoVT, HiVT) =
878 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
880 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
881 DAG.getValueType(LoVT));
882 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
883 DAG.getValueType(HiVT));
886 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
888 SDValue Vec = N->getOperand(0);
889 SDValue Elt = N->getOperand(1);
890 SDValue Idx = N->getOperand(2);
892 GetSplitVector(Vec, Lo, Hi);
894 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
895 unsigned IdxVal = CIdx->getZExtValue();
896 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
897 if (IdxVal < LoNumElts)
898 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
899 Lo.getValueType(), Lo, Elt, Idx);
901 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
902 DAG.getConstant(IdxVal - LoNumElts, dl,
903 TLI.getVectorIdxTy()));
907 // See if the target wants to custom expand this node.
908 if (CustomLowerNode(N, N->getValueType(0), true))
911 // Spill the vector to the stack.
912 EVT VecVT = Vec.getValueType();
913 EVT EltVT = VecVT.getVectorElementType();
914 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
915 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
916 MachinePointerInfo(), false, false, 0);
918 // Store the new element. This may be larger than the vector element type,
919 // so use a truncating store.
920 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
921 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
922 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
923 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
926 // Load the Lo part from the stack slot.
927 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
928 false, false, false, 0);
930 // Increment the pointer to the other part.
931 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
932 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
933 DAG.getConstant(IncrementSize, dl,
934 StackPtr.getValueType()));
936 // Load the Hi part from the stack slot.
937 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
938 false, false, false, MinAlign(Alignment, IncrementSize));
941 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
945 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
946 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
947 Hi = DAG.getUNDEF(HiVT);
950 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
952 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
955 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
957 ISD::LoadExtType ExtType = LD->getExtensionType();
958 SDValue Ch = LD->getChain();
959 SDValue Ptr = LD->getBasePtr();
960 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
961 EVT MemoryVT = LD->getMemoryVT();
962 unsigned Alignment = LD->getOriginalAlignment();
963 bool isVolatile = LD->isVolatile();
964 bool isNonTemporal = LD->isNonTemporal();
965 bool isInvariant = LD->isInvariant();
966 AAMDNodes AAInfo = LD->getAAInfo();
968 EVT LoMemVT, HiMemVT;
969 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
971 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
972 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
973 isInvariant, Alignment, AAInfo);
975 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
976 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
977 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
978 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
979 LD->getPointerInfo().getWithOffset(IncrementSize),
980 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
983 // Build a factor node to remember that this load is independent of the
985 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
988 // Legalized the chain result - switch anything that used the old chain to
990 ReplaceValueWith(SDValue(LD, 1), Ch);
993 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
994 SDValue &Lo, SDValue &Hi) {
997 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
999 SDValue Ch = MLD->getChain();
1000 SDValue Ptr = MLD->getBasePtr();
1001 SDValue Mask = MLD->getMask();
1002 unsigned Alignment = MLD->getOriginalAlignment();
1003 ISD::LoadExtType ExtType = MLD->getExtensionType();
1005 // if Alignment is equal to the vector size,
1006 // take the half of it for the second part
1007 unsigned SecondHalfAlignment =
1008 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1009 Alignment/2 : Alignment;
1011 SDValue MaskLo, MaskHi;
1012 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1014 EVT MemoryVT = MLD->getMemoryVT();
1015 EVT LoMemVT, HiMemVT;
1016 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1018 SDValue Src0 = MLD->getSrc0();
1019 SDValue Src0Lo, Src0Hi;
1020 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1022 MachineMemOperand *MMO = DAG.getMachineFunction().
1023 getMachineMemOperand(MLD->getPointerInfo(),
1024 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1025 Alignment, MLD->getAAInfo(), MLD->getRanges());
1027 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1030 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1031 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1032 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1034 MMO = DAG.getMachineFunction().
1035 getMachineMemOperand(MLD->getPointerInfo(),
1036 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1037 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1039 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1043 // Build a factor node to remember that this load is independent of the
1045 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1048 // Legalized the chain result - switch anything that used the old chain to
1050 ReplaceValueWith(SDValue(MLD, 1), Ch);
1054 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1055 SDValue &Lo, SDValue &Hi) {
1058 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1060 SDValue Ch = MGT->getChain();
1061 SDValue Ptr = MGT->getBasePtr();
1062 SDValue Mask = MGT->getMask();
1063 unsigned Alignment = MGT->getOriginalAlignment();
1065 SDValue MaskLo, MaskHi;
1066 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1068 EVT MemoryVT = MGT->getMemoryVT();
1069 EVT LoMemVT, HiMemVT;
1070 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1072 SDValue Src0Lo, Src0Hi;
1073 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1075 SDValue IndexHi, IndexLo;
1076 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MGT->getIndex(), dl);
1078 MachineMemOperand *MMO = DAG.getMachineFunction().
1079 getMachineMemOperand(MGT->getPointerInfo(),
1080 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1081 Alignment, MGT->getAAInfo(), MGT->getRanges());
1083 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1084 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1087 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1088 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1091 // Build a factor node to remember that this load is independent of the
1093 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1096 // Legalized the chain result - switch anything that used the old chain to
1098 ReplaceValueWith(SDValue(MGT, 1), Ch);
1102 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1103 assert(N->getValueType(0).isVector() &&
1104 N->getOperand(0).getValueType().isVector() &&
1105 "Operand types must be vectors");
1109 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1112 SDValue LL, LH, RL, RH;
1113 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1114 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1116 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1117 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1120 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1122 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1125 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1127 // If the input also splits, handle it directly for a compile time speedup.
1128 // Otherwise split it by hand.
1129 EVT InVT = N->getOperand(0).getValueType();
1130 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1131 GetSplitVector(N->getOperand(0), Lo, Hi);
1133 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1135 if (N->getOpcode() == ISD::FP_ROUND) {
1136 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1137 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1138 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1139 SDValue DTyOpLo = DAG.getValueType(LoVT);
1140 SDValue DTyOpHi = DAG.getValueType(HiVT);
1141 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1142 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1143 SDValue RndOp = N->getOperand(3);
1144 SDValue SatOp = N->getOperand(4);
1145 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1146 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1148 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1151 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1152 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1156 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1159 EVT SrcVT = N->getOperand(0).getValueType();
1160 EVT DestVT = N->getValueType(0);
1162 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1164 // We can do better than a generic split operation if the extend is doing
1165 // more than just doubling the width of the elements and the following are
1167 // - The number of vector elements is even,
1168 // - the source type is legal,
1169 // - the type of a split source is illegal,
1170 // - the type of an extended (by doubling element size) source is legal, and
1171 // - the type of that extended source when split is legal.
1173 // This won't necessarily completely legalize the operation, but it will
1174 // more effectively move in the right direction and prevent falling down
1175 // to scalarization in many cases due to the input vector being split too
1177 unsigned NumElements = SrcVT.getVectorNumElements();
1178 if ((NumElements & 1) == 0 &&
1179 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1180 LLVMContext &Ctx = *DAG.getContext();
1181 EVT NewSrcVT = EVT::getVectorVT(
1182 Ctx, EVT::getIntegerVT(
1183 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1186 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1187 EVT SplitLoVT, SplitHiVT;
1188 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1189 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1190 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1191 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1192 N->dump(&DAG); dbgs() << "\n");
1193 // Extend the source vector by one step.
1195 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1196 // Get the low and high halves of the new, extended one step, vector.
1197 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1198 // Extend those vector halves the rest of the way.
1199 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1200 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1204 // Fall back to the generic unary operator splitting otherwise.
1205 SplitVecRes_UnaryOp(N, Lo, Hi);
1208 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1209 SDValue &Lo, SDValue &Hi) {
1210 // The low and high parts of the original input give four input vectors.
1213 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1214 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1215 EVT NewVT = Inputs[0].getValueType();
1216 unsigned NewElts = NewVT.getVectorNumElements();
1218 // If Lo or Hi uses elements from at most two of the four input vectors, then
1219 // express it as a vector shuffle of those two inputs. Otherwise extract the
1220 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1221 SmallVector<int, 16> Ops;
1222 for (unsigned High = 0; High < 2; ++High) {
1223 SDValue &Output = High ? Hi : Lo;
1225 // Build a shuffle mask for the output, discovering on the fly which
1226 // input vectors to use as shuffle operands (recorded in InputUsed).
1227 // If building a suitable shuffle vector proves too hard, then bail
1228 // out with useBuildVector set.
1229 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1230 unsigned FirstMaskIdx = High * NewElts;
1231 bool useBuildVector = false;
1232 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1233 // The mask element. This indexes into the input.
1234 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1236 // The input vector this mask element indexes into.
1237 unsigned Input = (unsigned)Idx / NewElts;
1239 if (Input >= array_lengthof(Inputs)) {
1240 // The mask element does not index into any input vector.
1245 // Turn the index into an offset from the start of the input vector.
1246 Idx -= Input * NewElts;
1248 // Find or create a shuffle vector operand to hold this input.
1250 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1251 if (InputUsed[OpNo] == Input) {
1252 // This input vector is already an operand.
1254 } else if (InputUsed[OpNo] == -1U) {
1255 // Create a new operand for this input vector.
1256 InputUsed[OpNo] = Input;
1261 if (OpNo >= array_lengthof(InputUsed)) {
1262 // More than two input vectors used! Give up on trying to create a
1263 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1264 useBuildVector = true;
1268 // Add the mask index for the new shuffle vector.
1269 Ops.push_back(Idx + OpNo * NewElts);
1272 if (useBuildVector) {
1273 EVT EltVT = NewVT.getVectorElementType();
1274 SmallVector<SDValue, 16> SVOps;
1276 // Extract the input elements by hand.
1277 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1278 // The mask element. This indexes into the input.
1279 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1281 // The input vector this mask element indexes into.
1282 unsigned Input = (unsigned)Idx / NewElts;
1284 if (Input >= array_lengthof(Inputs)) {
1285 // The mask element is "undef" or indexes off the end of the input.
1286 SVOps.push_back(DAG.getUNDEF(EltVT));
1290 // Turn the index into an offset from the start of the input vector.
1291 Idx -= Input * NewElts;
1293 // Extract the vector element by hand.
1294 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1296 DAG.getConstant(Idx, dl,
1297 TLI.getVectorIdxTy())));
1300 // Construct the Lo/Hi output using a BUILD_VECTOR.
1301 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1302 } else if (InputUsed[0] == -1U) {
1303 // No input vectors were used! The result is undefined.
1304 Output = DAG.getUNDEF(NewVT);
1306 SDValue Op0 = Inputs[InputUsed[0]];
1307 // If only one input was used, use an undefined vector for the other.
1308 SDValue Op1 = InputUsed[1] == -1U ?
1309 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1310 // At least one input vector was used. Create a new shuffle vector.
1311 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1319 //===----------------------------------------------------------------------===//
1320 // Operand Vector Splitting
1321 //===----------------------------------------------------------------------===//
1323 /// SplitVectorOperand - This method is called when the specified operand of the
1324 /// specified node is found to need vector splitting. At this point, all of the
1325 /// result types of the node are known to be legal, but other operands of the
1326 /// node may need legalization as well as the specified one.
1327 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1328 DEBUG(dbgs() << "Split node operand: ";
1331 SDValue Res = SDValue();
1333 // See if the target wants to custom split this node.
1334 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1337 if (!Res.getNode()) {
1338 switch (N->getOpcode()) {
1341 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1345 report_fatal_error("Do not know how to split this operator's "
1348 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1349 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1350 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1351 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1352 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1354 Res = SplitVecOp_TruncateHelper(N);
1356 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1358 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1361 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1364 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1367 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1370 Res = SplitVecOp_VSELECT(N, OpNo);
1372 case ISD::FP_TO_SINT:
1373 case ISD::FP_TO_UINT:
1374 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1375 Res = SplitVecOp_TruncateHelper(N);
1377 Res = SplitVecOp_UnaryOp(N);
1379 case ISD::SINT_TO_FP:
1380 case ISD::UINT_TO_FP:
1381 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1382 Res = SplitVecOp_TruncateHelper(N);
1384 Res = SplitVecOp_UnaryOp(N);
1389 case ISD::FP_EXTEND:
1390 case ISD::SIGN_EXTEND:
1391 case ISD::ZERO_EXTEND:
1392 case ISD::ANY_EXTEND:
1394 Res = SplitVecOp_UnaryOp(N);
1399 // If the result is null, the sub-method took care of registering results etc.
1400 if (!Res.getNode()) return false;
1402 // If the result is N, the sub-method updated N in place. Tell the legalizer
1404 if (Res.getNode() == N)
1407 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1408 "Invalid operand expansion");
1410 ReplaceValueWith(SDValue(N, 0), Res);
1414 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1415 // The only possibility for an illegal operand is the mask, since result type
1416 // legalization would have handled this node already otherwise.
1417 assert(OpNo == 0 && "Illegal operand must be mask");
1419 SDValue Mask = N->getOperand(0);
1420 SDValue Src0 = N->getOperand(1);
1421 SDValue Src1 = N->getOperand(2);
1422 EVT Src0VT = Src0.getValueType();
1424 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1427 GetSplitVector(N->getOperand(0), Lo, Hi);
1428 assert(Lo.getValueType() == Hi.getValueType() &&
1429 "Lo and Hi have differing types");
1432 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1433 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1435 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1436 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1437 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1438 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1441 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1443 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1445 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1448 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1449 // The result has a legal vector type, but the input needs splitting.
1450 EVT ResVT = N->getValueType(0);
1453 GetSplitVector(N->getOperand(0), Lo, Hi);
1454 EVT InVT = Lo.getValueType();
1456 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1457 InVT.getVectorNumElements());
1459 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1460 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1462 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1465 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1466 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1467 // end up being split all the way down to individual components. Convert the
1468 // split pieces into integers and reassemble.
1470 GetSplitVector(N->getOperand(0), Lo, Hi);
1471 Lo = BitConvertToInteger(Lo);
1472 Hi = BitConvertToInteger(Hi);
1474 if (DAG.getDataLayout().isBigEndian())
1477 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1478 JoinIntegers(Lo, Hi));
1481 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1482 // We know that the extracted result type is legal.
1483 EVT SubVT = N->getValueType(0);
1484 SDValue Idx = N->getOperand(1);
1487 GetSplitVector(N->getOperand(0), Lo, Hi);
1489 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1490 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1492 if (IdxVal < LoElts) {
1493 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1494 "Extracted subvector crosses vector split!");
1495 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1497 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1498 DAG.getConstant(IdxVal - LoElts, dl,
1499 Idx.getValueType()));
1503 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1504 SDValue Vec = N->getOperand(0);
1505 SDValue Idx = N->getOperand(1);
1506 EVT VecVT = Vec.getValueType();
1508 if (isa<ConstantSDNode>(Idx)) {
1509 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1510 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1513 GetSplitVector(Vec, Lo, Hi);
1515 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1517 if (IdxVal < LoElts)
1518 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1519 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1520 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1521 Idx.getValueType())), 0);
1524 // See if the target wants to custom expand this node.
1525 if (CustomLowerNode(N, N->getValueType(0), true))
1528 // Store the vector to the stack.
1529 EVT EltVT = VecVT.getVectorElementType();
1531 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1532 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1533 MachinePointerInfo(), false, false, 0);
1535 // Load back the required element.
1536 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1537 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1538 MachinePointerInfo(), EltVT, false, false, false, 0);
1541 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1545 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1547 SDValue Ch = MGT->getChain();
1548 SDValue Ptr = MGT->getBasePtr();
1549 SDValue Index = MGT->getIndex();
1550 SDValue Mask = MGT->getMask();
1551 unsigned Alignment = MGT->getOriginalAlignment();
1553 SDValue MaskLo, MaskHi;
1554 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1556 EVT MemoryVT = MGT->getMemoryVT();
1557 EVT LoMemVT, HiMemVT;
1558 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1560 SDValue Src0Lo, Src0Hi;
1561 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1563 SDValue IndexHi, IndexLo;
1564 if (Index.getNode())
1565 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1567 IndexLo = IndexHi = Index;
1569 MachineMemOperand *MMO = DAG.getMachineFunction().
1570 getMachineMemOperand(MGT->getPointerInfo(),
1571 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1572 Alignment, MGT->getAAInfo(), MGT->getRanges());
1574 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1575 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1578 MMO = DAG.getMachineFunction().
1579 getMachineMemOperand(MGT->getPointerInfo(),
1580 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1581 Alignment, MGT->getAAInfo(),
1584 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1585 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1588 // Build a factor node to remember that this load is independent of the
1590 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1593 // Legalized the chain result - switch anything that used the old chain to
1595 ReplaceValueWith(SDValue(MGT, 1), Ch);
1597 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1599 ReplaceValueWith(SDValue(MGT, 0), Res);
1603 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1605 SDValue Ch = N->getChain();
1606 SDValue Ptr = N->getBasePtr();
1607 SDValue Mask = N->getMask();
1608 SDValue Data = N->getValue();
1609 EVT MemoryVT = N->getMemoryVT();
1610 unsigned Alignment = N->getOriginalAlignment();
1613 EVT LoMemVT, HiMemVT;
1614 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1616 SDValue DataLo, DataHi;
1617 GetSplitVector(Data, DataLo, DataHi);
1618 SDValue MaskLo, MaskHi;
1619 GetSplitVector(Mask, MaskLo, MaskHi);
1621 // if Alignment is equal to the vector size,
1622 // take the half of it for the second part
1623 unsigned SecondHalfAlignment =
1624 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1625 Alignment/2 : Alignment;
1628 MachineMemOperand *MMO = DAG.getMachineFunction().
1629 getMachineMemOperand(N->getPointerInfo(),
1630 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1631 Alignment, N->getAAInfo(), N->getRanges());
1633 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1634 N->isTruncatingStore());
1636 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1637 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1638 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1640 MMO = DAG.getMachineFunction().
1641 getMachineMemOperand(N->getPointerInfo(),
1642 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1643 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1645 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1646 N->isTruncatingStore());
1648 // Build a factor node to remember that this store is independent of the
1650 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1653 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1655 SDValue Ch = N->getChain();
1656 SDValue Ptr = N->getBasePtr();
1657 SDValue Mask = N->getMask();
1658 SDValue Index = N->getIndex();
1659 SDValue Data = N->getValue();
1660 EVT MemoryVT = N->getMemoryVT();
1661 unsigned Alignment = N->getOriginalAlignment();
1664 EVT LoMemVT, HiMemVT;
1665 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1667 SDValue DataLo, DataHi;
1668 GetSplitVector(Data, DataLo, DataHi);
1669 SDValue MaskLo, MaskHi;
1670 GetSplitVector(Mask, MaskLo, MaskHi);
1672 SDValue PtrLo, PtrHi;
1673 if (Ptr.getValueType().isVector()) // gather form vector of pointers
1674 std::tie(PtrLo, PtrHi) = DAG.SplitVector(Ptr, DL);
1676 PtrLo = PtrHi = Ptr;
1678 SDValue IndexHi, IndexLo;
1679 if (Index.getNode())
1680 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1682 IndexLo = IndexHi = Index;
1685 MachineMemOperand *MMO = DAG.getMachineFunction().
1686 getMachineMemOperand(N->getPointerInfo(),
1687 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1688 Alignment, N->getAAInfo(), N->getRanges());
1690 SDValue OpsLo[] = {Ch, DataLo, MaskLo, PtrLo, IndexLo};
1691 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1694 MMO = DAG.getMachineFunction().
1695 getMachineMemOperand(N->getPointerInfo(),
1696 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1697 Alignment, N->getAAInfo(), N->getRanges());
1699 SDValue OpsHi[] = {Ch, DataHi, MaskHi, PtrHi, IndexHi};
1700 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1703 // Build a factor node to remember that this store is independent of the
1705 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1708 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1709 assert(N->isUnindexed() && "Indexed store of vector?");
1710 assert(OpNo == 1 && "Can only split the stored value");
1713 bool isTruncating = N->isTruncatingStore();
1714 SDValue Ch = N->getChain();
1715 SDValue Ptr = N->getBasePtr();
1716 EVT MemoryVT = N->getMemoryVT();
1717 unsigned Alignment = N->getOriginalAlignment();
1718 bool isVol = N->isVolatile();
1719 bool isNT = N->isNonTemporal();
1720 AAMDNodes AAInfo = N->getAAInfo();
1722 GetSplitVector(N->getOperand(1), Lo, Hi);
1724 EVT LoMemVT, HiMemVT;
1725 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1727 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1730 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1731 LoMemVT, isVol, isNT, Alignment, AAInfo);
1733 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1734 isVol, isNT, Alignment, AAInfo);
1736 // Increment the pointer to the other half.
1737 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1738 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1741 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1742 N->getPointerInfo().getWithOffset(IncrementSize),
1743 HiMemVT, isVol, isNT, Alignment, AAInfo);
1745 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1746 N->getPointerInfo().getWithOffset(IncrementSize),
1747 isVol, isNT, Alignment, AAInfo);
1749 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1752 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1755 // The input operands all must have the same type, and we know the result
1756 // type is valid. Convert this to a buildvector which extracts all the
1758 // TODO: If the input elements are power-two vectors, we could convert this to
1759 // a new CONCAT_VECTORS node with elements that are half-wide.
1760 SmallVector<SDValue, 32> Elts;
1761 EVT EltVT = N->getValueType(0).getVectorElementType();
1762 for (const SDValue &Op : N->op_values()) {
1763 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1765 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1766 Op, DAG.getConstant(i, DL, TLI.getVectorIdxTy())));
1771 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1774 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1775 // The result type is legal, but the input type is illegal. If splitting
1776 // ends up with the result type of each half still being legal, just
1777 // do that. If, however, that would result in an illegal result type,
1778 // we can try to get more clever with power-two vectors. Specifically,
1779 // split the input type, but also widen the result element size, then
1780 // concatenate the halves and truncate again. For example, consider a target
1781 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1782 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1783 // %inlo = v4i32 extract_subvector %in, 0
1784 // %inhi = v4i32 extract_subvector %in, 4
1785 // %lo16 = v4i16 trunc v4i32 %inlo
1786 // %hi16 = v4i16 trunc v4i32 %inhi
1787 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1788 // %res = v8i8 trunc v8i16 %in16
1790 // Without this transform, the original truncate would end up being
1791 // scalarized, which is pretty much always a last resort.
1792 SDValue InVec = N->getOperand(0);
1793 EVT InVT = InVec->getValueType(0);
1794 EVT OutVT = N->getValueType(0);
1795 unsigned NumElements = OutVT.getVectorNumElements();
1796 bool IsFloat = OutVT.isFloatingPoint();
1798 // Widening should have already made sure this is a power-two vector
1799 // if we're trying to split it at all. assert() that's true, just in case.
1800 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1802 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1803 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1805 // If the input elements are only 1/2 the width of the result elements,
1806 // just use the normal splitting. Our trick only work if there's room
1807 // to split more than once.
1808 if (InElementSize <= OutElementSize * 2)
1809 return SplitVecOp_UnaryOp(N);
1812 // Extract the halves of the input via extract_subvector.
1813 SDValue InLoVec, InHiVec;
1814 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1815 // Truncate them to 1/2 the element size.
1816 EVT HalfElementVT = IsFloat ?
1817 EVT::getFloatingPointVT(InElementSize/2) :
1818 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1819 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1821 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1822 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1823 // Concatenate them to get the full intermediate truncation result.
1824 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1825 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1827 // Now finish up by truncating all the way down to the original result
1828 // type. This should normally be something that ends up being legal directly,
1829 // but in theory if a target has very wide vectors and an annoyingly
1830 // restricted set of legal types, this split can chain to build things up.
1832 DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1833 DAG.getTargetConstant(0, DL, TLI.getPointerTy())) :
1834 DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1837 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1838 assert(N->getValueType(0).isVector() &&
1839 N->getOperand(0).getValueType().isVector() &&
1840 "Operand types must be vectors");
1841 // The result has a legal vector type, but the input needs splitting.
1842 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1844 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1845 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1846 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1847 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1848 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1850 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1851 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1852 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1853 return PromoteTargetBoolean(Con, N->getValueType(0));
1857 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1858 // The result has a legal vector type, but the input needs splitting.
1859 EVT ResVT = N->getValueType(0);
1862 GetSplitVector(N->getOperand(0), Lo, Hi);
1863 EVT InVT = Lo.getValueType();
1865 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1866 InVT.getVectorNumElements());
1868 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1869 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1871 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1876 //===----------------------------------------------------------------------===//
1877 // Result Vector Widening
1878 //===----------------------------------------------------------------------===//
1880 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1881 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1885 // See if the target wants to custom widen this node.
1886 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1889 SDValue Res = SDValue();
1890 switch (N->getOpcode()) {
1893 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1897 llvm_unreachable("Do not know how to widen the result of this operator!");
1899 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1900 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1901 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1902 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1903 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1904 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1905 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1906 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1907 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1908 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1909 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1911 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1912 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1913 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1914 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1915 case ISD::VECTOR_SHUFFLE:
1916 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1919 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1932 Res = WidenVecRes_Binary(N);
1936 case ISD::FCOPYSIGN:
1946 Res = WidenVecRes_BinaryCanTrap(N);
1950 Res = WidenVecRes_POWI(N);
1956 Res = WidenVecRes_Shift(N);
1959 case ISD::ANY_EXTEND:
1960 case ISD::FP_EXTEND:
1962 case ISD::FP_TO_SINT:
1963 case ISD::FP_TO_UINT:
1964 case ISD::SIGN_EXTEND:
1965 case ISD::SINT_TO_FP:
1967 case ISD::UINT_TO_FP:
1968 case ISD::ZERO_EXTEND:
1969 Res = WidenVecRes_Convert(N);
1985 case ISD::FNEARBYINT:
1992 Res = WidenVecRes_Unary(N);
1995 Res = WidenVecRes_Ternary(N);
1999 // If Res is null, the sub-method took care of registering the result.
2001 SetWidenedVector(SDValue(N, ResNo), Res);
2004 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2005 // Ternary op widening.
2007 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2008 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2009 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2010 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2011 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2014 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2015 // Binary op widening.
2017 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2018 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2019 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2020 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
2023 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2024 // Binary op widening for operations that can trap.
2025 unsigned Opcode = N->getOpcode();
2027 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2028 EVT WidenEltVT = WidenVT.getVectorElementType();
2030 unsigned NumElts = VT.getVectorNumElements();
2031 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2032 NumElts = NumElts / 2;
2033 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2036 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2037 // Operation doesn't trap so just widen as normal.
2038 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2039 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2040 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
2043 // No legal vector version so unroll the vector operation and then widen.
2045 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2047 // Since the operation can trap, apply operation on the original vector.
2049 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2050 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2051 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2053 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2054 unsigned ConcatEnd = 0; // Current ConcatOps index.
2055 int Idx = 0; // Current Idx into input vectors.
2057 // NumElts := greatest legal vector size (at most WidenVT)
2058 // while (orig. vector has unhandled elements) {
2059 // take munches of size NumElts from the beginning and add to ConcatOps
2060 // NumElts := next smaller supported vector size or 1
2062 while (CurNumElts != 0) {
2063 while (CurNumElts >= NumElts) {
2064 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2065 DAG.getConstant(Idx, dl,
2066 TLI.getVectorIdxTy()));
2067 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2068 DAG.getConstant(Idx, dl,
2069 TLI.getVectorIdxTy()));
2070 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
2072 CurNumElts -= NumElts;
2075 NumElts = NumElts / 2;
2076 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2077 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2080 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2081 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
2083 DAG.getConstant(Idx, dl,
2084 TLI.getVectorIdxTy()));
2085 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
2087 DAG.getConstant(Idx, dl,
2088 TLI.getVectorIdxTy()));
2089 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2096 // Check to see if we have a single operation with the widen type.
2097 if (ConcatEnd == 1) {
2098 VT = ConcatOps[0].getValueType();
2100 return ConcatOps[0];
2103 // while (Some element of ConcatOps is not of type MaxVT) {
2104 // From the end of ConcatOps, collect elements of the same type and put
2105 // them into an op of the next larger supported type
2107 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2108 Idx = ConcatEnd - 1;
2109 VT = ConcatOps[Idx--].getValueType();
2110 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2113 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2117 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2118 } while (!TLI.isTypeLegal(NextVT));
2120 if (!VT.isVector()) {
2121 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2122 SDValue VecOp = DAG.getUNDEF(NextVT);
2123 unsigned NumToInsert = ConcatEnd - Idx - 1;
2124 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2125 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
2127 DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
2129 ConcatOps[Idx+1] = VecOp;
2130 ConcatEnd = Idx + 2;
2132 // Vector type, create a CONCAT_VECTORS of type NextVT
2133 SDValue undefVec = DAG.getUNDEF(VT);
2134 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2135 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2136 unsigned RealVals = ConcatEnd - Idx - 1;
2137 unsigned SubConcatEnd = 0;
2138 unsigned SubConcatIdx = Idx + 1;
2139 while (SubConcatEnd < RealVals)
2140 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2141 while (SubConcatEnd < OpsToConcat)
2142 SubConcatOps[SubConcatEnd++] = undefVec;
2143 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2144 NextVT, SubConcatOps);
2145 ConcatEnd = SubConcatIdx + 1;
2149 // Check to see if we have a single operation with the widen type.
2150 if (ConcatEnd == 1) {
2151 VT = ConcatOps[0].getValueType();
2153 return ConcatOps[0];
2156 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2157 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2158 if (NumOps != ConcatEnd ) {
2159 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2160 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2161 ConcatOps[j] = UndefVal;
2163 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2164 makeArrayRef(ConcatOps.data(), NumOps));
2167 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2168 SDValue InOp = N->getOperand(0);
2171 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2172 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2174 EVT InVT = InOp.getValueType();
2175 EVT InEltVT = InVT.getVectorElementType();
2176 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2178 unsigned Opcode = N->getOpcode();
2179 unsigned InVTNumElts = InVT.getVectorNumElements();
2181 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2182 InOp = GetWidenedVector(N->getOperand(0));
2183 InVT = InOp.getValueType();
2184 InVTNumElts = InVT.getVectorNumElements();
2185 if (InVTNumElts == WidenNumElts) {
2186 if (N->getNumOperands() == 1)
2187 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2188 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
2192 if (TLI.isTypeLegal(InWidenVT)) {
2193 // Because the result and the input are different vector types, widening
2194 // the result could create a legal type but widening the input might make
2195 // it an illegal type that might lead to repeatedly splitting the input
2196 // and then widening it. To avoid this, we widen the input only if
2197 // it results in a legal type.
2198 if (WidenNumElts % InVTNumElts == 0) {
2199 // Widen the input and call convert on the widened input vector.
2200 unsigned NumConcat = WidenNumElts/InVTNumElts;
2201 SmallVector<SDValue, 16> Ops(NumConcat);
2203 SDValue UndefVal = DAG.getUNDEF(InVT);
2204 for (unsigned i = 1; i != NumConcat; ++i)
2206 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2207 if (N->getNumOperands() == 1)
2208 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2209 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
2212 if (InVTNumElts % WidenNumElts == 0) {
2213 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2214 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2215 // Extract the input and convert the shorten input vector.
2216 if (N->getNumOperands() == 1)
2217 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2218 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
2222 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2223 SmallVector<SDValue, 16> Ops(WidenNumElts);
2224 EVT EltVT = WidenVT.getVectorElementType();
2225 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2227 for (i=0; i < MinElts; ++i) {
2228 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2229 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
2230 if (N->getNumOperands() == 1)
2231 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2233 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
2236 SDValue UndefVal = DAG.getUNDEF(EltVT);
2237 for (; i < WidenNumElts; ++i)
2240 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2243 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2244 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2245 SDValue InOp = GetWidenedVector(N->getOperand(0));
2246 SDValue ShOp = N->getOperand(1);
2247 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2250 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2251 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2252 SDValue InOp = GetWidenedVector(N->getOperand(0));
2253 SDValue ShOp = N->getOperand(1);
2255 EVT ShVT = ShOp.getValueType();
2256 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2257 ShOp = GetWidenedVector(ShOp);
2258 ShVT = ShOp.getValueType();
2260 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2261 ShVT.getVectorElementType(),
2262 WidenVT.getVectorNumElements());
2263 if (ShVT != ShWidenVT)
2264 ShOp = ModifyToType(ShOp, ShWidenVT);
2266 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2269 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2270 // Unary op widening.
2271 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2272 SDValue InOp = GetWidenedVector(N->getOperand(0));
2273 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2276 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2277 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2278 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2279 cast<VTSDNode>(N->getOperand(1))->getVT()
2280 .getVectorElementType(),
2281 WidenVT.getVectorNumElements());
2282 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2283 return DAG.getNode(N->getOpcode(), SDLoc(N),
2284 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2287 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2288 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2289 return GetWidenedVector(WidenVec);
2292 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2293 SDValue InOp = N->getOperand(0);
2294 EVT InVT = InOp.getValueType();
2295 EVT VT = N->getValueType(0);
2296 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2299 switch (getTypeAction(InVT)) {
2300 case TargetLowering::TypeLegal:
2302 case TargetLowering::TypePromoteInteger:
2303 // If the incoming type is a vector that is being promoted, then
2304 // we know that the elements are arranged differently and that we
2305 // must perform the conversion using a stack slot.
2306 if (InVT.isVector())
2309 // If the InOp is promoted to the same size, convert it. Otherwise,
2310 // fall out of the switch and widen the promoted input.
2311 InOp = GetPromotedInteger(InOp);
2312 InVT = InOp.getValueType();
2313 if (WidenVT.bitsEq(InVT))
2314 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2316 case TargetLowering::TypeSoftenFloat:
2317 case TargetLowering::TypePromoteFloat:
2318 case TargetLowering::TypeExpandInteger:
2319 case TargetLowering::TypeExpandFloat:
2320 case TargetLowering::TypeScalarizeVector:
2321 case TargetLowering::TypeSplitVector:
2323 case TargetLowering::TypeWidenVector:
2324 // If the InOp is widened to the same size, convert it. Otherwise, fall
2325 // out of the switch and widen the widened input.
2326 InOp = GetWidenedVector(InOp);
2327 InVT = InOp.getValueType();
2328 if (WidenVT.bitsEq(InVT))
2329 // The input widens to the same size. Convert to the widen value.
2330 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2334 unsigned WidenSize = WidenVT.getSizeInBits();
2335 unsigned InSize = InVT.getSizeInBits();
2336 // x86mmx is not an acceptable vector element type, so don't try.
2337 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2338 // Determine new input vector type. The new input vector type will use
2339 // the same element type (if its a vector) or use the input type as a
2340 // vector. It is the same size as the type to widen to.
2342 unsigned NewNumElts = WidenSize / InSize;
2343 if (InVT.isVector()) {
2344 EVT InEltVT = InVT.getVectorElementType();
2345 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2346 WidenSize / InEltVT.getSizeInBits());
2348 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2351 if (TLI.isTypeLegal(NewInVT)) {
2352 // Because the result and the input are different vector types, widening
2353 // the result could create a legal type but widening the input might make
2354 // it an illegal type that might lead to repeatedly splitting the input
2355 // and then widening it. To avoid this, we widen the input only if
2356 // it results in a legal type.
2357 SmallVector<SDValue, 16> Ops(NewNumElts);
2358 SDValue UndefVal = DAG.getUNDEF(InVT);
2360 for (unsigned i = 1; i < NewNumElts; ++i)
2364 if (InVT.isVector())
2365 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2367 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2368 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2372 return CreateStackStoreLoad(InOp, WidenVT);
2375 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2377 // Build a vector with undefined for the new nodes.
2378 EVT VT = N->getValueType(0);
2380 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2381 // type. The UNDEFs need to have the same type as the existing operands.
2382 EVT EltVT = N->getOperand(0).getValueType();
2383 unsigned NumElts = VT.getVectorNumElements();
2385 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2386 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2388 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2389 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2390 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2392 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2395 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2396 EVT InVT = N->getOperand(0).getValueType();
2397 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2399 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2400 unsigned NumInElts = InVT.getVectorNumElements();
2401 unsigned NumOperands = N->getNumOperands();
2403 bool InputWidened = false; // Indicates we need to widen the input.
2404 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2405 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2406 // Add undef vectors to widen to correct length.
2407 unsigned NumConcat = WidenVT.getVectorNumElements() /
2408 InVT.getVectorNumElements();
2409 SDValue UndefVal = DAG.getUNDEF(InVT);
2410 SmallVector<SDValue, 16> Ops(NumConcat);
2411 for (unsigned i=0; i < NumOperands; ++i)
2412 Ops[i] = N->getOperand(i);
2413 for (unsigned i = NumOperands; i != NumConcat; ++i)
2415 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2418 InputWidened = true;
2419 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2420 // The inputs and the result are widen to the same value.
2422 for (i=1; i < NumOperands; ++i)
2423 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2426 if (i == NumOperands)
2427 // Everything but the first operand is an UNDEF so just return the
2428 // widened first operand.
2429 return GetWidenedVector(N->getOperand(0));
2431 if (NumOperands == 2) {
2432 // Replace concat of two operands with a shuffle.
2433 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2434 for (unsigned i = 0; i < NumInElts; ++i) {
2436 MaskOps[i + NumInElts] = i + WidenNumElts;
2438 return DAG.getVectorShuffle(WidenVT, dl,
2439 GetWidenedVector(N->getOperand(0)),
2440 GetWidenedVector(N->getOperand(1)),
2446 // Fall back to use extracts and build vector.
2447 EVT EltVT = WidenVT.getVectorElementType();
2448 SmallVector<SDValue, 16> Ops(WidenNumElts);
2450 for (unsigned i=0; i < NumOperands; ++i) {
2451 SDValue InOp = N->getOperand(i);
2453 InOp = GetWidenedVector(InOp);
2454 for (unsigned j=0; j < NumInElts; ++j)
2455 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2456 DAG.getConstant(j, dl, TLI.getVectorIdxTy()));
2458 SDValue UndefVal = DAG.getUNDEF(EltVT);
2459 for (; Idx < WidenNumElts; ++Idx)
2460 Ops[Idx] = UndefVal;
2461 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2464 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2466 SDValue InOp = N->getOperand(0);
2467 SDValue RndOp = N->getOperand(3);
2468 SDValue SatOp = N->getOperand(4);
2470 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2471 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2473 EVT InVT = InOp.getValueType();
2474 EVT InEltVT = InVT.getVectorElementType();
2475 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2477 SDValue DTyOp = DAG.getValueType(WidenVT);
2478 SDValue STyOp = DAG.getValueType(InWidenVT);
2479 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2481 unsigned InVTNumElts = InVT.getVectorNumElements();
2482 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2483 InOp = GetWidenedVector(InOp);
2484 InVT = InOp.getValueType();
2485 InVTNumElts = InVT.getVectorNumElements();
2486 if (InVTNumElts == WidenNumElts)
2487 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2491 if (TLI.isTypeLegal(InWidenVT)) {
2492 // Because the result and the input are different vector types, widening
2493 // the result could create a legal type but widening the input might make
2494 // it an illegal type that might lead to repeatedly splitting the input
2495 // and then widening it. To avoid this, we widen the input only if
2496 // it results in a legal type.
2497 if (WidenNumElts % InVTNumElts == 0) {
2498 // Widen the input and call convert on the widened input vector.
2499 unsigned NumConcat = WidenNumElts/InVTNumElts;
2500 SmallVector<SDValue, 16> Ops(NumConcat);
2502 SDValue UndefVal = DAG.getUNDEF(InVT);
2503 for (unsigned i = 1; i != NumConcat; ++i)
2506 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2507 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2511 if (InVTNumElts % WidenNumElts == 0) {
2512 // Extract the input and convert the shorten input vector.
2513 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2514 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
2515 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2520 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2521 SmallVector<SDValue, 16> Ops(WidenNumElts);
2522 EVT EltVT = WidenVT.getVectorElementType();
2523 DTyOp = DAG.getValueType(EltVT);
2524 STyOp = DAG.getValueType(InEltVT);
2526 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2528 for (i=0; i < MinElts; ++i) {
2529 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2530 DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
2531 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2535 SDValue UndefVal = DAG.getUNDEF(EltVT);
2536 for (; i < WidenNumElts; ++i)
2539 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2542 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2543 EVT VT = N->getValueType(0);
2544 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2545 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2546 SDValue InOp = N->getOperand(0);
2547 SDValue Idx = N->getOperand(1);
2550 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2551 InOp = GetWidenedVector(InOp);
2553 EVT InVT = InOp.getValueType();
2555 // Check if we can just return the input vector after widening.
2556 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2557 if (IdxVal == 0 && InVT == WidenVT)
2560 // Check if we can extract from the vector.
2561 unsigned InNumElts = InVT.getVectorNumElements();
2562 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2563 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2565 // We could try widening the input to the right length but for now, extract
2566 // the original elements, fill the rest with undefs and build a vector.
2567 SmallVector<SDValue, 16> Ops(WidenNumElts);
2568 EVT EltVT = VT.getVectorElementType();
2569 unsigned NumElts = VT.getVectorNumElements();
2571 for (i=0; i < NumElts; ++i)
2572 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2573 DAG.getConstant(IdxVal + i, dl, TLI.getVectorIdxTy()));
2575 SDValue UndefVal = DAG.getUNDEF(EltVT);
2576 for (; i < WidenNumElts; ++i)
2578 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2581 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2582 SDValue InOp = GetWidenedVector(N->getOperand(0));
2583 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2584 InOp.getValueType(), InOp,
2585 N->getOperand(1), N->getOperand(2));
2588 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2589 LoadSDNode *LD = cast<LoadSDNode>(N);
2590 ISD::LoadExtType ExtType = LD->getExtensionType();
2593 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2594 if (ExtType != ISD::NON_EXTLOAD)
2595 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2597 Result = GenWidenVectorLoads(LdChain, LD);
2599 // If we generate a single load, we can use that for the chain. Otherwise,
2600 // build a factor node to remember the multiple loads are independent and
2603 if (LdChain.size() == 1)
2604 NewChain = LdChain[0];
2606 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2608 // Modified the chain - switch anything that used the old chain to use
2610 ReplaceValueWith(SDValue(N, 1), NewChain);
2615 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2617 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2618 SDValue Mask = N->getMask();
2619 EVT MaskVT = Mask.getValueType();
2620 SDValue Src0 = GetWidenedVector(N->getSrc0());
2621 ISD::LoadExtType ExtType = N->getExtensionType();
2624 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2625 Mask = GetWidenedVector(Mask);
2627 EVT BoolVT = getSetCCResultType(WidenVT);
2629 // We can't use ModifyToType() because we should fill the mask with
2631 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2632 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2634 unsigned NumConcat = WidenNumElts / MaskNumElts;
2635 SmallVector<SDValue, 16> Ops(NumConcat);
2636 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2638 for (unsigned i = 1; i != NumConcat; ++i)
2641 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2644 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2645 Mask, Src0, N->getMemoryVT(),
2646 N->getMemOperand(), ExtType);
2647 // Legalized the chain result - switch anything that used the old chain to
2649 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2653 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2654 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2655 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2656 WidenVT, N->getOperand(0));
2659 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2660 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2661 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2663 SDValue Cond1 = N->getOperand(0);
2664 EVT CondVT = Cond1.getValueType();
2665 if (CondVT.isVector()) {
2666 EVT CondEltVT = CondVT.getVectorElementType();
2667 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2668 CondEltVT, WidenNumElts);
2669 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2670 Cond1 = GetWidenedVector(Cond1);
2672 // If we have to split the condition there is no point in widening the
2673 // select. This would result in an cycle of widening the select ->
2674 // widening the condition operand -> splitting the condition operand ->
2675 // splitting the select -> widening the select. Instead split this select
2676 // further and widen the resulting type.
2677 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2678 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2679 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2683 if (Cond1.getValueType() != CondWidenVT)
2684 Cond1 = ModifyToType(Cond1, CondWidenVT);
2687 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2688 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2689 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2690 return DAG.getNode(N->getOpcode(), SDLoc(N),
2691 WidenVT, Cond1, InOp1, InOp2);
2694 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2695 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2696 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2697 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2698 InOp1.getValueType(), N->getOperand(0),
2699 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2702 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2703 assert(N->getValueType(0).isVector() ==
2704 N->getOperand(0).getValueType().isVector() &&
2705 "Scalar/Vector type mismatch");
2706 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2708 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2709 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2710 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2711 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2712 InOp1, InOp2, N->getOperand(2));
2715 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2716 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2717 return DAG.getUNDEF(WidenVT);
2720 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2721 EVT VT = N->getValueType(0);
2724 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2725 unsigned NumElts = VT.getVectorNumElements();
2726 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2728 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2729 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2731 // Adjust mask based on new input vector length.
2732 SmallVector<int, 16> NewMask;
2733 for (unsigned i = 0; i != NumElts; ++i) {
2734 int Idx = N->getMaskElt(i);
2735 if (Idx < (int)NumElts)
2736 NewMask.push_back(Idx);
2738 NewMask.push_back(Idx - NumElts + WidenNumElts);
2740 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2741 NewMask.push_back(-1);
2742 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2745 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2746 assert(N->getValueType(0).isVector() &&
2747 N->getOperand(0).getValueType().isVector() &&
2748 "Operands must be vectors");
2749 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2750 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2752 SDValue InOp1 = N->getOperand(0);
2753 EVT InVT = InOp1.getValueType();
2754 assert(InVT.isVector() && "can not widen non-vector type");
2755 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2756 InVT.getVectorElementType(), WidenNumElts);
2758 // The input and output types often differ here, and it could be that while
2759 // we'd prefer to widen the result type, the input operands have been split.
2760 // In this case, we also need to split the result of this node as well.
2761 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2762 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2763 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2767 InOp1 = GetWidenedVector(InOp1);
2768 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2770 // Assume that the input and output will be widen appropriately. If not,
2771 // we will have to unroll it at some point.
2772 assert(InOp1.getValueType() == WidenInVT &&
2773 InOp2.getValueType() == WidenInVT &&
2774 "Input not widened to expected type!");
2776 return DAG.getNode(ISD::SETCC, SDLoc(N),
2777 WidenVT, InOp1, InOp2, N->getOperand(2));
2781 //===----------------------------------------------------------------------===//
2782 // Widen Vector Operand
2783 //===----------------------------------------------------------------------===//
2784 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2785 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2788 SDValue Res = SDValue();
2790 // See if the target wants to custom widen this node.
2791 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2794 switch (N->getOpcode()) {
2797 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2801 llvm_unreachable("Do not know how to widen this operator's operand!");
2803 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2804 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2805 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2806 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2807 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2808 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2809 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2811 case ISD::ANY_EXTEND:
2812 case ISD::SIGN_EXTEND:
2813 case ISD::ZERO_EXTEND:
2814 Res = WidenVecOp_EXTEND(N);
2817 case ISD::FP_EXTEND:
2818 case ISD::FP_TO_SINT:
2819 case ISD::FP_TO_UINT:
2820 case ISD::SINT_TO_FP:
2821 case ISD::UINT_TO_FP:
2823 Res = WidenVecOp_Convert(N);
2827 // If Res is null, the sub-method took care of registering the result.
2828 if (!Res.getNode()) return false;
2830 // If the result is N, the sub-method updated N in place. Tell the legalizer
2832 if (Res.getNode() == N)
2836 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2837 "Invalid operand expansion");
2839 ReplaceValueWith(SDValue(N, 0), Res);
2843 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2845 EVT VT = N->getValueType(0);
2847 SDValue InOp = N->getOperand(0);
2848 // If some legalization strategy other than widening is used on the operand,
2849 // we can't safely assume that just extending the low lanes is the correct
2851 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2852 return WidenVecOp_Convert(N);
2853 InOp = GetWidenedVector(InOp);
2854 assert(VT.getVectorNumElements() <
2855 InOp.getValueType().getVectorNumElements() &&
2856 "Input wasn't widened!");
2858 // We may need to further widen the operand until it has the same total
2859 // vector size as the result.
2860 EVT InVT = InOp.getValueType();
2861 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2862 EVT InEltVT = InVT.getVectorElementType();
2863 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2864 EVT FixedVT = (MVT::SimpleValueType)i;
2865 EVT FixedEltVT = FixedVT.getVectorElementType();
2866 if (TLI.isTypeLegal(FixedVT) &&
2867 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2868 FixedEltVT == InEltVT) {
2869 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2870 "Not enough elements in the fixed type for the operand!");
2871 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2872 "We can't have the same type as we started with!");
2873 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2874 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
2875 DAG.getUNDEF(FixedVT), InOp,
2876 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2878 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2879 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2883 InVT = InOp.getValueType();
2884 if (InVT.getSizeInBits() != VT.getSizeInBits())
2885 // We couldn't find a legal vector type that was a widening of the input
2886 // and could be extended in-register to the result type, so we have to
2888 return WidenVecOp_Convert(N);
2891 // Use special DAG nodes to represent the operation of extending the
2893 switch (N->getOpcode()) {
2895 llvm_unreachable("Extend legalization on on extend operation!");
2896 case ISD::ANY_EXTEND:
2897 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2898 case ISD::SIGN_EXTEND:
2899 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2900 case ISD::ZERO_EXTEND:
2901 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2905 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2906 // Since the result is legal and the input is illegal, it is unlikely
2907 // that we can fix the input to a legal type so unroll the convert
2908 // into some scalar code and create a nasty build vector.
2909 EVT VT = N->getValueType(0);
2910 EVT EltVT = VT.getVectorElementType();
2912 unsigned NumElts = VT.getVectorNumElements();
2913 SDValue InOp = N->getOperand(0);
2914 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2915 InOp = GetWidenedVector(InOp);
2916 EVT InVT = InOp.getValueType();
2917 EVT InEltVT = InVT.getVectorElementType();
2919 unsigned Opcode = N->getOpcode();
2920 SmallVector<SDValue, 16> Ops(NumElts);
2921 for (unsigned i=0; i < NumElts; ++i)
2922 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2923 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2924 DAG.getConstant(i, dl,
2925 TLI.getVectorIdxTy())));
2927 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2930 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2931 EVT VT = N->getValueType(0);
2932 SDValue InOp = GetWidenedVector(N->getOperand(0));
2933 EVT InWidenVT = InOp.getValueType();
2936 // Check if we can convert between two legal vector types and extract.
2937 unsigned InWidenSize = InWidenVT.getSizeInBits();
2938 unsigned Size = VT.getSizeInBits();
2939 // x86mmx is not an acceptable vector element type, so don't try.
2940 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2941 unsigned NewNumElts = InWidenSize / Size;
2942 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2943 if (TLI.isTypeLegal(NewVT)) {
2944 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2945 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2946 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
2950 return CreateStackStoreLoad(InOp, VT);
2953 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2954 // If the input vector is not legal, it is likely that we will not find a
2955 // legal vector of the same size. Replace the concatenate vector with a
2956 // nasty build vector.
2957 EVT VT = N->getValueType(0);
2958 EVT EltVT = VT.getVectorElementType();
2960 unsigned NumElts = VT.getVectorNumElements();
2961 SmallVector<SDValue, 16> Ops(NumElts);
2963 EVT InVT = N->getOperand(0).getValueType();
2964 unsigned NumInElts = InVT.getVectorNumElements();
2967 unsigned NumOperands = N->getNumOperands();
2968 for (unsigned i=0; i < NumOperands; ++i) {
2969 SDValue InOp = N->getOperand(i);
2970 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2971 InOp = GetWidenedVector(InOp);
2972 for (unsigned j=0; j < NumInElts; ++j)
2973 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2974 DAG.getConstant(j, dl, TLI.getVectorIdxTy()));
2976 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2979 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2980 SDValue InOp = GetWidenedVector(N->getOperand(0));
2981 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
2982 N->getValueType(0), InOp, N->getOperand(1));
2985 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2986 SDValue InOp = GetWidenedVector(N->getOperand(0));
2987 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2988 N->getValueType(0), InOp, N->getOperand(1));
2991 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2992 // We have to widen the value but we want only to store the original
2994 StoreSDNode *ST = cast<StoreSDNode>(N);
2996 SmallVector<SDValue, 16> StChain;
2997 if (ST->isTruncatingStore())
2998 GenWidenVectorTruncStores(StChain, ST);
3000 GenWidenVectorStores(StChain, ST);
3002 if (StChain.size() == 1)
3005 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3008 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3009 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3010 SDValue Mask = MST->getMask();
3011 EVT MaskVT = Mask.getValueType();
3012 SDValue StVal = MST->getValue();
3014 SDValue WideVal = GetWidenedVector(StVal);
3017 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3018 Mask = GetWidenedVector(Mask);
3020 // The mask should be widened as well
3021 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3022 // We can't use ModifyToType() because we should fill the mask with
3024 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3025 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3027 unsigned NumConcat = WidenNumElts / MaskNumElts;
3028 SmallVector<SDValue, 16> Ops(NumConcat);
3029 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3031 for (unsigned i = 1; i != NumConcat; ++i)
3034 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3036 assert(Mask.getValueType().getVectorNumElements() ==
3037 WideVal.getValueType().getVectorNumElements() &&
3038 "Mask and data vectors should have the same number of elements");
3039 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3040 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3044 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3045 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3046 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3049 // WARNING: In this code we widen the compare instruction with garbage.
3050 // This garbage may contain denormal floats which may be slow. Is this a real
3051 // concern ? Should we zero the unused lanes if this is a float compare ?
3053 // Get a new SETCC node to compare the newly widened operands.
3054 // Only some of the compared elements are legal.
3055 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
3056 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3057 SVT, InOp0, InOp1, N->getOperand(2));
3059 // Extract the needed results from the result vector.
3060 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3061 SVT.getVectorElementType(),
3062 N->getValueType(0).getVectorNumElements());
3063 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
3065 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3067 return PromoteTargetBoolean(CC, N->getValueType(0));
3071 //===----------------------------------------------------------------------===//
3072 // Vector Widening Utilities
3073 //===----------------------------------------------------------------------===//
3075 // Utility function to find the type to chop up a widen vector for load/store
3076 // TLI: Target lowering used to determine legal types.
3077 // Width: Width left need to load/store.
3078 // WidenVT: The widen vector type to load to/store from
3079 // Align: If 0, don't allow use of a wider type
3080 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3082 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3083 unsigned Width, EVT WidenVT,
3084 unsigned Align = 0, unsigned WidenEx = 0) {
3085 EVT WidenEltVT = WidenVT.getVectorElementType();
3086 unsigned WidenWidth = WidenVT.getSizeInBits();
3087 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3088 unsigned AlignInBits = Align*8;
3090 // If we have one element to load/store, return it.
3091 EVT RetVT = WidenEltVT;
3092 if (Width == WidenEltWidth)
3095 // See if there is larger legal integer than the element type to load/store
3097 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3098 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3099 EVT MemVT((MVT::SimpleValueType) VT);
3100 unsigned MemVTWidth = MemVT.getSizeInBits();
3101 if (MemVT.getSizeInBits() <= WidenEltWidth)
3103 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3104 if ((Action == TargetLowering::TypeLegal ||
3105 Action == TargetLowering::TypePromoteInteger) &&
3106 (WidenWidth % MemVTWidth) == 0 &&
3107 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3108 (MemVTWidth <= Width ||
3109 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3115 // See if there is a larger vector type to load/store that has the same vector
3116 // element type and is evenly divisible with the WidenVT.
3117 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3118 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3119 EVT MemVT = (MVT::SimpleValueType) VT;
3120 unsigned MemVTWidth = MemVT.getSizeInBits();
3121 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3122 (WidenWidth % MemVTWidth) == 0 &&
3123 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3124 (MemVTWidth <= Width ||
3125 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3126 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3134 // Builds a vector type from scalar loads
3135 // VecTy: Resulting Vector type
3136 // LDOps: Load operators to build a vector type
3137 // [Start,End) the list of loads to use.
3138 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3139 SmallVectorImpl<SDValue> &LdOps,
3140 unsigned Start, unsigned End) {
3141 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3142 SDLoc dl(LdOps[Start]);
3143 EVT LdTy = LdOps[Start].getValueType();
3144 unsigned Width = VecTy.getSizeInBits();
3145 unsigned NumElts = Width / LdTy.getSizeInBits();
3146 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3149 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3151 for (unsigned i = Start + 1; i != End; ++i) {
3152 EVT NewLdTy = LdOps[i].getValueType();
3153 if (NewLdTy != LdTy) {
3154 NumElts = Width / NewLdTy.getSizeInBits();
3155 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3156 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3157 // Readjust position and vector position based on new load type
3158 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3161 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3162 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy()));
3164 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3167 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3169 // The strategy assumes that we can efficiently load powers of two widths.
3170 // The routines chops the vector into the largest vector loads with the same
3171 // element type or scalar loads and then recombines it to the widen vector
3173 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3174 unsigned WidenWidth = WidenVT.getSizeInBits();
3175 EVT LdVT = LD->getMemoryVT();
3177 assert(LdVT.isVector() && WidenVT.isVector());
3178 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3181 SDValue Chain = LD->getChain();
3182 SDValue BasePtr = LD->getBasePtr();
3183 unsigned Align = LD->getAlignment();
3184 bool isVolatile = LD->isVolatile();
3185 bool isNonTemporal = LD->isNonTemporal();
3186 bool isInvariant = LD->isInvariant();
3187 AAMDNodes AAInfo = LD->getAAInfo();
3189 int LdWidth = LdVT.getSizeInBits();
3190 int WidthDiff = WidenWidth - LdWidth; // Difference
3191 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3193 // Find the vector type that can load from.
3194 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3195 int NewVTWidth = NewVT.getSizeInBits();
3196 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3197 isVolatile, isNonTemporal, isInvariant, Align,
3199 LdChain.push_back(LdOp.getValue(1));
3201 // Check if we can load the element with one instruction
3202 if (LdWidth <= NewVTWidth) {
3203 if (!NewVT.isVector()) {
3204 unsigned NumElts = WidenWidth / NewVTWidth;
3205 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3206 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3207 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3209 if (NewVT == WidenVT)
3212 assert(WidenWidth % NewVTWidth == 0);
3213 unsigned NumConcat = WidenWidth / NewVTWidth;
3214 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3215 SDValue UndefVal = DAG.getUNDEF(NewVT);
3216 ConcatOps[0] = LdOp;
3217 for (unsigned i = 1; i != NumConcat; ++i)
3218 ConcatOps[i] = UndefVal;
3219 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3222 // Load vector by using multiple loads from largest vector to scalar
3223 SmallVector<SDValue, 16> LdOps;
3224 LdOps.push_back(LdOp);
3226 LdWidth -= NewVTWidth;
3227 unsigned Offset = 0;
3229 while (LdWidth > 0) {
3230 unsigned Increment = NewVTWidth / 8;
3231 Offset += Increment;
3232 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3233 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3236 if (LdWidth < NewVTWidth) {
3237 // Our current type we are using is too large, find a better size
3238 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3239 NewVTWidth = NewVT.getSizeInBits();
3240 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3241 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3242 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3244 LdChain.push_back(L.getValue(1));
3245 if (L->getValueType(0).isVector()) {
3246 SmallVector<SDValue, 16> Loads;
3248 unsigned size = L->getValueSizeInBits(0);
3249 while (size < LdOp->getValueSizeInBits(0)) {
3250 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3251 size += L->getValueSizeInBits(0);
3253 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3256 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3257 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3258 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3260 LdChain.push_back(L.getValue(1));
3266 LdWidth -= NewVTWidth;
3269 // Build the vector from the loads operations
3270 unsigned End = LdOps.size();
3271 if (!LdOps[0].getValueType().isVector())
3272 // All the loads are scalar loads.
3273 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3275 // If the load contains vectors, build the vector using concat vector.
3276 // All of the vectors used to loads are power of 2 and the scalars load
3277 // can be combined to make a power of 2 vector.
3278 SmallVector<SDValue, 16> ConcatOps(End);
3281 EVT LdTy = LdOps[i].getValueType();
3282 // First combine the scalar loads to a vector
3283 if (!LdTy.isVector()) {
3284 for (--i; i >= 0; --i) {
3285 LdTy = LdOps[i].getValueType();
3286 if (LdTy.isVector())
3289 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3291 ConcatOps[--Idx] = LdOps[i];
3292 for (--i; i >= 0; --i) {
3293 EVT NewLdTy = LdOps[i].getValueType();
3294 if (NewLdTy != LdTy) {
3295 // Create a larger vector
3296 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3297 makeArrayRef(&ConcatOps[Idx], End - Idx));
3301 ConcatOps[--Idx] = LdOps[i];
3304 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3305 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3306 makeArrayRef(&ConcatOps[Idx], End - Idx));
3308 // We need to fill the rest with undefs to build the vector
3309 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3310 SmallVector<SDValue, 16> WidenOps(NumOps);
3311 SDValue UndefVal = DAG.getUNDEF(LdTy);
3314 for (; i != End-Idx; ++i)
3315 WidenOps[i] = ConcatOps[Idx+i];
3316 for (; i != NumOps; ++i)
3317 WidenOps[i] = UndefVal;
3319 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3323 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3325 ISD::LoadExtType ExtType) {
3326 // For extension loads, it may not be more efficient to chop up the vector
3327 // and then extended it. Instead, we unroll the load and build a new vector.
3328 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3329 EVT LdVT = LD->getMemoryVT();
3331 assert(LdVT.isVector() && WidenVT.isVector());
3334 SDValue Chain = LD->getChain();
3335 SDValue BasePtr = LD->getBasePtr();
3336 unsigned Align = LD->getAlignment();
3337 bool isVolatile = LD->isVolatile();
3338 bool isNonTemporal = LD->isNonTemporal();
3339 bool isInvariant = LD->isInvariant();
3340 AAMDNodes AAInfo = LD->getAAInfo();
3342 EVT EltVT = WidenVT.getVectorElementType();
3343 EVT LdEltVT = LdVT.getVectorElementType();
3344 unsigned NumElts = LdVT.getVectorNumElements();
3346 // Load each element and widen
3347 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3348 SmallVector<SDValue, 16> Ops(WidenNumElts);
3349 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3350 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3351 LD->getPointerInfo(),
3352 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3354 LdChain.push_back(Ops[0].getValue(1));
3355 unsigned i = 0, Offset = Increment;
3356 for (i=1; i < NumElts; ++i, Offset += Increment) {
3357 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3359 DAG.getConstant(Offset, dl,
3360 BasePtr.getValueType()));
3361 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3362 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3363 isVolatile, isNonTemporal, isInvariant, Align,
3365 LdChain.push_back(Ops[i].getValue(1));
3368 // Fill the rest with undefs
3369 SDValue UndefVal = DAG.getUNDEF(EltVT);
3370 for (; i != WidenNumElts; ++i)
3373 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3377 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3379 // The strategy assumes that we can efficiently store powers of two widths.
3380 // The routines chops the vector into the largest vector stores with the same
3381 // element type or scalar stores.
3382 SDValue Chain = ST->getChain();
3383 SDValue BasePtr = ST->getBasePtr();
3384 unsigned Align = ST->getAlignment();
3385 bool isVolatile = ST->isVolatile();
3386 bool isNonTemporal = ST->isNonTemporal();
3387 AAMDNodes AAInfo = ST->getAAInfo();
3388 SDValue ValOp = GetWidenedVector(ST->getValue());
3391 EVT StVT = ST->getMemoryVT();
3392 unsigned StWidth = StVT.getSizeInBits();
3393 EVT ValVT = ValOp.getValueType();
3394 unsigned ValWidth = ValVT.getSizeInBits();
3395 EVT ValEltVT = ValVT.getVectorElementType();
3396 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3397 assert(StVT.getVectorElementType() == ValEltVT);
3399 int Idx = 0; // current index to store
3400 unsigned Offset = 0; // offset from base to store
3401 while (StWidth != 0) {
3402 // Find the largest vector type we can store with
3403 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3404 unsigned NewVTWidth = NewVT.getSizeInBits();
3405 unsigned Increment = NewVTWidth / 8;
3406 if (NewVT.isVector()) {
3407 unsigned NumVTElts = NewVT.getVectorNumElements();
3409 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3410 DAG.getConstant(Idx, dl,
3411 TLI.getVectorIdxTy()));
3412 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3413 ST->getPointerInfo().getWithOffset(Offset),
3414 isVolatile, isNonTemporal,
3415 MinAlign(Align, Offset), AAInfo));
3416 StWidth -= NewVTWidth;
3417 Offset += Increment;
3419 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3420 DAG.getConstant(Increment, dl,
3421 BasePtr.getValueType()));
3422 } while (StWidth != 0 && StWidth >= NewVTWidth);
3424 // Cast the vector to the scalar type we can store
3425 unsigned NumElts = ValWidth / NewVTWidth;
3426 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3427 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3428 // Readjust index position based on new vector type
3429 Idx = Idx * ValEltWidth / NewVTWidth;
3431 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3432 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy()));
3433 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3434 ST->getPointerInfo().getWithOffset(Offset),
3435 isVolatile, isNonTemporal,
3436 MinAlign(Align, Offset), AAInfo));
3437 StWidth -= NewVTWidth;
3438 Offset += Increment;
3439 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3440 DAG.getConstant(Increment, dl,
3441 BasePtr.getValueType()));
3442 } while (StWidth != 0 && StWidth >= NewVTWidth);
3443 // Restore index back to be relative to the original widen element type
3444 Idx = Idx * NewVTWidth / ValEltWidth;
3450 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3452 // For extension loads, it may not be more efficient to truncate the vector
3453 // and then store it. Instead, we extract each element and then store it.
3454 SDValue Chain = ST->getChain();
3455 SDValue BasePtr = ST->getBasePtr();
3456 unsigned Align = ST->getAlignment();
3457 bool isVolatile = ST->isVolatile();
3458 bool isNonTemporal = ST->isNonTemporal();
3459 AAMDNodes AAInfo = ST->getAAInfo();
3460 SDValue ValOp = GetWidenedVector(ST->getValue());
3463 EVT StVT = ST->getMemoryVT();
3464 EVT ValVT = ValOp.getValueType();
3466 // It must be true that we the widen vector type is bigger than where
3467 // we need to store.
3468 assert(StVT.isVector() && ValOp.getValueType().isVector());
3469 assert(StVT.bitsLT(ValOp.getValueType()));
3471 // For truncating stores, we can not play the tricks of chopping legal
3472 // vector types and bit cast it to the right type. Instead, we unroll
3474 EVT StEltVT = StVT.getVectorElementType();
3475 EVT ValEltVT = ValVT.getVectorElementType();
3476 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3477 unsigned NumElts = StVT.getVectorNumElements();
3478 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3479 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3480 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3481 ST->getPointerInfo(), StEltVT,
3482 isVolatile, isNonTemporal, Align,
3484 unsigned Offset = Increment;
3485 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3486 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3488 DAG.getConstant(Offset, dl,
3489 BasePtr.getValueType()));
3490 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3491 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3492 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3493 ST->getPointerInfo().getWithOffset(Offset),
3494 StEltVT, isVolatile, isNonTemporal,
3495 MinAlign(Align, Offset), AAInfo));
3499 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3500 /// input vector must have the same element type as NVT.
3501 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3502 // Note that InOp might have been widened so it might already have
3503 // the right width or it might need be narrowed.
3504 EVT InVT = InOp.getValueType();
3505 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3506 "input and widen element type must match");
3509 // Check if InOp already has the right width.
3513 unsigned InNumElts = InVT.getVectorNumElements();
3514 unsigned WidenNumElts = NVT.getVectorNumElements();
3515 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3516 unsigned NumConcat = WidenNumElts / InNumElts;
3517 SmallVector<SDValue, 16> Ops(NumConcat);
3518 SDValue UndefVal = DAG.getUNDEF(InVT);
3520 for (unsigned i = 1; i != NumConcat; ++i)
3523 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3526 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3527 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3528 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3530 // Fall back to extract and build.
3531 SmallVector<SDValue, 16> Ops(WidenNumElts);
3532 EVT EltVT = NVT.getVectorElementType();
3533 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3535 for (Idx = 0; Idx < MinNumElts; ++Idx)
3536 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3537 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
3539 SDValue UndefVal = DAG.getUNDEF(EltVT);
3540 for ( ; Idx < WidenNumElts; ++Idx)
3541 Ops[Idx] = UndefVal;
3542 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);