1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
59 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
60 case ISD::CONVERT_RNDSAT:
61 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
62 case ISD::CTLZ_ZERO_UNDEF:
63 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
64 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
65 case ISD::CTTZ_ZERO_UNDEF:
66 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
67 case ISD::EXTRACT_VECTOR_ELT:
68 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
69 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
70 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
71 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
72 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
73 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
74 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
78 case ISD::UMAX: Res = PromoteIntRes_SimpleIntBinOp(N); break;
79 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
80 case ISD::SIGN_EXTEND_INREG:
81 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
82 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
83 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
84 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
85 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
86 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
88 case ISD::EXTRACT_SUBVECTOR:
89 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
90 case ISD::VECTOR_SHUFFLE:
91 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
92 case ISD::INSERT_VECTOR_ELT:
93 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
94 case ISD::BUILD_VECTOR:
95 Res = PromoteIntRes_BUILD_VECTOR(N); break;
96 case ISD::SCALAR_TO_VECTOR:
97 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
98 case ISD::CONCAT_VECTORS:
99 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
101 case ISD::SIGN_EXTEND:
102 case ISD::ZERO_EXTEND:
103 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
105 case ISD::FP_TO_SINT:
106 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
108 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
115 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
118 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
121 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
124 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
126 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
128 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
130 case ISD::ATOMIC_LOAD:
131 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
133 case ISD::ATOMIC_LOAD_ADD:
134 case ISD::ATOMIC_LOAD_SUB:
135 case ISD::ATOMIC_LOAD_AND:
136 case ISD::ATOMIC_LOAD_OR:
137 case ISD::ATOMIC_LOAD_XOR:
138 case ISD::ATOMIC_LOAD_NAND:
139 case ISD::ATOMIC_LOAD_MIN:
140 case ISD::ATOMIC_LOAD_MAX:
141 case ISD::ATOMIC_LOAD_UMIN:
142 case ISD::ATOMIC_LOAD_UMAX:
143 case ISD::ATOMIC_SWAP:
144 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
146 case ISD::ATOMIC_CMP_SWAP:
147 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
148 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
152 // If the result is null then the sub-method took care of registering it.
154 SetPromotedInteger(SDValue(N, ResNo), Res);
157 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
159 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
160 return GetPromotedInteger(Op);
163 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
164 // Sign-extend the new bits, and continue the assertion.
165 SDValue Op = SExtPromotedInteger(N->getOperand(0));
166 return DAG.getNode(ISD::AssertSext, SDLoc(N),
167 Op.getValueType(), Op, N->getOperand(1));
170 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
171 // Zero the new bits, and continue the assertion.
172 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
173 return DAG.getNode(ISD::AssertZext, SDLoc(N),
174 Op.getValueType(), Op, N->getOperand(1));
177 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
178 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
179 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
180 N->getMemoryVT(), ResVT,
181 N->getChain(), N->getBasePtr(),
182 N->getMemOperand(), N->getOrdering(),
184 // Legalized the chain result - switch anything that used the old chain to
186 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
190 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
191 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
192 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
194 N->getChain(), N->getBasePtr(),
195 Op2, N->getMemOperand(), N->getOrdering(),
197 // Legalized the chain result - switch anything that used the old chain to
199 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
203 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
206 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
207 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
208 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
210 // Only use the result of getSetCCResultType if it is legal,
211 // otherwise just use the promoted result type (NVT).
212 if (!TLI.isTypeLegal(SVT))
215 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
216 SDValue Res = DAG.getAtomicCmpSwap(
217 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
218 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
219 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
221 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
222 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
223 return Res.getValue(1);
226 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
227 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
229 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
230 SDValue Res = DAG.getAtomicCmpSwap(
231 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
232 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
233 N->getFailureOrdering(), N->getSynchScope());
234 // Update the use to N with the newly created Res.
235 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
236 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
240 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
241 SDValue InOp = N->getOperand(0);
242 EVT InVT = InOp.getValueType();
243 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
244 EVT OutVT = N->getValueType(0);
245 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
248 switch (getTypeAction(InVT)) {
249 case TargetLowering::TypeLegal:
251 case TargetLowering::TypePromoteInteger:
252 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
253 // The input promotes to the same size. Convert the promoted value.
254 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
256 case TargetLowering::TypeSoftenFloat:
257 // Promote the integer operand by hand.
258 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
259 case TargetLowering::TypePromoteFloat: {
260 // Convert the promoted float by hand.
261 if (NOutVT.bitsEq(NInVT)) {
262 SDValue PromotedOp = GetPromotedFloat(InOp);
263 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
264 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
265 DAG.getValueType(OutVT));
269 case TargetLowering::TypeExpandInteger:
270 case TargetLowering::TypeExpandFloat:
272 case TargetLowering::TypeScalarizeVector:
273 // Convert the element to an integer and promote it by hand.
274 if (!NOutVT.isVector())
275 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
276 BitConvertToInteger(GetScalarizedVector(InOp)));
278 case TargetLowering::TypeSplitVector: {
279 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
280 // pieces of the input into integers and reassemble in the final type.
282 GetSplitVector(N->getOperand(0), Lo, Hi);
283 Lo = BitConvertToInteger(Lo);
284 Hi = BitConvertToInteger(Hi);
286 if (DAG.getDataLayout().isBigEndian())
289 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
290 EVT::getIntegerVT(*DAG.getContext(),
291 NOutVT.getSizeInBits()),
292 JoinIntegers(Lo, Hi));
293 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
295 case TargetLowering::TypeWidenVector:
296 // The input is widened to the same size. Convert to the widened value.
297 // Make sure that the outgoing value is not a vector, because this would
298 // make us bitcast between two vectors which are legalized in different ways.
299 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
300 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
303 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
304 CreateStackStoreLoad(InOp, OutVT));
307 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
308 SDValue Op = GetPromotedInteger(N->getOperand(0));
309 EVT OVT = N->getValueType(0);
310 EVT NVT = Op.getValueType();
313 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
315 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
316 DAG.getConstant(DiffBits, dl,
317 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
320 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
321 SDValue Op = GetPromotedInteger(N->getOperand(0));
322 EVT OVT = N->getValueType(0);
323 EVT NVT = Op.getValueType();
326 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
328 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
329 DAG.getConstant(DiffBits, dl,
330 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
333 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
334 // The pair element type may be legal, or may not promote to the same type as
335 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
336 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
337 TLI.getTypeToTransformTo(*DAG.getContext(),
338 N->getValueType(0)), JoinIntegers(N->getOperand(0),
342 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
343 EVT VT = N->getValueType(0);
344 // FIXME there is no actual debug info here
346 // Zero extend things like i1, sign extend everything else. It shouldn't
347 // matter in theory which one we pick, but this tends to give better code?
348 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
349 SDValue Result = DAG.getNode(Opc, dl,
350 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
352 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
356 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
357 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
358 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
359 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
360 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
361 "can only promote integers");
362 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
363 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
364 N->getOperand(1), N->getOperand(2),
365 N->getOperand(3), N->getOperand(4), CvtCode);
368 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
369 // Zero extend to the promoted type and do the count there.
370 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
372 EVT OVT = N->getValueType(0);
373 EVT NVT = Op.getValueType();
374 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
375 // Subtract off the extra leading bits in the bigger type.
377 ISD::SUB, dl, NVT, Op,
378 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
382 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
383 // Zero extend to the promoted type and do the count there.
384 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
385 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
388 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
389 SDValue Op = GetPromotedInteger(N->getOperand(0));
390 EVT OVT = N->getValueType(0);
391 EVT NVT = Op.getValueType();
393 if (N->getOpcode() == ISD::CTTZ) {
394 // The count is the same in the promoted type except if the original
395 // value was zero. This can be handled by setting the bit just off
396 // the top of the original type.
397 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
398 OVT.getScalarSizeInBits());
399 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
401 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
404 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
406 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
407 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
411 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
412 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
413 unsigned NewOpc = N->getOpcode();
416 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
417 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
418 // and SINT conversions are Custom, there is no way to tell which is
419 // preferable. We choose SINT because that's the right thing on PPC.)
420 if (N->getOpcode() == ISD::FP_TO_UINT &&
421 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
422 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
423 NewOpc = ISD::FP_TO_SINT;
425 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
427 // Assert that the converted value fits in the original type. If it doesn't
428 // (eg: because the value being converted is too big), then the result of the
429 // original operation was undefined anyway, so the assert is still correct.
430 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
431 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
432 DAG.getValueType(N->getValueType(0).getScalarType()));
435 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
436 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
439 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
441 return DAG.getNode(ISD::AssertZext, dl,
442 NVT, Res, DAG.getValueType(N->getValueType(0)));
445 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
446 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
449 if (getTypeAction(N->getOperand(0).getValueType())
450 == TargetLowering::TypePromoteInteger) {
451 SDValue Res = GetPromotedInteger(N->getOperand(0));
452 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
454 // If the result and operand types are the same after promotion, simplify
455 // to an in-register extension.
456 if (NVT == Res.getValueType()) {
457 // The high bits are not guaranteed to be anything. Insert an extend.
458 if (N->getOpcode() == ISD::SIGN_EXTEND)
459 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
460 DAG.getValueType(N->getOperand(0).getValueType()));
461 if (N->getOpcode() == ISD::ZERO_EXTEND)
462 return DAG.getZeroExtendInReg(Res, dl,
463 N->getOperand(0).getValueType().getScalarType());
464 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
469 // Otherwise, just extend the original operand all the way to the larger type.
470 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
473 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
474 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
475 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
476 ISD::LoadExtType ExtType =
477 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
479 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
480 N->getMemoryVT(), N->getMemOperand());
482 // Legalized the chain result - switch anything that used the old chain to
484 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
488 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
489 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
490 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
492 SDValue Mask = N->getMask();
493 EVT NewMaskVT = getSetCCResultType(NVT);
494 if (NewMaskVT != N->getMask().getValueType())
495 Mask = PromoteTargetBoolean(Mask, NewMaskVT);
498 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
499 Mask, ExtSrc0, N->getMemoryVT(),
500 N->getMemOperand(), ISD::SEXTLOAD);
501 // Legalized the chain result - switch anything that used the old chain to
503 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
506 /// Promote the overflow flag of an overflowing arithmetic node.
507 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
508 // Simply change the return type of the boolean result.
509 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
510 EVT ValueVTs[] = { N->getValueType(0), NVT };
511 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
512 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
513 DAG.getVTList(ValueVTs), Ops);
515 // Modified the sum result - switch anything that used the old sum to use
517 ReplaceValueWith(SDValue(N, 0), Res);
519 return SDValue(Res.getNode(), 1);
522 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
524 return PromoteIntRes_Overflow(N);
526 // The operation overflowed iff the result in the larger type is not the
527 // sign extension of its truncation to the original type.
528 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
529 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
530 EVT OVT = N->getOperand(0).getValueType();
531 EVT NVT = LHS.getValueType();
534 // Do the arithmetic in the larger type.
535 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
536 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
538 // Calculate the overflow flag: sign extend the arithmetic result from
539 // the original type.
540 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
541 DAG.getValueType(OVT));
542 // Overflowed if and only if this is not equal to Res.
543 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
545 // Use the calculated overflow everywhere.
546 ReplaceValueWith(SDValue(N, 1), Ofl);
551 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
552 // Sign extend the input.
553 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
554 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
555 return DAG.getNode(N->getOpcode(), SDLoc(N),
556 LHS.getValueType(), LHS, RHS);
559 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
560 SDValue LHS = GetPromotedInteger(N->getOperand(1));
561 SDValue RHS = GetPromotedInteger(N->getOperand(2));
562 return DAG.getSelect(SDLoc(N),
563 LHS.getValueType(), N->getOperand(0), LHS, RHS);
566 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
567 SDValue Mask = N->getOperand(0);
568 EVT OpTy = N->getOperand(1).getValueType();
570 // Promote all the way up to the canonical SetCC type.
571 Mask = PromoteTargetBoolean(Mask, OpTy);
572 SDValue LHS = GetPromotedInteger(N->getOperand(1));
573 SDValue RHS = GetPromotedInteger(N->getOperand(2));
574 return DAG.getNode(ISD::VSELECT, SDLoc(N),
575 LHS.getValueType(), Mask, LHS, RHS);
578 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
579 SDValue LHS = GetPromotedInteger(N->getOperand(2));
580 SDValue RHS = GetPromotedInteger(N->getOperand(3));
581 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
582 LHS.getValueType(), N->getOperand(0),
583 N->getOperand(1), LHS, RHS, N->getOperand(4));
586 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
587 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
589 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
591 // Only use the result of getSetCCResultType if it is legal,
592 // otherwise just use the promoted result type (NVT).
593 if (!TLI.isTypeLegal(SVT))
597 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
598 "Vector compare must return a vector result!");
600 SDValue LHS = N->getOperand(0);
601 SDValue RHS = N->getOperand(1);
602 if (LHS.getValueType() != RHS.getValueType()) {
603 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
604 !LHS.getValueType().isVector())
605 LHS = GetPromotedInteger(LHS);
606 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
607 !RHS.getValueType().isVector())
608 RHS = GetPromotedInteger(RHS);
611 // Get the SETCC result using the canonical SETCC type.
612 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
615 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
616 // Convert to the expected type.
617 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
620 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
621 SDValue LHS = N->getOperand(0);
622 SDValue RHS = N->getOperand(1);
623 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
624 LHS = GetPromotedInteger(LHS);
625 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
626 RHS = ZExtPromotedInteger(RHS);
627 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
630 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
631 SDValue Op = GetPromotedInteger(N->getOperand(0));
632 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
633 Op.getValueType(), Op, N->getOperand(1));
636 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
637 // The input may have strange things in the top bits of the registers, but
638 // these operations don't care. They may have weird bits going out, but
639 // that too is okay if they are integer operations.
640 SDValue LHS = GetPromotedInteger(N->getOperand(0));
641 SDValue RHS = GetPromotedInteger(N->getOperand(1));
642 return DAG.getNode(N->getOpcode(), SDLoc(N),
643 LHS.getValueType(), LHS, RHS);
646 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
647 SDValue LHS = N->getOperand(0);
648 SDValue RHS = N->getOperand(1);
649 // The input value must be properly sign extended.
650 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
651 LHS = SExtPromotedInteger(LHS);
652 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
653 RHS = ZExtPromotedInteger(RHS);
654 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
657 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
658 SDValue LHS = N->getOperand(0);
659 SDValue RHS = N->getOperand(1);
660 // The input value must be properly zero extended.
661 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
662 LHS = ZExtPromotedInteger(LHS);
663 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
664 RHS = ZExtPromotedInteger(RHS);
665 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
668 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
669 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
671 SDValue InOp = N->getOperand(0);
674 switch (getTypeAction(InOp.getValueType())) {
675 default: llvm_unreachable("Unknown type action!");
676 case TargetLowering::TypeLegal:
677 case TargetLowering::TypeExpandInteger:
680 case TargetLowering::TypePromoteInteger:
681 Res = GetPromotedInteger(InOp);
683 case TargetLowering::TypeSplitVector:
684 EVT InVT = InOp.getValueType();
685 assert(InVT.isVector() && "Cannot split scalar types");
686 unsigned NumElts = InVT.getVectorNumElements();
687 assert(NumElts == NVT.getVectorNumElements() &&
688 "Dst and Src must have the same number of elements");
689 assert(isPowerOf2_32(NumElts) &&
690 "Promoted vector type must be a power of two");
693 GetSplitVector(InOp, EOp1, EOp2);
695 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
697 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
698 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
700 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
703 // Truncate to NVT instead of VT
704 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
707 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
709 return PromoteIntRes_Overflow(N);
711 // The operation overflowed iff the result in the larger type is not the
712 // zero extension of its truncation to the original type.
713 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
714 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
715 EVT OVT = N->getOperand(0).getValueType();
716 EVT NVT = LHS.getValueType();
719 // Do the arithmetic in the larger type.
720 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
721 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
723 // Calculate the overflow flag: zero extend the arithmetic result from
724 // the original type.
725 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
726 // Overflowed if and only if this is not equal to Res.
727 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
729 // Use the calculated overflow everywhere.
730 ReplaceValueWith(SDValue(N, 1), Ofl);
735 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
736 // Promote the overflow bit trivially.
738 return PromoteIntRes_Overflow(N);
740 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
742 EVT SmallVT = LHS.getValueType();
744 // To determine if the result overflowed in a larger type, we extend the
745 // input to the larger type, do the multiply (checking if it overflows),
746 // then also check the high bits of the result to see if overflow happened
748 if (N->getOpcode() == ISD::SMULO) {
749 LHS = SExtPromotedInteger(LHS);
750 RHS = SExtPromotedInteger(RHS);
752 LHS = ZExtPromotedInteger(LHS);
753 RHS = ZExtPromotedInteger(RHS);
755 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
756 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
758 // Overflow occurred if it occurred in the larger type, or if the high part
759 // of the result does not zero/sign-extend the low part. Check this second
760 // possibility first.
762 if (N->getOpcode() == ISD::UMULO) {
763 // Unsigned overflow occurred if the high part is non-zero.
764 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
765 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
767 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
768 DAG.getConstant(0, DL, Hi.getValueType()),
771 // Signed overflow occurred if the high part does not sign extend the low.
772 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
773 Mul, DAG.getValueType(SmallVT));
774 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
777 // The only other way for overflow to occur is if the multiplication in the
778 // larger type itself overflowed.
779 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
780 SDValue(Mul.getNode(), 1));
782 // Use the calculated overflow everywhere.
783 ReplaceValueWith(SDValue(N, 1), Overflow);
787 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
788 // Zero extend the input.
789 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
790 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
791 return DAG.getNode(N->getOpcode(), SDLoc(N),
792 LHS.getValueType(), LHS, RHS);
795 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
796 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
797 N->getValueType(0)));
800 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
801 SDValue Chain = N->getOperand(0); // Get the chain.
802 SDValue Ptr = N->getOperand(1); // Get the pointer.
803 EVT VT = N->getValueType(0);
806 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
807 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
808 // The argument is passed as NumRegs registers of type RegVT.
810 SmallVector<SDValue, 8> Parts(NumRegs);
811 for (unsigned i = 0; i < NumRegs; ++i) {
812 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
813 N->getConstantOperandVal(3));
814 Chain = Parts[i].getValue(1);
817 // Handle endianness of the load.
818 if (DAG.getDataLayout().isBigEndian())
819 std::reverse(Parts.begin(), Parts.end());
821 // Assemble the parts in the promoted type.
822 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
823 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
824 for (unsigned i = 1; i < NumRegs; ++i) {
825 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
826 // Shift it to the right position and "or" it in.
827 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
828 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
829 TLI.getPointerTy(DAG.getDataLayout())));
830 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
833 // Modified the chain result - switch anything that used the old chain to
835 ReplaceValueWith(SDValue(N, 1), Chain);
840 //===----------------------------------------------------------------------===//
841 // Integer Operand Promotion
842 //===----------------------------------------------------------------------===//
844 /// PromoteIntegerOperand - This method is called when the specified operand of
845 /// the specified node is found to need promotion. At this point, all of the
846 /// result types of the node are known to be legal, but other operands of the
847 /// node may need promotion or expansion as well as the specified one.
848 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
849 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
850 SDValue Res = SDValue();
852 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
855 switch (N->getOpcode()) {
858 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
859 N->dump(&DAG); dbgs() << "\n";
861 llvm_unreachable("Do not know how to promote this operator's operand!");
863 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
864 case ISD::ATOMIC_STORE:
865 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
867 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
868 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
869 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
870 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
871 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
872 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
873 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
874 case ISD::CONVERT_RNDSAT:
875 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
876 case ISD::INSERT_VECTOR_ELT:
877 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
878 case ISD::SCALAR_TO_VECTOR:
879 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
881 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
882 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
883 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
884 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
885 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
886 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
888 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
890 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
892 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
893 case ISD::FP16_TO_FP:
894 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
895 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
896 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
902 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
905 // If the result is null, the sub-method took care of registering results etc.
906 if (!Res.getNode()) return false;
908 // If the result is N, the sub-method updated N in place. Tell the legalizer
910 if (Res.getNode() == N)
913 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
914 "Invalid operand expansion");
916 ReplaceValueWith(SDValue(N, 0), Res);
920 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
921 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
922 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
923 ISD::CondCode CCCode) {
924 // We have to insert explicit sign or zero extends. Note that we could
925 // insert sign extends for ALL conditions, but zero extend is cheaper on
926 // many machines (an AND instead of two shifts), so prefer it.
928 default: llvm_unreachable("Unknown integer comparison!");
931 SDValue OpL = GetPromotedInteger(NewLHS);
932 SDValue OpR = GetPromotedInteger(NewRHS);
934 // We would prefer to promote the comparison operand with sign extension,
935 // if we find the operand is actually to truncate an AssertSext. With this
936 // optimization, we can avoid inserting real truncate instruction, which
937 // is redudant eventually.
938 if (OpL->getOpcode() == ISD::AssertSext &&
939 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
940 OpR->getOpcode() == ISD::AssertSext &&
941 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
945 NewLHS = ZExtPromotedInteger(NewLHS);
946 NewRHS = ZExtPromotedInteger(NewRHS);
954 // ALL of these operations will work if we either sign or zero extend
955 // the operands (including the unsigned comparisons!). Zero extend is
956 // usually a simpler/cheaper operation, so prefer it.
957 NewLHS = ZExtPromotedInteger(NewLHS);
958 NewRHS = ZExtPromotedInteger(NewRHS);
964 NewLHS = SExtPromotedInteger(NewLHS);
965 NewRHS = SExtPromotedInteger(NewRHS);
970 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
971 SDValue Op = GetPromotedInteger(N->getOperand(0));
972 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
975 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
976 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
977 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
978 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
979 N->getOrdering(), N->getSynchScope());
982 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
983 // This should only occur in unusual situations like bitcasting to an
984 // x86_fp80, so just turn it into a store+load
985 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
988 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
989 assert(OpNo == 2 && "Don't know how to promote this operand!");
991 SDValue LHS = N->getOperand(2);
992 SDValue RHS = N->getOperand(3);
993 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
995 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
997 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
998 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1002 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1003 assert(OpNo == 1 && "only know how to promote condition");
1005 // Promote all the way up to the canonical SetCC type.
1006 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1008 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1009 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1010 N->getOperand(2)), 0);
1013 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1014 // Since the result type is legal, the operands must promote to it.
1015 EVT OVT = N->getOperand(0).getValueType();
1016 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1017 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1018 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1021 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1022 DAG.getConstant(OVT.getSizeInBits(), dl,
1023 TLI.getPointerTy(DAG.getDataLayout())));
1024 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1027 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1028 // The vector type is legal but the element type is not. This implies
1029 // that the vector is a power-of-two in length and that the element
1030 // type does not have a strange size (eg: it is not i1).
1031 EVT VecVT = N->getValueType(0);
1032 unsigned NumElts = VecVT.getVectorNumElements();
1033 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1034 "Legal vector of one illegal element?");
1036 // Promote the inserted value. The type does not need to match the
1037 // vector element type. Check that any extra bits introduced will be
1039 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1040 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1041 "Type of inserted value narrower than vector element type!");
1043 SmallVector<SDValue, 16> NewOps;
1044 for (unsigned i = 0; i < NumElts; ++i)
1045 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1047 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1050 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1051 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1052 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1053 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1054 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1055 "can only promote integer arguments");
1056 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1057 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1058 N->getOperand(1), N->getOperand(2),
1059 N->getOperand(3), N->getOperand(4), CvtCode);
1062 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1065 // Promote the inserted value. This is valid because the type does not
1066 // have to match the vector element type.
1068 // Check that any extra bits introduced will be truncated away.
1069 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1070 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1071 "Type of inserted value narrower than vector element type!");
1072 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1073 GetPromotedInteger(N->getOperand(1)),
1078 assert(OpNo == 2 && "Different operand and result vector types?");
1080 // Promote the index.
1081 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1082 TLI.getVectorIdxTy(DAG.getDataLayout()));
1083 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1084 N->getOperand(1), Idx), 0);
1087 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1088 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1089 // the operand in place.
1090 return SDValue(DAG.UpdateNodeOperands(N,
1091 GetPromotedInteger(N->getOperand(0))), 0);
1094 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1095 assert(OpNo == 0 && "Only know how to promote the condition!");
1096 SDValue Cond = N->getOperand(0);
1097 EVT OpTy = N->getOperand(1).getValueType();
1099 // Promote all the way up to the canonical SetCC type.
1100 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1101 Cond = PromoteTargetBoolean(Cond, OpVT);
1103 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1104 N->getOperand(2)), 0);
1107 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1108 assert(OpNo == 0 && "Don't know how to promote this operand!");
1110 SDValue LHS = N->getOperand(0);
1111 SDValue RHS = N->getOperand(1);
1112 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1114 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1115 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1116 N->getOperand(3), N->getOperand(4)), 0);
1119 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1120 assert(OpNo == 0 && "Don't know how to promote this operand!");
1122 SDValue LHS = N->getOperand(0);
1123 SDValue RHS = N->getOperand(1);
1124 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1126 // The CC (#2) is always legal.
1127 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1130 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1131 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1132 ZExtPromotedInteger(N->getOperand(1))), 0);
1135 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1136 SDValue Op = GetPromotedInteger(N->getOperand(0));
1138 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1139 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1140 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1143 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1144 return SDValue(DAG.UpdateNodeOperands(N,
1145 SExtPromotedInteger(N->getOperand(0))), 0);
1148 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1149 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1150 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1153 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1155 // Truncate the value and store the result.
1156 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1157 N->getMemoryVT(), N->getMemOperand());
1160 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo){
1162 SDValue DataOp = N->getValue();
1163 EVT DataVT = DataOp.getValueType();
1164 SDValue Mask = N->getMask();
1165 EVT MaskVT = Mask.getValueType();
1168 bool TruncateStore = false;
1169 if (!TLI.isTypeLegal(DataVT)) {
1170 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger) {
1171 DataOp = GetPromotedInteger(DataOp);
1172 if (!TLI.isTypeLegal(MaskVT))
1173 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1174 TruncateStore = true;
1177 assert(getTypeAction(DataVT) == TargetLowering::TypeWidenVector &&
1178 "Unexpected data legalization in MSTORE");
1179 DataOp = GetWidenedVector(DataOp);
1181 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
1182 Mask = GetWidenedVector(Mask);
1184 EVT BoolVT = getSetCCResultType(DataOp.getValueType());
1186 // We can't use ModifyToType() because we should fill the mask with
1188 unsigned WidenNumElts = BoolVT.getVectorNumElements();
1189 unsigned MaskNumElts = MaskVT.getVectorNumElements();
1191 unsigned NumConcat = WidenNumElts / MaskNumElts;
1192 SmallVector<SDValue, 16> Ops(NumConcat);
1193 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
1195 for (unsigned i = 1; i != NumConcat; ++i)
1198 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
1203 Mask = PromoteTargetBoolean(N->getMask(), DataOp.getValueType());
1204 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1205 N->getMemoryVT(), N->getMemOperand(),
1209 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo){
1210 assert(OpNo == 2 && "Only know how to promote the mask!");
1211 EVT DataVT = N->getValueType(0);
1212 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1213 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1214 NewOps[OpNo] = Mask;
1215 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1218 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1219 SDValue Op = GetPromotedInteger(N->getOperand(0));
1220 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1223 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1224 return SDValue(DAG.UpdateNodeOperands(N,
1225 ZExtPromotedInteger(N->getOperand(0))), 0);
1228 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1230 SDValue Op = GetPromotedInteger(N->getOperand(0));
1231 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1232 return DAG.getZeroExtendInReg(Op, dl,
1233 N->getOperand(0).getValueType().getScalarType());
1237 //===----------------------------------------------------------------------===//
1238 // Integer Result Expansion
1239 //===----------------------------------------------------------------------===//
1241 /// ExpandIntegerResult - This method is called when the specified result of the
1242 /// specified node is found to need expansion. At this point, the node may also
1243 /// have invalid operands or may have other results that need promotion, we just
1244 /// know that (at least) one result needs expansion.
1245 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1246 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1248 Lo = Hi = SDValue();
1250 // See if the target wants to custom expand this node.
1251 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1254 switch (N->getOpcode()) {
1257 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1258 N->dump(&DAG); dbgs() << "\n";
1260 llvm_unreachable("Do not know how to expand the result of this operator!");
1262 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1263 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1264 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1265 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1267 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1268 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1269 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1270 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1271 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1273 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1274 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1275 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1276 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1277 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1278 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1279 case ISD::CTLZ_ZERO_UNDEF:
1280 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1281 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1282 case ISD::CTTZ_ZERO_UNDEF:
1283 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1284 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1285 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1286 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1287 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1288 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1289 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1290 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1291 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1292 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1293 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1294 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1295 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1296 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1297 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1299 case ISD::ATOMIC_LOAD_ADD:
1300 case ISD::ATOMIC_LOAD_SUB:
1301 case ISD::ATOMIC_LOAD_AND:
1302 case ISD::ATOMIC_LOAD_OR:
1303 case ISD::ATOMIC_LOAD_XOR:
1304 case ISD::ATOMIC_LOAD_NAND:
1305 case ISD::ATOMIC_LOAD_MIN:
1306 case ISD::ATOMIC_LOAD_MAX:
1307 case ISD::ATOMIC_LOAD_UMIN:
1308 case ISD::ATOMIC_LOAD_UMAX:
1309 case ISD::ATOMIC_SWAP:
1310 case ISD::ATOMIC_CMP_SWAP: {
1311 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1312 SplitInteger(Tmp.first, Lo, Hi);
1313 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1316 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1317 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1318 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1319 SDValue Tmp = DAG.getAtomicCmpSwap(
1320 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1321 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1322 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1323 AN->getSynchScope());
1325 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1326 // success simply by comparing the loaded value against the ingoing
1328 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1329 N->getOperand(2), ISD::SETEQ);
1331 SplitInteger(Tmp, Lo, Hi);
1332 ReplaceValueWith(SDValue(N, 1), Success);
1333 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1339 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1342 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1345 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1348 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1352 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1355 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1357 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1359 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1362 // If Lo/Hi is null, the sub-method took care of registering results etc.
1364 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1367 /// Lower an atomic node to the appropriate builtin call.
1368 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1369 unsigned Opc = Node->getOpcode();
1370 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1371 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1372 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1374 return ExpandChainLibCall(LC, Node, false);
1377 /// N is a shift by a value that needs to be expanded,
1378 /// and the shift amount is a constant 'Amt'. Expand the operation.
1379 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1380 SDValue &Lo, SDValue &Hi) {
1382 // Expand the incoming operand to be shifted, so that we have its parts
1384 GetExpandedInteger(N->getOperand(0), InL, InH);
1386 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1387 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1394 EVT NVT = InL.getValueType();
1395 unsigned VTBits = N->getValueType(0).getSizeInBits();
1396 unsigned NVTBits = NVT.getSizeInBits();
1397 EVT ShTy = N->getOperand(1).getValueType();
1399 if (N->getOpcode() == ISD::SHL) {
1400 if (Amt.ugt(VTBits)) {
1401 Lo = Hi = DAG.getConstant(0, DL, NVT);
1402 } else if (Amt.ugt(NVTBits)) {
1403 Lo = DAG.getConstant(0, DL, NVT);
1404 Hi = DAG.getNode(ISD::SHL, DL,
1405 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1406 } else if (Amt == NVTBits) {
1407 Lo = DAG.getConstant(0, DL, NVT);
1409 } else if (Amt == 1 &&
1410 TLI.isOperationLegalOrCustom(ISD::ADDC,
1411 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1412 // Emit this X << 1 as X+X.
1413 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1414 SDValue LoOps[2] = { InL, InL };
1415 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1416 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1417 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1419 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1420 Hi = DAG.getNode(ISD::OR, DL, NVT,
1421 DAG.getNode(ISD::SHL, DL, NVT, InH,
1422 DAG.getConstant(Amt, DL, ShTy)),
1423 DAG.getNode(ISD::SRL, DL, NVT, InL,
1424 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1429 if (N->getOpcode() == ISD::SRL) {
1430 if (Amt.ugt(VTBits)) {
1431 Lo = Hi = DAG.getConstant(0, DL, NVT);
1432 } else if (Amt.ugt(NVTBits)) {
1433 Lo = DAG.getNode(ISD::SRL, DL,
1434 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1435 Hi = DAG.getConstant(0, DL, NVT);
1436 } else if (Amt == NVTBits) {
1438 Hi = DAG.getConstant(0, DL, NVT);
1440 Lo = DAG.getNode(ISD::OR, DL, NVT,
1441 DAG.getNode(ISD::SRL, DL, NVT, InL,
1442 DAG.getConstant(Amt, DL, ShTy)),
1443 DAG.getNode(ISD::SHL, DL, NVT, InH,
1444 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1445 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1450 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1451 if (Amt.ugt(VTBits)) {
1452 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1453 DAG.getConstant(NVTBits - 1, DL, ShTy));
1454 } else if (Amt.ugt(NVTBits)) {
1455 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1456 DAG.getConstant(Amt - NVTBits, DL, ShTy));
1457 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1458 DAG.getConstant(NVTBits - 1, DL, ShTy));
1459 } else if (Amt == NVTBits) {
1461 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1462 DAG.getConstant(NVTBits - 1, DL, ShTy));
1464 Lo = DAG.getNode(ISD::OR, DL, NVT,
1465 DAG.getNode(ISD::SRL, DL, NVT, InL,
1466 DAG.getConstant(Amt, DL, ShTy)),
1467 DAG.getNode(ISD::SHL, DL, NVT, InH,
1468 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1469 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1473 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1474 /// this shift based on knowledge of the high bit of the shift amount. If we
1475 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1477 bool DAGTypeLegalizer::
1478 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1479 SDValue Amt = N->getOperand(1);
1480 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1481 EVT ShTy = Amt.getValueType();
1482 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1483 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1484 assert(isPowerOf2_32(NVTBits) &&
1485 "Expanded integer type size not a power of two!");
1488 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1489 APInt KnownZero, KnownOne;
1490 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1492 // If we don't know anything about the high bits, exit.
1493 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1496 // Get the incoming operand to be shifted.
1498 GetExpandedInteger(N->getOperand(0), InL, InH);
1500 // If we know that any of the high bits of the shift amount are one, then we
1501 // can do this as a couple of simple shifts.
1502 if (KnownOne.intersects(HighBitMask)) {
1503 // Mask out the high bit, which we know is set.
1504 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1505 DAG.getConstant(~HighBitMask, dl, ShTy));
1507 switch (N->getOpcode()) {
1508 default: llvm_unreachable("Unknown shift");
1510 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1511 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1514 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1515 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1518 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1519 DAG.getConstant(NVTBits - 1, dl, ShTy));
1520 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1525 // If we know that all of the high bits of the shift amount are zero, then we
1526 // can do this as a couple of simple shifts.
1527 if ((KnownZero & HighBitMask) == HighBitMask) {
1528 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1529 // shift if x is zero. We can use XOR here because x is known to be smaller
1531 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1532 DAG.getConstant(NVTBits - 1, dl, ShTy));
1535 switch (N->getOpcode()) {
1536 default: llvm_unreachable("Unknown shift");
1537 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1539 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1542 // When shifting right the arithmetic for Lo and Hi is swapped.
1543 if (N->getOpcode() != ISD::SHL)
1544 std::swap(InL, InH);
1546 // Use a little trick to get the bits that move from Lo to Hi. First
1547 // shift by one bit.
1548 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1549 // Then compute the remaining shift with amount-1.
1550 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1552 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1553 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1555 if (N->getOpcode() != ISD::SHL)
1563 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1565 bool DAGTypeLegalizer::
1566 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1567 SDValue Amt = N->getOperand(1);
1568 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1569 EVT ShTy = Amt.getValueType();
1570 unsigned NVTBits = NVT.getSizeInBits();
1571 assert(isPowerOf2_32(NVTBits) &&
1572 "Expanded integer type size not a power of two!");
1575 // Get the incoming operand to be shifted.
1577 GetExpandedInteger(N->getOperand(0), InL, InH);
1579 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1580 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1581 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1582 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1583 Amt, NVBitsNode, ISD::SETULT);
1584 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1585 Amt, DAG.getConstant(0, dl, ShTy),
1588 SDValue LoS, HiS, LoL, HiL;
1589 switch (N->getOpcode()) {
1590 default: llvm_unreachable("Unknown shift");
1592 // Short: ShAmt < NVTBits
1593 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1594 HiS = DAG.getNode(ISD::OR, dl, NVT,
1595 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1596 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1598 // Long: ShAmt >= NVTBits
1599 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1600 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1602 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1603 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1604 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1607 // Short: ShAmt < NVTBits
1608 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1609 LoS = DAG.getNode(ISD::OR, dl, NVT,
1610 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1611 // FIXME: If Amt is zero, the following shift generates an undefined result
1612 // on some architectures.
1613 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1615 // Long: ShAmt >= NVTBits
1616 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1617 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1619 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1620 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1621 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1624 // Short: ShAmt < NVTBits
1625 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1626 LoS = DAG.getNode(ISD::OR, dl, NVT,
1627 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1628 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1630 // Long: ShAmt >= NVTBits
1631 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1632 DAG.getConstant(NVTBits - 1, dl, ShTy));
1633 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1635 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1636 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1637 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1642 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1643 SDValue &Lo, SDValue &Hi) {
1645 // Expand the subcomponents.
1646 SDValue LHSL, LHSH, RHSL, RHSH;
1647 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1648 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1650 EVT NVT = LHSL.getValueType();
1651 SDValue LoOps[2] = { LHSL, RHSL };
1652 SDValue HiOps[3] = { LHSH, RHSH };
1654 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1655 // them. TODO: Teach operation legalization how to expand unsupported
1656 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1657 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1658 // generate a value of this type in the expanded code sequence.
1660 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1661 ISD::ADDC : ISD::SUBC,
1662 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1665 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1666 if (N->getOpcode() == ISD::ADD) {
1667 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1668 HiOps[2] = Lo.getValue(1);
1669 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1671 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1672 HiOps[2] = Lo.getValue(1);
1673 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1679 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1680 ISD::UADDO : ISD::USUBO,
1681 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1683 SDVTList VTList = DAG.getVTList(NVT, NVT);
1684 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1686 if (N->getOpcode() == ISD::ADD) {
1688 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1689 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1692 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1693 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1695 SDValue OVF = Lo.getValue(1);
1698 case TargetLoweringBase::UndefinedBooleanContent:
1699 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);
1701 case TargetLoweringBase::ZeroOrOneBooleanContent:
1702 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
1704 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1705 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
1710 if (N->getOpcode() == ISD::ADD) {
1711 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1712 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1713 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1715 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1716 DAG.getConstant(1, dl, NVT),
1717 DAG.getConstant(0, dl, NVT));
1718 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1720 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1721 DAG.getConstant(1, dl, NVT), Carry1);
1722 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1724 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1725 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1727 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1728 LoOps[0], LoOps[1], ISD::SETULT);
1729 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1730 DAG.getConstant(1, dl, NVT),
1731 DAG.getConstant(0, dl, NVT));
1732 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1736 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1737 SDValue &Lo, SDValue &Hi) {
1738 // Expand the subcomponents.
1739 SDValue LHSL, LHSH, RHSL, RHSH;
1741 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1742 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1743 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1744 SDValue LoOps[2] = { LHSL, RHSL };
1745 SDValue HiOps[3] = { LHSH, RHSH };
1747 if (N->getOpcode() == ISD::ADDC) {
1748 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1749 HiOps[2] = Lo.getValue(1);
1750 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1752 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1753 HiOps[2] = Lo.getValue(1);
1754 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1757 // Legalized the flag result - switch anything that used the old flag to
1759 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1762 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1763 SDValue &Lo, SDValue &Hi) {
1764 // Expand the subcomponents.
1765 SDValue LHSL, LHSH, RHSL, RHSH;
1767 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1768 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1769 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1770 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1771 SDValue HiOps[3] = { LHSH, RHSH };
1773 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1774 HiOps[2] = Lo.getValue(1);
1775 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1777 // Legalized the flag result - switch anything that used the old flag to
1779 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1782 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1783 SDValue &Lo, SDValue &Hi) {
1784 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1786 SDValue Op = N->getOperand(0);
1787 if (Op.getValueType().bitsLE(NVT)) {
1788 // The low part is any extension of the input (which degenerates to a copy).
1789 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1790 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1792 // For example, extension of an i48 to an i64. The operand type necessarily
1793 // promotes to the result type, so will end up being expanded too.
1794 assert(getTypeAction(Op.getValueType()) ==
1795 TargetLowering::TypePromoteInteger &&
1796 "Only know how to promote this result!");
1797 SDValue Res = GetPromotedInteger(Op);
1798 assert(Res.getValueType() == N->getValueType(0) &&
1799 "Operand over promoted?");
1800 // Split the promoted operand. This will simplify when it is expanded.
1801 SplitInteger(Res, Lo, Hi);
1805 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1806 SDValue &Lo, SDValue &Hi) {
1808 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1809 EVT NVT = Lo.getValueType();
1810 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1811 unsigned NVTBits = NVT.getSizeInBits();
1812 unsigned EVTBits = EVT.getSizeInBits();
1814 if (NVTBits < EVTBits) {
1815 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1816 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1817 EVTBits - NVTBits)));
1819 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1820 // The high part replicates the sign bit of Lo, make it explicit.
1821 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1822 DAG.getConstant(NVTBits - 1, dl,
1823 TLI.getPointerTy(DAG.getDataLayout())));
1827 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1828 SDValue &Lo, SDValue &Hi) {
1830 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1831 EVT NVT = Lo.getValueType();
1832 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1833 unsigned NVTBits = NVT.getSizeInBits();
1834 unsigned EVTBits = EVT.getSizeInBits();
1836 if (NVTBits < EVTBits) {
1837 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1838 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1839 EVTBits - NVTBits)));
1841 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1842 // The high part must be zero, make it explicit.
1843 Hi = DAG.getConstant(0, dl, NVT);
1847 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
1848 SDValue &Lo, SDValue &Hi) {
1850 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1851 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
1852 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
1855 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1856 SDValue &Lo, SDValue &Hi) {
1858 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1859 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1860 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1863 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1864 SDValue &Lo, SDValue &Hi) {
1865 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1866 unsigned NBitWidth = NVT.getSizeInBits();
1867 auto Constant = cast<ConstantSDNode>(N);
1868 const APInt &Cst = Constant->getAPIntValue();
1869 bool IsTarget = Constant->isTargetOpcode();
1870 bool IsOpaque = Constant->isOpaque();
1872 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1873 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1877 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1878 SDValue &Lo, SDValue &Hi) {
1880 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1881 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1882 EVT NVT = Lo.getValueType();
1884 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1885 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1887 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1888 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1890 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1891 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1892 DAG.getConstant(NVT.getSizeInBits(), dl,
1894 Hi = DAG.getConstant(0, dl, NVT);
1897 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1898 SDValue &Lo, SDValue &Hi) {
1900 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1901 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1902 EVT NVT = Lo.getValueType();
1903 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1904 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1905 Hi = DAG.getConstant(0, dl, NVT);
1908 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1909 SDValue &Lo, SDValue &Hi) {
1911 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1912 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1913 EVT NVT = Lo.getValueType();
1915 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1916 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1918 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1919 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1921 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1922 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1923 DAG.getConstant(NVT.getSizeInBits(), dl,
1925 Hi = DAG.getConstant(0, dl, NVT);
1928 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1931 EVT VT = N->getValueType(0);
1933 SDValue Op = N->getOperand(0);
1934 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1935 Op = GetPromotedFloat(Op);
1937 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1938 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1939 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, true/*irrelevant*/, dl).first,
1943 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1946 EVT VT = N->getValueType(0);
1948 SDValue Op = N->getOperand(0);
1949 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1950 Op = GetPromotedFloat(Op);
1952 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1953 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1954 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, false/*irrelevant*/, dl).first,
1958 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1959 SDValue &Lo, SDValue &Hi) {
1960 if (ISD::isNormalLoad(N)) {
1961 ExpandRes_NormalLoad(N, Lo, Hi);
1965 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1967 EVT VT = N->getValueType(0);
1968 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1969 SDValue Ch = N->getChain();
1970 SDValue Ptr = N->getBasePtr();
1971 ISD::LoadExtType ExtType = N->getExtensionType();
1972 unsigned Alignment = N->getAlignment();
1973 bool isVolatile = N->isVolatile();
1974 bool isNonTemporal = N->isNonTemporal();
1975 bool isInvariant = N->isInvariant();
1976 AAMDNodes AAInfo = N->getAAInfo();
1979 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1981 if (N->getMemoryVT().bitsLE(NVT)) {
1982 EVT MemVT = N->getMemoryVT();
1984 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1985 MemVT, isVolatile, isNonTemporal, isInvariant,
1988 // Remember the chain.
1989 Ch = Lo.getValue(1);
1991 if (ExtType == ISD::SEXTLOAD) {
1992 // The high part is obtained by SRA'ing all but one of the bits of the
1994 unsigned LoSize = Lo.getValueType().getSizeInBits();
1995 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1996 DAG.getConstant(LoSize - 1, dl,
1997 TLI.getPointerTy(DAG.getDataLayout())));
1998 } else if (ExtType == ISD::ZEXTLOAD) {
1999 // The high part is just a zero.
2000 Hi = DAG.getConstant(0, dl, NVT);
2002 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
2003 // The high part is undefined.
2004 Hi = DAG.getUNDEF(NVT);
2006 } else if (DAG.getDataLayout().isLittleEndian()) {
2007 // Little-endian - low bits are at low addresses.
2008 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
2009 isVolatile, isNonTemporal, isInvariant, Alignment,
2012 unsigned ExcessBits =
2013 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2014 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2016 // Increment the pointer to the other half.
2017 unsigned IncrementSize = NVT.getSizeInBits()/8;
2018 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2019 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2020 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2021 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2022 isVolatile, isNonTemporal, isInvariant,
2023 MinAlign(Alignment, IncrementSize), AAInfo);
2025 // Build a factor node to remember that this load is independent of the
2027 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2030 // Big-endian - high bits are at low addresses. Favor aligned loads at
2031 // the cost of some bit-fiddling.
2032 EVT MemVT = N->getMemoryVT();
2033 unsigned EBytes = MemVT.getStoreSize();
2034 unsigned IncrementSize = NVT.getSizeInBits()/8;
2035 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2037 // Load both the high bits and maybe some of the low bits.
2038 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2039 EVT::getIntegerVT(*DAG.getContext(),
2040 MemVT.getSizeInBits() - ExcessBits),
2041 isVolatile, isNonTemporal, isInvariant, Alignment,
2044 // Increment the pointer to the other half.
2045 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2046 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2047 // Load the rest of the low bits.
2048 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2049 N->getPointerInfo().getWithOffset(IncrementSize),
2050 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2051 isVolatile, isNonTemporal, isInvariant,
2052 MinAlign(Alignment, IncrementSize), AAInfo);
2054 // Build a factor node to remember that this load is independent of the
2056 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2059 if (ExcessBits < NVT.getSizeInBits()) {
2060 // Transfer low bits from the bottom of Hi to the top of Lo.
2062 ISD::OR, dl, NVT, Lo,
2063 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2064 DAG.getConstant(ExcessBits, dl,
2065 TLI.getPointerTy(DAG.getDataLayout()))));
2066 // Move high bits to the right position in Hi.
2067 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2069 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2070 TLI.getPointerTy(DAG.getDataLayout())));
2074 // Legalized the chain result - switch anything that used the old chain to
2076 ReplaceValueWith(SDValue(N, 1), Ch);
2079 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2080 SDValue &Lo, SDValue &Hi) {
2082 SDValue LL, LH, RL, RH;
2083 GetExpandedInteger(N->getOperand(0), LL, LH);
2084 GetExpandedInteger(N->getOperand(1), RL, RH);
2085 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2086 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2089 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2090 SDValue &Lo, SDValue &Hi) {
2091 EVT VT = N->getValueType(0);
2092 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2095 SDValue LL, LH, RL, RH;
2096 GetExpandedInteger(N->getOperand(0), LL, LH);
2097 GetExpandedInteger(N->getOperand(1), RL, RH);
2099 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2102 // If nothing else, we can make a libcall.
2103 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2105 LC = RTLIB::MUL_I16;
2106 else if (VT == MVT::i32)
2107 LC = RTLIB::MUL_I32;
2108 else if (VT == MVT::i64)
2109 LC = RTLIB::MUL_I64;
2110 else if (VT == MVT::i128)
2111 LC = RTLIB::MUL_I128;
2112 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2114 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2115 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true/*irrelevant*/, dl).first,
2119 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2122 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2123 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2124 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2127 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
2130 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2131 SDValue &Lo, SDValue &Hi) {
2132 SDValue LHS = Node->getOperand(0);
2133 SDValue RHS = Node->getOperand(1);
2136 // Expand the result by simply replacing it with the equivalent
2137 // non-overflow-checking operation.
2138 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2139 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2141 SplitInteger(Sum, Lo, Hi);
2143 // Compute the overflow.
2145 // LHSSign -> LHS >= 0
2146 // RHSSign -> RHS >= 0
2147 // SumSign -> Sum >= 0
2150 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2152 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2154 EVT OType = Node->getValueType(1);
2155 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2157 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2158 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2159 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2160 Node->getOpcode() == ISD::SADDO ?
2161 ISD::SETEQ : ISD::SETNE);
2163 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2164 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2166 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2168 // Use the calculated overflow everywhere.
2169 ReplaceValueWith(SDValue(Node, 1), Cmp);
2172 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2173 SDValue &Lo, SDValue &Hi) {
2174 EVT VT = N->getValueType(0);
2176 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2178 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2179 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2180 SplitInteger(Res.getValue(0), Lo, Hi);
2184 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2186 LC = RTLIB::SDIV_I16;
2187 else if (VT == MVT::i32)
2188 LC = RTLIB::SDIV_I32;
2189 else if (VT == MVT::i64)
2190 LC = RTLIB::SDIV_I64;
2191 else if (VT == MVT::i128)
2192 LC = RTLIB::SDIV_I128;
2193 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2195 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2198 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2199 SDValue &Lo, SDValue &Hi) {
2200 EVT VT = N->getValueType(0);
2203 // If we can emit an efficient shift operation, do so now. Check to see if
2204 // the RHS is a constant.
2205 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2206 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
2208 // If we can determine that the high bit of the shift is zero or one, even if
2209 // the low bits are variable, emit this shift in an optimized form.
2210 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2213 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2215 if (N->getOpcode() == ISD::SHL) {
2216 PartsOpc = ISD::SHL_PARTS;
2217 } else if (N->getOpcode() == ISD::SRL) {
2218 PartsOpc = ISD::SRL_PARTS;
2220 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2221 PartsOpc = ISD::SRA_PARTS;
2224 // Next check to see if the target supports this SHL_PARTS operation or if it
2225 // will custom expand it.
2226 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2227 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2228 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2229 Action == TargetLowering::Custom) {
2230 // Expand the subcomponents.
2232 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2233 EVT VT = LHSL.getValueType();
2235 // If the shift amount operand is coming from a vector legalization it may
2236 // have an illegal type. Fix that first by casting the operand, otherwise
2237 // the new SHL_PARTS operation would need further legalization.
2238 SDValue ShiftOp = N->getOperand(1);
2239 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2240 assert(ShiftTy.getScalarType().getSizeInBits() >=
2241 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2242 "ShiftAmountTy is too small to cover the range of this type!");
2243 if (ShiftOp.getValueType() != ShiftTy)
2244 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2246 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2247 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2248 Hi = Lo.getValue(1);
2252 // Otherwise, emit a libcall.
2253 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2255 if (N->getOpcode() == ISD::SHL) {
2256 isSigned = false; /*sign irrelevant*/
2258 LC = RTLIB::SHL_I16;
2259 else if (VT == MVT::i32)
2260 LC = RTLIB::SHL_I32;
2261 else if (VT == MVT::i64)
2262 LC = RTLIB::SHL_I64;
2263 else if (VT == MVT::i128)
2264 LC = RTLIB::SHL_I128;
2265 } else if (N->getOpcode() == ISD::SRL) {
2268 LC = RTLIB::SRL_I16;
2269 else if (VT == MVT::i32)
2270 LC = RTLIB::SRL_I32;
2271 else if (VT == MVT::i64)
2272 LC = RTLIB::SRL_I64;
2273 else if (VT == MVT::i128)
2274 LC = RTLIB::SRL_I128;
2276 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2279 LC = RTLIB::SRA_I16;
2280 else if (VT == MVT::i32)
2281 LC = RTLIB::SRA_I32;
2282 else if (VT == MVT::i64)
2283 LC = RTLIB::SRA_I64;
2284 else if (VT == MVT::i128)
2285 LC = RTLIB::SRA_I128;
2288 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2289 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2290 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, isSigned, dl).first, Lo, Hi);
2294 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2295 llvm_unreachable("Unsupported shift!");
2298 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2299 SDValue &Lo, SDValue &Hi) {
2300 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2302 SDValue Op = N->getOperand(0);
2303 if (Op.getValueType().bitsLE(NVT)) {
2304 // The low part is sign extension of the input (degenerates to a copy).
2305 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2306 // The high part is obtained by SRA'ing all but one of the bits of low part.
2307 unsigned LoSize = NVT.getSizeInBits();
2309 ISD::SRA, dl, NVT, Lo,
2310 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
2312 // For example, extension of an i48 to an i64. The operand type necessarily
2313 // promotes to the result type, so will end up being expanded too.
2314 assert(getTypeAction(Op.getValueType()) ==
2315 TargetLowering::TypePromoteInteger &&
2316 "Only know how to promote this result!");
2317 SDValue Res = GetPromotedInteger(Op);
2318 assert(Res.getValueType() == N->getValueType(0) &&
2319 "Operand over promoted?");
2320 // Split the promoted operand. This will simplify when it is expanded.
2321 SplitInteger(Res, Lo, Hi);
2322 unsigned ExcessBits =
2323 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2324 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2325 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2330 void DAGTypeLegalizer::
2331 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2333 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2334 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2336 if (EVT.bitsLE(Lo.getValueType())) {
2337 // sext_inreg the low part if needed.
2338 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2341 // The high part gets the sign extension from the lo-part. This handles
2342 // things like sextinreg V:i64 from i8.
2343 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2344 DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl,
2345 TLI.getPointerTy(DAG.getDataLayout())));
2347 // For example, extension of an i48 to an i64. Leave the low part alone,
2348 // sext_inreg the high part.
2349 unsigned ExcessBits =
2350 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2351 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2352 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2357 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2358 SDValue &Lo, SDValue &Hi) {
2359 EVT VT = N->getValueType(0);
2361 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2363 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2364 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2365 SplitInteger(Res.getValue(1), Lo, Hi);
2369 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2371 LC = RTLIB::SREM_I16;
2372 else if (VT == MVT::i32)
2373 LC = RTLIB::SREM_I32;
2374 else if (VT == MVT::i64)
2375 LC = RTLIB::SREM_I64;
2376 else if (VT == MVT::i128)
2377 LC = RTLIB::SREM_I128;
2378 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2380 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2383 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2384 SDValue &Lo, SDValue &Hi) {
2385 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2387 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2388 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
2390 DAG.getConstant(NVT.getSizeInBits(), dl,
2391 TLI.getPointerTy(DAG.getDataLayout())));
2392 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2395 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2396 SDValue &Lo, SDValue &Hi) {
2397 SDValue LHS = N->getOperand(0);
2398 SDValue RHS = N->getOperand(1);
2401 // Expand the result by simply replacing it with the equivalent
2402 // non-overflow-checking operation.
2403 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2404 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2406 SplitInteger(Sum, Lo, Hi);
2408 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2409 // overflows iff a - b > a.
2410 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2411 N->getOpcode () == ISD::UADDO ?
2412 ISD::SETULT : ISD::SETUGT);
2414 // Use the calculated overflow everywhere.
2415 ReplaceValueWith(SDValue(N, 1), Ofl);
2418 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2419 SDValue &Lo, SDValue &Hi) {
2420 EVT VT = N->getValueType(0);
2423 // A divide for UMULO should be faster than a function call.
2424 if (N->getOpcode() == ISD::UMULO) {
2425 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2427 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2428 SplitInteger(MUL, Lo, Hi);
2430 // A divide for UMULO will be faster than a function call. Select to
2431 // make sure we aren't using 0.
2432 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2433 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ);
2434 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2435 DAG.getConstant(1, dl, VT), RHS);
2436 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2437 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2439 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2440 DAG.getConstant(0, dl, N->getValueType(1)),
2442 ReplaceValueWith(SDValue(N, 1), Overflow);
2446 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2447 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2448 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2450 // Replace this with a libcall that will check overflow.
2451 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2453 LC = RTLIB::MULO_I32;
2454 else if (VT == MVT::i64)
2455 LC = RTLIB::MULO_I64;
2456 else if (VT == MVT::i128)
2457 LC = RTLIB::MULO_I128;
2458 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2460 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2461 // Temporary for the overflow value, default it to zero.
2462 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2463 DAG.getConstant(0, dl, PtrVT), Temp,
2464 MachinePointerInfo(), false, false, 0);
2466 TargetLowering::ArgListTy Args;
2467 TargetLowering::ArgListEntry Entry;
2468 for (const SDValue &Op : N->op_values()) {
2469 EVT ArgVT = Op.getValueType();
2470 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2473 Entry.isSExt = true;
2474 Entry.isZExt = false;
2475 Args.push_back(Entry);
2478 // Also pass the address of the overflow check.
2480 Entry.Ty = PtrTy->getPointerTo();
2481 Entry.isSExt = true;
2482 Entry.isZExt = false;
2483 Args.push_back(Entry);
2485 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2487 TargetLowering::CallLoweringInfo CLI(DAG);
2488 CLI.setDebugLoc(dl).setChain(Chain)
2489 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2492 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2494 SplitInteger(CallInfo.first, Lo, Hi);
2495 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2496 MachinePointerInfo(), false, false, false, 0);
2497 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2498 DAG.getConstant(0, dl, PtrVT),
2500 // Use the overflow from the libcall everywhere.
2501 ReplaceValueWith(SDValue(N, 1), Ofl);
2504 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2505 SDValue &Lo, SDValue &Hi) {
2506 EVT VT = N->getValueType(0);
2508 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2510 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2511 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2512 SplitInteger(Res.getValue(0), Lo, Hi);
2516 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2518 LC = RTLIB::UDIV_I16;
2519 else if (VT == MVT::i32)
2520 LC = RTLIB::UDIV_I32;
2521 else if (VT == MVT::i64)
2522 LC = RTLIB::UDIV_I64;
2523 else if (VT == MVT::i128)
2524 LC = RTLIB::UDIV_I128;
2525 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2527 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2530 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2531 SDValue &Lo, SDValue &Hi) {
2532 EVT VT = N->getValueType(0);
2534 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2536 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2537 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2538 SplitInteger(Res.getValue(1), Lo, Hi);
2542 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2544 LC = RTLIB::UREM_I16;
2545 else if (VT == MVT::i32)
2546 LC = RTLIB::UREM_I32;
2547 else if (VT == MVT::i64)
2548 LC = RTLIB::UREM_I64;
2549 else if (VT == MVT::i128)
2550 LC = RTLIB::UREM_I128;
2551 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2553 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
2556 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2557 SDValue &Lo, SDValue &Hi) {
2558 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2560 SDValue Op = N->getOperand(0);
2561 if (Op.getValueType().bitsLE(NVT)) {
2562 // The low part is zero extension of the input (degenerates to a copy).
2563 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2564 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
2566 // For example, extension of an i48 to an i64. The operand type necessarily
2567 // promotes to the result type, so will end up being expanded too.
2568 assert(getTypeAction(Op.getValueType()) ==
2569 TargetLowering::TypePromoteInteger &&
2570 "Only know how to promote this result!");
2571 SDValue Res = GetPromotedInteger(Op);
2572 assert(Res.getValueType() == N->getValueType(0) &&
2573 "Operand over promoted?");
2574 // Split the promoted operand. This will simplify when it is expanded.
2575 SplitInteger(Res, Lo, Hi);
2576 unsigned ExcessBits =
2577 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2578 Hi = DAG.getZeroExtendInReg(Hi, dl,
2579 EVT::getIntegerVT(*DAG.getContext(),
2584 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2585 SDValue &Lo, SDValue &Hi) {
2587 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2588 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2589 SDValue Zero = DAG.getConstant(0, dl, VT);
2590 SDValue Swap = DAG.getAtomicCmpSwap(
2591 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2592 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2593 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2594 cast<AtomicSDNode>(N)->getOrdering(),
2595 cast<AtomicSDNode>(N)->getOrdering(),
2596 cast<AtomicSDNode>(N)->getSynchScope());
2598 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2599 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2602 //===----------------------------------------------------------------------===//
2603 // Integer Operand Expansion
2604 //===----------------------------------------------------------------------===//
2606 /// ExpandIntegerOperand - This method is called when the specified operand of
2607 /// the specified node is found to need expansion. At this point, all of the
2608 /// result types of the node are known to be legal, but other operands of the
2609 /// node may need promotion or expansion as well as the specified one.
2610 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2611 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2612 SDValue Res = SDValue();
2614 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2617 switch (N->getOpcode()) {
2620 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2621 N->dump(&DAG); dbgs() << "\n";
2623 llvm_unreachable("Do not know how to expand this operator's operand!");
2625 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2626 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2627 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2628 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2629 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2630 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2631 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2632 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2633 case ISD::SETCCE: Res = ExpandIntOp_SETCCE(N); break;
2634 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2635 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2636 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2637 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2643 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2644 case ISD::RETURNADDR:
2645 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2647 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2650 // If the result is null, the sub-method took care of registering results etc.
2651 if (!Res.getNode()) return false;
2653 // If the result is N, the sub-method updated N in place. Tell the legalizer
2655 if (Res.getNode() == N)
2658 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2659 "Invalid operand expansion");
2661 ReplaceValueWith(SDValue(N, 0), Res);
2665 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2666 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2667 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2669 ISD::CondCode &CCCode,
2671 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2672 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2673 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2675 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2676 if (RHSLo == RHSHi) {
2677 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2678 if (RHSCST->isAllOnesValue()) {
2679 // Equality comparison to -1.
2680 NewLHS = DAG.getNode(ISD::AND, dl,
2681 LHSLo.getValueType(), LHSLo, LHSHi);
2688 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2689 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2690 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2691 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
2695 // If this is a comparison of the sign bit, just look at the top part.
2697 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2698 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2699 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2705 // FIXME: This generated code sucks.
2706 ISD::CondCode LowCC;
2708 default: llvm_unreachable("Unknown integer setcc!");
2710 case ISD::SETULT: LowCC = ISD::SETULT; break;
2712 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2714 case ISD::SETULE: LowCC = ISD::SETULE; break;
2716 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2719 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2720 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2721 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2723 // NOTE: on targets without efficient SELECT of bools, we can always use
2724 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2725 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2728 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2729 TLI.isTypeLegal(RHSLo.getValueType()))
2730 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2731 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2732 if (!Tmp1.getNode())
2733 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2734 LHSLo, RHSLo, LowCC);
2735 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2736 TLI.isTypeLegal(RHSHi.getValueType()))
2737 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2738 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2739 if (!Tmp2.getNode())
2740 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2741 getSetCCResultType(LHSHi.getValueType()),
2742 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2744 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2745 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2746 if ((Tmp1C && Tmp1C->isNullValue()) ||
2747 (Tmp2C && Tmp2C->isNullValue() &&
2748 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2749 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2750 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2751 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2752 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2753 // low part is known false, returns high part.
2754 // For LE / GE, if high part is known false, ignore the low part.
2755 // For LT / GT, if high part is known true, ignore the low part.
2761 if (LHSHi == RHSHi) {
2762 // Comparing the low bits is enough.
2768 // Lower with SETCCE if the target supports it.
2769 // FIXME: Make all targets support this, then remove the other lowering.
2770 if (TLI.getOperationAction(
2772 TLI.getTypeToExpandTo(*DAG.getContext(), LHSLo.getValueType())) ==
2773 TargetLowering::Custom) {
2774 // SETCCE can detect < and >= directly. For > and <=, flip operands and
2776 bool FlipOperands = false;
2778 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
2779 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
2780 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
2781 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
2785 std::swap(LHSLo, RHSLo);
2786 std::swap(LHSHi, RHSHi);
2788 // Perform a wide subtraction, feeding the carry from the low part into
2789 // SETCCE. The SETCCE operation is essentially looking at the high part of
2790 // the result of LHS - RHS. It is negative iff LHS < RHS. It is zero or
2791 // positive iff LHS >= RHS.
2792 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), MVT::Glue);
2793 SDValue LowCmp = DAG.getNode(ISD::SUBC, dl, VTList, LHSLo, RHSLo);
2795 DAG.getNode(ISD::SETCCE, dl, getSetCCResultType(LHSLo.getValueType()),
2796 LHSHi, RHSHi, LowCmp.getValue(1), DAG.getCondCode(CCCode));
2802 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2803 LHSHi, RHSHi, ISD::SETEQ, false,
2804 DagCombineInfo, dl);
2805 if (!NewLHS.getNode())
2806 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2807 LHSHi, RHSHi, ISD::SETEQ);
2808 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2809 NewLHS, Tmp1, Tmp2);
2813 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2814 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2815 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2816 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2818 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2819 // against zero to select between true and false values.
2820 if (!NewRHS.getNode()) {
2821 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2822 CCCode = ISD::SETNE;
2825 // Update N to have the operands specified.
2826 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2827 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2828 N->getOperand(4)), 0);
2831 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2832 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2833 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2834 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2836 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2837 // against zero to select between true and false values.
2838 if (!NewRHS.getNode()) {
2839 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2840 CCCode = ISD::SETNE;
2843 // Update N to have the operands specified.
2844 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2845 N->getOperand(2), N->getOperand(3),
2846 DAG.getCondCode(CCCode)), 0);
2849 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2850 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2851 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2852 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2854 // If ExpandSetCCOperands returned a scalar, use it.
2855 if (!NewRHS.getNode()) {
2856 assert(NewLHS.getValueType() == N->getValueType(0) &&
2857 "Unexpected setcc expansion!");
2861 // Otherwise, update N to have the operands specified.
2862 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2863 DAG.getCondCode(CCCode)), 0);
2866 SDValue DAGTypeLegalizer::ExpandIntOp_SETCCE(SDNode *N) {
2867 SDValue LHS = N->getOperand(0);
2868 SDValue RHS = N->getOperand(1);
2869 SDValue Carry = N->getOperand(2);
2870 SDValue Cond = N->getOperand(3);
2871 SDLoc dl = SDLoc(N);
2873 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2874 GetExpandedInteger(LHS, LHSLo, LHSHi);
2875 GetExpandedInteger(RHS, RHSLo, RHSHi);
2877 // Expand to a SUBE for the low part and a smaller SETCCE for the high.
2878 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), MVT::Glue);
2879 SDValue LowCmp = DAG.getNode(ISD::SUBE, dl, VTList, LHSLo, RHSLo, Carry);
2880 return DAG.getNode(ISD::SETCCE, dl, N->getValueType(0), LHSHi, RHSHi,
2881 LowCmp.getValue(1), Cond);
2884 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2885 // The value being shifted is legal, but the shift amount is too big.
2886 // It follows that either the result of the shift is undefined, or the
2887 // upper half of the shift amount is zero. Just use the lower half.
2889 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2890 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2893 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2894 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2895 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2896 // constant to valid type.
2898 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2899 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2902 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2903 SDValue Op = N->getOperand(0);
2904 EVT DstVT = N->getValueType(0);
2905 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2906 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2907 "Don't know how to expand this SINT_TO_FP!");
2908 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, SDLoc(N)).first;
2911 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2912 if (ISD::isNormalStore(N))
2913 return ExpandOp_NormalStore(N, OpNo);
2915 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2916 assert(OpNo == 1 && "Can only expand the stored value so far");
2918 EVT VT = N->getOperand(1).getValueType();
2919 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2920 SDValue Ch = N->getChain();
2921 SDValue Ptr = N->getBasePtr();
2922 unsigned Alignment = N->getAlignment();
2923 bool isVolatile = N->isVolatile();
2924 bool isNonTemporal = N->isNonTemporal();
2925 AAMDNodes AAInfo = N->getAAInfo();
2929 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2931 if (N->getMemoryVT().bitsLE(NVT)) {
2932 GetExpandedInteger(N->getValue(), Lo, Hi);
2933 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2934 N->getMemoryVT(), isVolatile, isNonTemporal,
2938 if (DAG.getDataLayout().isLittleEndian()) {
2939 // Little-endian - low bits are at low addresses.
2940 GetExpandedInteger(N->getValue(), Lo, Hi);
2942 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2943 isVolatile, isNonTemporal, Alignment, AAInfo);
2945 unsigned ExcessBits =
2946 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2947 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2949 // Increment the pointer to the other half.
2950 unsigned IncrementSize = NVT.getSizeInBits()/8;
2951 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2952 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2953 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2954 N->getPointerInfo().getWithOffset(IncrementSize),
2955 NEVT, isVolatile, isNonTemporal,
2956 MinAlign(Alignment, IncrementSize), AAInfo);
2957 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2960 // Big-endian - high bits are at low addresses. Favor aligned stores at
2961 // the cost of some bit-fiddling.
2962 GetExpandedInteger(N->getValue(), Lo, Hi);
2964 EVT ExtVT = N->getMemoryVT();
2965 unsigned EBytes = ExtVT.getStoreSize();
2966 unsigned IncrementSize = NVT.getSizeInBits()/8;
2967 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2968 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2969 ExtVT.getSizeInBits() - ExcessBits);
2971 if (ExcessBits < NVT.getSizeInBits()) {
2972 // Transfer high bits from the top of Lo to the bottom of Hi.
2973 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2974 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2975 TLI.getPointerTy(DAG.getDataLayout())));
2977 ISD::OR, dl, NVT, Hi,
2978 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2979 DAG.getConstant(ExcessBits, dl,
2980 TLI.getPointerTy(DAG.getDataLayout()))));
2983 // Store both the high bits and maybe some of the low bits.
2984 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2985 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2987 // Increment the pointer to the other half.
2988 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2989 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2990 // Store the lowest ExcessBits bits in the second half.
2991 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2992 N->getPointerInfo().getWithOffset(IncrementSize),
2993 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2994 isVolatile, isNonTemporal,
2995 MinAlign(Alignment, IncrementSize), AAInfo);
2996 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2999 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
3001 GetExpandedInteger(N->getOperand(0), InL, InH);
3002 // Just truncate the low part of the source.
3003 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
3006 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
3007 SDValue Op = N->getOperand(0);
3008 EVT SrcVT = Op.getValueType();
3009 EVT DstVT = N->getValueType(0);
3012 // The following optimization is valid only if every value in SrcVT (when
3013 // treated as signed) is representable in DstVT. Check that the mantissa
3014 // size of DstVT is >= than the number of bits in SrcVT -1.
3015 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
3016 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
3017 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
3018 // Do a signed conversion then adjust the result.
3019 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
3020 SignedConv = TLI.LowerOperation(SignedConv, DAG);
3022 // The result of the signed conversion needs adjusting if the 'sign bit' of
3023 // the incoming integer was set. To handle this, we dynamically test to see
3024 // if it is set, and, if so, add a fudge factor.
3026 const uint64_t F32TwoE32 = 0x4F800000ULL;
3027 const uint64_t F32TwoE64 = 0x5F800000ULL;
3028 const uint64_t F32TwoE128 = 0x7F800000ULL;
3031 if (SrcVT == MVT::i32)
3032 FF = APInt(32, F32TwoE32);
3033 else if (SrcVT == MVT::i64)
3034 FF = APInt(32, F32TwoE64);
3035 else if (SrcVT == MVT::i128)
3036 FF = APInt(32, F32TwoE128);
3038 llvm_unreachable("Unsupported UINT_TO_FP!");
3040 // Check whether the sign bit is set.
3042 GetExpandedInteger(Op, Lo, Hi);
3043 SDValue SignSet = DAG.getSetCC(dl,
3044 getSetCCResultType(Hi.getValueType()),
3046 DAG.getConstant(0, dl, Hi.getValueType()),
3049 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
3051 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
3052 TLI.getPointerTy(DAG.getDataLayout()));
3054 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
3055 SDValue Zero = DAG.getIntPtrConstant(0, dl);
3056 SDValue Four = DAG.getIntPtrConstant(4, dl);
3057 if (DAG.getDataLayout().isBigEndian())
3058 std::swap(Zero, Four);
3059 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
3061 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
3062 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
3064 Alignment = std::min(Alignment, 4u);
3066 // Load the value out, extending it from f32 to the destination float type.
3067 // FIXME: Avoid the extend by constructing the right constant pool?
3068 SDValue Fudge = DAG.getExtLoad(
3069 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
3070 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
3071 false, false, false, Alignment);
3072 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
3075 // Otherwise, use a libcall.
3076 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
3077 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3078 "Don't know how to expand this UINT_TO_FP!");
3079 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, dl).first;
3082 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
3084 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3085 cast<AtomicSDNode>(N)->getMemoryVT(),
3087 N->getOperand(1), N->getOperand(2),
3088 cast<AtomicSDNode>(N)->getMemOperand(),
3089 cast<AtomicSDNode>(N)->getOrdering(),
3090 cast<AtomicSDNode>(N)->getSynchScope());
3091 return Swap.getValue(1);
3095 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
3096 SDValue InOp0 = N->getOperand(0);
3097 EVT InVT = InOp0.getValueType();
3099 EVT OutVT = N->getValueType(0);
3100 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3101 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3102 unsigned OutNumElems = OutVT.getVectorNumElements();
3103 EVT NOutVTElem = NOutVT.getVectorElementType();
3106 SDValue BaseIdx = N->getOperand(1);
3108 SmallVector<SDValue, 8> Ops;
3109 Ops.reserve(OutNumElems);
3110 for (unsigned i = 0; i != OutNumElems; ++i) {
3112 // Extract the element from the original vector.
3113 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3114 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
3115 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3116 InVT.getVectorElementType(), N->getOperand(0), Index);
3118 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3119 // Insert the converted element to the new vector.
3123 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3127 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3128 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3129 EVT VT = N->getValueType(0);
3132 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3134 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3135 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3136 EVT OutVT = V0.getValueType();
3138 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3142 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3143 EVT OutVT = N->getValueType(0);
3144 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3145 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3146 unsigned NumElems = N->getNumOperands();
3147 EVT NOutVTElem = NOutVT.getVectorElementType();
3151 SmallVector<SDValue, 8> Ops;
3152 Ops.reserve(NumElems);
3153 for (unsigned i = 0; i != NumElems; ++i) {
3155 // BUILD_VECTOR integer operand types are allowed to be larger than the
3156 // result's element type. This may still be true after the promotion. For
3157 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3158 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3159 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3160 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3162 Op = N->getOperand(i);
3166 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3169 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3173 assert(!N->getOperand(0).getValueType().isVector() &&
3174 "Input must be a scalar");
3176 EVT OutVT = N->getValueType(0);
3177 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3178 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3179 EVT NOutVTElem = NOutVT.getVectorElementType();
3181 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3183 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3186 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3189 EVT OutVT = N->getValueType(0);
3190 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3191 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3193 EVT InElemTy = OutVT.getVectorElementType();
3194 EVT OutElemTy = NOutVT.getVectorElementType();
3196 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3197 unsigned NumOutElem = NOutVT.getVectorNumElements();
3198 unsigned NumOperands = N->getNumOperands();
3199 assert(NumElem * NumOperands == NumOutElem &&
3200 "Unexpected number of elements");
3202 // Take the elements from the first vector.
3203 SmallVector<SDValue, 8> Ops(NumOutElem);
3204 for (unsigned i = 0; i < NumOperands; ++i) {
3205 SDValue Op = N->getOperand(i);
3206 for (unsigned j = 0; j < NumElem; ++j) {
3207 SDValue Ext = DAG.getNode(
3208 ISD::EXTRACT_VECTOR_ELT, dl, InElemTy, Op,
3209 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3210 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3214 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3217 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3218 EVT OutVT = N->getValueType(0);
3219 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3220 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3222 EVT NOutVTElem = NOutVT.getVectorElementType();
3225 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3227 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3228 NOutVTElem, N->getOperand(1));
3229 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3230 V0, ConvElem, N->getOperand(2));
3233 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3235 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3236 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
3237 TLI.getVectorIdxTy(DAG.getDataLayout()));
3238 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3239 V0->getValueType(0).getScalarType(), V0, V1);
3241 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3242 // element types. If this is the case then we need to expand the outgoing
3243 // value and not truncate it.
3244 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3247 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
3249 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3250 MVT InVT = V0.getValueType().getSimpleVT();
3251 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
3252 N->getValueType(0).getVectorNumElements());
3253 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
3254 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
3257 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3259 unsigned NumElems = N->getNumOperands();
3261 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3263 SmallVector<SDValue, 8> NewOps;
3264 NewOps.reserve(NumElems);
3266 // For each incoming vector
3267 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3268 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3269 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3270 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3272 for (unsigned i=0; i<NumElem; ++i) {
3273 // Extract element from incoming vector
3274 SDValue Ex = DAG.getNode(
3275 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
3276 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3277 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3278 NewOps.push_back(Tr);
3282 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);