1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
70 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
71 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
73 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
77 case ISD::UMAX: Res = PromoteIntRes_SimpleIntBinOp(N); break;
78 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
79 case ISD::SIGN_EXTEND_INREG:
80 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
81 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
82 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
83 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
84 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
85 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
87 case ISD::EXTRACT_SUBVECTOR:
88 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
89 case ISD::VECTOR_SHUFFLE:
90 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
91 case ISD::INSERT_VECTOR_ELT:
92 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
93 case ISD::BUILD_VECTOR:
94 Res = PromoteIntRes_BUILD_VECTOR(N); break;
95 case ISD::SCALAR_TO_VECTOR:
96 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
97 case ISD::CONCAT_VECTORS:
98 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
100 case ISD::SIGN_EXTEND:
101 case ISD::ZERO_EXTEND:
102 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
104 case ISD::FP_TO_SINT:
105 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
107 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
114 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
117 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
120 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
123 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
125 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
127 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
129 case ISD::ATOMIC_LOAD:
130 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
132 case ISD::ATOMIC_LOAD_ADD:
133 case ISD::ATOMIC_LOAD_SUB:
134 case ISD::ATOMIC_LOAD_AND:
135 case ISD::ATOMIC_LOAD_OR:
136 case ISD::ATOMIC_LOAD_XOR:
137 case ISD::ATOMIC_LOAD_NAND:
138 case ISD::ATOMIC_LOAD_MIN:
139 case ISD::ATOMIC_LOAD_MAX:
140 case ISD::ATOMIC_LOAD_UMIN:
141 case ISD::ATOMIC_LOAD_UMAX:
142 case ISD::ATOMIC_SWAP:
143 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
145 case ISD::ATOMIC_CMP_SWAP:
146 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
147 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
151 // If the result is null then the sub-method took care of registering it.
153 SetPromotedInteger(SDValue(N, ResNo), Res);
156 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
158 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
159 return GetPromotedInteger(Op);
162 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
163 // Sign-extend the new bits, and continue the assertion.
164 SDValue Op = SExtPromotedInteger(N->getOperand(0));
165 return DAG.getNode(ISD::AssertSext, SDLoc(N),
166 Op.getValueType(), Op, N->getOperand(1));
169 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
170 // Zero the new bits, and continue the assertion.
171 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
172 return DAG.getNode(ISD::AssertZext, SDLoc(N),
173 Op.getValueType(), Op, N->getOperand(1));
176 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
177 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
178 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
179 N->getMemoryVT(), ResVT,
180 N->getChain(), N->getBasePtr(),
181 N->getMemOperand(), N->getOrdering(),
183 // Legalized the chain result - switch anything that used the old chain to
185 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
189 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
190 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
191 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
193 N->getChain(), N->getBasePtr(),
194 Op2, N->getMemOperand(), N->getOrdering(),
196 // Legalized the chain result - switch anything that used the old chain to
198 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
202 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
205 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
206 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
207 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
209 // Only use the result of getSetCCResultType if it is legal,
210 // otherwise just use the promoted result type (NVT).
211 if (!TLI.isTypeLegal(SVT))
214 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
215 SDValue Res = DAG.getAtomicCmpSwap(
216 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
217 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
218 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
220 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
221 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
222 return Res.getValue(1);
225 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
226 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
228 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
229 SDValue Res = DAG.getAtomicCmpSwap(
230 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
231 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
232 N->getFailureOrdering(), N->getSynchScope());
233 // Update the use to N with the newly created Res.
234 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
235 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
240 SDValue InOp = N->getOperand(0);
241 EVT InVT = InOp.getValueType();
242 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
243 EVT OutVT = N->getValueType(0);
244 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
247 switch (getTypeAction(InVT)) {
248 case TargetLowering::TypeLegal:
250 case TargetLowering::TypePromoteInteger:
251 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
252 // The input promotes to the same size. Convert the promoted value.
253 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
255 case TargetLowering::TypeSoftenFloat:
256 // Promote the integer operand by hand.
257 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
258 case TargetLowering::TypePromoteFloat: {
259 // Convert the promoted float by hand.
260 if (NOutVT.bitsEq(NInVT)) {
261 SDValue PromotedOp = GetPromotedFloat(InOp);
262 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
263 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
264 DAG.getValueType(OutVT));
268 case TargetLowering::TypeExpandInteger:
269 case TargetLowering::TypeExpandFloat:
271 case TargetLowering::TypeScalarizeVector:
272 // Convert the element to an integer and promote it by hand.
273 if (!NOutVT.isVector())
274 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
275 BitConvertToInteger(GetScalarizedVector(InOp)));
277 case TargetLowering::TypeSplitVector: {
278 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
279 // pieces of the input into integers and reassemble in the final type.
281 GetSplitVector(N->getOperand(0), Lo, Hi);
282 Lo = BitConvertToInteger(Lo);
283 Hi = BitConvertToInteger(Hi);
285 if (DAG.getDataLayout().isBigEndian())
288 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
289 EVT::getIntegerVT(*DAG.getContext(),
290 NOutVT.getSizeInBits()),
291 JoinIntegers(Lo, Hi));
292 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
294 case TargetLowering::TypeWidenVector:
295 // The input is widened to the same size. Convert to the widened value.
296 // Make sure that the outgoing value is not a vector, because this would
297 // make us bitcast between two vectors which are legalized in different ways.
298 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
299 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
302 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
303 CreateStackStoreLoad(InOp, OutVT));
306 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
307 SDValue Op = GetPromotedInteger(N->getOperand(0));
308 EVT OVT = N->getValueType(0);
309 EVT NVT = Op.getValueType();
312 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
313 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
314 DAG.getConstant(DiffBits, dl, TLI.getShiftAmountTy(NVT)));
317 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
318 // The pair element type may be legal, or may not promote to the same type as
319 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
320 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
321 TLI.getTypeToTransformTo(*DAG.getContext(),
322 N->getValueType(0)), JoinIntegers(N->getOperand(0),
326 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
327 EVT VT = N->getValueType(0);
328 // FIXME there is no actual debug info here
330 // Zero extend things like i1, sign extend everything else. It shouldn't
331 // matter in theory which one we pick, but this tends to give better code?
332 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
333 SDValue Result = DAG.getNode(Opc, dl,
334 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
336 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
340 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
341 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
342 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
343 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
344 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
345 "can only promote integers");
346 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
347 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
348 N->getOperand(1), N->getOperand(2),
349 N->getOperand(3), N->getOperand(4), CvtCode);
352 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
353 // Zero extend to the promoted type and do the count there.
354 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
356 EVT OVT = N->getValueType(0);
357 EVT NVT = Op.getValueType();
358 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
359 // Subtract off the extra leading bits in the bigger type.
361 ISD::SUB, dl, NVT, Op,
362 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
366 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
367 // Zero extend to the promoted type and do the count there.
368 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
369 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
372 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
373 SDValue Op = GetPromotedInteger(N->getOperand(0));
374 EVT OVT = N->getValueType(0);
375 EVT NVT = Op.getValueType();
377 if (N->getOpcode() == ISD::CTTZ) {
378 // The count is the same in the promoted type except if the original
379 // value was zero. This can be handled by setting the bit just off
380 // the top of the original type.
381 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
382 OVT.getScalarSizeInBits());
383 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
385 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
388 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
390 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
391 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
395 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
396 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
397 unsigned NewOpc = N->getOpcode();
400 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
401 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
402 // and SINT conversions are Custom, there is no way to tell which is
403 // preferable. We choose SINT because that's the right thing on PPC.)
404 if (N->getOpcode() == ISD::FP_TO_UINT &&
405 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
406 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
407 NewOpc = ISD::FP_TO_SINT;
409 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
411 // Assert that the converted value fits in the original type. If it doesn't
412 // (eg: because the value being converted is too big), then the result of the
413 // original operation was undefined anyway, so the assert is still correct.
414 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
415 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
416 DAG.getValueType(N->getValueType(0).getScalarType()));
419 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
420 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
423 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
425 return DAG.getNode(ISD::AssertZext, dl,
426 NVT, Res, DAG.getValueType(N->getValueType(0)));
429 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
430 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
433 if (getTypeAction(N->getOperand(0).getValueType())
434 == TargetLowering::TypePromoteInteger) {
435 SDValue Res = GetPromotedInteger(N->getOperand(0));
436 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
438 // If the result and operand types are the same after promotion, simplify
439 // to an in-register extension.
440 if (NVT == Res.getValueType()) {
441 // The high bits are not guaranteed to be anything. Insert an extend.
442 if (N->getOpcode() == ISD::SIGN_EXTEND)
443 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
444 DAG.getValueType(N->getOperand(0).getValueType()));
445 if (N->getOpcode() == ISD::ZERO_EXTEND)
446 return DAG.getZeroExtendInReg(Res, dl,
447 N->getOperand(0).getValueType().getScalarType());
448 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
453 // Otherwise, just extend the original operand all the way to the larger type.
454 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
457 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
458 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
459 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
460 ISD::LoadExtType ExtType =
461 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
463 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
464 N->getMemoryVT(), N->getMemOperand());
466 // Legalized the chain result - switch anything that used the old chain to
468 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
472 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
473 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
474 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
476 SDValue Mask = N->getMask();
477 EVT NewMaskVT = getSetCCResultType(NVT);
478 if (NewMaskVT != N->getMask().getValueType())
479 Mask = PromoteTargetBoolean(Mask, NewMaskVT);
482 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
483 Mask, ExtSrc0, N->getMemoryVT(),
484 N->getMemOperand(), ISD::SEXTLOAD);
485 // Legalized the chain result - switch anything that used the old chain to
487 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
490 /// Promote the overflow flag of an overflowing arithmetic node.
491 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
492 // Simply change the return type of the boolean result.
493 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
494 EVT ValueVTs[] = { N->getValueType(0), NVT };
495 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
496 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
497 DAG.getVTList(ValueVTs), Ops);
499 // Modified the sum result - switch anything that used the old sum to use
501 ReplaceValueWith(SDValue(N, 0), Res);
503 return SDValue(Res.getNode(), 1);
506 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
508 return PromoteIntRes_Overflow(N);
510 // The operation overflowed iff the result in the larger type is not the
511 // sign extension of its truncation to the original type.
512 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
513 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
514 EVT OVT = N->getOperand(0).getValueType();
515 EVT NVT = LHS.getValueType();
518 // Do the arithmetic in the larger type.
519 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
520 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
522 // Calculate the overflow flag: sign extend the arithmetic result from
523 // the original type.
524 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
525 DAG.getValueType(OVT));
526 // Overflowed if and only if this is not equal to Res.
527 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
529 // Use the calculated overflow everywhere.
530 ReplaceValueWith(SDValue(N, 1), Ofl);
535 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
536 // Sign extend the input.
537 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
538 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
539 return DAG.getNode(N->getOpcode(), SDLoc(N),
540 LHS.getValueType(), LHS, RHS);
543 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
544 SDValue LHS = GetPromotedInteger(N->getOperand(1));
545 SDValue RHS = GetPromotedInteger(N->getOperand(2));
546 return DAG.getSelect(SDLoc(N),
547 LHS.getValueType(), N->getOperand(0), LHS, RHS);
550 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
551 SDValue Mask = N->getOperand(0);
552 EVT OpTy = N->getOperand(1).getValueType();
554 // Promote all the way up to the canonical SetCC type.
555 Mask = PromoteTargetBoolean(Mask, OpTy);
556 SDValue LHS = GetPromotedInteger(N->getOperand(1));
557 SDValue RHS = GetPromotedInteger(N->getOperand(2));
558 return DAG.getNode(ISD::VSELECT, SDLoc(N),
559 LHS.getValueType(), Mask, LHS, RHS);
562 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
563 SDValue LHS = GetPromotedInteger(N->getOperand(2));
564 SDValue RHS = GetPromotedInteger(N->getOperand(3));
565 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
566 LHS.getValueType(), N->getOperand(0),
567 N->getOperand(1), LHS, RHS, N->getOperand(4));
570 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
571 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
573 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
575 // Only use the result of getSetCCResultType if it is legal,
576 // otherwise just use the promoted result type (NVT).
577 if (!TLI.isTypeLegal(SVT))
581 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
582 "Vector compare must return a vector result!");
584 SDValue LHS = N->getOperand(0);
585 SDValue RHS = N->getOperand(1);
586 if (LHS.getValueType() != RHS.getValueType()) {
587 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
588 !LHS.getValueType().isVector())
589 LHS = GetPromotedInteger(LHS);
590 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
591 !RHS.getValueType().isVector())
592 RHS = GetPromotedInteger(RHS);
595 // Get the SETCC result using the canonical SETCC type.
596 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
599 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
600 // Convert to the expected type.
601 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
604 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
605 SDValue LHS = N->getOperand(0);
606 SDValue RHS = N->getOperand(1);
607 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
608 LHS = GetPromotedInteger(LHS);
609 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
610 RHS = ZExtPromotedInteger(RHS);
611 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
614 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
615 SDValue Op = GetPromotedInteger(N->getOperand(0));
616 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
617 Op.getValueType(), Op, N->getOperand(1));
620 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
621 // The input may have strange things in the top bits of the registers, but
622 // these operations don't care. They may have weird bits going out, but
623 // that too is okay if they are integer operations.
624 SDValue LHS = GetPromotedInteger(N->getOperand(0));
625 SDValue RHS = GetPromotedInteger(N->getOperand(1));
626 return DAG.getNode(N->getOpcode(), SDLoc(N),
627 LHS.getValueType(), LHS, RHS);
630 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
631 SDValue LHS = N->getOperand(0);
632 SDValue RHS = N->getOperand(1);
633 // The input value must be properly sign extended.
634 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
635 LHS = SExtPromotedInteger(LHS);
636 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
637 RHS = ZExtPromotedInteger(RHS);
638 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
641 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
642 SDValue LHS = N->getOperand(0);
643 SDValue RHS = N->getOperand(1);
644 // The input value must be properly zero extended.
645 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
646 LHS = ZExtPromotedInteger(LHS);
647 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
648 RHS = ZExtPromotedInteger(RHS);
649 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
652 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
653 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
655 SDValue InOp = N->getOperand(0);
658 switch (getTypeAction(InOp.getValueType())) {
659 default: llvm_unreachable("Unknown type action!");
660 case TargetLowering::TypeLegal:
661 case TargetLowering::TypeExpandInteger:
664 case TargetLowering::TypePromoteInteger:
665 Res = GetPromotedInteger(InOp);
667 case TargetLowering::TypeSplitVector:
668 EVT InVT = InOp.getValueType();
669 assert(InVT.isVector() && "Cannot split scalar types");
670 unsigned NumElts = InVT.getVectorNumElements();
671 assert(NumElts == NVT.getVectorNumElements() &&
672 "Dst and Src must have the same number of elements");
673 assert(isPowerOf2_32(NumElts) &&
674 "Promoted vector type must be a power of two");
677 GetSplitVector(InOp, EOp1, EOp2);
679 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
681 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
682 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
684 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
687 // Truncate to NVT instead of VT
688 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
691 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
693 return PromoteIntRes_Overflow(N);
695 // The operation overflowed iff the result in the larger type is not the
696 // zero extension of its truncation to the original type.
697 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
698 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
699 EVT OVT = N->getOperand(0).getValueType();
700 EVT NVT = LHS.getValueType();
703 // Do the arithmetic in the larger type.
704 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
705 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
707 // Calculate the overflow flag: zero extend the arithmetic result from
708 // the original type.
709 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
710 // Overflowed if and only if this is not equal to Res.
711 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
713 // Use the calculated overflow everywhere.
714 ReplaceValueWith(SDValue(N, 1), Ofl);
719 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
720 // Promote the overflow bit trivially.
722 return PromoteIntRes_Overflow(N);
724 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
726 EVT SmallVT = LHS.getValueType();
728 // To determine if the result overflowed in a larger type, we extend the
729 // input to the larger type, do the multiply (checking if it overflows),
730 // then also check the high bits of the result to see if overflow happened
732 if (N->getOpcode() == ISD::SMULO) {
733 LHS = SExtPromotedInteger(LHS);
734 RHS = SExtPromotedInteger(RHS);
736 LHS = ZExtPromotedInteger(LHS);
737 RHS = ZExtPromotedInteger(RHS);
739 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
740 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
742 // Overflow occurred if it occurred in the larger type, or if the high part
743 // of the result does not zero/sign-extend the low part. Check this second
744 // possibility first.
746 if (N->getOpcode() == ISD::UMULO) {
747 // Unsigned overflow occurred if the high part is non-zero.
748 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
749 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
751 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
752 DAG.getConstant(0, DL, Hi.getValueType()),
755 // Signed overflow occurred if the high part does not sign extend the low.
756 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
757 Mul, DAG.getValueType(SmallVT));
758 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
761 // The only other way for overflow to occur is if the multiplication in the
762 // larger type itself overflowed.
763 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
764 SDValue(Mul.getNode(), 1));
766 // Use the calculated overflow everywhere.
767 ReplaceValueWith(SDValue(N, 1), Overflow);
771 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
772 // Zero extend the input.
773 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
774 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
775 return DAG.getNode(N->getOpcode(), SDLoc(N),
776 LHS.getValueType(), LHS, RHS);
779 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
780 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
781 N->getValueType(0)));
784 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
785 SDValue Chain = N->getOperand(0); // Get the chain.
786 SDValue Ptr = N->getOperand(1); // Get the pointer.
787 EVT VT = N->getValueType(0);
790 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
791 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
792 // The argument is passed as NumRegs registers of type RegVT.
794 SmallVector<SDValue, 8> Parts(NumRegs);
795 for (unsigned i = 0; i < NumRegs; ++i) {
796 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
797 N->getConstantOperandVal(3));
798 Chain = Parts[i].getValue(1);
801 // Handle endianness of the load.
802 if (DAG.getDataLayout().isBigEndian())
803 std::reverse(Parts.begin(), Parts.end());
805 // Assemble the parts in the promoted type.
806 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
807 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
808 for (unsigned i = 1; i < NumRegs; ++i) {
809 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
810 // Shift it to the right position and "or" it in.
811 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
812 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
813 TLI.getPointerTy(DAG.getDataLayout())));
814 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
817 // Modified the chain result - switch anything that used the old chain to
819 ReplaceValueWith(SDValue(N, 1), Chain);
824 //===----------------------------------------------------------------------===//
825 // Integer Operand Promotion
826 //===----------------------------------------------------------------------===//
828 /// PromoteIntegerOperand - This method is called when the specified operand of
829 /// the specified node is found to need promotion. At this point, all of the
830 /// result types of the node are known to be legal, but other operands of the
831 /// node may need promotion or expansion as well as the specified one.
832 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
833 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
834 SDValue Res = SDValue();
836 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
839 switch (N->getOpcode()) {
842 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
843 N->dump(&DAG); dbgs() << "\n";
845 llvm_unreachable("Do not know how to promote this operator's operand!");
847 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
848 case ISD::ATOMIC_STORE:
849 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
851 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
852 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
853 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
854 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
855 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
856 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
857 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
858 case ISD::CONVERT_RNDSAT:
859 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
860 case ISD::INSERT_VECTOR_ELT:
861 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
862 case ISD::SCALAR_TO_VECTOR:
863 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
865 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
866 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
867 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
868 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
869 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
870 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
872 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
874 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
876 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
877 case ISD::FP16_TO_FP:
878 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
879 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
880 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
886 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
889 // If the result is null, the sub-method took care of registering results etc.
890 if (!Res.getNode()) return false;
892 // If the result is N, the sub-method updated N in place. Tell the legalizer
894 if (Res.getNode() == N)
897 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
898 "Invalid operand expansion");
900 ReplaceValueWith(SDValue(N, 0), Res);
904 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
905 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
906 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
907 ISD::CondCode CCCode) {
908 // We have to insert explicit sign or zero extends. Note that we could
909 // insert sign extends for ALL conditions, but zero extend is cheaper on
910 // many machines (an AND instead of two shifts), so prefer it.
912 default: llvm_unreachable("Unknown integer comparison!");
915 SDValue OpL = GetPromotedInteger(NewLHS);
916 SDValue OpR = GetPromotedInteger(NewRHS);
918 // We would prefer to promote the comparison operand with sign extension,
919 // if we find the operand is actually to truncate an AssertSext. With this
920 // optimization, we can avoid inserting real truncate instruction, which
921 // is redudant eventually.
922 if (OpL->getOpcode() == ISD::AssertSext &&
923 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
924 OpR->getOpcode() == ISD::AssertSext &&
925 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
929 NewLHS = ZExtPromotedInteger(NewLHS);
930 NewRHS = ZExtPromotedInteger(NewRHS);
938 // ALL of these operations will work if we either sign or zero extend
939 // the operands (including the unsigned comparisons!). Zero extend is
940 // usually a simpler/cheaper operation, so prefer it.
941 NewLHS = ZExtPromotedInteger(NewLHS);
942 NewRHS = ZExtPromotedInteger(NewRHS);
948 NewLHS = SExtPromotedInteger(NewLHS);
949 NewRHS = SExtPromotedInteger(NewRHS);
954 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
955 SDValue Op = GetPromotedInteger(N->getOperand(0));
956 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
959 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
960 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
961 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
962 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
963 N->getOrdering(), N->getSynchScope());
966 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
967 // This should only occur in unusual situations like bitcasting to an
968 // x86_fp80, so just turn it into a store+load
969 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
972 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
973 assert(OpNo == 2 && "Don't know how to promote this operand!");
975 SDValue LHS = N->getOperand(2);
976 SDValue RHS = N->getOperand(3);
977 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
979 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
981 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
982 N->getOperand(1), LHS, RHS, N->getOperand(4)),
986 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
987 assert(OpNo == 1 && "only know how to promote condition");
989 // Promote all the way up to the canonical SetCC type.
990 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
992 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
993 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
994 N->getOperand(2)), 0);
997 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
998 // Since the result type is legal, the operands must promote to it.
999 EVT OVT = N->getOperand(0).getValueType();
1000 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1001 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1002 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1005 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1006 DAG.getConstant(OVT.getSizeInBits(), dl,
1007 TLI.getPointerTy(DAG.getDataLayout())));
1008 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1011 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1012 // The vector type is legal but the element type is not. This implies
1013 // that the vector is a power-of-two in length and that the element
1014 // type does not have a strange size (eg: it is not i1).
1015 EVT VecVT = N->getValueType(0);
1016 unsigned NumElts = VecVT.getVectorNumElements();
1017 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1018 "Legal vector of one illegal element?");
1020 // Promote the inserted value. The type does not need to match the
1021 // vector element type. Check that any extra bits introduced will be
1023 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1024 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1025 "Type of inserted value narrower than vector element type!");
1027 SmallVector<SDValue, 16> NewOps;
1028 for (unsigned i = 0; i < NumElts; ++i)
1029 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1031 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1034 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1035 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1036 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1037 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1038 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1039 "can only promote integer arguments");
1040 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1041 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1042 N->getOperand(1), N->getOperand(2),
1043 N->getOperand(3), N->getOperand(4), CvtCode);
1046 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1049 // Promote the inserted value. This is valid because the type does not
1050 // have to match the vector element type.
1052 // Check that any extra bits introduced will be truncated away.
1053 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1054 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1055 "Type of inserted value narrower than vector element type!");
1056 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1057 GetPromotedInteger(N->getOperand(1)),
1062 assert(OpNo == 2 && "Different operand and result vector types?");
1064 // Promote the index.
1065 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1066 TLI.getVectorIdxTy(DAG.getDataLayout()));
1067 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1068 N->getOperand(1), Idx), 0);
1071 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1072 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1073 // the operand in place.
1074 return SDValue(DAG.UpdateNodeOperands(N,
1075 GetPromotedInteger(N->getOperand(0))), 0);
1078 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1079 assert(OpNo == 0 && "Only know how to promote the condition!");
1080 SDValue Cond = N->getOperand(0);
1081 EVT OpTy = N->getOperand(1).getValueType();
1083 // Promote all the way up to the canonical SetCC type.
1084 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1085 Cond = PromoteTargetBoolean(Cond, OpVT);
1087 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1088 N->getOperand(2)), 0);
1091 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1092 assert(OpNo == 0 && "Don't know how to promote this operand!");
1094 SDValue LHS = N->getOperand(0);
1095 SDValue RHS = N->getOperand(1);
1096 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1098 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1099 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1100 N->getOperand(3), N->getOperand(4)), 0);
1103 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1104 assert(OpNo == 0 && "Don't know how to promote this operand!");
1106 SDValue LHS = N->getOperand(0);
1107 SDValue RHS = N->getOperand(1);
1108 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1110 // The CC (#2) is always legal.
1111 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1114 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1115 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1116 ZExtPromotedInteger(N->getOperand(1))), 0);
1119 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1120 SDValue Op = GetPromotedInteger(N->getOperand(0));
1122 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1123 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1124 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1127 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1128 return SDValue(DAG.UpdateNodeOperands(N,
1129 SExtPromotedInteger(N->getOperand(0))), 0);
1132 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1133 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1134 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1137 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1139 // Truncate the value and store the result.
1140 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1141 N->getMemoryVT(), N->getMemOperand());
1144 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo){
1146 SDValue DataOp = N->getValue();
1147 EVT DataVT = DataOp.getValueType();
1148 SDValue Mask = N->getMask();
1149 EVT MaskVT = Mask.getValueType();
1152 bool TruncateStore = false;
1153 if (!TLI.isTypeLegal(DataVT)) {
1154 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger) {
1155 DataOp = GetPromotedInteger(DataOp);
1156 if (!TLI.isTypeLegal(MaskVT))
1157 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1158 TruncateStore = true;
1161 assert(getTypeAction(DataVT) == TargetLowering::TypeWidenVector &&
1162 "Unexpected data legalization in MSTORE");
1163 DataOp = GetWidenedVector(DataOp);
1165 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
1166 Mask = GetWidenedVector(Mask);
1168 EVT BoolVT = getSetCCResultType(DataOp.getValueType());
1170 // We can't use ModifyToType() because we should fill the mask with
1172 unsigned WidenNumElts = BoolVT.getVectorNumElements();
1173 unsigned MaskNumElts = MaskVT.getVectorNumElements();
1175 unsigned NumConcat = WidenNumElts / MaskNumElts;
1176 SmallVector<SDValue, 16> Ops(NumConcat);
1177 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
1179 for (unsigned i = 1; i != NumConcat; ++i)
1182 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
1187 Mask = PromoteTargetBoolean(N->getMask(), DataOp.getValueType());
1188 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1189 N->getMemoryVT(), N->getMemOperand(),
1193 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo){
1194 assert(OpNo == 2 && "Only know how to promote the mask!");
1195 EVT DataVT = N->getValueType(0);
1196 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1197 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1198 NewOps[OpNo] = Mask;
1199 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1202 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1203 SDValue Op = GetPromotedInteger(N->getOperand(0));
1204 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1207 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1208 return SDValue(DAG.UpdateNodeOperands(N,
1209 ZExtPromotedInteger(N->getOperand(0))), 0);
1212 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1214 SDValue Op = GetPromotedInteger(N->getOperand(0));
1215 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1216 return DAG.getZeroExtendInReg(Op, dl,
1217 N->getOperand(0).getValueType().getScalarType());
1221 //===----------------------------------------------------------------------===//
1222 // Integer Result Expansion
1223 //===----------------------------------------------------------------------===//
1225 /// ExpandIntegerResult - This method is called when the specified result of the
1226 /// specified node is found to need expansion. At this point, the node may also
1227 /// have invalid operands or may have other results that need promotion, we just
1228 /// know that (at least) one result needs expansion.
1229 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1230 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1232 Lo = Hi = SDValue();
1234 // See if the target wants to custom expand this node.
1235 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1238 switch (N->getOpcode()) {
1241 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1242 N->dump(&DAG); dbgs() << "\n";
1244 llvm_unreachable("Do not know how to expand the result of this operator!");
1246 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1247 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1248 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1249 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1251 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1252 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1253 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1254 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1255 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1257 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1258 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1259 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1260 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1261 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1262 case ISD::CTLZ_ZERO_UNDEF:
1263 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1264 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1265 case ISD::CTTZ_ZERO_UNDEF:
1266 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1267 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1268 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1269 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1270 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1271 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1272 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1273 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1274 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1275 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1276 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1277 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1278 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1279 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1281 case ISD::ATOMIC_LOAD_ADD:
1282 case ISD::ATOMIC_LOAD_SUB:
1283 case ISD::ATOMIC_LOAD_AND:
1284 case ISD::ATOMIC_LOAD_OR:
1285 case ISD::ATOMIC_LOAD_XOR:
1286 case ISD::ATOMIC_LOAD_NAND:
1287 case ISD::ATOMIC_LOAD_MIN:
1288 case ISD::ATOMIC_LOAD_MAX:
1289 case ISD::ATOMIC_LOAD_UMIN:
1290 case ISD::ATOMIC_LOAD_UMAX:
1291 case ISD::ATOMIC_SWAP:
1292 case ISD::ATOMIC_CMP_SWAP: {
1293 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1294 SplitInteger(Tmp.first, Lo, Hi);
1295 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1298 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1299 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1300 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1301 SDValue Tmp = DAG.getAtomicCmpSwap(
1302 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1303 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1304 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1305 AN->getSynchScope());
1307 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1308 // success simply by comparing the loaded value against the ingoing
1310 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1311 N->getOperand(2), ISD::SETEQ);
1313 SplitInteger(Tmp, Lo, Hi);
1314 ReplaceValueWith(SDValue(N, 1), Success);
1315 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1321 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1324 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1327 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1330 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1334 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1337 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1339 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1341 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1344 // If Lo/Hi is null, the sub-method took care of registering results etc.
1346 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1349 /// Lower an atomic node to the appropriate builtin call.
1350 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1351 unsigned Opc = Node->getOpcode();
1352 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1353 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1354 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1356 return ExpandChainLibCall(LC, Node, false);
1359 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1360 /// and the shift amount is a constant 'Amt'. Expand the operation.
1361 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1362 SDValue &Lo, SDValue &Hi) {
1364 // Expand the incoming operand to be shifted, so that we have its parts
1366 GetExpandedInteger(N->getOperand(0), InL, InH);
1368 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1369 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1376 EVT NVT = InL.getValueType();
1377 unsigned VTBits = N->getValueType(0).getSizeInBits();
1378 unsigned NVTBits = NVT.getSizeInBits();
1379 EVT ShTy = N->getOperand(1).getValueType();
1381 if (N->getOpcode() == ISD::SHL) {
1383 Lo = Hi = DAG.getConstant(0, DL, NVT);
1384 } else if (Amt > NVTBits) {
1385 Lo = DAG.getConstant(0, DL, NVT);
1386 Hi = DAG.getNode(ISD::SHL, DL,
1387 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1388 } else if (Amt == NVTBits) {
1389 Lo = DAG.getConstant(0, DL, NVT);
1391 } else if (Amt == 1 &&
1392 TLI.isOperationLegalOrCustom(ISD::ADDC,
1393 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1394 // Emit this X << 1 as X+X.
1395 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1396 SDValue LoOps[2] = { InL, InL };
1397 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1398 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1399 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1401 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1402 Hi = DAG.getNode(ISD::OR, DL, NVT,
1403 DAG.getNode(ISD::SHL, DL, NVT, InH,
1404 DAG.getConstant(Amt, DL, ShTy)),
1405 DAG.getNode(ISD::SRL, DL, NVT, InL,
1406 DAG.getConstant(NVTBits - Amt, DL, ShTy)));
1411 if (N->getOpcode() == ISD::SRL) {
1413 Lo = DAG.getConstant(0, DL, NVT);
1414 Hi = DAG.getConstant(0, DL, NVT);
1415 } else if (Amt > NVTBits) {
1416 Lo = DAG.getNode(ISD::SRL, DL,
1417 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1418 Hi = DAG.getConstant(0, DL, NVT);
1419 } else if (Amt == NVTBits) {
1421 Hi = DAG.getConstant(0, DL, NVT);
1423 Lo = DAG.getNode(ISD::OR, DL, NVT,
1424 DAG.getNode(ISD::SRL, DL, NVT, InL,
1425 DAG.getConstant(Amt, DL, ShTy)),
1426 DAG.getNode(ISD::SHL, DL, NVT, InH,
1427 DAG.getConstant(NVTBits - Amt, DL, ShTy)));
1428 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1433 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1435 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1436 DAG.getConstant(NVTBits - 1, DL, ShTy));
1437 } else if (Amt > NVTBits) {
1438 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1439 DAG.getConstant(Amt-NVTBits, DL, ShTy));
1440 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1441 DAG.getConstant(NVTBits - 1, DL, ShTy));
1442 } else if (Amt == NVTBits) {
1444 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1445 DAG.getConstant(NVTBits - 1, DL, ShTy));
1447 Lo = DAG.getNode(ISD::OR, DL, NVT,
1448 DAG.getNode(ISD::SRL, DL, NVT, InL,
1449 DAG.getConstant(Amt, DL, ShTy)),
1450 DAG.getNode(ISD::SHL, DL, NVT, InH,
1451 DAG.getConstant(NVTBits - Amt, DL, ShTy)));
1452 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1456 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1457 /// this shift based on knowledge of the high bit of the shift amount. If we
1458 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1460 bool DAGTypeLegalizer::
1461 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1462 SDValue Amt = N->getOperand(1);
1463 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1464 EVT ShTy = Amt.getValueType();
1465 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1466 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1467 assert(isPowerOf2_32(NVTBits) &&
1468 "Expanded integer type size not a power of two!");
1471 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1472 APInt KnownZero, KnownOne;
1473 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1475 // If we don't know anything about the high bits, exit.
1476 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1479 // Get the incoming operand to be shifted.
1481 GetExpandedInteger(N->getOperand(0), InL, InH);
1483 // If we know that any of the high bits of the shift amount are one, then we
1484 // can do this as a couple of simple shifts.
1485 if (KnownOne.intersects(HighBitMask)) {
1486 // Mask out the high bit, which we know is set.
1487 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1488 DAG.getConstant(~HighBitMask, dl, ShTy));
1490 switch (N->getOpcode()) {
1491 default: llvm_unreachable("Unknown shift");
1493 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1494 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1497 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1498 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1501 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1502 DAG.getConstant(NVTBits - 1, dl, ShTy));
1503 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1508 // If we know that all of the high bits of the shift amount are zero, then we
1509 // can do this as a couple of simple shifts.
1510 if ((KnownZero & HighBitMask) == HighBitMask) {
1511 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1512 // shift if x is zero. We can use XOR here because x is known to be smaller
1514 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1515 DAG.getConstant(NVTBits - 1, dl, ShTy));
1518 switch (N->getOpcode()) {
1519 default: llvm_unreachable("Unknown shift");
1520 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1522 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1525 // When shifting right the arithmetic for Lo and Hi is swapped.
1526 if (N->getOpcode() != ISD::SHL)
1527 std::swap(InL, InH);
1529 // Use a little trick to get the bits that move from Lo to Hi. First
1530 // shift by one bit.
1531 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1532 // Then compute the remaining shift with amount-1.
1533 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1535 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1536 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1538 if (N->getOpcode() != ISD::SHL)
1546 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1548 bool DAGTypeLegalizer::
1549 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1550 SDValue Amt = N->getOperand(1);
1551 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1552 EVT ShTy = Amt.getValueType();
1553 unsigned NVTBits = NVT.getSizeInBits();
1554 assert(isPowerOf2_32(NVTBits) &&
1555 "Expanded integer type size not a power of two!");
1558 // Get the incoming operand to be shifted.
1560 GetExpandedInteger(N->getOperand(0), InL, InH);
1562 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1563 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1564 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1565 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1566 Amt, NVBitsNode, ISD::SETULT);
1567 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1568 Amt, DAG.getConstant(0, dl, ShTy),
1571 SDValue LoS, HiS, LoL, HiL;
1572 switch (N->getOpcode()) {
1573 default: llvm_unreachable("Unknown shift");
1575 // Short: ShAmt < NVTBits
1576 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1577 HiS = DAG.getNode(ISD::OR, dl, NVT,
1578 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1579 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1581 // Long: ShAmt >= NVTBits
1582 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1583 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1585 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1586 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1587 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1590 // Short: ShAmt < NVTBits
1591 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1592 LoS = DAG.getNode(ISD::OR, dl, NVT,
1593 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1594 // FIXME: If Amt is zero, the following shift generates an undefined result
1595 // on some architectures.
1596 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1598 // Long: ShAmt >= NVTBits
1599 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1600 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1602 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1603 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1604 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1607 // Short: ShAmt < NVTBits
1608 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1609 LoS = DAG.getNode(ISD::OR, dl, NVT,
1610 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1611 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1613 // Long: ShAmt >= NVTBits
1614 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1615 DAG.getConstant(NVTBits - 1, dl, ShTy));
1616 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1618 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1619 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1620 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1625 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1626 SDValue &Lo, SDValue &Hi) {
1628 // Expand the subcomponents.
1629 SDValue LHSL, LHSH, RHSL, RHSH;
1630 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1631 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1633 EVT NVT = LHSL.getValueType();
1634 SDValue LoOps[2] = { LHSL, RHSL };
1635 SDValue HiOps[3] = { LHSH, RHSH };
1637 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1638 // them. TODO: Teach operation legalization how to expand unsupported
1639 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1640 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1641 // generate a value of this type in the expanded code sequence.
1643 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1644 ISD::ADDC : ISD::SUBC,
1645 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1648 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1649 if (N->getOpcode() == ISD::ADD) {
1650 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1651 HiOps[2] = Lo.getValue(1);
1652 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1654 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1655 HiOps[2] = Lo.getValue(1);
1656 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1662 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1663 ISD::UADDO : ISD::USUBO,
1664 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1666 SDVTList VTList = DAG.getVTList(NVT, NVT);
1667 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1669 if (N->getOpcode() == ISD::ADD) {
1671 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1672 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1675 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1676 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1678 SDValue OVF = Lo.getValue(1);
1681 case TargetLoweringBase::UndefinedBooleanContent:
1682 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);
1684 case TargetLoweringBase::ZeroOrOneBooleanContent:
1685 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
1687 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1688 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
1693 if (N->getOpcode() == ISD::ADD) {
1694 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1695 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1696 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1698 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1699 DAG.getConstant(1, dl, NVT),
1700 DAG.getConstant(0, dl, NVT));
1701 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1703 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1704 DAG.getConstant(1, dl, NVT), Carry1);
1705 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1707 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1708 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1710 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1711 LoOps[0], LoOps[1], ISD::SETULT);
1712 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1713 DAG.getConstant(1, dl, NVT),
1714 DAG.getConstant(0, dl, NVT));
1715 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1719 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1720 SDValue &Lo, SDValue &Hi) {
1721 // Expand the subcomponents.
1722 SDValue LHSL, LHSH, RHSL, RHSH;
1724 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1725 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1726 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1727 SDValue LoOps[2] = { LHSL, RHSL };
1728 SDValue HiOps[3] = { LHSH, RHSH };
1730 if (N->getOpcode() == ISD::ADDC) {
1731 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1732 HiOps[2] = Lo.getValue(1);
1733 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1735 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1736 HiOps[2] = Lo.getValue(1);
1737 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1740 // Legalized the flag result - switch anything that used the old flag to
1742 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1745 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1746 SDValue &Lo, SDValue &Hi) {
1747 // Expand the subcomponents.
1748 SDValue LHSL, LHSH, RHSL, RHSH;
1750 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1751 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1752 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1753 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1754 SDValue HiOps[3] = { LHSH, RHSH };
1756 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1757 HiOps[2] = Lo.getValue(1);
1758 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1760 // Legalized the flag result - switch anything that used the old flag to
1762 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1765 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1766 SDValue &Lo, SDValue &Hi) {
1767 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1768 SplitInteger(Res, Lo, Hi);
1771 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1772 SDValue &Lo, SDValue &Hi) {
1773 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1775 SDValue Op = N->getOperand(0);
1776 if (Op.getValueType().bitsLE(NVT)) {
1777 // The low part is any extension of the input (which degenerates to a copy).
1778 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1779 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1781 // For example, extension of an i48 to an i64. The operand type necessarily
1782 // promotes to the result type, so will end up being expanded too.
1783 assert(getTypeAction(Op.getValueType()) ==
1784 TargetLowering::TypePromoteInteger &&
1785 "Only know how to promote this result!");
1786 SDValue Res = GetPromotedInteger(Op);
1787 assert(Res.getValueType() == N->getValueType(0) &&
1788 "Operand over promoted?");
1789 // Split the promoted operand. This will simplify when it is expanded.
1790 SplitInteger(Res, Lo, Hi);
1794 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1795 SDValue &Lo, SDValue &Hi) {
1797 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1798 EVT NVT = Lo.getValueType();
1799 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1800 unsigned NVTBits = NVT.getSizeInBits();
1801 unsigned EVTBits = EVT.getSizeInBits();
1803 if (NVTBits < EVTBits) {
1804 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1805 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1806 EVTBits - NVTBits)));
1808 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1809 // The high part replicates the sign bit of Lo, make it explicit.
1810 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1811 DAG.getConstant(NVTBits - 1, dl,
1812 TLI.getPointerTy(DAG.getDataLayout())));
1816 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1817 SDValue &Lo, SDValue &Hi) {
1819 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1820 EVT NVT = Lo.getValueType();
1821 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1822 unsigned NVTBits = NVT.getSizeInBits();
1823 unsigned EVTBits = EVT.getSizeInBits();
1825 if (NVTBits < EVTBits) {
1826 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1827 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1828 EVTBits - NVTBits)));
1830 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1831 // The high part must be zero, make it explicit.
1832 Hi = DAG.getConstant(0, dl, NVT);
1836 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1837 SDValue &Lo, SDValue &Hi) {
1839 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1840 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1841 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1844 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1845 SDValue &Lo, SDValue &Hi) {
1846 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1847 unsigned NBitWidth = NVT.getSizeInBits();
1848 auto Constant = cast<ConstantSDNode>(N);
1849 const APInt &Cst = Constant->getAPIntValue();
1850 bool IsTarget = Constant->isTargetOpcode();
1851 bool IsOpaque = Constant->isOpaque();
1853 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1854 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1858 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1859 SDValue &Lo, SDValue &Hi) {
1861 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1862 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1863 EVT NVT = Lo.getValueType();
1865 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1866 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1868 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1869 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1871 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1872 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1873 DAG.getConstant(NVT.getSizeInBits(), dl,
1875 Hi = DAG.getConstant(0, dl, NVT);
1878 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1879 SDValue &Lo, SDValue &Hi) {
1881 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1882 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1883 EVT NVT = Lo.getValueType();
1884 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1885 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1886 Hi = DAG.getConstant(0, dl, NVT);
1889 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1890 SDValue &Lo, SDValue &Hi) {
1892 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1893 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1894 EVT NVT = Lo.getValueType();
1896 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1897 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1899 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1900 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1902 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1903 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1904 DAG.getConstant(NVT.getSizeInBits(), dl,
1906 Hi = DAG.getConstant(0, dl, NVT);
1909 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1912 EVT VT = N->getValueType(0);
1914 SDValue Op = N->getOperand(0);
1915 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1916 Op = GetPromotedFloat(Op);
1918 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1919 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1920 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1925 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1928 EVT VT = N->getValueType(0);
1930 SDValue Op = N->getOperand(0);
1931 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1932 Op = GetPromotedFloat(Op);
1934 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1935 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1936 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1941 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1942 SDValue &Lo, SDValue &Hi) {
1943 if (ISD::isNormalLoad(N)) {
1944 ExpandRes_NormalLoad(N, Lo, Hi);
1948 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1950 EVT VT = N->getValueType(0);
1951 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1952 SDValue Ch = N->getChain();
1953 SDValue Ptr = N->getBasePtr();
1954 ISD::LoadExtType ExtType = N->getExtensionType();
1955 unsigned Alignment = N->getAlignment();
1956 bool isVolatile = N->isVolatile();
1957 bool isNonTemporal = N->isNonTemporal();
1958 bool isInvariant = N->isInvariant();
1959 AAMDNodes AAInfo = N->getAAInfo();
1962 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1964 if (N->getMemoryVT().bitsLE(NVT)) {
1965 EVT MemVT = N->getMemoryVT();
1967 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1968 MemVT, isVolatile, isNonTemporal, isInvariant,
1971 // Remember the chain.
1972 Ch = Lo.getValue(1);
1974 if (ExtType == ISD::SEXTLOAD) {
1975 // The high part is obtained by SRA'ing all but one of the bits of the
1977 unsigned LoSize = Lo.getValueType().getSizeInBits();
1978 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1979 DAG.getConstant(LoSize - 1, dl,
1980 TLI.getPointerTy(DAG.getDataLayout())));
1981 } else if (ExtType == ISD::ZEXTLOAD) {
1982 // The high part is just a zero.
1983 Hi = DAG.getConstant(0, dl, NVT);
1985 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1986 // The high part is undefined.
1987 Hi = DAG.getUNDEF(NVT);
1989 } else if (DAG.getDataLayout().isLittleEndian()) {
1990 // Little-endian - low bits are at low addresses.
1991 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1992 isVolatile, isNonTemporal, isInvariant, Alignment,
1995 unsigned ExcessBits =
1996 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1997 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1999 // Increment the pointer to the other half.
2000 unsigned IncrementSize = NVT.getSizeInBits()/8;
2001 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2002 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2003 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2004 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2005 isVolatile, isNonTemporal, isInvariant,
2006 MinAlign(Alignment, IncrementSize), AAInfo);
2008 // Build a factor node to remember that this load is independent of the
2010 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2013 // Big-endian - high bits are at low addresses. Favor aligned loads at
2014 // the cost of some bit-fiddling.
2015 EVT MemVT = N->getMemoryVT();
2016 unsigned EBytes = MemVT.getStoreSize();
2017 unsigned IncrementSize = NVT.getSizeInBits()/8;
2018 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2020 // Load both the high bits and maybe some of the low bits.
2021 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2022 EVT::getIntegerVT(*DAG.getContext(),
2023 MemVT.getSizeInBits() - ExcessBits),
2024 isVolatile, isNonTemporal, isInvariant, Alignment,
2027 // Increment the pointer to the other half.
2028 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2029 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2030 // Load the rest of the low bits.
2031 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2032 N->getPointerInfo().getWithOffset(IncrementSize),
2033 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2034 isVolatile, isNonTemporal, isInvariant,
2035 MinAlign(Alignment, IncrementSize), AAInfo);
2037 // Build a factor node to remember that this load is independent of the
2039 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2042 if (ExcessBits < NVT.getSizeInBits()) {
2043 // Transfer low bits from the bottom of Hi to the top of Lo.
2045 ISD::OR, dl, NVT, Lo,
2046 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2047 DAG.getConstant(ExcessBits, dl,
2048 TLI.getPointerTy(DAG.getDataLayout()))));
2049 // Move high bits to the right position in Hi.
2050 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2052 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2053 TLI.getPointerTy(DAG.getDataLayout())));
2057 // Legalized the chain result - switch anything that used the old chain to
2059 ReplaceValueWith(SDValue(N, 1), Ch);
2062 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2063 SDValue &Lo, SDValue &Hi) {
2065 SDValue LL, LH, RL, RH;
2066 GetExpandedInteger(N->getOperand(0), LL, LH);
2067 GetExpandedInteger(N->getOperand(1), RL, RH);
2068 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2069 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2072 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2073 SDValue &Lo, SDValue &Hi) {
2074 EVT VT = N->getValueType(0);
2075 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2078 SDValue LL, LH, RL, RH;
2079 GetExpandedInteger(N->getOperand(0), LL, LH);
2080 GetExpandedInteger(N->getOperand(1), RL, RH);
2082 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2085 // If nothing else, we can make a libcall.
2086 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2088 LC = RTLIB::MUL_I16;
2089 else if (VT == MVT::i32)
2090 LC = RTLIB::MUL_I32;
2091 else if (VT == MVT::i64)
2092 LC = RTLIB::MUL_I64;
2093 else if (VT == MVT::i128)
2094 LC = RTLIB::MUL_I128;
2095 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2097 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2098 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2103 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2104 SDValue &Lo, SDValue &Hi) {
2105 SDValue LHS = Node->getOperand(0);
2106 SDValue RHS = Node->getOperand(1);
2109 // Expand the result by simply replacing it with the equivalent
2110 // non-overflow-checking operation.
2111 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2112 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2114 SplitInteger(Sum, Lo, Hi);
2116 // Compute the overflow.
2118 // LHSSign -> LHS >= 0
2119 // RHSSign -> RHS >= 0
2120 // SumSign -> Sum >= 0
2123 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2125 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2127 EVT OType = Node->getValueType(1);
2128 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2130 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2131 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2132 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2133 Node->getOpcode() == ISD::SADDO ?
2134 ISD::SETEQ : ISD::SETNE);
2136 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2137 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2139 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2141 // Use the calculated overflow everywhere.
2142 ReplaceValueWith(SDValue(Node, 1), Cmp);
2145 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2146 SDValue &Lo, SDValue &Hi) {
2147 EVT VT = N->getValueType(0);
2149 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2151 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2152 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2153 SplitInteger(Res.getValue(0), Lo, Hi);
2157 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2159 LC = RTLIB::SDIV_I16;
2160 else if (VT == MVT::i32)
2161 LC = RTLIB::SDIV_I32;
2162 else if (VT == MVT::i64)
2163 LC = RTLIB::SDIV_I64;
2164 else if (VT == MVT::i128)
2165 LC = RTLIB::SDIV_I128;
2166 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2168 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2171 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2172 SDValue &Lo, SDValue &Hi) {
2173 EVT VT = N->getValueType(0);
2176 // If we can emit an efficient shift operation, do so now. Check to see if
2177 // the RHS is a constant.
2178 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2179 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2181 // If we can determine that the high bit of the shift is zero or one, even if
2182 // the low bits are variable, emit this shift in an optimized form.
2183 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2186 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2188 if (N->getOpcode() == ISD::SHL) {
2189 PartsOpc = ISD::SHL_PARTS;
2190 } else if (N->getOpcode() == ISD::SRL) {
2191 PartsOpc = ISD::SRL_PARTS;
2193 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2194 PartsOpc = ISD::SRA_PARTS;
2197 // Next check to see if the target supports this SHL_PARTS operation or if it
2198 // will custom expand it.
2199 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2200 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2201 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2202 Action == TargetLowering::Custom) {
2203 // Expand the subcomponents.
2205 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2206 EVT VT = LHSL.getValueType();
2208 // If the shift amount operand is coming from a vector legalization it may
2209 // have an illegal type. Fix that first by casting the operand, otherwise
2210 // the new SHL_PARTS operation would need further legalization.
2211 SDValue ShiftOp = N->getOperand(1);
2212 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2213 assert(ShiftTy.getScalarType().getSizeInBits() >=
2214 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2215 "ShiftAmountTy is too small to cover the range of this type!");
2216 if (ShiftOp.getValueType() != ShiftTy)
2217 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2219 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2220 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2221 Hi = Lo.getValue(1);
2225 // Otherwise, emit a libcall.
2226 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2228 if (N->getOpcode() == ISD::SHL) {
2229 isSigned = false; /*sign irrelevant*/
2231 LC = RTLIB::SHL_I16;
2232 else if (VT == MVT::i32)
2233 LC = RTLIB::SHL_I32;
2234 else if (VT == MVT::i64)
2235 LC = RTLIB::SHL_I64;
2236 else if (VT == MVT::i128)
2237 LC = RTLIB::SHL_I128;
2238 } else if (N->getOpcode() == ISD::SRL) {
2241 LC = RTLIB::SRL_I16;
2242 else if (VT == MVT::i32)
2243 LC = RTLIB::SRL_I32;
2244 else if (VT == MVT::i64)
2245 LC = RTLIB::SRL_I64;
2246 else if (VT == MVT::i128)
2247 LC = RTLIB::SRL_I128;
2249 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2252 LC = RTLIB::SRA_I16;
2253 else if (VT == MVT::i32)
2254 LC = RTLIB::SRA_I32;
2255 else if (VT == MVT::i64)
2256 LC = RTLIB::SRA_I64;
2257 else if (VT == MVT::i128)
2258 LC = RTLIB::SRA_I128;
2261 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2262 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2263 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2268 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2269 llvm_unreachable("Unsupported shift!");
2272 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2273 SDValue &Lo, SDValue &Hi) {
2274 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2276 SDValue Op = N->getOperand(0);
2277 if (Op.getValueType().bitsLE(NVT)) {
2278 // The low part is sign extension of the input (degenerates to a copy).
2279 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2280 // The high part is obtained by SRA'ing all but one of the bits of low part.
2281 unsigned LoSize = NVT.getSizeInBits();
2283 ISD::SRA, dl, NVT, Lo,
2284 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
2286 // For example, extension of an i48 to an i64. The operand type necessarily
2287 // promotes to the result type, so will end up being expanded too.
2288 assert(getTypeAction(Op.getValueType()) ==
2289 TargetLowering::TypePromoteInteger &&
2290 "Only know how to promote this result!");
2291 SDValue Res = GetPromotedInteger(Op);
2292 assert(Res.getValueType() == N->getValueType(0) &&
2293 "Operand over promoted?");
2294 // Split the promoted operand. This will simplify when it is expanded.
2295 SplitInteger(Res, Lo, Hi);
2296 unsigned ExcessBits =
2297 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2298 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2299 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2304 void DAGTypeLegalizer::
2305 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2307 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2308 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2310 if (EVT.bitsLE(Lo.getValueType())) {
2311 // sext_inreg the low part if needed.
2312 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2315 // The high part gets the sign extension from the lo-part. This handles
2316 // things like sextinreg V:i64 from i8.
2317 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2318 DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl,
2319 TLI.getPointerTy(DAG.getDataLayout())));
2321 // For example, extension of an i48 to an i64. Leave the low part alone,
2322 // sext_inreg the high part.
2323 unsigned ExcessBits =
2324 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2325 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2326 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2331 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2332 SDValue &Lo, SDValue &Hi) {
2333 EVT VT = N->getValueType(0);
2335 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2337 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2338 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2339 SplitInteger(Res.getValue(1), Lo, Hi);
2343 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2345 LC = RTLIB::SREM_I16;
2346 else if (VT == MVT::i32)
2347 LC = RTLIB::SREM_I32;
2348 else if (VT == MVT::i64)
2349 LC = RTLIB::SREM_I64;
2350 else if (VT == MVT::i128)
2351 LC = RTLIB::SREM_I128;
2352 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2354 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2357 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2358 SDValue &Lo, SDValue &Hi) {
2359 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2361 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2362 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
2364 DAG.getConstant(NVT.getSizeInBits(), dl,
2365 TLI.getPointerTy(DAG.getDataLayout())));
2366 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2369 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2370 SDValue &Lo, SDValue &Hi) {
2371 SDValue LHS = N->getOperand(0);
2372 SDValue RHS = N->getOperand(1);
2375 // Expand the result by simply replacing it with the equivalent
2376 // non-overflow-checking operation.
2377 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2378 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2380 SplitInteger(Sum, Lo, Hi);
2382 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2383 // overflows iff a - b > a.
2384 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2385 N->getOpcode () == ISD::UADDO ?
2386 ISD::SETULT : ISD::SETUGT);
2388 // Use the calculated overflow everywhere.
2389 ReplaceValueWith(SDValue(N, 1), Ofl);
2392 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2393 SDValue &Lo, SDValue &Hi) {
2394 EVT VT = N->getValueType(0);
2397 // A divide for UMULO should be faster than a function call.
2398 if (N->getOpcode() == ISD::UMULO) {
2399 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2401 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2402 SplitInteger(MUL, Lo, Hi);
2404 // A divide for UMULO will be faster than a function call. Select to
2405 // make sure we aren't using 0.
2406 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2407 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ);
2408 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2409 DAG.getConstant(1, dl, VT), RHS);
2410 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2411 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2413 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2414 DAG.getConstant(0, dl, N->getValueType(1)),
2416 ReplaceValueWith(SDValue(N, 1), Overflow);
2420 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2421 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2422 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2424 // Replace this with a libcall that will check overflow.
2425 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2427 LC = RTLIB::MULO_I32;
2428 else if (VT == MVT::i64)
2429 LC = RTLIB::MULO_I64;
2430 else if (VT == MVT::i128)
2431 LC = RTLIB::MULO_I128;
2432 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2434 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2435 // Temporary for the overflow value, default it to zero.
2436 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2437 DAG.getConstant(0, dl, PtrVT), Temp,
2438 MachinePointerInfo(), false, false, 0);
2440 TargetLowering::ArgListTy Args;
2441 TargetLowering::ArgListEntry Entry;
2442 for (const SDValue &Op : N->op_values()) {
2443 EVT ArgVT = Op.getValueType();
2444 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2447 Entry.isSExt = true;
2448 Entry.isZExt = false;
2449 Args.push_back(Entry);
2452 // Also pass the address of the overflow check.
2454 Entry.Ty = PtrTy->getPointerTo();
2455 Entry.isSExt = true;
2456 Entry.isZExt = false;
2457 Args.push_back(Entry);
2459 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2461 TargetLowering::CallLoweringInfo CLI(DAG);
2462 CLI.setDebugLoc(dl).setChain(Chain)
2463 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2466 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2468 SplitInteger(CallInfo.first, Lo, Hi);
2469 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2470 MachinePointerInfo(), false, false, false, 0);
2471 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2472 DAG.getConstant(0, dl, PtrVT),
2474 // Use the overflow from the libcall everywhere.
2475 ReplaceValueWith(SDValue(N, 1), Ofl);
2478 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2479 SDValue &Lo, SDValue &Hi) {
2480 EVT VT = N->getValueType(0);
2482 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2484 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2485 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2486 SplitInteger(Res.getValue(0), Lo, Hi);
2490 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2492 LC = RTLIB::UDIV_I16;
2493 else if (VT == MVT::i32)
2494 LC = RTLIB::UDIV_I32;
2495 else if (VT == MVT::i64)
2496 LC = RTLIB::UDIV_I64;
2497 else if (VT == MVT::i128)
2498 LC = RTLIB::UDIV_I128;
2499 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2501 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2504 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2505 SDValue &Lo, SDValue &Hi) {
2506 EVT VT = N->getValueType(0);
2508 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2510 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2511 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2512 SplitInteger(Res.getValue(1), Lo, Hi);
2516 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2518 LC = RTLIB::UREM_I16;
2519 else if (VT == MVT::i32)
2520 LC = RTLIB::UREM_I32;
2521 else if (VT == MVT::i64)
2522 LC = RTLIB::UREM_I64;
2523 else if (VT == MVT::i128)
2524 LC = RTLIB::UREM_I128;
2525 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2527 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2530 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2531 SDValue &Lo, SDValue &Hi) {
2532 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2534 SDValue Op = N->getOperand(0);
2535 if (Op.getValueType().bitsLE(NVT)) {
2536 // The low part is zero extension of the input (degenerates to a copy).
2537 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2538 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
2540 // For example, extension of an i48 to an i64. The operand type necessarily
2541 // promotes to the result type, so will end up being expanded too.
2542 assert(getTypeAction(Op.getValueType()) ==
2543 TargetLowering::TypePromoteInteger &&
2544 "Only know how to promote this result!");
2545 SDValue Res = GetPromotedInteger(Op);
2546 assert(Res.getValueType() == N->getValueType(0) &&
2547 "Operand over promoted?");
2548 // Split the promoted operand. This will simplify when it is expanded.
2549 SplitInteger(Res, Lo, Hi);
2550 unsigned ExcessBits =
2551 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2552 Hi = DAG.getZeroExtendInReg(Hi, dl,
2553 EVT::getIntegerVT(*DAG.getContext(),
2558 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2559 SDValue &Lo, SDValue &Hi) {
2561 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2562 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2563 SDValue Zero = DAG.getConstant(0, dl, VT);
2564 SDValue Swap = DAG.getAtomicCmpSwap(
2565 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2566 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2567 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2568 cast<AtomicSDNode>(N)->getOrdering(),
2569 cast<AtomicSDNode>(N)->getOrdering(),
2570 cast<AtomicSDNode>(N)->getSynchScope());
2572 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2573 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2576 //===----------------------------------------------------------------------===//
2577 // Integer Operand Expansion
2578 //===----------------------------------------------------------------------===//
2580 /// ExpandIntegerOperand - This method is called when the specified operand of
2581 /// the specified node is found to need expansion. At this point, all of the
2582 /// result types of the node are known to be legal, but other operands of the
2583 /// node may need promotion or expansion as well as the specified one.
2584 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2585 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2586 SDValue Res = SDValue();
2588 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2591 switch (N->getOpcode()) {
2594 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2595 N->dump(&DAG); dbgs() << "\n";
2597 llvm_unreachable("Do not know how to expand this operator's operand!");
2599 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2600 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2601 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2602 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2603 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2604 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2605 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2606 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2607 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2608 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2609 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2610 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2616 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2617 case ISD::RETURNADDR:
2618 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2620 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2623 // If the result is null, the sub-method took care of registering results etc.
2624 if (!Res.getNode()) return false;
2626 // If the result is N, the sub-method updated N in place. Tell the legalizer
2628 if (Res.getNode() == N)
2631 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2632 "Invalid operand expansion");
2634 ReplaceValueWith(SDValue(N, 0), Res);
2638 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2639 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2640 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2642 ISD::CondCode &CCCode,
2644 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2645 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2646 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2648 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2649 if (RHSLo == RHSHi) {
2650 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2651 if (RHSCST->isAllOnesValue()) {
2652 // Equality comparison to -1.
2653 NewLHS = DAG.getNode(ISD::AND, dl,
2654 LHSLo.getValueType(), LHSLo, LHSHi);
2661 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2662 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2663 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2664 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
2668 // If this is a comparison of the sign bit, just look at the top part.
2670 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2671 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2672 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2678 // FIXME: This generated code sucks.
2679 ISD::CondCode LowCC;
2681 default: llvm_unreachable("Unknown integer setcc!");
2683 case ISD::SETULT: LowCC = ISD::SETULT; break;
2685 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2687 case ISD::SETULE: LowCC = ISD::SETULE; break;
2689 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2692 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2693 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2694 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2696 // NOTE: on targets without efficient SELECT of bools, we can always use
2697 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2698 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2701 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2702 TLI.isTypeLegal(RHSLo.getValueType()))
2703 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2704 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2705 if (!Tmp1.getNode())
2706 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2707 LHSLo, RHSLo, LowCC);
2708 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2709 TLI.isTypeLegal(RHSHi.getValueType()))
2710 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2711 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2712 if (!Tmp2.getNode())
2713 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2714 getSetCCResultType(LHSHi.getValueType()),
2715 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2717 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2718 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2719 if ((Tmp1C && Tmp1C->isNullValue()) ||
2720 (Tmp2C && Tmp2C->isNullValue() &&
2721 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2722 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2723 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2724 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2725 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2726 // low part is known false, returns high part.
2727 // For LE / GE, if high part is known false, ignore the low part.
2728 // For LT / GT, if high part is known true, ignore the low part.
2734 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2735 LHSHi, RHSHi, ISD::SETEQ, false,
2736 DagCombineInfo, dl);
2737 if (!NewLHS.getNode())
2738 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2739 LHSHi, RHSHi, ISD::SETEQ);
2740 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2741 NewLHS, Tmp1, Tmp2);
2745 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2746 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2747 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2748 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2750 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2751 // against zero to select between true and false values.
2752 if (!NewRHS.getNode()) {
2753 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2754 CCCode = ISD::SETNE;
2757 // Update N to have the operands specified.
2758 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2759 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2760 N->getOperand(4)), 0);
2763 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2764 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2765 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2766 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2768 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2769 // against zero to select between true and false values.
2770 if (!NewRHS.getNode()) {
2771 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2772 CCCode = ISD::SETNE;
2775 // Update N to have the operands specified.
2776 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2777 N->getOperand(2), N->getOperand(3),
2778 DAG.getCondCode(CCCode)), 0);
2781 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2782 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2783 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2784 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2786 // If ExpandSetCCOperands returned a scalar, use it.
2787 if (!NewRHS.getNode()) {
2788 assert(NewLHS.getValueType() == N->getValueType(0) &&
2789 "Unexpected setcc expansion!");
2793 // Otherwise, update N to have the operands specified.
2794 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2795 DAG.getCondCode(CCCode)), 0);
2798 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2799 // The value being shifted is legal, but the shift amount is too big.
2800 // It follows that either the result of the shift is undefined, or the
2801 // upper half of the shift amount is zero. Just use the lower half.
2803 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2804 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2807 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2808 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2809 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2810 // constant to valid type.
2812 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2813 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2816 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2817 SDValue Op = N->getOperand(0);
2818 EVT DstVT = N->getValueType(0);
2819 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2820 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2821 "Don't know how to expand this SINT_TO_FP!");
2822 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2825 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2826 if (ISD::isNormalStore(N))
2827 return ExpandOp_NormalStore(N, OpNo);
2829 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2830 assert(OpNo == 1 && "Can only expand the stored value so far");
2832 EVT VT = N->getOperand(1).getValueType();
2833 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2834 SDValue Ch = N->getChain();
2835 SDValue Ptr = N->getBasePtr();
2836 unsigned Alignment = N->getAlignment();
2837 bool isVolatile = N->isVolatile();
2838 bool isNonTemporal = N->isNonTemporal();
2839 AAMDNodes AAInfo = N->getAAInfo();
2843 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2845 if (N->getMemoryVT().bitsLE(NVT)) {
2846 GetExpandedInteger(N->getValue(), Lo, Hi);
2847 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2848 N->getMemoryVT(), isVolatile, isNonTemporal,
2852 if (DAG.getDataLayout().isLittleEndian()) {
2853 // Little-endian - low bits are at low addresses.
2854 GetExpandedInteger(N->getValue(), Lo, Hi);
2856 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2857 isVolatile, isNonTemporal, Alignment, AAInfo);
2859 unsigned ExcessBits =
2860 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2861 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2863 // Increment the pointer to the other half.
2864 unsigned IncrementSize = NVT.getSizeInBits()/8;
2865 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2866 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2867 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2868 N->getPointerInfo().getWithOffset(IncrementSize),
2869 NEVT, isVolatile, isNonTemporal,
2870 MinAlign(Alignment, IncrementSize), AAInfo);
2871 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2874 // Big-endian - high bits are at low addresses. Favor aligned stores at
2875 // the cost of some bit-fiddling.
2876 GetExpandedInteger(N->getValue(), Lo, Hi);
2878 EVT ExtVT = N->getMemoryVT();
2879 unsigned EBytes = ExtVT.getStoreSize();
2880 unsigned IncrementSize = NVT.getSizeInBits()/8;
2881 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2882 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2883 ExtVT.getSizeInBits() - ExcessBits);
2885 if (ExcessBits < NVT.getSizeInBits()) {
2886 // Transfer high bits from the top of Lo to the bottom of Hi.
2887 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2888 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2889 TLI.getPointerTy(DAG.getDataLayout())));
2891 ISD::OR, dl, NVT, Hi,
2892 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2893 DAG.getConstant(ExcessBits, dl,
2894 TLI.getPointerTy(DAG.getDataLayout()))));
2897 // Store both the high bits and maybe some of the low bits.
2898 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2899 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2901 // Increment the pointer to the other half.
2902 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2903 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2904 // Store the lowest ExcessBits bits in the second half.
2905 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2906 N->getPointerInfo().getWithOffset(IncrementSize),
2907 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2908 isVolatile, isNonTemporal,
2909 MinAlign(Alignment, IncrementSize), AAInfo);
2910 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2913 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2915 GetExpandedInteger(N->getOperand(0), InL, InH);
2916 // Just truncate the low part of the source.
2917 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2920 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2921 SDValue Op = N->getOperand(0);
2922 EVT SrcVT = Op.getValueType();
2923 EVT DstVT = N->getValueType(0);
2926 // The following optimization is valid only if every value in SrcVT (when
2927 // treated as signed) is representable in DstVT. Check that the mantissa
2928 // size of DstVT is >= than the number of bits in SrcVT -1.
2929 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2930 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2931 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2932 // Do a signed conversion then adjust the result.
2933 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2934 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2936 // The result of the signed conversion needs adjusting if the 'sign bit' of
2937 // the incoming integer was set. To handle this, we dynamically test to see
2938 // if it is set, and, if so, add a fudge factor.
2940 const uint64_t F32TwoE32 = 0x4F800000ULL;
2941 const uint64_t F32TwoE64 = 0x5F800000ULL;
2942 const uint64_t F32TwoE128 = 0x7F800000ULL;
2945 if (SrcVT == MVT::i32)
2946 FF = APInt(32, F32TwoE32);
2947 else if (SrcVT == MVT::i64)
2948 FF = APInt(32, F32TwoE64);
2949 else if (SrcVT == MVT::i128)
2950 FF = APInt(32, F32TwoE128);
2952 llvm_unreachable("Unsupported UINT_TO_FP!");
2954 // Check whether the sign bit is set.
2956 GetExpandedInteger(Op, Lo, Hi);
2957 SDValue SignSet = DAG.getSetCC(dl,
2958 getSetCCResultType(Hi.getValueType()),
2960 DAG.getConstant(0, dl, Hi.getValueType()),
2963 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2965 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2966 TLI.getPointerTy(DAG.getDataLayout()));
2968 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2969 SDValue Zero = DAG.getIntPtrConstant(0, dl);
2970 SDValue Four = DAG.getIntPtrConstant(4, dl);
2971 if (DAG.getDataLayout().isBigEndian())
2972 std::swap(Zero, Four);
2973 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2975 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2976 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2978 Alignment = std::min(Alignment, 4u);
2980 // Load the value out, extending it from f32 to the destination float type.
2981 // FIXME: Avoid the extend by constructing the right constant pool?
2982 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2984 MachinePointerInfo::getConstantPool(),
2986 false, false, false, Alignment);
2987 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2990 // Otherwise, use a libcall.
2991 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2992 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2993 "Don't know how to expand this UINT_TO_FP!");
2994 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2997 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2999 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3000 cast<AtomicSDNode>(N)->getMemoryVT(),
3002 N->getOperand(1), N->getOperand(2),
3003 cast<AtomicSDNode>(N)->getMemOperand(),
3004 cast<AtomicSDNode>(N)->getOrdering(),
3005 cast<AtomicSDNode>(N)->getSynchScope());
3006 return Swap.getValue(1);
3010 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
3011 SDValue InOp0 = N->getOperand(0);
3012 EVT InVT = InOp0.getValueType();
3014 EVT OutVT = N->getValueType(0);
3015 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3016 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3017 unsigned OutNumElems = OutVT.getVectorNumElements();
3018 EVT NOutVTElem = NOutVT.getVectorElementType();
3021 SDValue BaseIdx = N->getOperand(1);
3023 SmallVector<SDValue, 8> Ops;
3024 Ops.reserve(OutNumElems);
3025 for (unsigned i = 0; i != OutNumElems; ++i) {
3027 // Extract the element from the original vector.
3028 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3029 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
3030 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3031 InVT.getVectorElementType(), N->getOperand(0), Index);
3033 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3034 // Insert the converted element to the new vector.
3038 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3042 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3043 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3044 EVT VT = N->getValueType(0);
3047 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3049 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3050 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3051 EVT OutVT = V0.getValueType();
3053 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3057 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3058 EVT OutVT = N->getValueType(0);
3059 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3060 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3061 unsigned NumElems = N->getNumOperands();
3062 EVT NOutVTElem = NOutVT.getVectorElementType();
3066 SmallVector<SDValue, 8> Ops;
3067 Ops.reserve(NumElems);
3068 for (unsigned i = 0; i != NumElems; ++i) {
3070 // BUILD_VECTOR integer operand types are allowed to be larger than the
3071 // result's element type. This may still be true after the promotion. For
3072 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3073 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3074 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3075 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3077 Op = N->getOperand(i);
3081 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3084 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3088 assert(!N->getOperand(0).getValueType().isVector() &&
3089 "Input must be a scalar");
3091 EVT OutVT = N->getValueType(0);
3092 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3093 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3094 EVT NOutVTElem = NOutVT.getVectorElementType();
3096 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3098 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3101 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3104 EVT OutVT = N->getValueType(0);
3105 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3106 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3108 EVT InElemTy = OutVT.getVectorElementType();
3109 EVT OutElemTy = NOutVT.getVectorElementType();
3111 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3112 unsigned NumOutElem = NOutVT.getVectorNumElements();
3113 unsigned NumOperands = N->getNumOperands();
3114 assert(NumElem * NumOperands == NumOutElem &&
3115 "Unexpected number of elements");
3117 // Take the elements from the first vector.
3118 SmallVector<SDValue, 8> Ops(NumOutElem);
3119 for (unsigned i = 0; i < NumOperands; ++i) {
3120 SDValue Op = N->getOperand(i);
3121 for (unsigned j = 0; j < NumElem; ++j) {
3122 SDValue Ext = DAG.getNode(
3123 ISD::EXTRACT_VECTOR_ELT, dl, InElemTy, Op,
3124 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3125 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3129 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3132 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3133 EVT OutVT = N->getValueType(0);
3134 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3135 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3137 EVT NOutVTElem = NOutVT.getVectorElementType();
3140 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3142 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3143 NOutVTElem, N->getOperand(1));
3144 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3145 V0, ConvElem, N->getOperand(2));
3148 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3150 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3151 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
3152 TLI.getVectorIdxTy(DAG.getDataLayout()));
3153 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3154 V0->getValueType(0).getScalarType(), V0, V1);
3156 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3157 // element types. If this is the case then we need to expand the outgoing
3158 // value and not truncate it.
3159 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3162 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
3164 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3165 MVT InVT = V0.getValueType().getSimpleVT();
3166 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
3167 N->getValueType(0).getVectorNumElements());
3168 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
3169 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
3172 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3174 unsigned NumElems = N->getNumOperands();
3176 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3178 SmallVector<SDValue, 8> NewOps;
3179 NewOps.reserve(NumElems);
3181 // For each incoming vector
3182 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3183 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3184 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3185 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3187 for (unsigned i=0; i<NumElem; ++i) {
3188 // Extract element from incoming vector
3189 SDValue Ex = DAG.getNode(
3190 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
3191 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3192 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3193 NewOps.push_back(Tr);
3197 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);