1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDNodeDbgValue.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
33 /// CountResults - The results of target nodes have register or immediate
34 /// operands first, then an optional chain, and optional glue operands (which do
35 /// not go into the resulting MachineInstr).
36 unsigned InstrEmitter::CountResults(SDNode *Node) {
37 unsigned N = Node->getNumValues();
38 while (N && Node->getValueType(N - 1) == MVT::Glue)
40 if (N && Node->getValueType(N - 1) == MVT::Other)
41 --N; // Skip over chain result.
45 /// CountOperands - The inputs to target nodes have any actual inputs first,
46 /// followed by an optional chain operand, then an optional glue operand.
47 /// Compute the number of actual operands that will go into the resulting
49 unsigned InstrEmitter::CountOperands(SDNode *Node) {
50 unsigned N = Node->getNumOperands();
51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
54 --N; // Ignore chain if it exists.
58 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
59 /// implicit physical register output.
61 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
65 // Just use the input register directly!
66 SDValue Op(Node, ResNo);
69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
70 (void)isNew; // Silence compiler warning.
71 assert(isNew && "Node emitted out of order - early");
75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
76 // the CopyToReg'd destination register instead of creating a new vreg.
78 const TargetRegisterClass *UseRC = NULL;
79 EVT VT = Node->getValueType(ResNo);
81 // Stick to the preferred register classes for legal types.
82 if (TLI->isTypeLegal(VT))
83 UseRC = TLI->getRegClassFor(VT);
85 if (!IsClone && !IsCloned)
86 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
90 if (User->getOpcode() == ISD::CopyToReg &&
91 User->getOperand(2).getNode() == Node &&
92 User->getOperand(2).getResNo() == ResNo) {
93 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
94 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
97 } else if (DestReg != SrcReg)
100 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
101 SDValue Op = User->getOperand(i);
102 if (Op.getNode() != Node || Op.getResNo() != ResNo)
104 EVT VT = Node->getValueType(Op.getResNo());
105 if (VT == MVT::Other || VT == MVT::Glue)
108 if (User->isMachineOpcode()) {
109 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
110 const TargetRegisterClass *RC = 0;
111 if (i+II.getNumDefs() < II.getNumOperands())
112 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
116 const TargetRegisterClass *ComRC =
117 TRI->getCommonSubClass(UseRC, RC);
118 // If multiple uses expect disjoint register classes, we emit
119 // copies in AddRegisterOperand.
131 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
132 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
134 // Figure out the register class to create for the destreg.
136 DstRC = MRI->getRegClass(VRBase);
138 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
141 DstRC = TLI->getRegClassFor(VT);
144 // If all uses are reading from the src physical register and copying the
145 // register is either impossible or very expensive, then don't create a copy.
146 if (MatchReg && SrcRC->getCopyCost() < 0) {
149 // Create the reg, emit the copy.
150 VRBase = MRI->createVirtualRegister(DstRC);
151 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
152 VRBase).addReg(SrcReg);
155 SDValue Op(Node, ResNo);
158 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
159 (void)isNew; // Silence compiler warning.
160 assert(isNew && "Node emitted out of order - early");
163 /// getDstOfCopyToRegUse - If the only use of the specified result number of
164 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
165 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
166 unsigned ResNo) const {
167 if (!Node->hasOneUse())
170 SDNode *User = *Node->use_begin();
171 if (User->getOpcode() == ISD::CopyToReg &&
172 User->getOperand(2).getNode() == Node &&
173 User->getOperand(2).getResNo() == ResNo) {
174 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
175 if (TargetRegisterInfo::isVirtualRegister(Reg))
181 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
182 const MCInstrDesc &II,
183 bool IsClone, bool IsCloned,
184 DenseMap<SDValue, unsigned> &VRBaseMap) {
185 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
186 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
188 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
189 // If the specific node value is only used by a CopyToReg and the dest reg
190 // is a vreg in the same register class, use the CopyToReg'd destination
191 // register instead of creating a new vreg.
193 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
194 if (II.OpInfo[i].isOptionalDef()) {
195 // Optional def must be a physical register.
196 unsigned NumResults = CountResults(Node);
197 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
198 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
199 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
202 if (!VRBase && !IsClone && !IsCloned)
203 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
206 if (User->getOpcode() == ISD::CopyToReg &&
207 User->getOperand(2).getNode() == Node &&
208 User->getOperand(2).getResNo() == i) {
209 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
210 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
211 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
214 MI->addOperand(MachineOperand::CreateReg(Reg, true));
221 // Create the result registers for this node and add the result regs to
222 // the machine instruction.
224 assert(RC && "Isn't a register operand!");
225 VRBase = MRI->createVirtualRegister(RC);
226 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
232 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
233 (void)isNew; // Silence compiler warning.
234 assert(isNew && "Node emitted out of order - early");
238 /// getVR - Return the virtual register corresponding to the specified result
239 /// of the specified node.
240 unsigned InstrEmitter::getVR(SDValue Op,
241 DenseMap<SDValue, unsigned> &VRBaseMap) {
242 if (Op.isMachineOpcode() &&
243 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
244 // Add an IMPLICIT_DEF instruction before every use.
245 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
246 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
247 // does not include operand register class info.
249 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
250 VReg = MRI->createVirtualRegister(RC);
252 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
253 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
257 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
258 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
263 /// AddRegisterOperand - Add the specified register as an operand to the
264 /// specified machine instr. Insert register copies if the register is
265 /// not in the required register class.
267 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
269 const MCInstrDesc *II,
270 DenseMap<SDValue, unsigned> &VRBaseMap,
271 bool IsDebug, bool IsClone, bool IsCloned) {
272 assert(Op.getValueType() != MVT::Other &&
273 Op.getValueType() != MVT::Glue &&
274 "Chain and glue operands should occur at end of operand list!");
275 // Get/emit the operand.
276 unsigned VReg = getVR(Op, VRBaseMap);
277 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
279 const MCInstrDesc &MCID = MI->getDesc();
280 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
281 MCID.OpInfo[IIOpNum].isOptionalDef();
283 // If the instruction requires a register in a different class, create
284 // a new virtual register and copy the value into it, but first attempt to
285 // shrink VReg's register class within reason. For example, if VReg == GR32
286 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
287 const unsigned MinRCSize = 4;
289 const TargetRegisterClass *DstRC = 0;
290 if (IIOpNum < II->getNumOperands())
291 DstRC = TII->getRegClass(*II, IIOpNum, TRI);
292 assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
293 "Don't have operand info for this instruction!");
294 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
295 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
296 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
297 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
302 // If this value has only one use, that use is a kill. This is a
303 // conservative approximation. InstrEmitter does trivial coalescing
304 // with CopyFromReg nodes, so don't emit kill flags for them.
305 // Avoid kill flags on Schedule cloned nodes, since there will be
307 // Tied operands are never killed, so we need to check that. And that
308 // means we need to determine the index of the operand.
309 bool isKill = Op.hasOneUse() &&
310 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
312 !(IsClone || IsCloned);
314 unsigned Idx = MI->getNumOperands();
316 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
318 bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
323 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
324 false/*isImp*/, isKill,
325 false/*isDead*/, false/*isUndef*/,
326 false/*isEarlyClobber*/,
327 0/*SubReg*/, IsDebug));
330 /// AddOperand - Add the specified operand to the specified machine instr. II
331 /// specifies the instruction information for the node, and IIOpNum is the
332 /// operand number (in the II) that we are adding. IIOpNum and II are used for
334 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
336 const MCInstrDesc *II,
337 DenseMap<SDValue, unsigned> &VRBaseMap,
338 bool IsDebug, bool IsClone, bool IsCloned) {
339 if (Op.isMachineOpcode()) {
340 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
341 IsDebug, IsClone, IsCloned);
342 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
343 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
344 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
345 const ConstantFP *CFP = F->getConstantFPValue();
346 MI->addOperand(MachineOperand::CreateFPImm(CFP));
347 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
348 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
349 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
350 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
351 TGA->getTargetFlags()));
352 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
353 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
354 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
355 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
356 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
357 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
358 JT->getTargetFlags()));
359 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
360 int Offset = CP->getOffset();
361 unsigned Align = CP->getAlignment();
362 Type *Type = CP->getType();
363 // MachineConstantPool wants an explicit alignment.
365 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
367 // Alignment of vector types. FIXME!
368 Align = TM->getTargetData()->getTypeAllocSize(Type);
373 MachineConstantPool *MCP = MF->getConstantPool();
374 if (CP->isMachineConstantPoolEntry())
375 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
377 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
378 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
379 CP->getTargetFlags()));
380 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
381 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
382 ES->getTargetFlags()));
383 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
384 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
385 BA->getTargetFlags()));
387 assert(Op.getValueType() != MVT::Other &&
388 Op.getValueType() != MVT::Glue &&
389 "Chain and glue operands should occur at end of operand list!");
390 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
391 IsDebug, IsClone, IsCloned);
395 /// EmitSubregNode - Generate machine code for subreg nodes.
397 void InstrEmitter::EmitSubregNode(SDNode *Node,
398 DenseMap<SDValue, unsigned> &VRBaseMap,
399 bool IsClone, bool IsCloned) {
401 unsigned Opc = Node->getMachineOpcode();
403 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
404 // the CopyToReg'd destination register instead of creating a new vreg.
405 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
408 if (User->getOpcode() == ISD::CopyToReg &&
409 User->getOperand(2).getNode() == Node) {
410 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
411 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
418 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
419 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub
420 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
422 // Figure out the register class to create for the destreg.
423 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
424 MachineInstr *DefMI = MRI->getVRegDef(VReg);
425 unsigned SrcReg, DstReg, DefSubIdx;
427 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
428 SubIdx == DefSubIdx) {
430 // r1025 = s/zext r1024, 4
431 // r1026 = extract_subreg r1025, 4
433 // r1026 = copy r1024
434 const TargetRegisterClass *TRC = MRI->getRegClass(SrcReg);
435 VRBase = MRI->createVirtualRegister(TRC);
436 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
437 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
439 const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
440 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
441 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
443 // Figure out the register class to create for the destreg.
444 // Note that if we're going to directly use an existing register,
445 // it must be precisely the required class, and not a subclass
447 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
449 assert(SRC && "Couldn't find source register class");
450 VRBase = MRI->createVirtualRegister(SRC);
453 // Create the extract_subreg machine instruction.
454 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
455 TII->get(TargetOpcode::COPY), VRBase);
457 // Add source, and subreg index
458 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
460 assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg())&&
461 "Cannot yet extract from physregs");
462 MI->getOperand(1).setSubReg(SubIdx);
463 MBB->insert(InsertPos, MI);
465 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
466 Opc == TargetOpcode::SUBREG_TO_REG) {
467 SDValue N0 = Node->getOperand(0);
468 SDValue N1 = Node->getOperand(1);
469 SDValue N2 = Node->getOperand(2);
470 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
472 // Figure out the register class to create for the destreg. It should be
473 // the largest legal register class supporting SubIdx sub-registers.
474 // RegisterCoalescer will constrain it further if it decides to eliminate
475 // the INSERT_SUBREG instruction.
477 // %dst = INSERT_SUBREG %src, %sub, SubIdx
479 // is lowered by TwoAddressInstructionPass to:
482 // %dst:SubIdx = COPY %sub
484 // There is no constraint on the %src register class.
486 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0));
487 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
488 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
490 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
491 VRBase = MRI->createVirtualRegister(SRC);
493 // Create the insert_subreg or subreg_to_reg machine instruction.
494 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
495 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
497 // If creating a subreg_to_reg, then the first input operand
498 // is an implicit value immediate, otherwise it's a register
499 if (Opc == TargetOpcode::SUBREG_TO_REG) {
500 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
501 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
503 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
505 // Add the subregster being inserted
506 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
508 MI->addOperand(MachineOperand::CreateImm(SubIdx));
509 MBB->insert(InsertPos, MI);
511 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
514 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
515 (void)isNew; // Silence compiler warning.
516 assert(isNew && "Node emitted out of order - early");
519 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
520 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
521 /// register is constrained to be in a particular register class.
524 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
525 DenseMap<SDValue, unsigned> &VRBaseMap) {
526 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
528 // Create the new VReg in the destination class and emit a copy.
529 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
530 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
531 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
532 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
533 NewVReg).addReg(VReg);
536 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
537 (void)isNew; // Silence compiler warning.
538 assert(isNew && "Node emitted out of order - early");
541 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
543 void InstrEmitter::EmitRegSequence(SDNode *Node,
544 DenseMap<SDValue, unsigned> &VRBaseMap,
545 bool IsClone, bool IsCloned) {
546 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
547 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
548 unsigned NewVReg = MRI->createVirtualRegister(RC);
549 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
550 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
551 unsigned NumOps = Node->getNumOperands();
552 assert((NumOps & 1) == 1 &&
553 "REG_SEQUENCE must have an odd number of operands!");
554 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
555 for (unsigned i = 1; i != NumOps; ++i) {
556 SDValue Op = Node->getOperand(i);
558 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
559 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
560 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
561 const TargetRegisterClass *SRC =
562 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
563 if (SRC && SRC != RC) {
564 MRI->setRegClass(NewVReg, SRC);
568 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
572 MBB->insert(InsertPos, MI);
574 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
575 (void)isNew; // Silence compiler warning.
576 assert(isNew && "Node emitted out of order - early");
579 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
582 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
583 DenseMap<SDValue, unsigned> &VRBaseMap) {
584 uint64_t Offset = SD->getOffset();
585 MDNode* MDPtr = SD->getMDPtr();
586 DebugLoc DL = SD->getDebugLoc();
588 if (SD->getKind() == SDDbgValue::FRAMEIX) {
589 // Stack address; this needs to be lowered in target-dependent fashion.
590 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
591 unsigned FrameIx = SD->getFrameIx();
592 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
594 // Otherwise, we're going to create an instruction here.
595 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
596 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
597 if (SD->getKind() == SDDbgValue::SDNODE) {
598 SDNode *Node = SD->getSDNode();
599 SDValue Op = SDValue(Node, SD->getResNo());
600 // It's possible we replaced this SDNode with other(s) and therefore
601 // didn't generate code for it. It's better to catch these cases where
602 // they happen and transfer the debug info, but trying to guarantee that
603 // in all cases would be very fragile; this is a safeguard for any
605 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
606 if (I==VRBaseMap.end())
607 MIB.addReg(0U); // undef
609 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
610 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
611 } else if (SD->getKind() == SDDbgValue::CONST) {
612 const Value *V = SD->getConst();
613 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
614 if (CI->getBitWidth() > 64)
617 MIB.addImm(CI->getSExtValue());
618 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
621 // Could be an Undef. In any case insert an Undef so we can see what we
626 // Insert an Undef so we can see what we dropped.
630 MIB.addImm(Offset).addMetadata(MDPtr);
634 /// EmitMachineNode - Generate machine code for a target-specific node and
635 /// needed dependencies.
638 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
639 DenseMap<SDValue, unsigned> &VRBaseMap) {
640 unsigned Opc = Node->getMachineOpcode();
642 // Handle subreg insert/extract specially
643 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
644 Opc == TargetOpcode::INSERT_SUBREG ||
645 Opc == TargetOpcode::SUBREG_TO_REG) {
646 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
650 // Handle COPY_TO_REGCLASS specially.
651 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
652 EmitCopyToRegClassNode(Node, VRBaseMap);
656 // Handle REG_SEQUENCE specially.
657 if (Opc == TargetOpcode::REG_SEQUENCE) {
658 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
662 if (Opc == TargetOpcode::IMPLICIT_DEF)
663 // We want a unique VR for each IMPLICIT_DEF use.
666 const MCInstrDesc &II = TII->get(Opc);
667 unsigned NumResults = CountResults(Node);
668 unsigned NodeOperands = CountOperands(Node);
669 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
671 unsigned NumMIOperands = NodeOperands + NumResults;
673 assert(NumMIOperands >= II.getNumOperands() &&
674 "Too few operands for a variadic node!");
676 assert(NumMIOperands >= II.getNumOperands() &&
677 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
678 "#operands for dag node doesn't match .td file!");
681 // Create the new machine instruction.
682 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
684 // The MachineInstr constructor adds implicit-def operands. Scan through
685 // these to determine which are dead.
686 if (MI->getNumOperands() != 0 &&
687 Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
688 // First, collect all used registers.
689 SmallVector<unsigned, 8> UsedRegs;
690 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser())
691 if (F->getOpcode() == ISD::CopyFromReg)
692 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
694 // Collect declared implicit uses.
695 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
696 UsedRegs.append(MCID.getImplicitUses(),
697 MCID.getImplicitUses() + MCID.getNumImplicitUses());
698 // In addition to declared implicit uses, we must also check for
699 // direct RegisterSDNode operands.
700 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
701 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
702 unsigned Reg = R->getReg();
703 if (TargetRegisterInfo::isPhysicalRegister(Reg))
704 UsedRegs.push_back(Reg);
707 // Then mark unused registers as dead.
708 MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
711 // Add result register values for things that are defined by this
714 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
716 // Emit all of the actual operands of this instruction, adding them to the
717 // instruction as appropriate.
718 bool HasOptPRefs = II.getNumDefs() > NumResults;
719 assert((!HasOptPRefs || !HasPhysRegOuts) &&
720 "Unable to cope with optional defs and phys regs defs!");
721 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
722 for (unsigned i = NumSkip; i != NodeOperands; ++i)
723 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
724 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
726 // Transfer all of the memory reference descriptions of this instruction.
727 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
728 cast<MachineSDNode>(Node)->memoperands_end());
730 // Insert the instruction into position in the block. This needs to
731 // happen before any custom inserter hook is called so that the
732 // hook knows where in the block to insert the replacement code.
733 MBB->insert(InsertPos, MI);
735 // Additional results must be physical register defs.
736 if (HasPhysRegOuts) {
737 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
738 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
739 if (Node->hasAnyUseOfValue(i))
740 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
741 // If there are no uses, mark the register as dead now, so that
742 // MachineLICM/Sink can see that it's dead. Don't do this if the
743 // node has a Glue value, for the benefit of targets still using
744 // Glue for values in physregs.
745 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue)
746 MI->addRegisterDead(Reg, TRI);
750 // If the instruction has implicit defs and the node doesn't, mark the
751 // implicit def as dead. If the node has any glue outputs, we don't do this
752 // because we don't know what implicit defs are being used by glued nodes.
753 if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue)
754 if (const unsigned *IDList = II.getImplicitDefs()) {
755 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs();
757 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI);
760 // Run post-isel target hook to adjust this instruction if needed.
762 if (II.hasPostISelHook())
764 TLI->AdjustInstrPostInstrSelection(MI, Node);
767 /// EmitSpecialNode - Generate machine code for a target-independent node and
768 /// needed dependencies.
770 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
771 DenseMap<SDValue, unsigned> &VRBaseMap) {
772 switch (Node->getOpcode()) {
777 llvm_unreachable("This target-independent node should have been selected!");
779 case ISD::EntryToken:
780 llvm_unreachable("EntryToken should have been excluded from the schedule!");
782 case ISD::MERGE_VALUES:
783 case ISD::TokenFactor: // fall thru
785 case ISD::CopyToReg: {
787 SDValue SrcVal = Node->getOperand(2);
788 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
789 SrcReg = R->getReg();
791 SrcReg = getVR(SrcVal, VRBaseMap);
793 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
794 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
797 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
798 DestReg).addReg(SrcReg);
801 case ISD::CopyFromReg: {
802 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
803 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
806 case ISD::EH_LABEL: {
807 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
808 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
809 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
813 case ISD::INLINEASM: {
814 unsigned NumOps = Node->getNumOperands();
815 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
816 --NumOps; // Ignore the glue operand.
818 // Create the inline asm machine instruction.
819 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
820 TII->get(TargetOpcode::INLINEASM));
822 // Add the asm string as an external symbol operand.
823 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
824 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
825 MI->addOperand(MachineOperand::CreateES(AsmStr));
827 // Add the HasSideEffect and isAlignStack bits.
829 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
831 MI->addOperand(MachineOperand::CreateImm(ExtraInfo));
833 // Add all of the operand registers to the instruction.
834 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
836 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
837 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
839 MI->addOperand(MachineOperand::CreateImm(Flags));
840 ++i; // Skip the ID value.
842 switch (InlineAsm::getKind(Flags)) {
843 default: llvm_unreachable("Bad flags!");
844 case InlineAsm::Kind_RegDef:
845 for (; NumVals; --NumVals, ++i) {
846 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
847 // FIXME: Add dead flags for physical and virtual registers defined.
848 // For now, mark physical register defs as implicit to help fast
849 // regalloc. This makes inline asm look a lot like calls.
850 MI->addOperand(MachineOperand::CreateReg(Reg, true,
851 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
854 case InlineAsm::Kind_RegDefEarlyClobber:
855 case InlineAsm::Kind_Clobber:
856 for (; NumVals; --NumVals, ++i) {
857 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
858 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
859 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
863 /*isEarlyClobber=*/ true));
866 case InlineAsm::Kind_RegUse: // Use of register.
867 case InlineAsm::Kind_Imm: // Immediate.
868 case InlineAsm::Kind_Mem: // Addressing mode.
869 // The addressing mode has been selected, just add all of the
870 // operands to the machine instruction.
871 for (; NumVals; --NumVals, ++i)
872 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
873 /*IsDebug=*/false, IsClone, IsCloned);
878 // Get the mdnode from the asm if it exists and add it to the instruction.
879 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
880 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
882 MI->addOperand(MachineOperand::CreateMetadata(MD));
884 MBB->insert(InsertPos, MI);
890 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
891 /// at the given position in the given block.
892 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
893 MachineBasicBlock::iterator insertpos)
894 : MF(mbb->getParent()),
895 MRI(&MF->getRegInfo()),
896 TM(&MF->getTarget()),
897 TII(TM->getInstrInfo()),
898 TRI(TM->getRegisterInfo()),
899 TLI(TM->getTargetLowering()),
900 MBB(mbb), InsertPos(insertpos) {