1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "regalloc"
34 #include "RenderMachineFunction.h"
36 #include "VirtRegMap.h"
37 #include "VirtRegRewriter.h"
38 #include "llvm/CodeGen/CalcSpillWeights.h"
39 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
40 #include "llvm/CodeGen/LiveStackAnalysis.h"
41 #include "llvm/CodeGen/RegAllocPBQP.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/PBQP/HeuristicSolver.h"
46 #include "llvm/CodeGen/PBQP/Graph.h"
47 #include "llvm/CodeGen/PBQP/Heuristics/Briggs.h"
48 #include "llvm/CodeGen/RegAllocRegistry.h"
49 #include "llvm/CodeGen/RegisterCoalescer.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetMachine.h"
61 static RegisterRegAlloc
62 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
63 llvm::createPBQPRegisterAllocator);
66 pbqpCoalescing("pbqp-coalescing",
67 cl::desc("Attempt coalescing during PBQP register allocation."),
68 cl::init(false), cl::Hidden);
71 pbqpBuilder("pbqp-builder",
72 cl::desc("Use new builder system."),
73 cl::init(false), cl::Hidden);
77 pbqpPreSplitting("pbqp-pre-splitting",
78 cl::desc("Pre-splite before PBQP register allocation."),
79 cl::init(false), cl::Hidden);
81 char RegAllocPBQP::ID = 0;
83 unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::ConstNodeItr node) const {
84 Node2VReg::const_iterator vregItr = node2VReg.find(node);
85 assert(vregItr != node2VReg.end() && "No vreg for node.");
86 return vregItr->second;
89 PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
90 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
91 assert(nodeItr != vreg2Node.end() && "No node for vreg.");
92 return nodeItr->second;
96 const PBQPRAProblem::AllowedSet&
97 PBQPRAProblem::getAllowedSet(unsigned vreg) const {
98 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
99 assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
100 const AllowedSet &allowedSet = allowedSetItr->second;
104 unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
105 assert(isPRegOption(vreg, option) && "Not a preg option.");
107 const AllowedSet& allowedSet = getAllowedSet(vreg);
108 assert(option <= allowedSet.size() && "Option outside allowed set.");
109 return allowedSet[option - 1];
112 std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(MachineFunction *mf,
113 const LiveIntervals *lis,
114 const MachineLoopInfo *loopInfo,
115 const RegSet &vregs) {
117 typedef std::vector<const LiveInterval*> LIVector;
119 MachineRegisterInfo *mri = &mf->getRegInfo();
120 const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
122 std::auto_ptr<PBQPRAProblem> p(new PBQPRAProblem());
123 PBQP::Graph &g = p->getGraph();
126 // Collect the set of preg intervals, record that they're used in the MF.
127 for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end();
129 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
130 pregs.insert(itr->first);
131 mri->setPhysRegUsed(itr->first);
135 BitVector reservedRegs = tri->getReservedRegs(*mf);
137 // Iterate over vregs.
138 for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
139 vregItr != vregEnd; ++vregItr) {
140 unsigned vreg = *vregItr;
141 const TargetRegisterClass *trc = mri->getRegClass(vreg);
142 const LiveInterval *vregLI = &lis->getInterval(vreg);
144 // Compute an initial allowed set for the current vreg.
145 typedef std::vector<unsigned> VRAllowed;
147 for (TargetRegisterClass::iterator aoItr = trc->allocation_order_begin(*mf),
148 aoEnd = trc->allocation_order_end(*mf);
149 aoItr != aoEnd; ++aoItr) {
150 unsigned preg = *aoItr;
151 if (!reservedRegs.test(preg)) {
152 vrAllowed.push_back(preg);
156 // Remove any physical registers which overlap.
157 for (RegSet::const_iterator pregItr = pregs.begin(),
158 pregEnd = pregs.end();
159 pregItr != pregEnd; ++pregItr) {
160 unsigned preg = *pregItr;
161 const LiveInterval *pregLI = &lis->getInterval(preg);
166 if (!vregLI->overlaps(*pregLI))
169 // Remove the register from the allowed set.
170 VRAllowed::iterator eraseItr =
171 std::find(vrAllowed.begin(), vrAllowed.end(), preg);
173 if (eraseItr != vrAllowed.end()) {
174 vrAllowed.erase(eraseItr);
177 // Also remove any aliases.
178 const unsigned *aliasItr = tri->getAliasSet(preg);
180 for (; *aliasItr != 0; ++aliasItr) {
181 VRAllowed::iterator eraseItr =
182 std::find(vrAllowed.begin(), vrAllowed.end(), *aliasItr);
184 if (eraseItr != vrAllowed.end()) {
185 vrAllowed.erase(eraseItr);
191 // Construct the node.
192 PBQP::Graph::NodeItr node =
193 g.addNode(PBQP::Vector(vrAllowed.size() + 1, 0));
195 // Record the mapping and allowed set in the problem.
196 p->recordVReg(vreg, node, vrAllowed.begin(), vrAllowed.end());
198 PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ?
199 vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min();
201 addSpillCosts(g.getNodeCosts(node), spillCost);
204 for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end();
205 vr1Itr != vrEnd; ++vr1Itr) {
206 unsigned vr1 = *vr1Itr;
207 const LiveInterval &l1 = lis->getInterval(vr1);
208 const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
210 for (RegSet::const_iterator vr2Itr = llvm::next(vr1Itr);
211 vr2Itr != vrEnd; ++vr2Itr) {
212 unsigned vr2 = *vr2Itr;
213 const LiveInterval &l2 = lis->getInterval(vr2);
214 const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
216 assert(!l2.empty() && "Empty interval in vreg set?");
217 if (l1.overlaps(l2)) {
218 PBQP::Graph::EdgeItr edge =
219 g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2),
220 PBQP::Matrix(vr1Allowed.size()+1, vr2Allowed.size()+1, 0));
222 addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri);
230 void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec,
231 PBQP::PBQPNum spillCost) {
232 costVec[0] = spillCost;
235 void PBQPBuilder::addInterferenceCosts(
236 PBQP::Matrix &costMat,
237 const PBQPRAProblem::AllowedSet &vr1Allowed,
238 const PBQPRAProblem::AllowedSet &vr2Allowed,
239 const TargetRegisterInfo *tri) {
240 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
241 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
243 for (unsigned i = 0; i < vr1Allowed.size(); ++i) {
244 unsigned preg1 = vr1Allowed[i];
246 for (unsigned j = 0; j < vr2Allowed.size(); ++j) {
247 unsigned preg2 = vr2Allowed[j];
249 if (tri->regsOverlap(preg1, preg2)) {
250 costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
256 std::auto_ptr<PBQPRAProblem> PBQPBuilderWithCoalescing::build(
258 const LiveIntervals *lis,
259 const MachineLoopInfo *loopInfo,
260 const RegSet &vregs) {
262 std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInfo, vregs);
263 PBQP::Graph &g = p->getGraph();
265 const TargetMachine &tm = mf->getTarget();
266 CoalescerPair cp(*tm.getInstrInfo(), *tm.getRegisterInfo());
268 // Scan the machine function and add a coalescing cost whenever CoalescerPair
270 for (MachineFunction::const_iterator mbbItr = mf->begin(),
272 mbbItr != mbbEnd; ++mbbItr) {
273 const MachineBasicBlock *mbb = &*mbbItr;
275 for (MachineBasicBlock::const_iterator miItr = mbb->begin(),
277 miItr != miEnd; ++miItr) {
278 const MachineInstr *mi = &*miItr;
280 if (!mi->isCopy() && !mi->isSubregToReg())
281 continue; // Not coalescable.
283 if (!cp.setRegisters(mi))
284 continue; // Not coalescable.
286 if (cp.getSrcReg() == cp.getDstReg())
287 continue; // Already coalesced.
289 if (cp.isCoalescable(mi)) {
291 unsigned dst = cp.getDstReg(),
292 src = cp.getSrcReg();
296 PBQP::PBQPNum cBenefit = std::pow(10.0f, loopInfo->getLoopDepth(mbb));
299 if (!lis->isAllocatable(dst))
302 const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
303 unsigned pregOpt = 0;
304 while (pregOpt < allowed.size() && allowed[pregOpt] != dst)
306 if (pregOpt < allowed.size()) {
307 ++pregOpt; // +1 to account for spill option.
308 PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
309 addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit);
312 const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
313 const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
314 PBQP::Graph::NodeItr node1 = p->getNodeForVReg(dst);
315 PBQP::Graph::NodeItr node2 = p->getNodeForVReg(src);
316 PBQP::Graph::EdgeItr edge = g.findEdge(node1, node2);
317 if (edge == g.edgesEnd()) {
318 edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1,
319 allowed2->size() + 1,
322 if (g.getEdgeNode1(edge) == node2) {
323 std::swap(node1, node2);
324 std::swap(allowed1, allowed2);
328 addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2,
339 void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
341 PBQP::PBQPNum benefit) {
342 costVec[pregOption] += -benefit;
345 void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
346 PBQP::Matrix &costMat,
347 const PBQPRAProblem::AllowedSet &vr1Allowed,
348 const PBQPRAProblem::AllowedSet &vr2Allowed,
349 PBQP::PBQPNum benefit) {
351 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
352 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
354 for (unsigned i = 0; i < vr1Allowed.size(); ++i) {
355 unsigned preg1 = vr1Allowed[i];
356 for (unsigned j = 0; j < vr2Allowed.size(); ++j) {
357 unsigned preg2 = vr2Allowed[j];
359 if (preg1 == preg2) {
360 costMat[i + 1][j + 1] += -benefit;
367 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
368 au.addRequired<SlotIndexes>();
369 au.addPreserved<SlotIndexes>();
370 au.addRequired<LiveIntervals>();
371 //au.addRequiredID(SplitCriticalEdgesID);
372 au.addRequired<RegisterCoalescer>();
373 au.addRequired<CalculateSpillWeights>();
374 au.addRequired<LiveStacks>();
375 au.addPreserved<LiveStacks>();
376 au.addRequired<MachineLoopInfo>();
377 au.addPreserved<MachineLoopInfo>();
378 if (pbqpPreSplitting)
379 au.addRequired<LoopSplitter>();
380 au.addRequired<VirtRegMap>();
381 au.addRequired<RenderMachineFunction>();
382 MachineFunctionPass::getAnalysisUsage(au);
385 template <typename RegContainer>
386 PBQP::Vector RegAllocPBQP::buildCostVector(unsigned vReg,
387 const RegContainer &allowed,
388 const CoalesceMap &coalesces,
389 PBQP::PBQPNum spillCost) const {
391 typedef typename RegContainer::const_iterator AllowedItr;
393 // Allocate vector. Additional element (0th) used for spill option
394 PBQP::Vector v(allowed.size() + 1, 0);
398 // Iterate over the allowed registers inserting coalesce benefits if there
401 for (AllowedItr itr = allowed.begin(), end = allowed.end();
402 itr != end; ++itr, ++ai) {
404 unsigned pReg = *itr;
406 CoalesceMap::const_iterator cmItr =
407 coalesces.find(RegPair(vReg, pReg));
409 // No coalesce - on to the next preg.
410 if (cmItr == coalesces.end())
413 // We have a coalesce - insert the benefit.
414 v[ai + 1] = -cmItr->second;
420 template <typename RegContainer>
421 PBQP::Matrix* RegAllocPBQP::buildInterferenceMatrix(
422 const RegContainer &allowed1, const RegContainer &allowed2) const {
424 typedef typename RegContainer::const_iterator RegContainerIterator;
426 // Construct a PBQP matrix representing the cost of allocation options. The
427 // rows and columns correspond to the allocation options for the two live
428 // intervals. Elements will be infinite where corresponding registers alias,
429 // since we cannot allocate aliasing registers to interfering live intervals.
430 // All other elements (non-aliasing combinations) will have zero cost. Note
431 // that the spill option (element 0,0) has zero cost, since we can allocate
432 // both intervals to memory safely (the cost for each individual allocation
433 // to memory is accounted for by the cost vectors for each live interval).
435 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
437 // Assume this is a zero matrix until proven otherwise. Zero matrices occur
438 // between interfering live ranges with non-overlapping register sets (e.g.
439 // non-overlapping reg classes, or disjoint sets of allowed regs within the
440 // same class). The term "overlapping" is used advisedly: sets which do not
441 // intersect, but contain registers which alias, will have non-zero matrices.
442 // We optimize zero matrices away to improve solver speed.
443 bool isZeroMatrix = true;
446 // Row index. Starts at 1, since the 0th row is for the spill option, which
450 // Iterate over allowed sets, insert infinities where required.
451 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
452 a1Itr != a1End; ++a1Itr) {
454 // Column index, starts at 1 as for row index.
456 unsigned reg1 = *a1Itr;
458 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
459 a2Itr != a2End; ++a2Itr) {
461 unsigned reg2 = *a2Itr;
463 // If the row/column regs are identical or alias insert an infinity.
464 if (tri->regsOverlap(reg1, reg2)) {
465 (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity();
466 isZeroMatrix = false;
475 // If this turns out to be a zero matrix...
477 // free it and return null.
482 // ...otherwise return the cost matrix.
486 template <typename RegContainer>
487 PBQP::Matrix* RegAllocPBQP::buildCoalescingMatrix(
488 const RegContainer &allowed1, const RegContainer &allowed2,
489 PBQP::PBQPNum cBenefit) const {
491 typedef typename RegContainer::const_iterator RegContainerIterator;
493 // Construct a PBQP Matrix representing the benefits of coalescing. As with
494 // interference matrices the rows and columns represent allowed registers
495 // for the LiveIntervals which are (potentially) to be coalesced. The amount
496 // -cBenefit will be placed in any element representing the same register
497 // for both intervals.
499 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
501 // Reset costs to zero.
504 // Assume the matrix is zero till proven otherwise. Zero matrices will be
505 // optimized away as in the interference case.
506 bool isZeroMatrix = true;
508 // Row index. Starts at 1, since the 0th row is for the spill option, which
512 // Iterate over the allowed sets, insert coalescing benefits where
514 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
515 a1Itr != a1End; ++a1Itr) {
517 // Column index, starts at 1 as for row index.
519 unsigned reg1 = *a1Itr;
521 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
522 a2Itr != a2End; ++a2Itr) {
524 // If the row and column represent the same register insert a beneficial
525 // cost to preference this allocation - it would allow us to eliminate a
527 if (reg1 == *a2Itr) {
528 (*m)[ri][ci] = -cBenefit;
529 isZeroMatrix = false;
538 // If this turns out to be a zero matrix...
540 // ...free it and return null.
548 RegAllocPBQP::CoalesceMap RegAllocPBQP::findCoalesces() {
550 typedef MachineFunction::const_iterator MFIterator;
551 typedef MachineBasicBlock::const_iterator MBBIterator;
552 typedef LiveInterval::const_vni_iterator VNIIterator;
554 CoalesceMap coalescesFound;
556 // To find coalesces we need to iterate over the function looking for
557 // copy instructions.
558 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end();
559 bbItr != bbEnd; ++bbItr) {
561 const MachineBasicBlock *mbb = &*bbItr;
563 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end();
564 iItr != iEnd; ++iItr) {
566 const MachineInstr *instr = &*iItr;
568 // If this isn't a copy then continue to the next instruction.
569 if (!instr->isCopy())
572 unsigned srcReg = instr->getOperand(1).getReg();
573 unsigned dstReg = instr->getOperand(0).getReg();
575 // If the registers are already the same our job is nice and easy.
576 if (dstReg == srcReg)
579 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg),
580 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg);
582 // If both registers are physical then we can't coalesce.
583 if (srcRegIsPhysical && dstRegIsPhysical)
586 // If it's a copy that includes two virtual register but the source and
587 // destination classes differ then we can't coalesce.
588 if (!srcRegIsPhysical && !dstRegIsPhysical &&
589 mri->getRegClass(srcReg) != mri->getRegClass(dstReg))
592 // If one is physical and one is virtual, check that the physical is
593 // allocatable in the class of the virtual.
594 if (srcRegIsPhysical && !dstRegIsPhysical) {
595 const TargetRegisterClass *dstRegClass = mri->getRegClass(dstReg);
596 if (std::find(dstRegClass->allocation_order_begin(*mf),
597 dstRegClass->allocation_order_end(*mf), srcReg) ==
598 dstRegClass->allocation_order_end(*mf))
601 if (!srcRegIsPhysical && dstRegIsPhysical) {
602 const TargetRegisterClass *srcRegClass = mri->getRegClass(srcReg);
603 if (std::find(srcRegClass->allocation_order_begin(*mf),
604 srcRegClass->allocation_order_end(*mf), dstReg) ==
605 srcRegClass->allocation_order_end(*mf))
609 // If we've made it here we have a copy with compatible register classes.
610 // We can probably coalesce, but we need to consider overlap.
611 const LiveInterval *srcLI = &lis->getInterval(srcReg),
612 *dstLI = &lis->getInterval(dstReg);
614 if (srcLI->overlaps(*dstLI)) {
615 // Even in the case of an overlap we might still be able to coalesce,
616 // but we need to make sure that no definition of either range occurs
617 // while the other range is live.
619 // Otherwise start by assuming we're ok.
622 // Test all defs of the source range.
624 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
625 vniItr != vniEnd; ++vniItr) {
627 // If we find a poorly defined def we err on the side of caution.
628 if (!(*vniItr)->def.isValid()) {
633 // If we find a def that kills the coalescing opportunity then
634 // record it and break from the loop.
635 if (dstLI->liveAt((*vniItr)->def)) {
641 // If we have a bad def give up, continue to the next instruction.
645 // Otherwise test definitions of the destination range.
647 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
648 vniItr != vniEnd; ++vniItr) {
650 // We want to make sure we skip the copy instruction itself.
651 if ((*vniItr)->getCopy() == instr)
654 if (!(*vniItr)->def.isValid()) {
659 if (srcLI->liveAt((*vniItr)->def)) {
665 // As before a bad def we give up and continue to the next instr.
670 // If we make it to here then either the ranges didn't overlap, or they
671 // did, but none of their definitions would prevent us from coalescing.
672 // We're good to go with the coalesce.
674 float cBenefit = std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb)) / 5.0;
676 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
677 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
682 return coalescesFound;
685 void RegAllocPBQP::findVRegIntervalsToAlloc() {
687 // Iterate over all live ranges.
688 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
691 // Ignore physical ones.
692 if (TargetRegisterInfo::isPhysicalRegister(itr->first))
695 LiveInterval *li = itr->second;
697 // If this live interval is non-empty we will use pbqp to allocate it.
698 // Empty intervals we allocate in a simple post-processing stage in
701 vregsToAlloc.insert(li->reg);
704 emptyIntervalVRegs.insert(li->reg);
709 PBQP::Graph RegAllocPBQP::constructPBQPProblem() {
711 typedef std::vector<const LiveInterval*> LIVector;
712 typedef std::vector<unsigned> RegVector;
714 // This will store the physical intervals for easy reference.
715 LIVector physIntervals;
717 // Start by clearing the old node <-> live interval mappings & allowed sets
722 // Populate physIntervals, update preg use:
723 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
726 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
727 physIntervals.push_back(itr->second);
728 mri->setPhysRegUsed(itr->second->reg);
732 // Iterate over vreg intervals, construct live interval <-> node number
734 for (RegSet::const_iterator itr = vregsToAlloc.begin(),
735 end = vregsToAlloc.end();
737 const LiveInterval *li = &lis->getInterval(*itr);
739 li2Node[li] = node2LI.size();
740 node2LI.push_back(li);
743 // Get the set of potential coalesces.
744 CoalesceMap coalesces;
746 if (pbqpCoalescing) {
747 coalesces = findCoalesces();
750 // Construct a PBQP solver for this problem
752 problemNodes.resize(vregsToAlloc.size());
754 // Resize allowedSets container appropriately.
755 allowedSets.resize(vregsToAlloc.size());
757 BitVector ReservedRegs = tri->getReservedRegs(*mf);
759 // Iterate over virtual register intervals to compute allowed sets...
760 for (unsigned node = 0; node < node2LI.size(); ++node) {
762 // Grab pointers to the interval and its register class.
763 const LiveInterval *li = node2LI[node];
764 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
766 // Start by assuming all allocable registers in the class are allowed...
768 TargetRegisterClass::iterator aob = liRC->allocation_order_begin(*mf);
769 TargetRegisterClass::iterator aoe = liRC->allocation_order_end(*mf);
770 for (TargetRegisterClass::iterator it = aob; it != aoe; ++it)
771 if (!ReservedRegs.test(*it))
772 liAllowed.push_back(*it);
774 // Eliminate the physical registers which overlap with this range, along
775 // with all their aliases.
776 for (LIVector::iterator pItr = physIntervals.begin(),
777 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) {
779 if (!li->overlaps(**pItr))
782 unsigned pReg = (*pItr)->reg;
784 // If we get here then the live intervals overlap, but we're still ok
785 // if they're coalescable.
786 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) {
787 DEBUG(dbgs() << "CoalescingOverride: (" << li->reg << ", " << pReg << ")\n");
791 // If we get here then we have a genuine exclusion.
793 // Remove the overlapping reg...
794 RegVector::iterator eraseItr =
795 std::find(liAllowed.begin(), liAllowed.end(), pReg);
797 if (eraseItr != liAllowed.end())
798 liAllowed.erase(eraseItr);
800 const unsigned *aliasItr = tri->getAliasSet(pReg);
803 // ...and its aliases.
804 for (; *aliasItr != 0; ++aliasItr) {
805 RegVector::iterator eraseItr =
806 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
808 if (eraseItr != liAllowed.end()) {
809 liAllowed.erase(eraseItr);
815 // Copy the allowed set into a member vector for use when constructing cost
816 // vectors & matrices, and mapping PBQP solutions back to assignments.
817 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end());
819 // Set the spill cost to the interval weight, or epsilon if the
820 // interval weight is zero
821 PBQP::PBQPNum spillCost = (li->weight != 0.0) ?
822 li->weight : std::numeric_limits<PBQP::PBQPNum>::min();
824 // Build a cost vector for this interval.
827 buildCostVector(li->reg, allowedSets[node], coalesces, spillCost));
832 // Now add the cost matrices...
833 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) {
834 const LiveInterval *li = node2LI[node1];
836 // Test for live range overlaps and insert interference matrices.
837 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) {
838 const LiveInterval *li2 = node2LI[node2];
840 CoalesceMap::const_iterator cmItr =
841 coalesces.find(RegPair(li->reg, li2->reg));
845 if (cmItr != coalesces.end()) {
846 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2],
849 else if (li->overlaps(*li2)) {
850 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
854 problem.addEdge(problemNodes[node1],
863 assert(problem.getNumNodes() == allowedSets.size());
865 std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, "
866 << problem.getNumEdges() << " edges.\n";
868 problem.printDot(std::cerr);
870 // We're done, PBQP problem constructed - return it.
874 void RegAllocPBQP::addStackInterval(const LiveInterval *spilled,
875 MachineRegisterInfo* mri) {
876 int stackSlot = vrm->getStackSlot(spilled->reg);
878 if (stackSlot == VirtRegMap::NO_STACK_SLOT)
881 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
882 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
885 if (stackInterval.getNumValNums() != 0)
886 vni = stackInterval.getValNumInfo(0);
888 vni = stackInterval.getNextValue(
889 SlotIndex(), 0, false, lss->getVNInfoAllocator());
891 LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
892 stackInterval.MergeRangesInAsValue(rhsInterval, vni);
895 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
897 // Set to true if we have any spills
898 bool anotherRoundNeeded = false;
900 // Clear the existing allocation.
903 // Iterate over the nodes mapping the PBQP solution to a register assignment.
904 for (unsigned node = 0; node < node2LI.size(); ++node) {
905 unsigned virtReg = node2LI[node]->reg,
906 allocSelection = solution.getSelection(problemNodes[node]);
909 // If the PBQP solution is non-zero it's a physical register...
910 if (allocSelection != 0) {
911 // Get the physical reg, subtracting 1 to account for the spill option.
912 unsigned physReg = allowedSets[node][allocSelection - 1];
914 DEBUG(dbgs() << "VREG " << virtReg << " -> "
915 << tri->getName(physReg) << " (Option: " << allocSelection << ")\n");
917 assert(physReg != 0);
919 // Add to the virt reg map and update the used phys regs.
920 vrm->assignVirt2Phys(virtReg, physReg);
922 // ...Otherwise it's a spill.
925 // Make sure we ignore this virtual reg on the next round
927 vregsToAlloc.erase(virtReg);
929 // Insert spill ranges for this live range
930 const LiveInterval *spillInterval = node2LI[node];
931 double oldSpillWeight = spillInterval->weight;
932 SmallVector<LiveInterval*, 8> spillIs;
933 rmf->rememberUseDefs(spillInterval);
934 std::vector<LiveInterval*> newSpills =
935 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
936 addStackInterval(spillInterval, mri);
937 rmf->rememberSpills(spillInterval, newSpills);
939 (void) oldSpillWeight;
940 DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Option: 0, Cost: "
941 << oldSpillWeight << ", New vregs: ");
943 // Copy any newly inserted live intervals into the list of regs to
945 for (std::vector<LiveInterval*>::const_iterator
946 itr = newSpills.begin(), end = newSpills.end();
949 assert(!(*itr)->empty() && "Empty spill range.");
951 DEBUG(dbgs() << (*itr)->reg << " ");
953 vregsToAlloc.insert((*itr)->reg);
956 DEBUG(dbgs() << ")\n");
958 // We need another round if spill intervals were added.
959 anotherRoundNeeded |= !newSpills.empty();
963 return !anotherRoundNeeded;
966 bool RegAllocPBQP::mapPBQPToRegAlloc2(const PBQPRAProblem &problem,
967 const PBQP::Solution &solution) {
968 // Set to true if we have any spills
969 bool anotherRoundNeeded = false;
971 // Clear the existing allocation.
974 const PBQP::Graph &g = problem.getGraph();
975 // Iterate over the nodes mapping the PBQP solution to a register
977 for (PBQP::Graph::ConstNodeItr node = g.nodesBegin(),
978 nodeEnd = g.nodesEnd();
979 node != nodeEnd; ++node) {
980 unsigned vreg = problem.getVRegForNode(node);
981 unsigned alloc = solution.getSelection(node);
983 if (problem.isPRegOption(vreg, alloc)) {
984 unsigned preg = problem.getPRegForOption(vreg, alloc);
985 DEBUG(dbgs() << "VREG " << vreg << " -> " << tri->getName(preg) << "\n");
986 assert(preg != 0 && "Invalid preg selected.");
987 vrm->assignVirt2Phys(vreg, preg);
988 } else if (problem.isSpillOption(vreg, alloc)) {
989 vregsToAlloc.erase(vreg);
990 const LiveInterval* spillInterval = &lis->getInterval(vreg);
991 double oldWeight = spillInterval->weight;
992 SmallVector<LiveInterval*, 8> spillIs;
993 rmf->rememberUseDefs(spillInterval);
994 std::vector<LiveInterval*> newSpills =
995 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
996 addStackInterval(spillInterval, mri);
997 rmf->rememberSpills(spillInterval, newSpills);
1000 DEBUG(dbgs() << "VREG " << vreg << " -> SPILLED (Cost: "
1001 << oldWeight << ", New vregs: ");
1003 // Copy any newly inserted live intervals into the list of regs to
1005 for (std::vector<LiveInterval*>::const_iterator
1006 itr = newSpills.begin(), end = newSpills.end();
1007 itr != end; ++itr) {
1008 assert(!(*itr)->empty() && "Empty spill range.");
1009 DEBUG(dbgs() << (*itr)->reg << " ");
1010 vregsToAlloc.insert((*itr)->reg);
1013 DEBUG(dbgs() << ")\n");
1015 // We need another round if spill intervals were added.
1016 anotherRoundNeeded |= !newSpills.empty();
1018 assert(false && "Unknown allocation option.");
1022 return !anotherRoundNeeded;
1026 void RegAllocPBQP::finalizeAlloc() const {
1027 typedef LiveIntervals::iterator LIIterator;
1028 typedef LiveInterval::Ranges::const_iterator LRIterator;
1030 // First allocate registers for the empty intervals.
1031 for (RegSet::const_iterator
1032 itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end();
1033 itr != end; ++itr) {
1034 LiveInterval *li = &lis->getInterval(*itr);
1036 unsigned physReg = vrm->getRegAllocPref(li->reg);
1039 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
1040 physReg = *liRC->allocation_order_begin(*mf);
1043 vrm->assignVirt2Phys(li->reg, physReg);
1046 // Finally iterate over the basic blocks to compute and set the live-in sets.
1047 SmallVector<MachineBasicBlock*, 8> liveInMBBs;
1048 MachineBasicBlock *entryMBB = &*mf->begin();
1050 for (LIIterator liItr = lis->begin(), liEnd = lis->end();
1051 liItr != liEnd; ++liItr) {
1053 const LiveInterval *li = liItr->second;
1056 // Get the physical register for this interval
1057 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
1060 else if (vrm->isAssignedReg(li->reg)) {
1061 reg = vrm->getPhys(li->reg);
1064 // Ranges which are assigned a stack slot only are ignored.
1069 // Filter out zero regs - they're for intervals that were spilled.
1073 // Iterate over the ranges of the current interval...
1074 for (LRIterator lrItr = li->begin(), lrEnd = li->end();
1075 lrItr != lrEnd; ++lrItr) {
1077 // Find the set of basic blocks which this range is live into...
1078 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
1079 // And add the physreg for this interval to their live-in sets.
1080 for (unsigned i = 0; i < liveInMBBs.size(); ++i) {
1081 if (liveInMBBs[i] != entryMBB) {
1082 if (!liveInMBBs[i]->isLiveIn(reg)) {
1083 liveInMBBs[i]->addLiveIn(reg);
1094 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
1097 tm = &mf->getTarget();
1098 tri = tm->getRegisterInfo();
1099 tii = tm->getInstrInfo();
1100 mri = &mf->getRegInfo();
1102 lis = &getAnalysis<LiveIntervals>();
1103 lss = &getAnalysis<LiveStacks>();
1104 loopInfo = &getAnalysis<MachineLoopInfo>();
1105 rmf = &getAnalysis<RenderMachineFunction>();
1107 vrm = &getAnalysis<VirtRegMap>();
1110 DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
1112 // Allocator main loop:
1114 // * Map current regalloc problem to a PBQP problem
1115 // * Solve the PBQP problem
1116 // * Map the solution back to a register allocation
1117 // * Spill if necessary
1119 // This process is continued till no more spills are generated.
1121 // Find the vreg intervals in need of allocation.
1122 findVRegIntervalsToAlloc();
1124 // If there are non-empty intervals allocate them using pbqp.
1125 if (!vregsToAlloc.empty()) {
1127 bool pbqpAllocComplete = false;
1131 while (!pbqpAllocComplete) {
1132 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
1134 PBQP::Graph problem = constructPBQPProblem();
1135 PBQP::Solution solution =
1136 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(problem);
1138 pbqpAllocComplete = mapPBQPToRegAlloc(solution);
1143 while (!pbqpAllocComplete) {
1144 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
1146 std::auto_ptr<PBQPRAProblem> problem =
1147 builder->build(mf, lis, loopInfo, vregsToAlloc);
1148 PBQP::Solution solution =
1149 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(
1150 problem->getGraph());
1152 pbqpAllocComplete = mapPBQPToRegAlloc2(*problem, solution);
1159 // Finalise allocation, allocate empty ranges.
1162 rmf->renderMachineFunction("After PBQP register allocation.", vrm);
1164 vregsToAlloc.clear();
1165 emptyIntervalVRegs.clear();
1168 allowedSets.clear();
1169 problemNodes.clear();
1171 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
1174 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
1176 rewriter->runOnMachineFunction(*mf, *vrm, lis);
1181 FunctionPass* createPBQPRegisterAllocator() {
1182 if (pbqpCoalescing) {
1183 return new RegAllocPBQP(
1184 std::auto_ptr<PBQPBuilder>(new PBQPBuilderWithCoalescing()));
1186 return new RegAllocPBQP(
1187 std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));