1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SlotIndexes.h"
26 #include "llvm/IR/BasicBlock.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/ModuleSlotTracker.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "codegen"
42 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
43 : BB(bb), Number(-1), AreSuccWeightsNormalized(false), xParent(&mf),
44 Alignment(0), IsLandingPad(false), AddressTaken(false),
45 CachedMCSymbol(nullptr) {
49 MachineBasicBlock::~MachineBasicBlock() {
52 /// getSymbol - Return the MCSymbol for this basic block.
54 MCSymbol *MachineBasicBlock::getSymbol() const {
55 if (!CachedMCSymbol) {
56 const MachineFunction *MF = getParent();
57 MCContext &Ctx = MF->getContext();
58 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
59 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
60 Twine(MF->getFunctionNumber()) +
61 "_" + Twine(getNumber()));
64 return CachedMCSymbol;
68 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
73 /// addNodeToList (MBB) - When an MBB is added to an MF, we need to update the
74 /// parent pointer of the MBB, the MBB numbering, and any instructions in the
75 /// MBB to be on the right operand list for registers.
77 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
78 /// gets the next available unique MBB number. If it is removed from a
79 /// MachineFunction, it goes back to being #-1.
80 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
81 MachineFunction &MF = *N->getParent();
82 N->Number = MF.addToMBBNumbering(N);
84 // Make sure the instructions have their operands in the reginfo lists.
85 MachineRegisterInfo &RegInfo = MF.getRegInfo();
86 for (MachineBasicBlock::instr_iterator
87 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
88 I->AddRegOperandsToUseLists(RegInfo);
91 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
92 N->getParent()->removeFromMBBNumbering(N->Number);
97 /// addNodeToList (MI) - When we add an instruction to a basic block
98 /// list, we update its parent pointer and add its operands from reg use/def
99 /// lists if appropriate.
100 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
101 assert(!N->getParent() && "machine instruction already in a basic block");
102 N->setParent(Parent);
104 // Add the instruction's register operands to their corresponding
106 MachineFunction *MF = Parent->getParent();
107 N->AddRegOperandsToUseLists(MF->getRegInfo());
110 /// removeNodeFromList (MI) - When we remove an instruction from a basic block
111 /// list, we update its parent pointer and remove its operands from reg use/def
112 /// lists if appropriate.
113 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
114 assert(N->getParent() && "machine instruction not in a basic block");
116 // Remove from the use/def lists.
117 if (MachineFunction *MF = N->getParent()->getParent())
118 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
120 N->setParent(nullptr);
123 /// transferNodesFromList (MI) - When moving a range of instructions from one
124 /// MBB list to another, we need to update the parent pointers and the use/def
126 void ilist_traits<MachineInstr>::
127 transferNodesFromList(ilist_traits<MachineInstr> &fromList,
128 ilist_iterator<MachineInstr> first,
129 ilist_iterator<MachineInstr> last) {
130 assert(Parent->getParent() == fromList.Parent->getParent() &&
131 "MachineInstr parent mismatch!");
133 // Splice within the same MBB -> no change.
134 if (Parent == fromList.Parent) return;
136 // If splicing between two blocks within the same function, just update the
138 for (; first != last; ++first)
139 first->setParent(Parent);
142 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
143 assert(!MI->getParent() && "MI is still in a block!");
144 Parent->getParent()->DeleteMachineInstr(MI);
147 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
148 instr_iterator I = instr_begin(), E = instr_end();
149 while (I != E && I->isPHI())
151 assert((I == E || !I->isInsideBundle()) &&
152 "First non-phi MI cannot be inside a bundle!");
156 MachineBasicBlock::iterator
157 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
159 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
161 // FIXME: This needs to change if we wish to bundle labels / dbg_values
162 // inside the bundle.
163 assert((I == E || !I->isInsideBundle()) &&
164 "First non-phi / non-label instruction is inside a bundle!");
168 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
169 iterator B = begin(), E = end(), I = E;
170 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
172 while (I != E && !I->isTerminator())
177 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
178 instr_iterator B = instr_begin(), E = instr_end(), I = E;
179 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
181 while (I != E && !I->isTerminator())
186 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
187 // Skip over begin-of-block dbg_value instructions.
188 iterator I = begin(), E = end();
189 while (I != E && I->isDebugValue())
194 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
195 // Skip over end-of-block dbg_value instructions.
196 instr_iterator B = instr_begin(), I = instr_end();
199 // Return instruction that starts a bundle.
200 if (I->isDebugValue() || I->isInsideBundle())
204 // The block is all debug values.
208 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
209 // A block with a landing pad successor only has one other successor.
212 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
213 if ((*I)->isLandingPad())
218 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
219 void MachineBasicBlock::dump() const {
224 StringRef MachineBasicBlock::getName() const {
225 if (const BasicBlock *LBB = getBasicBlock())
226 return LBB->getName();
231 /// Return a hopefully unique identifier for this block.
232 std::string MachineBasicBlock::getFullName() const {
235 Name = (getParent()->getName() + ":").str();
237 Name += getBasicBlock()->getName();
239 Name += ("BB" + Twine(getNumber())).str();
243 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
244 const MachineFunction *MF = getParent();
246 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
250 const Function *F = MF->getFunction();
251 const Module *M = F ? F->getParent() : nullptr;
252 ModuleSlotTracker MST(M);
253 print(OS, MST, Indexes);
256 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
257 SlotIndexes *Indexes) const {
258 const MachineFunction *MF = getParent();
260 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
266 OS << Indexes->getMBBStartIdx(this) << '\t';
268 OS << "BB#" << getNumber() << ": ";
270 const char *Comma = "";
271 if (const BasicBlock *LBB = getBasicBlock()) {
272 OS << Comma << "derived from LLVM BB ";
273 LBB->printAsOperand(OS, /*PrintType=*/false, MST);
276 if (isLandingPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
277 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
279 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
284 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
285 if (!livein_empty()) {
286 if (Indexes) OS << '\t';
288 for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
289 OS << ' ' << PrintReg(*I, TRI);
292 // Print the preds of this block according to the CFG.
294 if (Indexes) OS << '\t';
295 OS << " Predecessors according to CFG:";
296 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
297 OS << " BB#" << (*PI)->getNumber();
301 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
303 if (Indexes->hasIndex(I))
304 OS << Indexes->getInstructionIndex(I);
308 if (I->isInsideBundle())
313 // Print the successors of this block according to the CFG.
315 if (Indexes) OS << '\t';
316 OS << " Successors according to CFG:";
317 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
318 OS << " BB#" << (*SI)->getNumber();
319 if (!Weights.empty())
320 OS << '(' << *getWeightIterator(SI) << ')';
326 void MachineBasicBlock::printAsOperand(raw_ostream &OS, bool /*PrintType*/) const {
327 OS << "BB#" << getNumber();
330 void MachineBasicBlock::removeLiveIn(unsigned Reg) {
331 std::vector<unsigned>::iterator I =
332 std::find(LiveIns.begin(), LiveIns.end(), Reg);
333 if (I != LiveIns.end())
337 bool MachineBasicBlock::isLiveIn(unsigned Reg) const {
338 livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
339 return I != livein_end();
343 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) {
344 assert(getParent() && "MBB must be inserted in function");
345 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
346 assert(RC && "Register class is required");
347 assert((isLandingPad() || this == &getParent()->front()) &&
348 "Only the entry block and landing pads can have physreg live ins");
350 bool LiveIn = isLiveIn(PhysReg);
351 iterator I = SkipPHIsAndLabels(begin()), E = end();
352 MachineRegisterInfo &MRI = getParent()->getRegInfo();
353 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
355 // Look for an existing copy.
357 for (;I != E && I->isCopy(); ++I)
358 if (I->getOperand(1).getReg() == PhysReg) {
359 unsigned VirtReg = I->getOperand(0).getReg();
360 if (!MRI.constrainRegClass(VirtReg, RC))
361 llvm_unreachable("Incompatible live-in register class.");
365 // No luck, create a virtual register.
366 unsigned VirtReg = MRI.createVirtualRegister(RC);
367 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
368 .addReg(PhysReg, RegState::Kill);
374 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
375 getParent()->splice(NewAfter, this);
378 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
379 MachineFunction::iterator BBI = NewBefore;
380 getParent()->splice(++BBI, this);
383 void MachineBasicBlock::updateTerminator() {
384 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
385 // A block with no successors has no concerns with fall-through edges.
386 if (this->succ_empty()) return;
388 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
389 SmallVector<MachineOperand, 4> Cond;
390 DebugLoc dl; // FIXME: this is nowhere
391 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
393 assert(!B && "UpdateTerminators requires analyzable predecessors!");
396 // The block has an unconditional branch. If its successor is now
397 // its layout successor, delete the branch.
398 if (isLayoutSuccessor(TBB))
399 TII->RemoveBranch(*this);
401 // The block has an unconditional fallthrough. If its successor is not
402 // its layout successor, insert a branch. First we have to locate the
403 // only non-landing-pad successor, as that is the fallthrough block.
404 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
405 if ((*SI)->isLandingPad())
407 assert(!TBB && "Found more than one non-landing-pad successor!");
411 // If there is no non-landing-pad successor, the block has no
412 // fall-through edges to be concerned with.
416 // Finally update the unconditional successor to be reached via a branch
417 // if it would not be reached by fallthrough.
418 if (!isLayoutSuccessor(TBB))
419 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
423 // The block has a non-fallthrough conditional branch. If one of its
424 // successors is its layout successor, rewrite it to a fallthrough
425 // conditional branch.
426 if (isLayoutSuccessor(TBB)) {
427 if (TII->ReverseBranchCondition(Cond))
429 TII->RemoveBranch(*this);
430 TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
431 } else if (isLayoutSuccessor(FBB)) {
432 TII->RemoveBranch(*this);
433 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
436 // Walk through the successors and find the successor which is not
437 // a landing pad and is not the conditional branch destination (in TBB)
438 // as the fallthrough successor.
439 MachineBasicBlock *FallthroughBB = nullptr;
440 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
441 if ((*SI)->isLandingPad() || *SI == TBB)
443 assert(!FallthroughBB && "Found more than one fallthrough successor.");
446 if (!FallthroughBB && canFallThrough()) {
447 // We fallthrough to the same basic block as the conditional jump
448 // targets. Remove the conditional jump, leaving unconditional
450 // FIXME: This does not seem like a reasonable pattern to support, but it
451 // has been seen in the wild coming out of degenerate ARM test cases.
452 TII->RemoveBranch(*this);
454 // Finally update the unconditional successor to be reached via a branch
455 // if it would not be reached by fallthrough.
456 if (!isLayoutSuccessor(TBB))
457 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
461 // The block has a fallthrough conditional branch.
462 if (isLayoutSuccessor(TBB)) {
463 if (TII->ReverseBranchCondition(Cond)) {
464 // We can't reverse the condition, add an unconditional branch.
466 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
469 TII->RemoveBranch(*this);
470 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
471 } else if (!isLayoutSuccessor(FallthroughBB)) {
472 TII->RemoveBranch(*this);
473 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
479 void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) {
481 // If we see non-zero value for the first time it means we actually use Weight
482 // list, so we fill all Weights with 0's.
483 if (weight != 0 && Weights.empty())
484 Weights.resize(Successors.size());
486 if (weight != 0 || !Weights.empty()) {
487 Weights.push_back(weight);
488 AreSuccWeightsNormalized = false;
491 Successors.push_back(succ);
492 succ->addPredecessor(this);
495 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) {
496 succ->removePredecessor(this);
497 succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
498 assert(I != Successors.end() && "Not a current successor!");
500 // If Weight list is empty it means we don't use it (disabled optimization).
501 if (!Weights.empty()) {
502 weight_iterator WI = getWeightIterator(I);
509 MachineBasicBlock::succ_iterator
510 MachineBasicBlock::removeSuccessor(succ_iterator I) {
511 assert(I != Successors.end() && "Not a current successor!");
513 // If Weight list is empty it means we don't use it (disabled optimization).
514 if (!Weights.empty()) {
515 weight_iterator WI = getWeightIterator(I);
519 (*I)->removePredecessor(this);
520 return Successors.erase(I);
523 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
524 MachineBasicBlock *New) {
528 succ_iterator E = succ_end();
529 succ_iterator NewI = E;
530 succ_iterator OldI = E;
531 for (succ_iterator I = succ_begin(); I != E; ++I) {
543 assert(OldI != E && "Old is not a successor of this block");
544 Old->removePredecessor(this);
546 // If New isn't already a successor, let it take Old's place.
548 New->addPredecessor(this);
553 // New is already a successor.
554 // Update its weight instead of adding a duplicate edge.
555 if (!Weights.empty()) {
556 weight_iterator OldWI = getWeightIterator(OldI);
557 *getWeightIterator(NewI) += *OldWI;
558 Weights.erase(OldWI);
560 Successors.erase(OldI);
563 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
564 Predecessors.push_back(pred);
567 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
568 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
569 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
570 Predecessors.erase(I);
573 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
577 while (!fromMBB->succ_empty()) {
578 MachineBasicBlock *Succ = *fromMBB->succ_begin();
581 // If Weight list is empty it means we don't use it (disabled optimization).
582 if (!fromMBB->Weights.empty())
583 Weight = *fromMBB->Weights.begin();
585 addSuccessor(Succ, Weight);
586 fromMBB->removeSuccessor(Succ);
591 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
595 while (!fromMBB->succ_empty()) {
596 MachineBasicBlock *Succ = *fromMBB->succ_begin();
598 if (!fromMBB->Weights.empty())
599 Weight = *fromMBB->Weights.begin();
600 addSuccessor(Succ, Weight);
601 fromMBB->removeSuccessor(Succ);
603 // Fix up any PHI nodes in the successor.
604 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
605 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
606 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
607 MachineOperand &MO = MI->getOperand(i);
608 if (MO.getMBB() == fromMBB)
614 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
615 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
618 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
619 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
622 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
623 MachineFunction::const_iterator I(this);
624 return std::next(I) == MachineFunction::const_iterator(MBB);
627 bool MachineBasicBlock::canFallThrough() {
628 MachineFunction::iterator Fallthrough = this;
630 // If FallthroughBlock is off the end of the function, it can't fall through.
631 if (Fallthrough == getParent()->end())
634 // If FallthroughBlock isn't a successor, no fallthrough is possible.
635 if (!isSuccessor(Fallthrough))
638 // Analyze the branches, if any, at the end of the block.
639 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
640 SmallVector<MachineOperand, 4> Cond;
641 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
642 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
643 // If we couldn't analyze the branch, examine the last instruction.
644 // If the block doesn't end in a known control barrier, assume fallthrough
645 // is possible. The isPredicated check is needed because this code can be
646 // called during IfConversion, where an instruction which is normally a
647 // Barrier is predicated and thus no longer an actual control barrier.
648 return empty() || !back().isBarrier() || TII->isPredicated(&back());
651 // If there is no branch, control always falls through.
652 if (!TBB) return true;
654 // If there is some explicit branch to the fallthrough block, it can obviously
655 // reach, even though the branch should get folded to fall through implicitly.
656 if (MachineFunction::iterator(TBB) == Fallthrough ||
657 MachineFunction::iterator(FBB) == Fallthrough)
660 // If it's an unconditional branch to some block not the fall through, it
661 // doesn't fall through.
662 if (Cond.empty()) return false;
664 // Otherwise, if it is conditional and has no explicit false block, it falls
666 return FBB == nullptr;
670 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
671 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
672 // it in this generic function.
673 if (Succ->isLandingPad())
676 MachineFunction *MF = getParent();
677 DebugLoc dl; // FIXME: this is nowhere
679 // Performance might be harmed on HW that implements branching using exec mask
680 // where both sides of the branches are always executed.
681 if (MF->getTarget().requiresStructuredCFG())
684 // We may need to update this's terminator, but we can't do that if
685 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
686 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
687 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
688 SmallVector<MachineOperand, 4> Cond;
689 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
692 // Avoid bugpoint weirdness: A block may end with a conditional branch but
693 // jumps to the same MBB is either case. We have duplicate CFG edges in that
694 // case that we can't handle. Since this never happens in properly optimized
695 // code, just skip those edges.
696 if (TBB && TBB == FBB) {
697 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
698 << getNumber() << '\n');
702 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
703 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
704 DEBUG(dbgs() << "Splitting critical edge:"
705 " BB#" << getNumber()
706 << " -- BB#" << NMBB->getNumber()
707 << " -- BB#" << Succ->getNumber() << '\n');
709 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
710 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
712 LIS->insertMBBInMaps(NMBB);
714 Indexes->insertMBBInMaps(NMBB);
716 // On some targets like Mips, branches may kill virtual registers. Make sure
717 // that LiveVariables is properly updated after updateTerminator replaces the
719 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
721 // Collect a list of virtual registers killed by the terminators.
722 SmallVector<unsigned, 4> KilledRegs;
724 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
726 MachineInstr *MI = I;
727 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
728 OE = MI->operands_end(); OI != OE; ++OI) {
729 if (!OI->isReg() || OI->getReg() == 0 ||
730 !OI->isUse() || !OI->isKill() || OI->isUndef())
732 unsigned Reg = OI->getReg();
733 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
734 LV->getVarInfo(Reg).removeKill(MI)) {
735 KilledRegs.push_back(Reg);
736 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
737 OI->setIsKill(false);
742 SmallVector<unsigned, 4> UsedRegs;
744 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
746 MachineInstr *MI = I;
748 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
749 OE = MI->operands_end(); OI != OE; ++OI) {
750 if (!OI->isReg() || OI->getReg() == 0)
753 unsigned Reg = OI->getReg();
754 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
755 UsedRegs.push_back(Reg);
760 ReplaceUsesOfBlockWith(Succ, NMBB);
762 // If updateTerminator() removes instructions, we need to remove them from
764 SmallVector<MachineInstr*, 4> Terminators;
766 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
768 Terminators.push_back(I);
774 SmallVector<MachineInstr*, 4> NewTerminators;
775 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
777 NewTerminators.push_back(I);
779 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
780 E = Terminators.end(); I != E; ++I) {
781 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
782 NewTerminators.end())
783 Indexes->removeMachineInstrFromMaps(*I);
787 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
788 NMBB->addSuccessor(Succ);
789 if (!NMBB->isLayoutSuccessor(Succ)) {
791 MF->getSubtarget().getInstrInfo()->InsertBranch(*NMBB, Succ, nullptr, Cond,
795 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
797 // Some instructions may have been moved to NMBB by updateTerminator(),
798 // so we first remove any instruction that already has an index.
799 if (Indexes->hasIndex(I))
800 Indexes->removeMachineInstrFromMaps(I);
801 Indexes->insertMachineInstrInMaps(I);
806 // Fix PHI nodes in Succ so they refer to NMBB instead of this
807 for (MachineBasicBlock::instr_iterator
808 i = Succ->instr_begin(),e = Succ->instr_end();
809 i != e && i->isPHI(); ++i)
810 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
811 if (i->getOperand(ni+1).getMBB() == this)
812 i->getOperand(ni+1).setMBB(NMBB);
814 // Inherit live-ins from the successor
815 for (MachineBasicBlock::livein_iterator I = Succ->livein_begin(),
816 E = Succ->livein_end(); I != E; ++I)
819 // Update LiveVariables.
820 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
822 // Restore kills of virtual registers that were killed by the terminators.
823 while (!KilledRegs.empty()) {
824 unsigned Reg = KilledRegs.pop_back_val();
825 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
826 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
828 if (TargetRegisterInfo::isVirtualRegister(Reg))
829 LV->getVarInfo(Reg).Kills.push_back(I);
830 DEBUG(dbgs() << "Restored terminator kill: " << *I);
834 // Update relevant live-through information.
835 LV->addNewBlock(NMBB, this, Succ);
839 // After splitting the edge and updating SlotIndexes, live intervals may be
840 // in one of two situations, depending on whether this block was the last in
841 // the function. If the original block was the last in the function, all live
842 // intervals will end prior to the beginning of the new split block. If the
843 // original block was not at the end of the function, all live intervals will
844 // extend to the end of the new split block.
847 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
849 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
850 SlotIndex PrevIndex = StartIndex.getPrevSlot();
851 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
853 // Find the registers used from NMBB in PHIs in Succ.
854 SmallSet<unsigned, 8> PHISrcRegs;
855 for (MachineBasicBlock::instr_iterator
856 I = Succ->instr_begin(), E = Succ->instr_end();
857 I != E && I->isPHI(); ++I) {
858 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
859 if (I->getOperand(ni+1).getMBB() == NMBB) {
860 MachineOperand &MO = I->getOperand(ni);
861 unsigned Reg = MO.getReg();
862 PHISrcRegs.insert(Reg);
866 LiveInterval &LI = LIS->getInterval(Reg);
867 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
868 assert(VNI && "PHI sources should be live out of their predecessors.");
869 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
874 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
875 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
876 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
877 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
880 LiveInterval &LI = LIS->getInterval(Reg);
881 if (!LI.liveAt(PrevIndex))
884 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
885 if (isLiveOut && isLastMBB) {
886 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
887 assert(VNI && "LiveInterval should have VNInfo where it is live.");
888 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
889 } else if (!isLiveOut && !isLastMBB) {
890 LI.removeSegment(StartIndex, EndIndex);
894 // Update all intervals for registers whose uses may have been modified by
895 // updateTerminator().
896 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
899 if (MachineDominatorTree *MDT =
900 P->getAnalysisIfAvailable<MachineDominatorTree>())
901 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
903 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
904 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
905 // If one or the other blocks were not in a loop, the new block is not
906 // either, and thus LI doesn't need to be updated.
907 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
908 if (TIL == DestLoop) {
909 // Both in the same loop, the NMBB joins loop.
910 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
911 } else if (TIL->contains(DestLoop)) {
912 // Edge from an outer loop to an inner loop. Add to the outer loop.
913 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
914 } else if (DestLoop->contains(TIL)) {
915 // Edge from an inner loop to an outer loop. Add to the outer loop.
916 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
918 // Edge from two loops with no containment relation. Because these
919 // are natural loops, we know that the destination block must be the
920 // header of its loop (adding a branch into a loop elsewhere would
921 // create an irreducible loop).
922 assert(DestLoop->getHeader() == Succ &&
923 "Should not create irreducible loops!");
924 if (MachineLoop *P = DestLoop->getParentLoop())
925 P->addBasicBlockToLoop(NMBB, MLI->getBase());
933 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
934 /// neighboring instructions so the bundle won't be broken by removing MI.
935 static void unbundleSingleMI(MachineInstr *MI) {
936 // Removing the first instruction in a bundle.
937 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
938 MI->unbundleFromSucc();
939 // Removing the last instruction in a bundle.
940 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
941 MI->unbundleFromPred();
942 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
946 MachineBasicBlock::instr_iterator
947 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
949 return Insts.erase(I);
952 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
953 unbundleSingleMI(MI);
954 MI->clearFlag(MachineInstr::BundledPred);
955 MI->clearFlag(MachineInstr::BundledSucc);
956 return Insts.remove(MI);
959 MachineBasicBlock::instr_iterator
960 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
961 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
962 "Cannot insert instruction with bundle flags");
963 // Set the bundle flags when inserting inside a bundle.
964 if (I != instr_end() && I->isBundledWithPred()) {
965 MI->setFlag(MachineInstr::BundledPred);
966 MI->setFlag(MachineInstr::BundledSucc);
968 return Insts.insert(I, MI);
971 /// removeFromParent - This method unlinks 'this' from the containing function,
972 /// and returns it, but does not delete it.
973 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
974 assert(getParent() && "Not embedded in a function!");
975 getParent()->remove(this);
980 /// eraseFromParent - This method unlinks 'this' from the containing function,
982 void MachineBasicBlock::eraseFromParent() {
983 assert(getParent() && "Not embedded in a function!");
984 getParent()->erase(this);
988 /// ReplaceUsesOfBlockWith - Given a machine basic block that branched to
989 /// 'Old', change the code and CFG so that it branches to 'New' instead.
990 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
991 MachineBasicBlock *New) {
992 assert(Old != New && "Cannot replace self with self!");
994 MachineBasicBlock::instr_iterator I = instr_end();
995 while (I != instr_begin()) {
997 if (!I->isTerminator()) break;
999 // Scan the operands of this machine instruction, replacing any uses of Old
1001 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1002 if (I->getOperand(i).isMBB() &&
1003 I->getOperand(i).getMBB() == Old)
1004 I->getOperand(i).setMBB(New);
1007 // Update the successor information.
1008 replaceSuccessor(Old, New);
1011 /// CorrectExtraCFGEdges - Various pieces of code can cause excess edges in the
1012 /// CFG to be inserted. If we have proven that MBB can only branch to DestA and
1013 /// DestB, remove any other MBB successors from the CFG. DestA and DestB can be
1016 /// Besides DestA and DestB, retain other edges leading to LandingPads
1017 /// (currently there can be only one; we don't check or require that here).
1018 /// Note it is possible that DestA and/or DestB are LandingPads.
1019 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1020 MachineBasicBlock *DestB,
1022 // The values of DestA and DestB frequently come from a call to the
1023 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1024 // values from there.
1026 // 1. If both DestA and DestB are null, then the block ends with no branches
1027 // (it falls through to its successor).
1028 // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
1029 // with only an unconditional branch.
1030 // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
1031 // with a conditional branch that falls through to a successor (DestB).
1032 // 4. If DestA and DestB is set and isCond is true, then the block ends with a
1033 // conditional branch followed by an unconditional branch. DestA is the
1034 // 'true' destination and DestB is the 'false' destination.
1036 bool Changed = false;
1038 MachineFunction::iterator FallThru =
1039 std::next(MachineFunction::iterator(this));
1041 if (!DestA && !DestB) {
1042 // Block falls through to successor.
1045 } else if (DestA && !DestB) {
1047 // Block ends in conditional jump that falls through to successor.
1050 assert(DestA && DestB && isCond &&
1051 "CFG in a bad state. Cannot correct CFG edges");
1054 // Remove superfluous edges. I.e., those which aren't destinations of this
1055 // basic block, duplicate edges, or landing pads.
1056 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1057 MachineBasicBlock::succ_iterator SI = succ_begin();
1058 while (SI != succ_end()) {
1059 const MachineBasicBlock *MBB = *SI;
1060 if (!SeenMBBs.insert(MBB).second ||
1061 (MBB != DestA && MBB != DestB && !MBB->isLandingPad())) {
1062 // This is a superfluous edge, remove it.
1063 SI = removeSuccessor(SI);
1073 /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
1074 /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
1076 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1078 instr_iterator E = instr_end();
1082 // Skip debug declarations, we don't want a DebugLoc from them.
1083 while (MBBI != E && MBBI->isDebugValue())
1086 DL = MBBI->getDebugLoc();
1090 /// getSuccWeight - Return weight of the edge from this block to MBB.
1092 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1093 if (Weights.empty())
1096 return *getWeightIterator(Succ);
1099 /// Set successor weight of a given iterator.
1100 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) {
1101 if (Weights.empty())
1103 auto WeightIter = getWeightIterator(I);
1104 uint32_t OldWeight = *WeightIter;
1105 *WeightIter = weight;
1106 if (weight > OldWeight)
1107 AreSuccWeightsNormalized = false;
1110 /// Normalize all succesor weights so that the sum of them does not exceed
1111 /// UINT32_MAX. Return true if the weights are modified and false otherwise.
1112 /// Note that weights that are modified after calling this function are not
1113 /// guaranteed to be normalized.
1114 bool MachineBasicBlock::normalizeSuccWeights() {
1115 if (!AreSuccWeightsNormalized) {
1117 MachineBranchProbabilityInfo::normalizeEdgeWeights(Weights);
1118 AreSuccWeightsNormalized = true;
1124 /// getWeightIterator - Return wight iterator corresonding to the I successor
1126 MachineBasicBlock::weight_iterator MachineBasicBlock::
1127 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1128 assert(Weights.size() == Successors.size() && "Async weight list!");
1129 size_t index = std::distance(Successors.begin(), I);
1130 assert(index < Weights.size() && "Not a current successor!");
1131 return Weights.begin() + index;
1134 /// getWeightIterator - Return wight iterator corresonding to the I successor
1136 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1137 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1138 assert(Weights.size() == Successors.size() && "Async weight list!");
1139 const size_t index = std::distance(Successors.begin(), I);
1140 assert(index < Weights.size() && "Not a current successor!");
1141 return Weights.begin() + index;
1144 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1145 /// as of just before "MI".
1147 /// Search is localised to a neighborhood of
1148 /// Neighborhood instructions before (searching for defs or kills) and N
1149 /// instructions after (searching just for defs) MI.
1150 MachineBasicBlock::LivenessQueryResult
1151 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1152 unsigned Reg, const_iterator Before,
1153 unsigned Neighborhood) const {
1154 unsigned N = Neighborhood;
1156 // Start by searching backwards from Before, looking for kills, reads or defs.
1157 const_iterator I(Before);
1158 // If this is the first insn in the block, don't search backwards.
1163 MachineOperandIteratorBase::PhysRegInfo Analysis =
1164 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1166 if (Analysis.Defines)
1167 // Outputs happen after inputs so they take precedence if both are
1169 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1171 if (Analysis.Kills || Analysis.Clobbers)
1172 // Register killed, so isn't live.
1175 else if (Analysis.ReadsOverlap)
1176 // Defined or read without a previous kill - live.
1177 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1179 } while (I != begin() && --N > 0);
1182 // Did we get to the start of the block?
1184 // If so, the register's state is definitely defined by the live-in state.
1185 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1186 RAI.isValid(); ++RAI) {
1188 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1196 // Try searching forwards from Before, looking for reads or defs.
1197 I = const_iterator(Before);
1198 // If this is the last insn in the block, don't search forwards.
1200 for (++I; I != end() && N > 0; ++I, --N) {
1201 MachineOperandIteratorBase::PhysRegInfo Analysis =
1202 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1204 if (Analysis.ReadsOverlap)
1205 // Used, therefore must have been live.
1206 return (Analysis.Reads) ?
1207 LQR_Live : LQR_OverlappingLive;
1209 else if (Analysis.Clobbers || Analysis.Defines)
1210 // Defined (but not read) therefore cannot have been live.
1215 // At this point we have no idea of the liveness of the register.