1 //===-- InstrSelectionSupport.cpp -----------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Target-independent instruction selection code. See SparcInstrSelection.cpp
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/InstrSelectionSupport.h"
16 #include "llvm/CodeGen/InstrSelection.h"
17 #include "llvm/CodeGen/MachineInstrAnnot.h"
18 #include "llvm/CodeGen/MachineCodeForInstruction.h"
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetRegInfo.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Constants.h"
24 #include "llvm/BasicBlock.h"
25 #include "llvm/DerivedTypes.h"
26 #include "../../Target/Sparc/SparcInstrSelectionSupport.h" // FIXME!
29 // Generate code to load the constant into a TmpInstruction (virtual reg) and
30 // returns the virtual register.
32 static TmpInstruction*
33 InsertCodeToLoadConstant(Function *F,
36 std::vector<MachineInstr*>& loadConstVec,
37 TargetMachine& target)
39 // Create a tmp virtual register to hold the constant.
40 MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
41 TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
43 target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
46 // Record the mapping from the tmp VM instruction to machine instruction.
47 // Do this for all machine instructions that were not mapped to any
48 // other temp values created by
49 // tmpReg->addMachineInstruction(loadConstVec.back());
55 MachineOperand::MachineOperandType
56 ChooseRegOrImmed(int64_t intValue,
59 const TargetMachine& target,
61 unsigned int& getMachineRegNum,
62 int64_t& getImmedValue)
64 MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
69 target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
71 opType = isSigned? MachineOperand::MO_SignExtendedImmed
72 : MachineOperand::MO_UnextendedImmed;
73 getImmedValue = intValue;
75 else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
77 opType = MachineOperand::MO_MachineRegister;
78 getMachineRegNum = target.getRegInfo().getZeroRegNum();
85 MachineOperand::MachineOperandType
86 ChooseRegOrImmed(Value* val,
88 const TargetMachine& target,
90 unsigned int& getMachineRegNum,
91 int64_t& getImmedValue)
96 // To use reg or immed, constant needs to be integer, bool, or a NULL pointer
97 // TargetInstrInfo::ConvertConstantToIntType() does the right conversions:
100 target.getInstrInfo().ConvertConstantToIntType(target, val, val->getType(),
102 if (! isValidConstant)
103 return MachineOperand::MO_VirtualRegister;
105 // Now check if the constant value fits in the IMMED field.
107 return ChooseRegOrImmed((int64_t) valueToUse, val->getType()->isSigned(),
108 opCode, target, canUseImmed,
109 getMachineRegNum, getImmedValue);
112 //---------------------------------------------------------------------------
113 // Function: FixConstantOperandsForInstr
116 // Special handling for constant operands of a machine instruction
117 // -- if the constant is 0, use the hardwired 0 register, if any;
118 // -- if the constant fits in the IMMEDIATE field, use that field;
119 // -- else create instructions to put the constant into a register, either
120 // directly or by loading explicitly from the constant pool.
122 // In the first 2 cases, the operand of `minstr' is modified in place.
123 // Returns a vector of machine instructions generated for operands that
124 // fall under case 3; these must be inserted before `minstr'.
125 //---------------------------------------------------------------------------
127 std::vector<MachineInstr*>
128 FixConstantOperandsForInstr(Instruction* vmInstr,
129 MachineInstr* minstr,
130 TargetMachine& target)
132 std::vector<MachineInstr*> MVec;
134 MachineOpCode opCode = minstr->getOpCode();
135 const TargetInstrInfo& instrInfo = target.getInstrInfo();
136 int resultPos = instrInfo.getResultPos(opCode);
137 int immedPos = instrInfo.getImmedConstantPos(opCode);
139 Function *F = vmInstr->getParent()->getParent();
141 for (unsigned op=0; op < minstr->getNumOperands(); op++)
143 const MachineOperand& mop = minstr->getOperand(op);
145 // Skip the result position, preallocated machine registers, or operands
146 // that cannot be constants (CC regs or PC-relative displacements)
147 if (resultPos == (int)op ||
148 mop.getType() == MachineOperand::MO_MachineRegister ||
149 mop.getType() == MachineOperand::MO_CCRegister ||
150 mop.getType() == MachineOperand::MO_PCRelativeDisp)
153 bool constantThatMustBeLoaded = false;
154 unsigned int machineRegNum = 0;
155 int64_t immedValue = 0;
156 Value* opValue = NULL;
157 MachineOperand::MachineOperandType opType =
158 MachineOperand::MO_VirtualRegister;
160 // Operand may be a virtual register or a compile-time constant
161 if (mop.getType() == MachineOperand::MO_VirtualRegister)
163 assert(mop.getVRegValue() != NULL);
164 opValue = mop.getVRegValue();
165 if (Constant *opConst = dyn_cast<Constant>(opValue)) {
166 opType = ChooseRegOrImmed(opConst, opCode, target,
167 (immedPos == (int)op), machineRegNum,
169 if (opType == MachineOperand::MO_VirtualRegister)
170 constantThatMustBeLoaded = true;
175 assert(mop.isImmediate());
176 bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
178 // Bit-selection flags indicate an instruction that is extracting
179 // bits from its operand so ignore this even if it is a big constant.
180 if (mop.opHiBits32() || mop.opLoBits32() ||
181 mop.opHiBits64() || mop.opLoBits64())
184 opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
185 opCode, target, (immedPos == (int)op),
186 machineRegNum, immedValue);
188 if (opType == MachineOperand::MO_SignExtendedImmed ||
189 opType == MachineOperand::MO_UnextendedImmed) {
190 // The optype is an immediate value
191 // This means we need to change the opcode, e.g. ADDr -> ADDi
192 unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
193 minstr->setOpcode(newOpcode);
196 if (opType == mop.getType())
197 continue; // no change: this is the most common case
199 if (opType == MachineOperand::MO_VirtualRegister)
201 constantThatMustBeLoaded = true;
203 ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
204 : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
208 if (opType == MachineOperand::MO_MachineRegister)
209 minstr->SetMachineOperandReg(op, machineRegNum);
210 else if (opType == MachineOperand::MO_SignExtendedImmed ||
211 opType == MachineOperand::MO_UnextendedImmed) {
212 minstr->SetMachineOperandConst(op, opType, immedValue);
213 // The optype is or has become an immediate
214 // This means we need to change the opcode, e.g. ADDr -> ADDi
215 unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
216 minstr->setOpcode(newOpcode);
217 } else if (constantThatMustBeLoaded ||
218 (opValue && isa<GlobalValue>(opValue)))
219 { // opValue is a constant that must be explicitly loaded into a reg
221 TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
223 minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
228 // Also, check for implicit operands used by the machine instruction
229 // (no need to check those defined since they cannot be constants).
231 // -- arguments to a Call
232 // -- return value of a Return
233 // Any such operand that is a constant value needs to be fixed also.
234 // The current instructions with implicit refs (viz., Call and Return)
235 // have no immediate fields, so the constant always needs to be loaded
238 bool isCall = instrInfo.isCall(opCode);
239 unsigned lastCallArgNum = 0; // unused if not a call
240 CallArgsDescriptor* argDesc = NULL; // unused if not a call
242 argDesc = CallArgsDescriptor::get(minstr);
244 for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
245 if (isa<Constant>(minstr->getImplicitRef(i)) ||
246 isa<GlobalValue>(minstr->getImplicitRef(i)))
248 Value* oldVal = minstr->getImplicitRef(i);
249 TmpInstruction* tmpReg =
250 InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
251 minstr->setImplicitRef(i, tmpReg);
254 { // find and replace the argument in the CallArgsDescriptor
255 unsigned i=lastCallArgNum;
256 while (argDesc->getArgInfo(i).getArgVal() != oldVal)
258 assert(i < argDesc->getNumArgs() &&
259 "Constant operands to a call *must* be in the arg list");
261 argDesc->getArgInfo(i).replaceArgVal(tmpReg);