1 //===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the CriticalAntiDepBreaker class, which
11 // implements register anti-dependence breaking along a blocks
12 // critical path during post-RA scheduler.
14 //===----------------------------------------------------------------------===//
16 #include "CriticalAntiDepBreaker.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
29 #define DEBUG_TYPE "post-RA-sched"
31 CriticalAntiDepBreaker::CriticalAntiDepBreaker(MachineFunction &MFi,
32 const RegisterClassInfo &RCI)
33 : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
34 TII(MF.getTarget().getSubtargetImpl()->getInstrInfo()),
35 TRI(MF.getTarget().getSubtargetImpl()->getRegisterInfo()),
36 RegClassInfo(RCI), Classes(TRI->getNumRegs(), nullptr),
37 KillIndices(TRI->getNumRegs(), 0), DefIndices(TRI->getNumRegs(), 0),
38 KeepRegs(TRI->getNumRegs(), false) {}
40 CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
43 void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
44 const unsigned BBSize = BB->size();
45 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
46 // Clear out the register class data.
49 // Initialize the indices to indicate that no registers are live.
51 DefIndices[i] = BBSize;
54 // Clear "do not change" set.
57 bool IsReturnBlock = (BBSize != 0 && BB->back().isReturn());
59 // Examine the live-in regs of all successors.
60 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
61 SE = BB->succ_end(); SI != SE; ++SI)
62 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
63 E = (*SI)->livein_end(); I != E; ++I) {
64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
66 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
67 KillIndices[Reg] = BBSize;
68 DefIndices[Reg] = ~0u;
72 // Mark live-out callee-saved registers. In a return block this is
73 // all callee-saved registers. In non-return this is any
74 // callee-saved register that is not saved in the prolog.
75 const MachineFrameInfo *MFI = MF.getFrameInfo();
76 BitVector Pristine = MFI->getPristineRegs(BB);
77 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
78 if (!IsReturnBlock && !Pristine.test(*I)) continue;
79 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
81 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
82 KillIndices[Reg] = BBSize;
83 DefIndices[Reg] = ~0u;
88 void CriticalAntiDepBreaker::FinishBlock() {
93 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
94 unsigned InsertPosIndex) {
95 if (MI->isDebugValue())
97 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
99 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
100 if (KillIndices[Reg] != ~0u) {
101 // If Reg is currently live, then mark that it can't be renamed as
102 // we don't know the extent of its live-range anymore (now that it
103 // has been scheduled).
104 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
105 KillIndices[Reg] = Count;
106 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
107 // Any register which was defined within the previous scheduling region
108 // may have been rescheduled and its lifetime may overlap with registers
109 // in ways not reflected in our current liveness state. For each such
110 // register, adjust the liveness state to be conservatively correct.
111 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
113 // Move the def index to the end of the previous region, to reflect
114 // that the def could theoretically have been scheduled at the end.
115 DefIndices[Reg] = InsertPosIndex;
119 PrescanInstruction(MI);
120 ScanInstruction(MI, Count);
123 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
125 static const SDep *CriticalPathStep(const SUnit *SU) {
126 const SDep *Next = nullptr;
127 unsigned NextDepth = 0;
128 // Find the predecessor edge with the greatest depth.
129 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
131 const SUnit *PredSU = P->getSUnit();
132 unsigned PredLatency = P->getLatency();
133 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
134 // In the case of a latency tie, prefer an anti-dependency edge over
135 // other types of edges.
136 if (NextDepth < PredTotalLatency ||
137 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
138 NextDepth = PredTotalLatency;
145 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
146 // It's not safe to change register allocation for source operands of
147 // instructions that have special allocation requirements. Also assume all
148 // registers used in a call must not be changed (ABI).
149 // FIXME: The issue with predicated instruction is more complex. We are being
150 // conservative here because the kill markers cannot be trusted after
152 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
154 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
155 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
156 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
158 // The first R6 kill is not really a kill since it's killed by a predicated
159 // instruction which may not be executed. The second R6 def may or may not
160 // re-define R6 so it's not safe to change it since the last R6 use cannot be
162 bool Special = MI->isCall() ||
163 MI->hasExtraSrcRegAllocReq() ||
164 TII->isPredicated(MI);
166 // Scan the register operands for this instruction and update
167 // Classes and RegRefs.
168 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
169 MachineOperand &MO = MI->getOperand(i);
170 if (!MO.isReg()) continue;
171 unsigned Reg = MO.getReg();
172 if (Reg == 0) continue;
173 const TargetRegisterClass *NewRC = nullptr;
175 if (i < MI->getDesc().getNumOperands())
176 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
178 // For now, only allow the register to be changed if its register
179 // class is consistent across all uses.
180 if (!Classes[Reg] && NewRC)
181 Classes[Reg] = NewRC;
182 else if (!NewRC || Classes[Reg] != NewRC)
183 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
185 // Now check for aliases.
186 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
187 // If an alias of the reg is used during the live range, give up.
188 // Note that this allows us to skip checking if AntiDepReg
189 // overlaps with any of the aliases, among other things.
190 unsigned AliasReg = *AI;
191 if (Classes[AliasReg]) {
192 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
193 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
197 // If we're still willing to consider this register, note the reference.
198 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
199 RegRefs.insert(std::make_pair(Reg, &MO));
201 // If this reg is tied and live (Classes[Reg] is set to -1), we can't change
202 // it or any of its sub or super regs. We need to use KeepRegs to mark the
203 // reg because not all uses of the same reg within an instruction are
204 // necessarily tagged as tied.
205 // Example: an x86 "xor %eax, %eax" will have one source operand tied to the
206 // def register but not the second (see PR20020 for details).
207 // FIXME: can this check be relaxed to account for undef uses
208 // of a register? In the above 'xor' example, the uses of %eax are undef, so
209 // earlier instructions could still replace %eax even though the 'xor'
210 // itself can't be changed.
211 if (MI->isRegTiedToUseOperand(i) &&
212 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
213 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
214 SubRegs.isValid(); ++SubRegs) {
215 KeepRegs.set(*SubRegs);
217 for (MCSuperRegIterator SuperRegs(Reg, TRI);
218 SuperRegs.isValid(); ++SuperRegs) {
219 KeepRegs.set(*SuperRegs);
223 if (MO.isUse() && Special) {
224 if (!KeepRegs.test(Reg)) {
225 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
226 SubRegs.isValid(); ++SubRegs)
227 KeepRegs.set(*SubRegs);
233 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
236 // Proceeding upwards, registers that are defed but not used in this
237 // instruction are now dead.
239 if (!TII->isPredicated(MI)) {
240 // Predicated defs are modeled as read + write, i.e. similar to two
242 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
243 MachineOperand &MO = MI->getOperand(i);
246 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
247 if (MO.clobbersPhysReg(i)) {
248 DefIndices[i] = Count;
249 KillIndices[i] = ~0u;
251 Classes[i] = nullptr;
255 if (!MO.isReg()) continue;
256 unsigned Reg = MO.getReg();
257 if (Reg == 0) continue;
258 if (!MO.isDef()) continue;
260 // If we've already marked this reg as unchangeable, carry on.
261 if (KeepRegs.test(Reg)) continue;
263 // Ignore two-addr defs.
264 if (MI->isRegTiedToUseOperand(i)) continue;
266 // FIXME: we should use a SubRegIterator that includes self (as above), so
267 // we don't have to repeat all this code for the reg itself.
268 DefIndices[Reg] = Count;
269 KillIndices[Reg] = ~0u;
270 assert(((KillIndices[Reg] == ~0u) !=
271 (DefIndices[Reg] == ~0u)) &&
272 "Kill and Def maps aren't consistent for Reg!");
274 Classes[Reg] = nullptr;
276 // Repeat, for all subregs.
277 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
278 unsigned SubregReg = *SubRegs;
279 DefIndices[SubregReg] = Count;
280 KillIndices[SubregReg] = ~0u;
281 KeepRegs.reset(SubregReg);
282 Classes[SubregReg] = nullptr;
283 RegRefs.erase(SubregReg);
285 // Conservatively mark super-registers as unusable.
286 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
287 Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
290 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
291 MachineOperand &MO = MI->getOperand(i);
292 if (!MO.isReg()) continue;
293 unsigned Reg = MO.getReg();
294 if (Reg == 0) continue;
295 if (!MO.isUse()) continue;
297 const TargetRegisterClass *NewRC = nullptr;
298 if (i < MI->getDesc().getNumOperands())
299 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
301 // For now, only allow the register to be changed if its register
302 // class is consistent across all uses.
303 if (!Classes[Reg] && NewRC)
304 Classes[Reg] = NewRC;
305 else if (!NewRC || Classes[Reg] != NewRC)
306 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
308 RegRefs.insert(std::make_pair(Reg, &MO));
310 // FIXME: we should use an MCRegAliasIterator that includes self so we don't
311 // have to repeat all this code for the reg itself.
313 // It wasn't previously live but now it is, this is a kill.
314 if (KillIndices[Reg] == ~0u) {
315 KillIndices[Reg] = Count;
316 DefIndices[Reg] = ~0u;
317 assert(((KillIndices[Reg] == ~0u) !=
318 (DefIndices[Reg] == ~0u)) &&
319 "Kill and Def maps aren't consistent for Reg!");
321 // Repeat, for all aliases.
322 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
323 unsigned AliasReg = *AI;
324 if (KillIndices[AliasReg] == ~0u) {
325 KillIndices[AliasReg] = Count;
326 DefIndices[AliasReg] = ~0u;
332 // Check all machine operands that reference the antidependent register and must
333 // be replaced by NewReg. Return true if any of their parent instructions may
334 // clobber the new register.
336 // Note: AntiDepReg may be referenced by a two-address instruction such that
337 // it's use operand is tied to a def operand. We guard against the case in which
338 // the two-address instruction also defines NewReg, as may happen with
339 // pre/postincrement loads. In this case, both the use and def operands are in
340 // RegRefs because the def is inserted by PrescanInstruction and not erased
341 // during ScanInstruction. So checking for an instruction with definitions of
342 // both NewReg and AntiDepReg covers it.
344 CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
345 RegRefIter RegRefEnd,
348 for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
349 MachineOperand *RefOper = I->second;
351 // Don't allow the instruction defining AntiDepReg to earlyclobber its
352 // operands, in case they may be assigned to NewReg. In this case antidep
353 // breaking must fail, but it's too rare to bother optimizing.
354 if (RefOper->isDef() && RefOper->isEarlyClobber())
357 // Handle cases in which this instruction defines NewReg.
358 MachineInstr *MI = RefOper->getParent();
359 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
360 const MachineOperand &CheckOper = MI->getOperand(i);
362 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
365 if (!CheckOper.isReg() || !CheckOper.isDef() ||
366 CheckOper.getReg() != NewReg)
369 // Don't allow the instruction to define NewReg and AntiDepReg.
370 // When AntiDepReg is renamed it will be an illegal op.
371 if (RefOper->isDef())
374 // Don't allow an instruction using AntiDepReg to be earlyclobbered by
376 if (CheckOper.isEarlyClobber())
379 // Don't allow inline asm to define NewReg at all. Who knows what it's
381 if (MI->isInlineAsm())
388 unsigned CriticalAntiDepBreaker::
389 findSuitableFreeRegister(RegRefIter RegRefBegin,
390 RegRefIter RegRefEnd,
393 const TargetRegisterClass *RC,
394 SmallVectorImpl<unsigned> &Forbid)
396 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
397 for (unsigned i = 0; i != Order.size(); ++i) {
398 unsigned NewReg = Order[i];
399 // Don't replace a register with itself.
400 if (NewReg == AntiDepReg) continue;
401 // Don't replace a register with one that was recently used to repair
402 // an anti-dependence with this AntiDepReg, because that would
403 // re-introduce that anti-dependence.
404 if (NewReg == LastNewReg) continue;
405 // If any instructions that define AntiDepReg also define the NewReg, it's
406 // not suitable. For example, Instruction with multiple definitions can
407 // result in this condition.
408 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
409 // If NewReg is dead and NewReg's most recent def is not before
410 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
411 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
412 && "Kill and Def maps aren't consistent for AntiDepReg!");
413 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
414 && "Kill and Def maps aren't consistent for NewReg!");
415 if (KillIndices[NewReg] != ~0u ||
416 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
417 KillIndices[AntiDepReg] > DefIndices[NewReg])
419 // If NewReg overlaps any of the forbidden registers, we can't use it.
420 bool Forbidden = false;
421 for (SmallVectorImpl<unsigned>::iterator it = Forbid.begin(),
422 ite = Forbid.end(); it != ite; ++it)
423 if (TRI->regsOverlap(NewReg, *it)) {
427 if (Forbidden) continue;
431 // No registers are free and available!
435 unsigned CriticalAntiDepBreaker::
436 BreakAntiDependencies(const std::vector<SUnit>& SUnits,
437 MachineBasicBlock::iterator Begin,
438 MachineBasicBlock::iterator End,
439 unsigned InsertPosIndex,
440 DbgValueVector &DbgValues) {
441 // The code below assumes that there is at least one instruction,
442 // so just duck out immediately if the block is empty.
443 if (SUnits.empty()) return 0;
445 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
446 // This is used for updating debug information.
448 // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap
449 DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
451 // Find the node at the bottom of the critical path.
452 const SUnit *Max = nullptr;
453 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
454 const SUnit *SU = &SUnits[i];
455 MISUnitMap[SU->getInstr()] = SU;
456 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
462 DEBUG(dbgs() << "Critical path has total latency "
463 << (Max->getDepth() + Max->Latency) << "\n");
464 DEBUG(dbgs() << "Available regs:");
465 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
466 if (KillIndices[Reg] == ~0u)
467 DEBUG(dbgs() << " " << TRI->getName(Reg));
469 DEBUG(dbgs() << '\n');
473 // Track progress along the critical path through the SUnit graph as we walk
475 const SUnit *CriticalPathSU = Max;
476 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
478 // Consider this pattern:
487 // There are three anti-dependencies here, and without special care,
488 // we'd break all of them using the same register:
497 // because at each anti-dependence, B is the first register that
498 // isn't A which is free. This re-introduces anti-dependencies
499 // at all but one of the original anti-dependencies that we were
500 // trying to break. To avoid this, keep track of the most recent
501 // register that each register was replaced with, avoid
502 // using it to repair an anti-dependence on the same register.
503 // This lets us produce this:
512 // This still has an anti-dependence on B, but at least it isn't on the
513 // original critical path.
515 // TODO: If we tracked more than one register here, we could potentially
516 // fix that remaining critical edge too. This is a little more involved,
517 // because unlike the most recent register, less recent registers should
518 // still be considered, though only if no other registers are available.
519 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
521 // Attempt to break anti-dependence edges on the critical path. Walk the
522 // instructions from the bottom up, tracking information about liveness
523 // as we go to help determine which registers are available.
525 unsigned Count = InsertPosIndex - 1;
526 for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) {
527 MachineInstr *MI = --I;
528 if (MI->isDebugValue())
531 // Check if this instruction has a dependence on the critical path that
532 // is an anti-dependence that we may be able to break. If it is, set
533 // AntiDepReg to the non-zero register associated with the anti-dependence.
535 // We limit our attention to the critical path as a heuristic to avoid
536 // breaking anti-dependence edges that aren't going to significantly
537 // impact the overall schedule. There are a limited number of registers
538 // and we want to save them for the important edges.
540 // TODO: Instructions with multiple defs could have multiple
541 // anti-dependencies. The current code here only knows how to break one
542 // edge per instruction. Note that we'd have to be able to break all of
543 // the anti-dependencies in an instruction in order to be effective.
544 unsigned AntiDepReg = 0;
545 if (MI == CriticalPathMI) {
546 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
547 const SUnit *NextSU = Edge->getSUnit();
549 // Only consider anti-dependence edges.
550 if (Edge->getKind() == SDep::Anti) {
551 AntiDepReg = Edge->getReg();
552 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
553 if (!MRI.isAllocatable(AntiDepReg))
554 // Don't break anti-dependencies on non-allocatable registers.
556 else if (KeepRegs.test(AntiDepReg))
557 // Don't break anti-dependencies if a use down below requires
558 // this exact register.
561 // If the SUnit has other dependencies on the SUnit that it
562 // anti-depends on, don't bother breaking the anti-dependency
563 // since those edges would prevent such units from being
564 // scheduled past each other regardless.
566 // Also, if there are dependencies on other SUnits with the
567 // same register as the anti-dependency, don't attempt to
569 for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
570 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
571 if (P->getSUnit() == NextSU ?
572 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
573 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
579 CriticalPathSU = NextSU;
580 CriticalPathMI = CriticalPathSU->getInstr();
582 // We've reached the end of the critical path.
583 CriticalPathSU = nullptr;
584 CriticalPathMI = nullptr;
588 PrescanInstruction(MI);
590 SmallVector<unsigned, 2> ForbidRegs;
592 // If MI's defs have a special allocation requirement, don't allow
593 // any def registers to be changed. Also assume all registers
594 // defined in a call must not be changed (ABI).
595 if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI))
596 // If this instruction's defs have special allocation requirement, don't
597 // break this anti-dependency.
599 else if (AntiDepReg) {
600 // If this instruction has a use of AntiDepReg, breaking it
601 // is invalid. If the instruction defines other registers,
602 // save a list of them so that we don't pick a new register
603 // that overlaps any of them.
604 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
605 MachineOperand &MO = MI->getOperand(i);
606 if (!MO.isReg()) continue;
607 unsigned Reg = MO.getReg();
608 if (Reg == 0) continue;
609 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
613 if (MO.isDef() && Reg != AntiDepReg)
614 ForbidRegs.push_back(Reg);
618 // Determine AntiDepReg's register class, if it is live and is
619 // consistently used within a single class.
620 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg]
622 assert((AntiDepReg == 0 || RC != nullptr) &&
623 "Register should be live if it's causing an anti-dependence!");
624 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
627 // Look for a suitable register to use to break the anti-dependence.
629 // TODO: Instead of picking the first free register, consider which might
631 if (AntiDepReg != 0) {
632 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
633 std::multimap<unsigned, MachineOperand *>::iterator>
634 Range = RegRefs.equal_range(AntiDepReg);
635 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
637 LastNewReg[AntiDepReg],
639 DEBUG(dbgs() << "Breaking anti-dependence edge on "
640 << TRI->getName(AntiDepReg)
641 << " with " << RegRefs.count(AntiDepReg) << " references"
642 << " using " << TRI->getName(NewReg) << "!\n");
644 // Update the references to the old register to refer to the new
646 for (std::multimap<unsigned, MachineOperand *>::iterator
647 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
648 Q->second->setReg(NewReg);
649 // If the SU for the instruction being updated has debug information
650 // related to the anti-dependency register, make sure to update that
652 const SUnit *SU = MISUnitMap[Q->second->getParent()];
654 for (DbgValueVector::iterator DVI = DbgValues.begin(),
655 DVE = DbgValues.end(); DVI != DVE; ++DVI)
656 if (DVI->second == Q->second->getParent())
657 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
660 // We just went back in time and modified history; the
661 // liveness information for the anti-dependence reg is now
662 // inconsistent. Set the state as if it were dead.
663 Classes[NewReg] = Classes[AntiDepReg];
664 DefIndices[NewReg] = DefIndices[AntiDepReg];
665 KillIndices[NewReg] = KillIndices[AntiDepReg];
666 assert(((KillIndices[NewReg] == ~0u) !=
667 (DefIndices[NewReg] == ~0u)) &&
668 "Kill and Def maps aren't consistent for NewReg!");
670 Classes[AntiDepReg] = nullptr;
671 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
672 KillIndices[AntiDepReg] = ~0u;
673 assert(((KillIndices[AntiDepReg] == ~0u) !=
674 (DefIndices[AntiDepReg] == ~0u)) &&
675 "Kill and Def maps aren't consistent for AntiDepReg!");
677 RegRefs.erase(AntiDepReg);
678 LastNewReg[AntiDepReg] = NewReg;
683 ScanInstruction(MI, Count);