1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 // SDTCVecEltisVT - The specified operand is vector type with element type
73 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
77 // SDTCisSameNumEltsAs - The two specified operands have identical number
79 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
80 int OtherOperandNum = OtherOp;
83 //===----------------------------------------------------------------------===//
84 // Selection DAG Type Profile definitions.
86 // These use the constraints defined above to describe the type requirements of
87 // the various nodes. These are not hard coded into tblgen, allowing targets to
88 // add their own if needed.
91 // SDTypeProfile - This profile describes the type requirements of a Selection
93 class SDTypeProfile<int numresults, int numoperands,
94 list<SDTypeConstraint> constraints> {
95 int NumResults = numresults;
96 int NumOperands = numoperands;
97 list<SDTypeConstraint> Constraints = constraints;
101 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
102 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
103 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
104 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
105 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
106 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
108 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
109 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
111 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
112 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
114 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
115 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
118 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
119 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
121 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
122 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
124 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
125 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
127 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
128 SDTCisSameAs<0, 1>, SDTCisInt<0>
130 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
131 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
134 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
136 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
137 SDTCisSameAs<0, 1>, SDTCisFP<0>
139 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
140 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
142 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
143 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
145 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
146 SDTCisFP<0>, SDTCisInt<1>
148 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
149 SDTCisInt<0>, SDTCisFP<1>
151 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
152 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
153 SDTCisVTSmallerThanOp<2, 1>
156 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
157 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
160 def SDTSelect : SDTypeProfile<1, 3, [ // select
161 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
164 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
165 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
168 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
169 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
173 def SDTBr : SDTypeProfile<0, 1, [ // br
177 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc
178 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
181 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
182 SDTCisInt<0>, SDTCisVT<1, OtherVT>
185 def SDTBrind : SDTypeProfile<0, 1, [ // brind
189 def SDTCatchret : SDTypeProfile<0, 2, [ // catchret
190 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>
193 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
195 def SDTLoad : SDTypeProfile<1, 1, [ // load
199 def SDTStore : SDTypeProfile<0, 2, [ // store
203 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
204 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
207 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store
208 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>
211 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load
212 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>
215 def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather
216 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
217 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1>
220 def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter
221 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>,
222 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3>
225 def SDTVecShuffle : SDTypeProfile<1, 2, [
226 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
228 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
229 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
231 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
232 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
235 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
236 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
238 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
239 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
242 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
243 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
246 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier
247 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
250 def SDTAtomicFence : SDTypeProfile<0, 2, [
251 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
253 def SDTAtomic3 : SDTypeProfile<1, 3, [
254 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
256 def SDTAtomic2 : SDTypeProfile<1, 2, [
257 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
259 def SDTAtomicStore : SDTypeProfile<0, 2, [
260 SDTCisPtrTy<0>, SDTCisInt<1>
262 def SDTAtomicLoad : SDTypeProfile<1, 1, [
263 SDTCisInt<0>, SDTCisPtrTy<1>
266 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
267 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
270 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
271 SDTypeProfile<0, 1, constraints>;
272 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
273 SDTypeProfile<0, 2, constraints>;
275 //===----------------------------------------------------------------------===//
276 // Selection DAG Node Properties.
278 // Note: These are hard coded into tblgen.
280 class SDNodeProperty;
281 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
282 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
283 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
284 def SDNPOutGlue : SDNodeProperty; // Write a flag result
285 def SDNPInGlue : SDNodeProperty; // Read a flag operand
286 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
287 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
288 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
289 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
290 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
291 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
292 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
293 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
295 //===----------------------------------------------------------------------===//
296 // Selection DAG Pattern Operations
297 class SDPatternOperator;
299 //===----------------------------------------------------------------------===//
300 // Selection DAG Node definitions.
302 class SDNode<string opcode, SDTypeProfile typeprof,
303 list<SDNodeProperty> props = [], string sdclass = "SDNode">
304 : SDPatternOperator {
305 string Opcode = opcode;
306 string SDClass = sdclass;
307 list<SDNodeProperty> Properties = props;
308 SDTypeProfile TypeProfile = typeprof;
311 // Special TableGen-recognized dag nodes
317 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
318 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
319 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
320 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
321 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
322 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
323 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
324 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
325 "GlobalAddressSDNode">;
326 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
327 "GlobalAddressSDNode">;
328 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
329 "GlobalAddressSDNode">;
330 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
331 "GlobalAddressSDNode">;
332 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
333 "ConstantPoolSDNode">;
334 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
335 "ConstantPoolSDNode">;
336 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
338 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
340 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
342 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
344 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
345 "ExternalSymbolSDNode">;
346 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
347 "ExternalSymbolSDNode">;
348 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">;
349 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
350 "BlockAddressSDNode">;
351 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
352 "BlockAddressSDNode">;
354 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
355 [SDNPCommutative, SDNPAssociative]>;
356 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
357 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
358 [SDNPCommutative, SDNPAssociative]>;
359 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
360 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
361 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
362 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
363 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
364 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
365 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
366 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
367 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
368 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
369 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
370 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
371 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
372 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
373 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
374 def and : SDNode<"ISD::AND" , SDTIntBinOp,
375 [SDNPCommutative, SDNPAssociative]>;
376 def or : SDNode<"ISD::OR" , SDTIntBinOp,
377 [SDNPCommutative, SDNPAssociative]>;
378 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
379 [SDNPCommutative, SDNPAssociative]>;
380 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
381 [SDNPCommutative, SDNPOutGlue]>;
382 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
383 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
384 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
386 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
387 [SDNPOutGlue, SDNPInGlue]>;
388 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp>;
389 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp>;
390 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp>;
391 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;
393 def sabsdiff : SDNode<"ISD::SABSDIFF" , SDTIntBinOp>;
394 def uabsdiff : SDNode<"ISD::UABSDIFF" , SDTIntBinOp>;
395 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
396 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>;
397 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
398 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
399 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
400 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
401 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
402 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
403 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
404 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
405 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
406 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
407 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
408 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>;
409 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
410 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
412 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
413 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
414 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
415 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
416 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
417 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
418 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
419 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
420 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
421 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp>;
422 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
423 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>;
424 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
425 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
426 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
427 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
428 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
429 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
430 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
431 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
432 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
433 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
434 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
435 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
436 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
437 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
439 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
440 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
441 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
443 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
444 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
445 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
446 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
447 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
448 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
450 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
451 def select : SDNode<"ISD::SELECT" , SDTSelect>;
452 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
453 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
455 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
456 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
457 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
458 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
459 def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret,
460 [SDNPHasChain, SDNPSideEffect]>;
461 def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>;
462 def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone,
463 [SDNPHasChain, SDNPSideEffect]>;
465 def trap : SDNode<"ISD::TRAP" , SDTNone,
466 [SDNPHasChain, SDNPSideEffect]>;
467 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
468 [SDNPHasChain, SDNPSideEffect]>;
470 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
471 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
474 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
475 [SDNPHasChain, SDNPSideEffect]>;
477 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
478 [SDNPHasChain, SDNPSideEffect]>;
480 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
481 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
482 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
483 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
484 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
485 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
486 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
487 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
488 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
489 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
490 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
491 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
492 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
493 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
494 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
495 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
496 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
497 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
498 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
499 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
500 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
501 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
502 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
503 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
504 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
505 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
506 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
507 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
509 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore,
510 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
511 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
512 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
513 def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter,
514 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
515 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather,
516 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
518 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
519 // and truncst (see below).
520 def ld : SDNode<"ISD::LOAD" , SDTLoad,
521 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
522 def st : SDNode<"ISD::STORE" , SDTStore,
523 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
524 def ist : SDNode<"ISD::STORE" , SDTIStore,
525 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
527 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
528 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
529 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
531 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
532 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
533 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
534 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
535 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
536 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
538 // This operator does not do subvector type checking. The ARM
539 // backend, at least, needs it.
540 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
541 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
544 // This operator does subvector type checking.
545 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
546 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
548 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
549 // these internally. Don't reference these directly.
550 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
551 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
553 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
554 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
556 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
557 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
559 // Do not use cvt directly. Use cvt forms below
560 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
562 def SDT_assertext : SDTypeProfile<1, 1,
563 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
564 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
565 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
568 //===----------------------------------------------------------------------===//
569 // Selection DAG Condition Codes
571 class CondCode; // ISD::CondCode enums
572 def SETOEQ : CondCode; def SETOGT : CondCode;
573 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
574 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
575 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
576 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
578 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
579 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
582 //===----------------------------------------------------------------------===//
583 // Selection DAG Node Transformation Functions.
585 // This mechanism allows targets to manipulate nodes in the output DAG once a
586 // match has been formed. This is typically used to manipulate immediate
589 class SDNodeXForm<SDNode opc, code xformFunction> {
591 code XFormFunction = xformFunction;
594 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
596 //===----------------------------------------------------------------------===//
597 // PatPred Subclasses.
599 // These allow specifying different sorts of predicates that control whether a
604 class CodePatPred<code predicate> : PatPred {
605 code PredicateCode = predicate;
609 //===----------------------------------------------------------------------===//
610 // Selection DAG Pattern Fragments.
612 // Pattern fragments are reusable chunks of dags that match specific things.
613 // They can take arguments and have C++ predicates that control whether they
614 // match. They are intended to make the patterns for common instructions more
615 // compact and readable.
618 /// PatFrag - Represents a pattern fragment. This can match something on the
619 /// DAG, from a single node to multiple nested other fragments.
621 class PatFrag<dag ops, dag frag, code pred = [{}],
622 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
625 code PredicateCode = pred;
626 code ImmediateCode = [{}];
627 SDNodeXForm OperandTransform = xform;
630 // OutPatFrag is a pattern fragment that is used as part of an output pattern
631 // (not an input pattern). These do not have predicates or transforms, but are
632 // used to avoid repeated subexpressions in output patterns.
633 class OutPatFrag<dag ops, dag frag>
634 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
636 // PatLeaf's are pattern fragments that have no operands. This is just a helper
637 // to define immediates and other common things concisely.
638 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
639 : PatFrag<(ops), frag, pred, xform>;
642 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
643 // constraint is a function that is run on the immediate (always with the value
644 // sign extended out to an int64_t) as Imm. For example:
646 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
648 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
649 // is preferred over using PatLeaf because it allows the code generator to
650 // reason more about the constraint.
652 // If FastIsel should ignore all instructions that have an operand of this type,
653 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
654 // the code size of the generated fast instruction selector.
655 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
656 : PatFrag<(ops), (vt imm), [{}], xform> {
657 let ImmediateCode = pred;
658 bit FastIselShouldIgnore = 0;
664 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
665 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
667 def immAllOnesV: PatLeaf<(build_vector), [{
668 return ISD::isBuildVectorAllOnes(N);
670 def immAllZerosV: PatLeaf<(build_vector), [{
671 return ISD::isBuildVectorAllZeros(N);
676 // Other helper fragments.
677 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
678 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
679 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
681 // null_frag - The null pattern operator is used in multiclass instantiations
682 // which accept an SDPatternOperator for use in matching patterns for internal
683 // definitions. When expanding a pattern, if the null fragment is referenced
684 // in the expansion, the pattern is discarded and it is as-if '[]' had been
685 // specified. This allows multiclasses to have the isel patterns be optional.
686 def null_frag : SDPatternOperator;
689 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
690 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
692 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
693 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
696 // extending load fragments.
697 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
698 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
700 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
701 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
703 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
704 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
707 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
708 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
710 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
711 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
713 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
714 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
716 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
717 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
719 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
720 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
722 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
723 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
726 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
727 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
729 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
730 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
732 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
733 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
735 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
736 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
739 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
740 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
742 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
743 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
745 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
746 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
748 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
749 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
752 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
753 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
755 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
756 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
758 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
759 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
761 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
762 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
764 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
765 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
767 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
768 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
771 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
772 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
774 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
775 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
777 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
778 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
780 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
781 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
784 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
785 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
787 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
788 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
790 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
791 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
793 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
794 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
798 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
799 (st node:$val, node:$ptr), [{
800 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
802 def store : PatFrag<(ops node:$val, node:$ptr),
803 (unindexedstore node:$val, node:$ptr), [{
804 return !cast<StoreSDNode>(N)->isTruncatingStore();
807 // truncstore fragments.
808 def truncstore : PatFrag<(ops node:$val, node:$ptr),
809 (unindexedstore node:$val, node:$ptr), [{
810 return cast<StoreSDNode>(N)->isTruncatingStore();
812 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
813 (truncstore node:$val, node:$ptr), [{
814 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
816 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
817 (truncstore node:$val, node:$ptr), [{
818 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
820 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
821 (truncstore node:$val, node:$ptr), [{
822 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
824 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
825 (truncstore node:$val, node:$ptr), [{
826 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
828 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
829 (truncstore node:$val, node:$ptr), [{
830 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
833 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr),
834 (truncstore node:$val, node:$ptr), [{
835 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
838 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr),
839 (truncstore node:$val, node:$ptr), [{
840 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
843 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr),
844 (truncstore node:$val, node:$ptr), [{
845 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
848 // indexed store fragments.
849 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
850 (ist node:$val, node:$base, node:$offset), [{
851 return !cast<StoreSDNode>(N)->isTruncatingStore();
854 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
855 (istore node:$val, node:$base, node:$offset), [{
856 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
857 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
860 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
861 (ist node:$val, node:$base, node:$offset), [{
862 return cast<StoreSDNode>(N)->isTruncatingStore();
864 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
865 (itruncstore node:$val, node:$base, node:$offset), [{
866 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
867 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
869 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
870 (pre_truncst node:$val, node:$base, node:$offset), [{
871 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
873 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
874 (pre_truncst node:$val, node:$base, node:$offset), [{
875 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
877 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
878 (pre_truncst node:$val, node:$base, node:$offset), [{
879 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
881 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
882 (pre_truncst node:$val, node:$base, node:$offset), [{
883 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
885 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
886 (pre_truncst node:$val, node:$base, node:$offset), [{
887 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
890 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
891 (istore node:$val, node:$ptr, node:$offset), [{
892 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
893 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
896 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
897 (itruncstore node:$val, node:$base, node:$offset), [{
898 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
899 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
901 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
902 (post_truncst node:$val, node:$base, node:$offset), [{
903 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
905 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
906 (post_truncst node:$val, node:$base, node:$offset), [{
907 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
909 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
910 (post_truncst node:$val, node:$base, node:$offset), [{
911 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
913 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
914 (post_truncst node:$val, node:$base, node:$offset), [{
915 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
917 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
918 (post_truncst node:$val, node:$base, node:$offset), [{
919 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
922 // nontemporal store fragments.
923 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
924 (store node:$val, node:$ptr), [{
925 return cast<StoreSDNode>(N)->isNonTemporal();
928 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
929 (nontemporalstore node:$val, node:$ptr), [{
930 StoreSDNode *St = cast<StoreSDNode>(N);
931 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
934 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
935 (nontemporalstore node:$val, node:$ptr), [{
936 StoreSDNode *St = cast<StoreSDNode>(N);
937 return St->getAlignment() < St->getMemoryVT().getStoreSize();
940 // setcc convenience fragments.
941 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
942 (setcc node:$lhs, node:$rhs, SETOEQ)>;
943 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
944 (setcc node:$lhs, node:$rhs, SETOGT)>;
945 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
946 (setcc node:$lhs, node:$rhs, SETOGE)>;
947 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
948 (setcc node:$lhs, node:$rhs, SETOLT)>;
949 def setole : PatFrag<(ops node:$lhs, node:$rhs),
950 (setcc node:$lhs, node:$rhs, SETOLE)>;
951 def setone : PatFrag<(ops node:$lhs, node:$rhs),
952 (setcc node:$lhs, node:$rhs, SETONE)>;
953 def seto : PatFrag<(ops node:$lhs, node:$rhs),
954 (setcc node:$lhs, node:$rhs, SETO)>;
955 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
956 (setcc node:$lhs, node:$rhs, SETUO)>;
957 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
958 (setcc node:$lhs, node:$rhs, SETUEQ)>;
959 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
960 (setcc node:$lhs, node:$rhs, SETUGT)>;
961 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
962 (setcc node:$lhs, node:$rhs, SETUGE)>;
963 def setult : PatFrag<(ops node:$lhs, node:$rhs),
964 (setcc node:$lhs, node:$rhs, SETULT)>;
965 def setule : PatFrag<(ops node:$lhs, node:$rhs),
966 (setcc node:$lhs, node:$rhs, SETULE)>;
967 def setune : PatFrag<(ops node:$lhs, node:$rhs),
968 (setcc node:$lhs, node:$rhs, SETUNE)>;
969 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
970 (setcc node:$lhs, node:$rhs, SETEQ)>;
971 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
972 (setcc node:$lhs, node:$rhs, SETGT)>;
973 def setge : PatFrag<(ops node:$lhs, node:$rhs),
974 (setcc node:$lhs, node:$rhs, SETGE)>;
975 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
976 (setcc node:$lhs, node:$rhs, SETLT)>;
977 def setle : PatFrag<(ops node:$lhs, node:$rhs),
978 (setcc node:$lhs, node:$rhs, SETLE)>;
979 def setne : PatFrag<(ops node:$lhs, node:$rhs),
980 (setcc node:$lhs, node:$rhs, SETNE)>;
982 def atomic_cmp_swap_8 :
983 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
984 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
985 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
987 def atomic_cmp_swap_16 :
988 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
989 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
990 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
992 def atomic_cmp_swap_32 :
993 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
994 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
995 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
997 def atomic_cmp_swap_64 :
998 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
999 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
1000 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1003 multiclass binary_atomic_op<SDNode atomic_op> {
1004 def _8 : PatFrag<(ops node:$ptr, node:$val),
1005 (atomic_op node:$ptr, node:$val), [{
1006 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
1008 def _16 : PatFrag<(ops node:$ptr, node:$val),
1009 (atomic_op node:$ptr, node:$val), [{
1010 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
1012 def _32 : PatFrag<(ops node:$ptr, node:$val),
1013 (atomic_op node:$ptr, node:$val), [{
1014 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
1016 def _64 : PatFrag<(ops node:$ptr, node:$val),
1017 (atomic_op node:$ptr, node:$val), [{
1018 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1022 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
1023 defm atomic_swap : binary_atomic_op<atomic_swap>;
1024 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
1025 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
1026 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
1027 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
1028 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
1029 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
1030 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
1031 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
1032 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
1033 defm atomic_store : binary_atomic_op<atomic_store>;
1036 PatFrag<(ops node:$ptr),
1037 (atomic_load node:$ptr), [{
1038 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
1040 def atomic_load_16 :
1041 PatFrag<(ops node:$ptr),
1042 (atomic_load node:$ptr), [{
1043 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
1045 def atomic_load_32 :
1046 PatFrag<(ops node:$ptr),
1047 (atomic_load node:$ptr), [{
1048 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
1050 def atomic_load_64 :
1051 PatFrag<(ops node:$ptr),
1052 (atomic_load node:$ptr), [{
1053 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1056 //===----------------------------------------------------------------------===//
1057 // Selection DAG CONVERT_RNDSAT patterns
1059 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1060 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1061 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
1064 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1065 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1066 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
1069 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1070 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1071 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
1074 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1075 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1076 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
1079 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1080 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1081 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
1084 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1085 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1086 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
1089 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1090 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1091 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
1094 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1095 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1096 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
1099 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1100 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1101 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
1104 //===----------------------------------------------------------------------===//
1105 // Selection DAG Pattern Support.
1107 // Patterns are what are actually matched against by the target-flavored
1108 // instruction selection DAG. Instructions defined by the target implicitly
1109 // define patterns in most cases, but patterns can also be explicitly added when
1110 // an operation is defined by a sequence of instructions (e.g. loading a large
1111 // immediate value on RISC targets that do not support immediates as large as
1115 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1116 dag PatternToMatch = patternToMatch;
1117 list<dag> ResultInstrs = resultInstrs;
1118 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1119 int AddedComplexity = 0; // See class Instruction in Target.td.
1122 // Pat - A simple (but common) form of a pattern, which produces a simple result
1123 // not needing a full list.
1124 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1126 //===----------------------------------------------------------------------===//
1127 // Complex pattern definitions.
1130 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1131 // in C++. NumOperands is the number of operands returned by the select function;
1132 // SelectFunc is the name of the function used to pattern match the max. pattern;
1133 // RootNodes are the list of possible root nodes of the sub-dags to match.
1134 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1136 class ComplexPattern<ValueType ty, int numops, string fn,
1137 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
1139 int NumOperands = numops;
1140 string SelectFunc = fn;
1141 list<SDNode> RootNodes = roots;
1142 list<SDNodeProperty> Properties = props;