1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/IRBuilder.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
58 template<typename T> class SmallVectorImpl;
60 class TargetRegisterClass;
61 class TargetLibraryInfo;
62 class TargetLoweringObjectFile;
67 None, // No preference
68 Source, // Follow source order.
69 RegPressure, // Scheduling for lowest register pressure.
70 Hybrid, // Scheduling for both latency and register pressure.
71 ILP, // Scheduling for ILP in low register pressure mode.
72 VLIW // Scheduling for VLIW targets.
76 /// This base class for TargetLowering contains the SelectionDAG-independent
77 /// parts that can be used from the rest of CodeGen.
78 class TargetLoweringBase {
79 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
80 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
83 /// This enum indicates whether operations are valid for a target, and if not,
84 /// what action should be used to make them valid.
86 Legal, // The target natively supports this operation.
87 Promote, // This operation should be executed in a larger type.
88 Expand, // Try to expand this to other ops, otherwise use a libcall.
89 Custom // Use the LowerOperation hook to implement custom lowering.
92 /// This enum indicates whether a types are legal for a target, and if not,
93 /// what action should be used to make them valid.
94 enum LegalizeTypeAction {
95 TypeLegal, // The target natively supports this type.
96 TypePromoteInteger, // Replace this integer with a larger one.
97 TypeExpandInteger, // Split this integer into two of half the size.
98 TypeSoftenFloat, // Convert this float to a same size integer type.
99 TypeExpandFloat, // Split this float into two of half the size.
100 TypeScalarizeVector, // Replace this one-element vector with its element.
101 TypeSplitVector, // Split this vector into two of half the size.
102 TypeWidenVector // This vector should be widened into a larger vector.
105 /// LegalizeKind holds the legalization kind that needs to happen to EVT
106 /// in order to type-legalize it.
107 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
109 /// Enum that describes how the target represents true/false values.
110 enum BooleanContent {
111 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
112 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
113 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
116 /// Enum that describes what type of support for selects the target has.
117 enum SelectSupportKind {
118 ScalarValSelect, // The target supports scalar selects (ex: cmov).
119 ScalarCondVectorVal, // The target supports selects with a scalar condition
120 // and vector values (ex: cmov).
121 VectorMaskSelect // The target supports vector selects with a vector
122 // mask (ex: x86 blends).
125 static ISD::NodeType getExtendForContent(BooleanContent Content) {
127 case UndefinedBooleanContent:
128 // Extend by adding rubbish bits.
129 return ISD::ANY_EXTEND;
130 case ZeroOrOneBooleanContent:
131 // Extend by adding zero bits.
132 return ISD::ZERO_EXTEND;
133 case ZeroOrNegativeOneBooleanContent:
134 // Extend by copying the sign bit.
135 return ISD::SIGN_EXTEND;
137 llvm_unreachable("Invalid content kind");
140 /// NOTE: The constructor takes ownership of TLOF.
141 explicit TargetLoweringBase(const TargetMachine &TM,
142 const TargetLoweringObjectFile *TLOF);
143 virtual ~TargetLoweringBase();
146 /// \brief Initialize all of the actions to default values.
150 const TargetMachine &getTargetMachine() const { return TM; }
151 const DataLayout *getDataLayout() const { return DL; }
152 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
154 bool isBigEndian() const { return !IsLittleEndian; }
155 bool isLittleEndian() const { return IsLittleEndian; }
157 /// Return the pointer type for the given address space, defaults to
158 /// the pointer type from the data layout.
159 /// FIXME: The default needs to be removed once all the code is updated.
160 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
161 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
162 unsigned getPointerTypeSizeInBits(Type *Ty) const;
163 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
165 EVT getShiftAmountTy(EVT LHSTy) const;
167 /// Returns the type to be used for the index operand of:
168 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
169 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
170 virtual MVT getVectorIdxTy() const {
171 return getPointerTy();
174 /// Return true if the select operation is expensive for this target.
175 bool isSelectExpensive() const { return SelectIsExpensive; }
177 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
181 /// Return true if multiple condition registers are available.
182 bool hasMultipleConditionRegisters() const {
183 return HasMultipleConditionRegisters;
186 /// Return true if the target has BitExtract instructions.
187 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
189 /// Return the preferred vector type legalization action.
190 virtual TargetLoweringBase::LegalizeTypeAction
191 getPreferredVectorAction(EVT VT) const {
192 // The default action for one element vectors is to scalarize
193 if (VT.getVectorNumElements() == 1)
194 return TypeScalarizeVector;
195 // The default action for other vectors is to promote
196 return TypePromoteInteger;
199 // There are two general methods for expanding a BUILD_VECTOR node:
200 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
202 // 2. Build the vector on the stack and then load it.
203 // If this function returns true, then method (1) will be used, subject to
204 // the constraint that all of the necessary shuffles are legal (as determined
205 // by isShuffleMaskLegal). If this function returns false, then method (2) is
206 // always used. The vector type, and the number of defined values, are
209 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
210 unsigned DefinedValues) const {
211 return DefinedValues < 3;
214 /// Return true if integer divide is usually cheaper than a sequence of
215 /// several shifts, adds, and multiplies for this target.
216 bool isIntDivCheap() const { return IntDivIsCheap; }
218 /// Returns true if target has indicated at least one type should be bypassed.
219 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
221 /// Returns map of slow types for division or remainder with corresponding
223 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
224 return BypassSlowDivWidths;
227 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
228 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
230 /// Return true if Flow Control is an expensive operation that should be
232 bool isJumpExpensive() const { return JumpIsExpensive; }
234 /// Return true if selects are only cheaper than branches if the branch is
235 /// unlikely to be predicted right.
236 bool isPredictableSelectExpensive() const {
237 return PredictableSelectIsExpensive;
240 /// isLoadBitCastBeneficial() - Return true if the following transform
242 /// fold (conv (load x)) -> (load (conv*)x)
243 /// On architectures that don't natively support some vector loads efficiently,
244 /// casting the load to a smaller vector of larger types and loading
245 /// is more efficient, however, this can be undone by optimizations in
247 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
251 /// \brief Return if the target supports combining a
254 /// %andResult = and %val1, #imm-with-one-bit-set;
255 /// %icmpResult = icmp %andResult, 0
256 /// br i1 %icmpResult, label %dest1, label %dest2
258 /// into a single machine instruction of a form like:
260 /// brOnBitSet %register, #bitNumber, dest
262 bool isMaskAndBranchFoldingLegal() const {
263 return MaskAndBranchFoldingIsLegal;
266 /// Return true if the target can combine store(extractelement VectorTy,
268 /// \p Cost[out] gives the cost of that transformation when this is true.
269 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
270 unsigned &Cost) const {
274 /// Return true if target supports floating point exceptions.
275 bool hasFloatingPointExceptions() const {
276 return HasFloatingPointExceptions;
279 /// Return true if target always beneficiates from combining into FMA for a
280 /// given value type. This must typically return false on targets where FMA
281 /// takes more cycles to execute than FADD.
282 virtual bool enableAggressiveFMAFusion(EVT VT) const {
286 /// Return the ValueType of the result of SETCC operations.
287 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
289 /// Return the ValueType for comparison libcalls. Comparions libcalls include
290 /// floating point comparion calls, and Ordered/Unordered check calls on
291 /// floating point numbers.
293 MVT::SimpleValueType getCmpLibcallReturnType() const;
295 /// For targets without i1 registers, this gives the nature of the high-bits
296 /// of boolean values held in types wider than i1.
298 /// "Boolean values" are special true/false values produced by nodes like
299 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
300 /// Not to be confused with general values promoted from i1. Some cpus
301 /// distinguish between vectors of boolean and scalars; the isVec parameter
302 /// selects between the two kinds. For example on X86 a scalar boolean should
303 /// be zero extended from i1, while the elements of a vector of booleans
304 /// should be sign extended from i1.
306 /// Some cpus also treat floating point types the same way as they treat
307 /// vectors instead of the way they treat scalars.
308 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
310 return BooleanVectorContents;
311 return isFloat ? BooleanFloatContents : BooleanContents;
314 BooleanContent getBooleanContents(EVT Type) const {
315 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
318 /// Return target scheduling preference.
319 Sched::Preference getSchedulingPreference() const {
320 return SchedPreferenceInfo;
323 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
324 /// for different nodes. This function returns the preference (or none) for
326 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
330 /// Return the register class that should be used for the specified value
332 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
333 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
334 assert(RC && "This value type is not natively supported!");
338 /// Return the 'representative' register class for the specified value
341 /// The 'representative' register class is the largest legal super-reg
342 /// register class for the register class of the value type. For example, on
343 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
344 /// register class is GR64 on x86_64.
345 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
346 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
350 /// Return the cost of the 'representative' register class for the specified
352 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
353 return RepRegClassCostForVT[VT.SimpleTy];
356 /// Return true if the target has native support for the specified value type.
357 /// This means that it has a register that directly holds it without
358 /// promotions or expansions.
359 bool isTypeLegal(EVT VT) const {
360 assert(!VT.isSimple() ||
361 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
362 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
365 class ValueTypeActionImpl {
366 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
367 /// that indicates how instruction selection should deal with the type.
368 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
371 ValueTypeActionImpl() {
372 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
375 LegalizeTypeAction getTypeAction(MVT VT) const {
376 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
379 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
380 unsigned I = VT.SimpleTy;
381 ValueTypeActions[I] = Action;
385 const ValueTypeActionImpl &getValueTypeActions() const {
386 return ValueTypeActions;
389 /// Return how we should legalize values of this type, either it is already
390 /// legal (return 'Legal') or we need to promote it to a larger type (return
391 /// 'Promote'), or we need to expand it into multiple registers of smaller
392 /// integer type (return 'Expand'). 'Custom' is not an option.
393 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
394 return getTypeConversion(Context, VT).first;
396 LegalizeTypeAction getTypeAction(MVT VT) const {
397 return ValueTypeActions.getTypeAction(VT);
400 /// For types supported by the target, this is an identity function. For
401 /// types that must be promoted to larger types, this returns the larger type
402 /// to promote to. For integer types that are larger than the largest integer
403 /// register, this contains one step in the expansion to get to the smaller
404 /// register. For illegal floating point types, this returns the integer type
406 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
407 return getTypeConversion(Context, VT).second;
410 /// For types supported by the target, this is an identity function. For
411 /// types that must be expanded (i.e. integer types that are larger than the
412 /// largest integer register or illegal floating point types), this returns
413 /// the largest legal type it will be expanded to.
414 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
415 assert(!VT.isVector());
417 switch (getTypeAction(Context, VT)) {
420 case TypeExpandInteger:
421 VT = getTypeToTransformTo(Context, VT);
424 llvm_unreachable("Type is not legal nor is it to be expanded!");
429 /// Vector types are broken down into some number of legal first class types.
430 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
431 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
432 /// turns into 4 EVT::i32 values with both PPC and X86.
434 /// This method returns the number of registers needed, and the VT for each
435 /// register. It also returns the VT and quantity of the intermediate values
436 /// before they are promoted/expanded.
437 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
439 unsigned &NumIntermediates,
440 MVT &RegisterVT) const;
442 struct IntrinsicInfo {
443 unsigned opc; // target opcode
444 EVT memVT; // memory VT
445 const Value* ptrVal; // value representing memory location
446 int offset; // offset off of ptrVal
447 unsigned size; // the size of the memory location
448 // (taken from memVT if zero)
449 unsigned align; // alignment
450 bool vol; // is volatile?
451 bool readMem; // reads memory?
452 bool writeMem; // writes memory?
454 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
455 vol(false), readMem(false), writeMem(false) {}
458 /// Given an intrinsic, checks if on the target the intrinsic will need to map
459 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
460 /// true and store the intrinsic information into the IntrinsicInfo that was
461 /// passed to the function.
462 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
463 unsigned /*Intrinsic*/) const {
467 /// Returns true if the target can instruction select the specified FP
468 /// immediate natively. If false, the legalizer will materialize the FP
469 /// immediate as a load from a constant pool.
470 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
474 /// Targets can use this to indicate that they only support *some*
475 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
476 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
478 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
483 /// Returns true if the operation can trap for the value type.
485 /// VT must be a legal type. By default, we optimistically assume most
486 /// operations don't trap except for divide and remainder.
487 virtual bool canOpTrap(unsigned Op, EVT VT) const;
489 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
490 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
491 /// a VAND with a constant pool entry.
492 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
497 /// Return how this operation should be treated: either it is legal, needs to
498 /// be promoted to a larger size, needs to be expanded to some other code
499 /// sequence, or the target has a custom expander for it.
500 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
501 if (VT.isExtended()) return Expand;
502 // If a target-specific SDNode requires legalization, require the target
503 // to provide custom legalization for it.
504 if (Op > array_lengthof(OpActions[0])) return Custom;
505 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
506 return (LegalizeAction)OpActions[I][Op];
509 /// Return true if the specified operation is legal on this target or can be
510 /// made legal with custom lowering. This is used to help guide high-level
511 /// lowering decisions.
512 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
513 return (VT == MVT::Other || isTypeLegal(VT)) &&
514 (getOperationAction(Op, VT) == Legal ||
515 getOperationAction(Op, VT) == Custom);
518 /// Return true if the specified operation is legal on this target or can be
519 /// made legal using promotion. This is used to help guide high-level lowering
521 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
522 return (VT == MVT::Other || isTypeLegal(VT)) &&
523 (getOperationAction(Op, VT) == Legal ||
524 getOperationAction(Op, VT) == Promote);
527 /// Return true if the specified operation is illegal on this target or
528 /// unlikely to be made legal with custom lowering. This is used to help guide
529 /// high-level lowering decisions.
530 bool isOperationExpand(unsigned Op, EVT VT) const {
531 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
534 /// Return true if the specified operation is legal on this target.
535 bool isOperationLegal(unsigned Op, EVT VT) const {
536 return (VT == MVT::Other || isTypeLegal(VT)) &&
537 getOperationAction(Op, VT) == Legal;
540 /// Return how this load with extension should be treated: either it is legal,
541 /// needs to be promoted to a larger size, needs to be expanded to some other
542 /// code sequence, or the target has a custom expander for it.
543 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
544 if (VT.isExtended()) return Expand;
545 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
546 assert(ExtType < ISD::LAST_LOADEXT_TYPE && I < MVT::LAST_VALUETYPE &&
547 "Table isn't big enough!");
548 return (LegalizeAction)LoadExtActions[I][ExtType];
551 /// Return true if the specified load with extension is legal on this target.
552 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
553 return VT.isSimple() &&
554 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
557 /// Return how this store with truncation should be treated: either it is
558 /// legal, needs to be promoted to a larger size, needs to be expanded to some
559 /// other code sequence, or the target has a custom expander for it.
560 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
561 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
562 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
563 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
564 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
565 "Table isn't big enough!");
566 return (LegalizeAction)TruncStoreActions[ValI][MemI];
569 /// Return true if the specified store with truncation is legal on this
571 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
572 return isTypeLegal(ValVT) && MemVT.isSimple() &&
573 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
576 /// Return how the indexed load should be treated: either it is legal, needs
577 /// to be promoted to a larger size, needs to be expanded to some other code
578 /// sequence, or the target has a custom expander for it.
580 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
581 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
582 "Table isn't big enough!");
583 unsigned Ty = (unsigned)VT.SimpleTy;
584 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
587 /// Return true if the specified indexed load is legal on this target.
588 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
589 return VT.isSimple() &&
590 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
591 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
594 /// Return how the indexed store should be treated: either it is legal, needs
595 /// to be promoted to a larger size, needs to be expanded to some other code
596 /// sequence, or the target has a custom expander for it.
598 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
599 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
600 "Table isn't big enough!");
601 unsigned Ty = (unsigned)VT.SimpleTy;
602 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
605 /// Return true if the specified indexed load is legal on this target.
606 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
607 return VT.isSimple() &&
608 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
609 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
612 /// Return how the condition code should be treated: either it is legal, needs
613 /// to be expanded to some other code sequence, or the target has a custom
616 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
617 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
618 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
619 "Table isn't big enough!");
620 // See setCondCodeAction for how this is encoded.
621 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
622 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
623 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
624 assert(Action != Promote && "Can't promote condition code!");
628 /// Return true if the specified condition code is legal on this target.
629 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
631 getCondCodeAction(CC, VT) == Legal ||
632 getCondCodeAction(CC, VT) == Custom;
636 /// If the action for this operation is to promote, this method returns the
637 /// ValueType to promote to.
638 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
639 assert(getOperationAction(Op, VT) == Promote &&
640 "This operation isn't promoted!");
642 // See if this has an explicit type specified.
643 std::map<std::pair<unsigned, MVT::SimpleValueType>,
644 MVT::SimpleValueType>::const_iterator PTTI =
645 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
646 if (PTTI != PromoteToType.end()) return PTTI->second;
648 assert((VT.isInteger() || VT.isFloatingPoint()) &&
649 "Cannot autopromote this type, add it with AddPromotedToType.");
653 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
654 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
655 "Didn't find type to promote to!");
656 } while (!isTypeLegal(NVT) ||
657 getOperationAction(Op, NVT) == Promote);
661 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
662 /// operations except for the pointer size. If AllowUnknown is true, this
663 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
664 /// otherwise it will assert.
665 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
666 // Lower scalar pointers to native pointer types.
667 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
668 return getPointerTy(PTy->getAddressSpace());
670 if (Ty->isVectorTy()) {
671 VectorType *VTy = cast<VectorType>(Ty);
672 Type *Elm = VTy->getElementType();
673 // Lower vectors of pointers to native pointer types.
674 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
675 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
676 Elm = PointerTy.getTypeForEVT(Ty->getContext());
679 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
680 VTy->getNumElements());
682 return EVT::getEVT(Ty, AllowUnknown);
685 /// Return the MVT corresponding to this LLVM type. See getValueType.
686 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
687 return getValueType(Ty, AllowUnknown).getSimpleVT();
690 /// Return the desired alignment for ByVal or InAlloca aggregate function
691 /// arguments in the caller parameter area. This is the actual alignment, not
693 virtual unsigned getByValTypeAlignment(Type *Ty) const;
695 /// Return the type of registers that this ValueType will eventually require.
696 MVT getRegisterType(MVT VT) const {
697 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
698 return RegisterTypeForVT[VT.SimpleTy];
701 /// Return the type of registers that this ValueType will eventually require.
702 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
704 assert((unsigned)VT.getSimpleVT().SimpleTy <
705 array_lengthof(RegisterTypeForVT));
706 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
711 unsigned NumIntermediates;
712 (void)getVectorTypeBreakdown(Context, VT, VT1,
713 NumIntermediates, RegisterVT);
716 if (VT.isInteger()) {
717 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
719 llvm_unreachable("Unsupported extended type!");
722 /// Return the number of registers that this ValueType will eventually
725 /// This is one for any types promoted to live in larger registers, but may be
726 /// more than one for types (like i64) that are split into pieces. For types
727 /// like i140, which are first promoted then expanded, it is the number of
728 /// registers needed to hold all the bits of the original type. For an i140
729 /// on a 32 bit machine this means 5 registers.
730 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
732 assert((unsigned)VT.getSimpleVT().SimpleTy <
733 array_lengthof(NumRegistersForVT));
734 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
739 unsigned NumIntermediates;
740 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
742 if (VT.isInteger()) {
743 unsigned BitWidth = VT.getSizeInBits();
744 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
745 return (BitWidth + RegWidth - 1) / RegWidth;
747 llvm_unreachable("Unsupported extended type!");
750 /// If true, then instruction selection should seek to shrink the FP constant
751 /// of the specified type to a smaller type in order to save space and / or
753 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
755 /// When splitting a value of the specified type into parts, does the Lo
756 /// or Hi part come first? This usually follows the endianness, except
757 /// for ppcf128, where the Hi part always comes first.
758 bool hasBigEndianPartOrdering(EVT VT) const {
759 return isBigEndian() || VT == MVT::ppcf128;
762 /// If true, the target has custom DAG combine transformations that it can
763 /// perform for the specified node.
764 bool hasTargetDAGCombine(ISD::NodeType NT) const {
765 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
766 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
769 /// \brief Get maximum # of store operations permitted for llvm.memset
771 /// This function returns the maximum number of store operations permitted
772 /// to replace a call to llvm.memset. The value is set by the target at the
773 /// performance threshold for such a replacement. If OptSize is true,
774 /// return the limit for functions that have OptSize attribute.
775 unsigned getMaxStoresPerMemset(bool OptSize) const {
776 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
779 /// \brief Get maximum # of store operations permitted for llvm.memcpy
781 /// This function returns the maximum number of store operations permitted
782 /// to replace a call to llvm.memcpy. The value is set by the target at the
783 /// performance threshold for such a replacement. If OptSize is true,
784 /// return the limit for functions that have OptSize attribute.
785 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
786 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
789 /// \brief Get maximum # of store operations permitted for llvm.memmove
791 /// This function returns the maximum number of store operations permitted
792 /// to replace a call to llvm.memmove. The value is set by the target at the
793 /// performance threshold for such a replacement. If OptSize is true,
794 /// return the limit for functions that have OptSize attribute.
795 unsigned getMaxStoresPerMemmove(bool OptSize) const {
796 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
799 /// \brief Determine if the target supports unaligned memory accesses.
801 /// This function returns true if the target allows unaligned memory accesses
802 /// of the specified type in the given address space. If true, it also returns
803 /// whether the unaligned memory access is "fast" in the last argument by
804 /// reference. This is used, for example, in situations where an array
805 /// copy/move/set is converted to a sequence of store operations. Its use
806 /// helps to ensure that such replacements don't generate code that causes an
807 /// alignment error (trap) on the target machine.
808 virtual bool allowsMisalignedMemoryAccesses(EVT,
809 unsigned AddrSpace = 0,
811 bool * /*Fast*/ = nullptr) const {
815 /// Returns the target specific optimal type for load and store operations as
816 /// a result of memset, memcpy, and memmove lowering.
818 /// If DstAlign is zero that means it's safe to destination alignment can
819 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
820 /// a need to check it against alignment requirement, probably because the
821 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
822 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
823 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
824 /// does not need to be loaded. It returns EVT::Other if the type should be
825 /// determined using generic target-independent logic.
826 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
827 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
830 bool /*MemcpyStrSrc*/,
831 MachineFunction &/*MF*/) const {
835 /// Returns true if it's safe to use load / store of the specified type to
836 /// expand memcpy / memset inline.
838 /// This is mostly true for all types except for some special cases. For
839 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
840 /// fstpl which also does type conversion. Note the specified type doesn't
841 /// have to be legal as the hook is used before type legalization.
842 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
844 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
845 bool usesUnderscoreSetJmp() const {
846 return UseUnderscoreSetJmp;
849 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
850 bool usesUnderscoreLongJmp() const {
851 return UseUnderscoreLongJmp;
854 /// Return integer threshold on number of blocks to use jump tables rather
855 /// than if sequence.
856 int getMinimumJumpTableEntries() const {
857 return MinimumJumpTableEntries;
860 /// If a physical register, this specifies the register that
861 /// llvm.savestack/llvm.restorestack should save and restore.
862 unsigned getStackPointerRegisterToSaveRestore() const {
863 return StackPointerRegisterToSaveRestore;
866 /// If a physical register, this returns the register that receives the
867 /// exception address on entry to a landing pad.
868 unsigned getExceptionPointerRegister() const {
869 return ExceptionPointerRegister;
872 /// If a physical register, this returns the register that receives the
873 /// exception typeid on entry to a landing pad.
874 unsigned getExceptionSelectorRegister() const {
875 return ExceptionSelectorRegister;
878 /// Returns the target's jmp_buf size in bytes (if never set, the default is
880 unsigned getJumpBufSize() const {
884 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
886 unsigned getJumpBufAlignment() const {
887 return JumpBufAlignment;
890 /// Return the minimum stack alignment of an argument.
891 unsigned getMinStackArgumentAlignment() const {
892 return MinStackArgumentAlignment;
895 /// Return the minimum function alignment.
896 unsigned getMinFunctionAlignment() const {
897 return MinFunctionAlignment;
900 /// Return the preferred function alignment.
901 unsigned getPrefFunctionAlignment() const {
902 return PrefFunctionAlignment;
905 /// Return the preferred loop alignment.
906 unsigned getPrefLoopAlignment() const {
907 return PrefLoopAlignment;
910 /// Return whether the DAG builder should automatically insert fences and
911 /// reduce ordering for atomics.
912 bool getInsertFencesForAtomic() const {
913 return InsertFencesForAtomic;
916 /// Return true if the target stores stack protector cookies at a fixed offset
917 /// in some non-standard address space, and populates the address space and
918 /// offset as appropriate.
919 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
920 unsigned &/*Offset*/) const {
924 /// Returns the maximal possible offset which can be used for loads / stores
926 virtual unsigned getMaximalGlobalOffset() const {
930 /// Returns true if a cast between SrcAS and DestAS is a noop.
931 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
935 //===--------------------------------------------------------------------===//
936 /// \name Helpers for TargetTransformInfo implementations
939 /// Get the ISD node that corresponds to the Instruction class opcode.
940 int InstructionOpcodeToISD(unsigned Opcode) const;
942 /// Estimate the cost of type-legalization and the legalized type.
943 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
947 //===--------------------------------------------------------------------===//
948 /// \name Helpers for atomic expansion.
951 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
952 /// and expand AtomicCmpXchgInst.
953 virtual bool hasLoadLinkedStoreConditional() const { return false; }
955 /// Perform a load-linked operation on Addr, returning a "Value *" with the
956 /// corresponding pointee type. This may entail some non-trivial operations to
957 /// truncate or reconstruct types that will be illegal in the backend. See
958 /// ARMISelLowering for an example implementation.
959 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
960 AtomicOrdering Ord) const {
961 llvm_unreachable("Load linked unimplemented on this target");
964 /// Perform a store-conditional operation to Addr. Return the status of the
965 /// store. This should be 0 if the store succeeded, non-zero otherwise.
966 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
967 Value *Addr, AtomicOrdering Ord) const {
968 llvm_unreachable("Store conditional unimplemented on this target");
971 /// Inserts in the IR a target-specific intrinsic specifying a fence.
972 /// It is called by AtomicExpandPass before expanding an
973 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
974 /// RMW and CmpXchg set both IsStore and IsLoad to true.
975 /// This function should either return a nullptr, or a pointer to an IR-level
976 /// Instruction*. Even complex fence sequences can be represented by a
977 /// single Instruction* through an intrinsic to be lowered later.
978 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
979 /// Backends should override this method to produce target-specific intrinsic
980 /// for their fences.
981 /// FIXME: Please note that the default implementation here in terms of
982 /// IR-level fences exists for historical/compatibility reasons and is
983 /// *unsound* ! Fences cannot, in general, be used to restore sequential
984 /// consistency. For example, consider the following example:
985 /// atomic<int> x = y = 0;
986 /// int r1, r2, r3, r4;
997 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
998 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
999 /// IR-level fences can prevent it.
1001 virtual Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1002 bool IsStore, bool IsLoad) const {
1003 if (!getInsertFencesForAtomic())
1006 if (isAtLeastRelease(Ord) && IsStore)
1007 return Builder.CreateFence(Ord);
1012 virtual Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1013 bool IsStore, bool IsLoad) const {
1014 if (!getInsertFencesForAtomic())
1017 if (isAtLeastAcquire(Ord))
1018 return Builder.CreateFence(Ord);
1024 /// Returns true if the given (atomic) store should be expanded by the
1025 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1026 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1030 /// Returns true if the given (atomic) load should be expanded by the
1031 /// IR-level AtomicExpand pass into a load-linked instruction
1032 /// (through emitLoadLinked()).
1033 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1035 /// Returns true if the given AtomicRMW should be expanded by the
1036 /// IR-level AtomicExpand pass into a loop using LoadLinked/StoreConditional.
1037 virtual bool shouldExpandAtomicRMWInIR(AtomicRMWInst *RMWI) const {
1041 /// On some platforms, an AtomicRMW that never actually modifies the value
1042 /// (such as fetch_add of 0) can be turned into a fence followed by an
1043 /// atomic load. This may sound useless, but it makes it possible for the
1044 /// processor to keep the cacheline shared, dramatically improving
1045 /// performance. And such idempotent RMWs are useful for implementing some
1046 /// kinds of locks, see for example (justification + benchmarks):
1047 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1048 /// This method tries doing that transformation, returning the atomic load if
1049 /// it succeeds, and nullptr otherwise.
1050 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1051 /// another round of expansion.
1052 virtual LoadInst *lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1055 //===--------------------------------------------------------------------===//
1056 // TargetLowering Configuration Methods - These methods should be invoked by
1057 // the derived class constructor to configure this object for the target.
1060 /// \brief Reset the operation actions based on target options.
1061 virtual void resetOperationActions() {}
1064 /// Specify how the target extends the result of integer and floating point
1065 /// boolean values from i1 to a wider type. See getBooleanContents.
1066 void setBooleanContents(BooleanContent Ty) {
1067 BooleanContents = Ty;
1068 BooleanFloatContents = Ty;
1071 /// Specify how the target extends the result of integer and floating point
1072 /// boolean values from i1 to a wider type. See getBooleanContents.
1073 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1074 BooleanContents = IntTy;
1075 BooleanFloatContents = FloatTy;
1078 /// Specify how the target extends the result of a vector boolean value from a
1079 /// vector of i1 to a wider type. See getBooleanContents.
1080 void setBooleanVectorContents(BooleanContent Ty) {
1081 BooleanVectorContents = Ty;
1084 /// Specify the target scheduling preference.
1085 void setSchedulingPreference(Sched::Preference Pref) {
1086 SchedPreferenceInfo = Pref;
1089 /// Indicate whether this target prefers to use _setjmp to implement
1090 /// llvm.setjmp or the version without _. Defaults to false.
1091 void setUseUnderscoreSetJmp(bool Val) {
1092 UseUnderscoreSetJmp = Val;
1095 /// Indicate whether this target prefers to use _longjmp to implement
1096 /// llvm.longjmp or the version without _. Defaults to false.
1097 void setUseUnderscoreLongJmp(bool Val) {
1098 UseUnderscoreLongJmp = Val;
1101 /// Indicate the number of blocks to generate jump tables rather than if
1103 void setMinimumJumpTableEntries(int Val) {
1104 MinimumJumpTableEntries = Val;
1107 /// If set to a physical register, this specifies the register that
1108 /// llvm.savestack/llvm.restorestack should save and restore.
1109 void setStackPointerRegisterToSaveRestore(unsigned R) {
1110 StackPointerRegisterToSaveRestore = R;
1113 /// If set to a physical register, this sets the register that receives the
1114 /// exception address on entry to a landing pad.
1115 void setExceptionPointerRegister(unsigned R) {
1116 ExceptionPointerRegister = R;
1119 /// If set to a physical register, this sets the register that receives the
1120 /// exception typeid on entry to a landing pad.
1121 void setExceptionSelectorRegister(unsigned R) {
1122 ExceptionSelectorRegister = R;
1125 /// Tells the code generator not to expand operations into sequences that use
1126 /// the select operations if possible.
1127 void setSelectIsExpensive(bool isExpensive = true) {
1128 SelectIsExpensive = isExpensive;
1131 /// Tells the code generator that the target has multiple (allocatable)
1132 /// condition registers that can be used to store the results of comparisons
1133 /// for use by selects and conditional branches. With multiple condition
1134 /// registers, the code generator will not aggressively sink comparisons into
1135 /// the blocks of their users.
1136 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1137 HasMultipleConditionRegisters = hasManyRegs;
1140 /// Tells the code generator that the target has BitExtract instructions.
1141 /// The code generator will aggressively sink "shift"s into the blocks of
1142 /// their users if the users will generate "and" instructions which can be
1143 /// combined with "shift" to BitExtract instructions.
1144 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1145 HasExtractBitsInsn = hasExtractInsn;
1148 /// Tells the code generator not to expand sequence of operations into a
1149 /// separate sequences that increases the amount of flow control.
1150 void setJumpIsExpensive(bool isExpensive = true) {
1151 JumpIsExpensive = isExpensive;
1154 /// Tells the code generator that integer divide is expensive, and if
1155 /// possible, should be replaced by an alternate sequence of instructions not
1156 /// containing an integer divide.
1157 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1159 /// Tells the code generator that this target supports floating point
1160 /// exceptions and cares about preserving floating point exception behavior.
1161 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1162 HasFloatingPointExceptions = FPExceptions;
1165 /// Tells the code generator which bitwidths to bypass.
1166 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1167 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1170 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1171 /// signed divide by power of two; let the target handle it.
1172 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1174 /// Add the specified register class as an available regclass for the
1175 /// specified value type. This indicates the selector can handle values of
1176 /// that class natively.
1177 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1178 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1179 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1180 RegClassForVT[VT.SimpleTy] = RC;
1183 /// Remove all register classes.
1184 void clearRegisterClasses() {
1185 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1187 AvailableRegClasses.clear();
1190 /// \brief Remove all operation actions.
1191 void clearOperationActions() {
1194 /// Return the largest legal super-reg register class of the register class
1195 /// for the specified type and its associated "cost".
1196 virtual std::pair<const TargetRegisterClass*, uint8_t>
1197 findRepresentativeClass(MVT VT) const;
1199 /// Once all of the register classes are added, this allows us to compute
1200 /// derived properties we expose.
1201 void computeRegisterProperties();
1203 /// Indicate that the specified operation does not work with the specified
1204 /// type and indicate what to do about it.
1205 void setOperationAction(unsigned Op, MVT VT,
1206 LegalizeAction Action) {
1207 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1208 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1211 /// Indicate that the specified load with extension does not work with the
1212 /// specified type and indicate what to do about it.
1213 void setLoadExtAction(unsigned ExtType, MVT VT,
1214 LegalizeAction Action) {
1215 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1216 "Table isn't big enough!");
1217 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1220 /// Indicate that the specified truncating store does not work with the
1221 /// specified type and indicate what to do about it.
1222 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1223 LegalizeAction Action) {
1224 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1225 "Table isn't big enough!");
1226 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1229 /// Indicate that the specified indexed load does or does not work with the
1230 /// specified type and indicate what to do abort it.
1232 /// NOTE: All indexed mode loads are initialized to Expand in
1233 /// TargetLowering.cpp
1234 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1235 LegalizeAction Action) {
1236 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1237 (unsigned)Action < 0xf && "Table isn't big enough!");
1238 // Load action are kept in the upper half.
1239 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1240 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1243 /// Indicate that the specified indexed store does or does not work with the
1244 /// specified type and indicate what to do about it.
1246 /// NOTE: All indexed mode stores are initialized to Expand in
1247 /// TargetLowering.cpp
1248 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1249 LegalizeAction Action) {
1250 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1251 (unsigned)Action < 0xf && "Table isn't big enough!");
1252 // Store action are kept in the lower half.
1253 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1254 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1257 /// Indicate that the specified condition code is or isn't supported on the
1258 /// target and indicate what to do about it.
1259 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1260 LegalizeAction Action) {
1261 assert(VT < MVT::LAST_VALUETYPE &&
1262 (unsigned)CC < array_lengthof(CondCodeActions) &&
1263 "Table isn't big enough!");
1264 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1265 /// value and the upper 27 bits index into the second dimension of the array
1266 /// to select what 32-bit value to use.
1267 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1268 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1269 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1272 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1273 /// to trying a larger integer/fp until it can find one that works. If that
1274 /// default is insufficient, this method can be used by the target to override
1276 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1277 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1280 /// Targets should invoke this method for each target independent node that
1281 /// they want to provide a custom DAG combiner for by implementing the
1282 /// PerformDAGCombine virtual method.
1283 void setTargetDAGCombine(ISD::NodeType NT) {
1284 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1285 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1288 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1289 void setJumpBufSize(unsigned Size) {
1293 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1295 void setJumpBufAlignment(unsigned Align) {
1296 JumpBufAlignment = Align;
1299 /// Set the target's minimum function alignment (in log2(bytes))
1300 void setMinFunctionAlignment(unsigned Align) {
1301 MinFunctionAlignment = Align;
1304 /// Set the target's preferred function alignment. This should be set if
1305 /// there is a performance benefit to higher-than-minimum alignment (in
1307 void setPrefFunctionAlignment(unsigned Align) {
1308 PrefFunctionAlignment = Align;
1311 /// Set the target's preferred loop alignment. Default alignment is zero, it
1312 /// means the target does not care about loop alignment. The alignment is
1313 /// specified in log2(bytes).
1314 void setPrefLoopAlignment(unsigned Align) {
1315 PrefLoopAlignment = Align;
1318 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1319 void setMinStackArgumentAlignment(unsigned Align) {
1320 MinStackArgumentAlignment = Align;
1323 /// Set if the DAG builder should automatically insert fences and reduce the
1324 /// order of atomic memory operations to Monotonic.
1325 void setInsertFencesForAtomic(bool fence) {
1326 InsertFencesForAtomic = fence;
1330 //===--------------------------------------------------------------------===//
1331 // Addressing mode description hooks (used by LSR etc).
1334 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1335 /// instructions reading the address. This allows as much computation as
1336 /// possible to be done in the address mode for that operand. This hook lets
1337 /// targets also pass back when this should be done on intrinsics which
1339 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1340 SmallVectorImpl<Value*> &/*Ops*/,
1341 Type *&/*AccessTy*/) const {
1345 /// This represents an addressing mode of:
1346 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1347 /// If BaseGV is null, there is no BaseGV.
1348 /// If BaseOffs is zero, there is no base offset.
1349 /// If HasBaseReg is false, there is no base register.
1350 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1353 GlobalValue *BaseGV;
1357 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1360 /// Return true if the addressing mode represented by AM is legal for this
1361 /// target, for a load/store of the specified type.
1363 /// The type may be VoidTy, in which case only return true if the addressing
1364 /// mode is legal for a load/store of any legal type. TODO: Handle
1365 /// pre/postinc as well.
1366 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1368 /// \brief Return the cost of the scaling factor used in the addressing mode
1369 /// represented by AM for this target, for a load/store of the specified type.
1371 /// If the AM is supported, the return value must be >= 0.
1372 /// If the AM is not supported, it returns a negative value.
1373 /// TODO: Handle pre/postinc as well.
1374 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1375 // Default: assume that any scaling factor used in a legal AM is free.
1376 if (isLegalAddressingMode(AM, Ty)) return 0;
1380 /// Return true if the specified immediate is legal icmp immediate, that is
1381 /// the target has icmp instructions which can compare a register against the
1382 /// immediate without having to materialize the immediate into a register.
1383 virtual bool isLegalICmpImmediate(int64_t) const {
1387 /// Return true if the specified immediate is legal add immediate, that is the
1388 /// target has add instructions which can add a register with the immediate
1389 /// without having to materialize the immediate into a register.
1390 virtual bool isLegalAddImmediate(int64_t) const {
1394 /// Return true if it's significantly cheaper to shift a vector by a uniform
1395 /// scalar than by an amount which will vary across each lane. On x86, for
1396 /// example, there is a "psllw" instruction for the former case, but no simple
1397 /// instruction for a general "a << b" operation on vectors.
1398 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1402 /// Return true if it's free to truncate a value of type Ty1 to type
1403 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1404 /// by referencing its sub-register AX.
1405 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1409 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1410 /// whether a call is in tail position. Typically this means that both results
1411 /// would be assigned to the same register or stack slot, but it could mean
1412 /// the target performs adequate checks of its own before proceeding with the
1414 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1418 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1422 /// Return true if any actual instruction that defines a value of type Ty1
1423 /// implicitly zero-extends the value to Ty2 in the result register.
1425 /// This does not necessarily include registers defined in unknown ways, such
1426 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1427 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1428 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1429 /// values implicit zero-extend the result out to 64 bits.
1430 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1434 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1438 /// Return true if the target supplies and combines to a paired load
1439 /// two loaded values of type LoadedType next to each other in memory.
1440 /// RequiredAlignment gives the minimal alignment constraints that must be met
1441 /// to be able to select this paired load.
1443 /// This information is *not* used to generate actual paired loads, but it is
1444 /// used to generate a sequence of loads that is easier to combine into a
1446 /// For instance, something like this:
1447 /// a = load i64* addr
1448 /// b = trunc i64 a to i32
1449 /// c = lshr i64 a, 32
1450 /// d = trunc i64 c to i32
1451 /// will be optimized into:
1452 /// b = load i32* addr1
1453 /// d = load i32* addr2
1454 /// Where addr1 = addr2 +/- sizeof(i32).
1456 /// In other words, unless the target performs a post-isel load combining,
1457 /// this information should not be provided because it will generate more
1459 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1460 unsigned & /*RequiredAligment*/) const {
1464 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1465 unsigned & /*RequiredAligment*/) const {
1469 /// Return true if zero-extending the specific node Val to type VT2 is free
1470 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1471 /// because it's folded such as X86 zero-extending loads).
1472 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1473 return isZExtFree(Val.getValueType(), VT2);
1476 /// Return true if an fneg operation is free to the point where it is never
1477 /// worthwhile to replace it with a bitwise operation.
1478 virtual bool isFNegFree(EVT VT) const {
1479 assert(VT.isFloatingPoint());
1483 /// Return true if an fabs operation is free to the point where it is never
1484 /// worthwhile to replace it with a bitwise operation.
1485 virtual bool isFAbsFree(EVT VT) const {
1486 assert(VT.isFloatingPoint());
1490 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1491 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1492 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1494 /// NOTE: This may be called before legalization on types for which FMAs are
1495 /// not legal, but should return true if those types will eventually legalize
1496 /// to types that support FMAs. After legalization, it will only be called on
1497 /// types that support FMAs (via Legal or Custom actions)
1498 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1502 /// Return true if it's profitable to narrow operations of type VT1 to
1503 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1505 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1509 /// \brief Return true if it is beneficial to convert a load of a constant to
1510 /// just the constant itself.
1511 /// On some targets it might be more efficient to use a combination of
1512 /// arithmetic instructions to materialize the constant instead of loading it
1513 /// from a constant pool.
1514 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1518 //===--------------------------------------------------------------------===//
1519 // Runtime Library hooks
1522 /// Rename the default libcall routine name for the specified libcall.
1523 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1524 LibcallRoutineNames[Call] = Name;
1527 /// Get the libcall routine name for the specified libcall.
1528 const char *getLibcallName(RTLIB::Libcall Call) const {
1529 return LibcallRoutineNames[Call];
1532 /// Override the default CondCode to be used to test the result of the
1533 /// comparison libcall against zero.
1534 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1535 CmpLibcallCCs[Call] = CC;
1538 /// Get the CondCode that's to be used to test the result of the comparison
1539 /// libcall against zero.
1540 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1541 return CmpLibcallCCs[Call];
1544 /// Set the CallingConv that should be used for the specified libcall.
1545 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1546 LibcallCallingConvs[Call] = CC;
1549 /// Get the CallingConv that should be used for the specified libcall.
1550 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1551 return LibcallCallingConvs[Call];
1555 const TargetMachine &TM;
1556 const DataLayout *DL;
1557 const TargetLoweringObjectFile &TLOF;
1559 /// True if this is a little endian target.
1560 bool IsLittleEndian;
1562 /// Tells the code generator not to expand operations into sequences that use
1563 /// the select operations if possible.
1564 bool SelectIsExpensive;
1566 /// Tells the code generator that the target has multiple (allocatable)
1567 /// condition registers that can be used to store the results of comparisons
1568 /// for use by selects and conditional branches. With multiple condition
1569 /// registers, the code generator will not aggressively sink comparisons into
1570 /// the blocks of their users.
1571 bool HasMultipleConditionRegisters;
1573 /// Tells the code generator that the target has BitExtract instructions.
1574 /// The code generator will aggressively sink "shift"s into the blocks of
1575 /// their users if the users will generate "and" instructions which can be
1576 /// combined with "shift" to BitExtract instructions.
1577 bool HasExtractBitsInsn;
1579 /// Tells the code generator not to expand integer divides by constants into a
1580 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1581 /// model is in place. If we ever optimize for size, this will be set to true
1582 /// unconditionally.
1585 /// Tells the code generator to bypass slow divide or remainder
1586 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1587 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1588 /// div/rem when the operands are positive and less than 256.
1589 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1591 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1592 /// signed divide by power of two; let the target handle it.
1593 bool Pow2SDivIsCheap;
1595 /// Tells the code generator that it shouldn't generate extra flow control
1596 /// instructions and should attempt to combine flow control instructions via
1598 bool JumpIsExpensive;
1600 /// Whether the target supports or cares about preserving floating point
1601 /// exception behavior.
1602 bool HasFloatingPointExceptions;
1604 /// This target prefers to use _setjmp to implement llvm.setjmp.
1606 /// Defaults to false.
1607 bool UseUnderscoreSetJmp;
1609 /// This target prefers to use _longjmp to implement llvm.longjmp.
1611 /// Defaults to false.
1612 bool UseUnderscoreLongJmp;
1614 /// Number of blocks threshold to use jump tables.
1615 int MinimumJumpTableEntries;
1617 /// Information about the contents of the high-bits in boolean values held in
1618 /// a type wider than i1. See getBooleanContents.
1619 BooleanContent BooleanContents;
1621 /// Information about the contents of the high-bits in boolean values held in
1622 /// a type wider than i1. See getBooleanContents.
1623 BooleanContent BooleanFloatContents;
1625 /// Information about the contents of the high-bits in boolean vector values
1626 /// when the element type is wider than i1. See getBooleanContents.
1627 BooleanContent BooleanVectorContents;
1629 /// The target scheduling preference: shortest possible total cycles or lowest
1631 Sched::Preference SchedPreferenceInfo;
1633 /// The size, in bytes, of the target's jmp_buf buffers
1634 unsigned JumpBufSize;
1636 /// The alignment, in bytes, of the target's jmp_buf buffers
1637 unsigned JumpBufAlignment;
1639 /// The minimum alignment that any argument on the stack needs to have.
1640 unsigned MinStackArgumentAlignment;
1642 /// The minimum function alignment (used when optimizing for size, and to
1643 /// prevent explicitly provided alignment from leading to incorrect code).
1644 unsigned MinFunctionAlignment;
1646 /// The preferred function alignment (used when alignment unspecified and
1647 /// optimizing for speed).
1648 unsigned PrefFunctionAlignment;
1650 /// The preferred loop alignment.
1651 unsigned PrefLoopAlignment;
1653 /// Whether the DAG builder should automatically insert fences and reduce
1654 /// ordering for atomics. (This will be set for for most architectures with
1655 /// weak memory ordering.)
1656 bool InsertFencesForAtomic;
1658 /// If set to a physical register, this specifies the register that
1659 /// llvm.savestack/llvm.restorestack should save and restore.
1660 unsigned StackPointerRegisterToSaveRestore;
1662 /// If set to a physical register, this specifies the register that receives
1663 /// the exception address on entry to a landing pad.
1664 unsigned ExceptionPointerRegister;
1666 /// If set to a physical register, this specifies the register that receives
1667 /// the exception typeid on entry to a landing pad.
1668 unsigned ExceptionSelectorRegister;
1670 /// This indicates the default register class to use for each ValueType the
1671 /// target supports natively.
1672 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1673 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1674 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1676 /// This indicates the "representative" register class to use for each
1677 /// ValueType the target supports natively. This information is used by the
1678 /// scheduler to track register pressure. By default, the representative
1679 /// register class is the largest legal super-reg register class of the
1680 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1681 /// representative class would be GR32.
1682 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1684 /// This indicates the "cost" of the "representative" register class for each
1685 /// ValueType. The cost is used by the scheduler to approximate register
1687 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1689 /// For any value types we are promoting or expanding, this contains the value
1690 /// type that we are changing to. For Expanded types, this contains one step
1691 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1692 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1693 /// the same type (e.g. i32 -> i32).
1694 MVT TransformToType[MVT::LAST_VALUETYPE];
1696 /// For each operation and each value type, keep a LegalizeAction that
1697 /// indicates how instruction selection should deal with the operation. Most
1698 /// operations are Legal (aka, supported natively by the target), but
1699 /// operations that are not should be described. Note that operations on
1700 /// non-legal value types are not described here.
1701 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1703 /// For each load extension type and each value type, keep a LegalizeAction
1704 /// that indicates how instruction selection should deal with a load of a
1705 /// specific value type and extension type.
1706 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1708 /// For each value type pair keep a LegalizeAction that indicates whether a
1709 /// truncating store of a specific value type and truncating type is legal.
1710 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1712 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1713 /// that indicates how instruction selection should deal with the load /
1716 /// The first dimension is the value_type for the reference. The second
1717 /// dimension represents the various modes for load store.
1718 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1720 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1721 /// indicates how instruction selection should deal with the condition code.
1723 /// Because each CC action takes up 2 bits, we need to have the array size be
1724 /// large enough to fit all of the value types. This can be done by rounding
1725 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1726 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1728 ValueTypeActionImpl ValueTypeActions;
1732 getTypeConversion(LLVMContext &Context, EVT VT) const {
1733 // If this is a simple type, use the ComputeRegisterProp mechanism.
1734 if (VT.isSimple()) {
1735 MVT SVT = VT.getSimpleVT();
1736 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1737 MVT NVT = TransformToType[SVT.SimpleTy];
1738 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1741 (LA == TypeLegal || LA == TypeSoftenFloat ||
1742 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1743 && "Promote may not follow Expand or Promote");
1745 if (LA == TypeSplitVector)
1746 return LegalizeKind(LA, EVT::getVectorVT(Context,
1747 SVT.getVectorElementType(),
1748 SVT.getVectorNumElements()/2));
1749 if (LA == TypeScalarizeVector)
1750 return LegalizeKind(LA, SVT.getVectorElementType());
1751 return LegalizeKind(LA, NVT);
1754 // Handle Extended Scalar Types.
1755 if (!VT.isVector()) {
1756 assert(VT.isInteger() && "Float types must be simple");
1757 unsigned BitSize = VT.getSizeInBits();
1758 // First promote to a power-of-two size, then expand if necessary.
1759 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1760 EVT NVT = VT.getRoundIntegerType(Context);
1761 assert(NVT != VT && "Unable to round integer VT");
1762 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1763 // Avoid multi-step promotion.
1764 if (NextStep.first == TypePromoteInteger) return NextStep;
1765 // Return rounded integer type.
1766 return LegalizeKind(TypePromoteInteger, NVT);
1769 return LegalizeKind(TypeExpandInteger,
1770 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1773 // Handle vector types.
1774 unsigned NumElts = VT.getVectorNumElements();
1775 EVT EltVT = VT.getVectorElementType();
1777 // Vectors with only one element are always scalarized.
1779 return LegalizeKind(TypeScalarizeVector, EltVT);
1781 // Try to widen vector elements until the element type is a power of two and
1782 // promote it to a legal type later on, for example:
1783 // <3 x i8> -> <4 x i8> -> <4 x i32>
1784 if (EltVT.isInteger()) {
1785 // Vectors with a number of elements that is not a power of two are always
1786 // widened, for example <3 x i8> -> <4 x i8>.
1787 if (!VT.isPow2VectorType()) {
1788 NumElts = (unsigned)NextPowerOf2(NumElts);
1789 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1790 return LegalizeKind(TypeWidenVector, NVT);
1793 // Examine the element type.
1794 LegalizeKind LK = getTypeConversion(Context, EltVT);
1796 // If type is to be expanded, split the vector.
1797 // <4 x i140> -> <2 x i140>
1798 if (LK.first == TypeExpandInteger)
1799 return LegalizeKind(TypeSplitVector,
1800 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1802 // Promote the integer element types until a legal vector type is found
1803 // or until the element integer type is too big. If a legal type was not
1804 // found, fallback to the usual mechanism of widening/splitting the
1806 EVT OldEltVT = EltVT;
1808 // Increase the bitwidth of the element to the next pow-of-two
1809 // (which is greater than 8 bits).
1810 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1811 ).getRoundIntegerType(Context);
1813 // Stop trying when getting a non-simple element type.
1814 // Note that vector elements may be greater than legal vector element
1815 // types. Example: X86 XMM registers hold 64bit element on 32bit
1817 if (!EltVT.isSimple()) break;
1819 // Build a new vector type and check if it is legal.
1820 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1821 // Found a legal promoted vector type.
1822 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1823 return LegalizeKind(TypePromoteInteger,
1824 EVT::getVectorVT(Context, EltVT, NumElts));
1827 // Reset the type to the unexpanded type if we did not find a legal vector
1828 // type with a promoted vector element type.
1832 // Try to widen the vector until a legal type is found.
1833 // If there is no wider legal type, split the vector.
1835 // Round up to the next power of 2.
1836 NumElts = (unsigned)NextPowerOf2(NumElts);
1838 // If there is no simple vector type with this many elements then there
1839 // cannot be a larger legal vector type. Note that this assumes that
1840 // there are no skipped intermediate vector types in the simple types.
1841 if (!EltVT.isSimple()) break;
1842 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1843 if (LargerVector == MVT()) break;
1845 // If this type is legal then widen the vector.
1846 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1847 return LegalizeKind(TypeWidenVector, LargerVector);
1850 // Widen odd vectors to next power of two.
1851 if (!VT.isPow2VectorType()) {
1852 EVT NVT = VT.getPow2VectorType(Context);
1853 return LegalizeKind(TypeWidenVector, NVT);
1856 // Vectors with illegal element types are expanded.
1857 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1858 return LegalizeKind(TypeSplitVector, NVT);
1862 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1864 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1865 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1868 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1870 /// For operations that must be promoted to a specific type, this holds the
1871 /// destination type. This map should be sparse, so don't hold it as an
1874 /// Targets add entries to this map with AddPromotedToType(..), clients access
1875 /// this with getTypeToPromoteTo(..).
1876 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1879 /// Stores the name each libcall.
1880 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1882 /// The ISD::CondCode that should be used to test the result of each of the
1883 /// comparison libcall against zero.
1884 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1886 /// Stores the CallingConv that should be used for each libcall.
1887 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1890 /// \brief Specify maximum number of store instructions per memset call.
1892 /// When lowering \@llvm.memset this field specifies the maximum number of
1893 /// store operations that may be substituted for the call to memset. Targets
1894 /// must set this value based on the cost threshold for that target. Targets
1895 /// should assume that the memset will be done using as many of the largest
1896 /// store operations first, followed by smaller ones, if necessary, per
1897 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1898 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1899 /// store. This only applies to setting a constant array of a constant size.
1900 unsigned MaxStoresPerMemset;
1902 /// Maximum number of stores operations that may be substituted for the call
1903 /// to memset, used for functions with OptSize attribute.
1904 unsigned MaxStoresPerMemsetOptSize;
1906 /// \brief Specify maximum bytes of store instructions per memcpy call.
1908 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1909 /// store operations that may be substituted for a call to memcpy. Targets
1910 /// must set this value based on the cost threshold for that target. Targets
1911 /// should assume that the memcpy will be done using as many of the largest
1912 /// store operations first, followed by smaller ones, if necessary, per
1913 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1914 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1915 /// and one 1-byte store. This only applies to copying a constant array of
1917 unsigned MaxStoresPerMemcpy;
1919 /// Maximum number of store operations that may be substituted for a call to
1920 /// memcpy, used for functions with OptSize attribute.
1921 unsigned MaxStoresPerMemcpyOptSize;
1923 /// \brief Specify maximum bytes of store instructions per memmove call.
1925 /// When lowering \@llvm.memmove this field specifies the maximum number of
1926 /// store instructions that may be substituted for a call to memmove. Targets
1927 /// must set this value based on the cost threshold for that target. Targets
1928 /// should assume that the memmove will be done using as many of the largest
1929 /// store operations first, followed by smaller ones, if necessary, per
1930 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1931 /// with 8-bit alignment would result in nine 1-byte stores. This only
1932 /// applies to copying a constant array of constant size.
1933 unsigned MaxStoresPerMemmove;
1935 /// Maximum number of store instructions that may be substituted for a call to
1936 /// memmove, used for functions with OpSize attribute.
1937 unsigned MaxStoresPerMemmoveOptSize;
1939 /// Tells the code generator that select is more expensive than a branch if
1940 /// the branch is usually predicted right.
1941 bool PredictableSelectIsExpensive;
1943 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1944 /// a mask of a single bit, a compare, and a branch into a single instruction.
1945 bool MaskAndBranchFoldingIsLegal;
1948 /// Return true if the value types that can be represented by the specified
1949 /// register class are all legal.
1950 bool isLegalRC(const TargetRegisterClass *RC) const;
1952 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1953 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1954 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1957 /// This class defines information used to lower LLVM code to legal SelectionDAG
1958 /// operators that the target instruction selector can accept natively.
1960 /// This class also defines callbacks that targets must implement to lower
1961 /// target-specific constructs to SelectionDAG operators.
1962 class TargetLowering : public TargetLoweringBase {
1963 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1964 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1967 /// NOTE: The constructor takes ownership of TLOF.
1968 explicit TargetLowering(const TargetMachine &TM,
1969 const TargetLoweringObjectFile *TLOF);
1971 /// Returns true by value, base pointer and offset pointer and addressing mode
1972 /// by reference if the node's address can be legally represented as
1973 /// pre-indexed load / store address.
1974 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1975 SDValue &/*Offset*/,
1976 ISD::MemIndexedMode &/*AM*/,
1977 SelectionDAG &/*DAG*/) const {
1981 /// Returns true by value, base pointer and offset pointer and addressing mode
1982 /// by reference if this node can be combined with a load / store to form a
1983 /// post-indexed load / store.
1984 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1986 SDValue &/*Offset*/,
1987 ISD::MemIndexedMode &/*AM*/,
1988 SelectionDAG &/*DAG*/) const {
1992 /// Return the entry encoding for a jump table in the current function. The
1993 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1994 virtual unsigned getJumpTableEncoding() const;
1996 virtual const MCExpr *
1997 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1998 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1999 MCContext &/*Ctx*/) const {
2000 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2003 /// Returns relocation base for the given PIC jumptable.
2004 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2005 SelectionDAG &DAG) const;
2007 /// This returns the relocation base for the given PIC jumptable, the same as
2008 /// getPICJumpTableRelocBase, but as an MCExpr.
2009 virtual const MCExpr *
2010 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2011 unsigned JTI, MCContext &Ctx) const;
2013 /// Return true if folding a constant offset with the given GlobalAddress is
2014 /// legal. It is frequently not legal in PIC relocation models.
2015 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2017 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2018 SDValue &Chain) const;
2020 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2021 SDValue &NewLHS, SDValue &NewRHS,
2022 ISD::CondCode &CCCode, SDLoc DL) const;
2024 /// Returns a pair of (return value, chain).
2025 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2026 EVT RetVT, const SDValue *Ops,
2027 unsigned NumOps, bool isSigned,
2028 SDLoc dl, bool doesNotReturn = false,
2029 bool isReturnValueUsed = true) const;
2031 //===--------------------------------------------------------------------===//
2032 // TargetLowering Optimization Methods
2035 /// A convenience struct that encapsulates a DAG, and two SDValues for
2036 /// returning information from TargetLowering to its clients that want to
2038 struct TargetLoweringOpt {
2045 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2047 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2049 bool LegalTypes() const { return LegalTys; }
2050 bool LegalOperations() const { return LegalOps; }
2052 bool CombineTo(SDValue O, SDValue N) {
2058 /// Check to see if the specified operand of the specified instruction is a
2059 /// constant integer. If so, check to see if there are any bits set in the
2060 /// constant that are not demanded. If so, shrink the constant and return
2062 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2064 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2065 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2066 /// generalized for targets with other types of implicit widening casts.
2067 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2071 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2072 /// result of Op are ever used downstream. If we can use this information to
2073 /// simplify Op, create a new simplified DAG node and return true, returning
2074 /// the original and new nodes in Old and New. Otherwise, analyze the
2075 /// expression and return a mask of KnownOne and KnownZero bits for the
2076 /// expression (used to simplify the caller). The KnownZero/One bits may only
2077 /// be accurate for those bits in the DemandedMask.
2078 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2079 APInt &KnownZero, APInt &KnownOne,
2080 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2082 /// Determine which of the bits specified in Mask are known to be either zero
2083 /// or one and return them in the KnownZero/KnownOne bitsets.
2084 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2087 const SelectionDAG &DAG,
2088 unsigned Depth = 0) const;
2090 /// This method can be implemented by targets that want to expose additional
2091 /// information about sign bits to the DAG Combiner.
2092 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2093 const SelectionDAG &DAG,
2094 unsigned Depth = 0) const;
2096 struct DAGCombinerInfo {
2097 void *DC; // The DAG Combiner object.
2099 bool CalledByLegalizer;
2103 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2104 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2106 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2107 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2108 bool isAfterLegalizeVectorOps() const {
2109 return Level == AfterLegalizeDAG;
2111 CombineLevel getDAGCombineLevel() { return Level; }
2112 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2114 void AddToWorklist(SDNode *N);
2115 void RemoveFromWorklist(SDNode *N);
2116 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
2118 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2119 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2121 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2124 /// Return if the N is a constant or constant vector equal to the true value
2125 /// from getBooleanContents().
2126 bool isConstTrueVal(const SDNode *N) const;
2128 /// Return if the N is a constant or constant vector equal to the false value
2129 /// from getBooleanContents().
2130 bool isConstFalseVal(const SDNode *N) const;
2132 /// Try to simplify a setcc built with the specified operands and cc. If it is
2133 /// unable to simplify it, return a null SDValue.
2134 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2135 ISD::CondCode Cond, bool foldBooleans,
2136 DAGCombinerInfo &DCI, SDLoc dl) const;
2138 /// Returns true (and the GlobalValue and the offset) if the node is a
2139 /// GlobalAddress + offset.
2141 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2143 /// This method will be invoked for all target nodes and for any
2144 /// target-independent nodes that the target has registered with invoke it
2147 /// The semantics are as follows:
2149 /// SDValue.Val == 0 - No change was made
2150 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2151 /// otherwise - N should be replaced by the returned Operand.
2153 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2154 /// more complex transformations.
2156 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2158 /// Return true if it is profitable to move a following shift through this
2159 // node, adjusting any immediate operands as necessary to preserve semantics.
2160 // This transformation may not be desirable if it disrupts a particularly
2161 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2162 // By default, it returns true.
2163 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2167 /// Return true if the target has native support for the specified value type
2168 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2169 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2170 /// and some i16 instructions are slow.
2171 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2172 // By default, assume all legal types are desirable.
2173 return isTypeLegal(VT);
2176 /// Return true if it is profitable for dag combiner to transform a floating
2177 /// point op of specified opcode to a equivalent op of an integer
2178 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2179 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2184 /// This method query the target whether it is beneficial for dag combiner to
2185 /// promote the specified node. If true, it should return the desired
2186 /// promotion type by reference.
2187 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2191 //===--------------------------------------------------------------------===//
2192 // Lowering methods - These methods must be implemented by targets so that
2193 // the SelectionDAGBuilder code knows how to lower these.
2196 /// This hook must be implemented to lower the incoming (formal) arguments,
2197 /// described by the Ins array, into the specified DAG. The implementation
2198 /// should fill in the InVals array with legal-type argument values, and
2199 /// return the resulting token chain value.
2202 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2204 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2205 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2206 SmallVectorImpl<SDValue> &/*InVals*/) const {
2207 llvm_unreachable("Not Implemented");
2210 struct ArgListEntry {
2219 bool isInAlloca : 1;
2220 bool isReturned : 1;
2223 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2224 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2225 isReturned(false), Alignment(0) { }
2227 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2229 typedef std::vector<ArgListEntry> ArgListTy;
2231 /// This structure contains all information that is necessary for lowering
2232 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2233 /// needs to lower a call, and targets will see this struct in their LowerCall
2235 struct CallLoweringInfo {
2242 bool DoesNotReturn : 1;
2243 bool IsReturnValueUsed : 1;
2245 // IsTailCall should be modified by implementations of
2246 // TargetLowering::LowerCall that perform tail call conversions.
2249 unsigned NumFixedArgs;
2250 CallingConv::ID CallConv;
2255 ImmutableCallSite *CS;
2256 SmallVector<ISD::OutputArg, 32> Outs;
2257 SmallVector<SDValue, 32> OutVals;
2258 SmallVector<ISD::InputArg, 32> Ins;
2260 CallLoweringInfo(SelectionDAG &DAG)
2261 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2262 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2263 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2264 DAG(DAG), CS(nullptr) {}
2266 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2271 CallLoweringInfo &setChain(SDValue InChain) {
2276 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2277 SDValue Target, ArgListTy &&ArgsList,
2278 unsigned FixedArgs = -1) {
2283 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2284 Args = std::move(ArgsList);
2288 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2289 SDValue Target, ArgListTy &&ArgsList,
2290 ImmutableCallSite &Call) {
2293 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2294 DoesNotReturn = Call.doesNotReturn();
2295 IsVarArg = FTy->isVarArg();
2296 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2297 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2298 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2302 CallConv = Call.getCallingConv();
2303 NumFixedArgs = FTy->getNumParams();
2304 Args = std::move(ArgsList);
2311 CallLoweringInfo &setInRegister(bool Value = true) {
2316 CallLoweringInfo &setNoReturn(bool Value = true) {
2317 DoesNotReturn = Value;
2321 CallLoweringInfo &setVarArg(bool Value = true) {
2326 CallLoweringInfo &setTailCall(bool Value = true) {
2331 CallLoweringInfo &setDiscardResult(bool Value = true) {
2332 IsReturnValueUsed = !Value;
2336 CallLoweringInfo &setSExtResult(bool Value = true) {
2341 CallLoweringInfo &setZExtResult(bool Value = true) {
2346 ArgListTy &getArgs() {
2351 /// This function lowers an abstract call to a function into an actual call.
2352 /// This returns a pair of operands. The first element is the return value
2353 /// for the function (if RetTy is not VoidTy). The second element is the
2354 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2355 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2357 /// This hook must be implemented to lower calls into the the specified
2358 /// DAG. The outgoing arguments to the call are described by the Outs array,
2359 /// and the values to be returned by the call are described by the Ins
2360 /// array. The implementation should fill in the InVals array with legal-type
2361 /// return values from the call, and return the resulting token chain value.
2363 LowerCall(CallLoweringInfo &/*CLI*/,
2364 SmallVectorImpl<SDValue> &/*InVals*/) const {
2365 llvm_unreachable("Not Implemented");
2368 /// Target-specific cleanup for formal ByVal parameters.
2369 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2371 /// This hook should be implemented to check whether the return values
2372 /// described by the Outs array can fit into the return registers. If false
2373 /// is returned, an sret-demotion is performed.
2374 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2375 MachineFunction &/*MF*/, bool /*isVarArg*/,
2376 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2377 LLVMContext &/*Context*/) const
2379 // Return true by default to get preexisting behavior.
2383 /// This hook must be implemented to lower outgoing return values, described
2384 /// by the Outs array, into the specified DAG. The implementation should
2385 /// return the resulting token chain value.
2387 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2389 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2390 const SmallVectorImpl<SDValue> &/*OutVals*/,
2391 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2392 llvm_unreachable("Not Implemented");
2395 /// Return true if result of the specified node is used by a return node
2396 /// only. It also compute and return the input chain for the tail call.
2398 /// This is used to determine whether it is possible to codegen a libcall as
2399 /// tail call at legalization time.
2400 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2404 /// Return true if the target may be able emit the call instruction as a tail
2405 /// call. This is used by optimization passes to determine if it's profitable
2406 /// to duplicate return instructions to enable tailcall optimization.
2407 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2411 /// Return the builtin name for the __builtin___clear_cache intrinsic
2412 /// Default is to invoke the clear cache library call
2413 virtual const char * getClearCacheBuiltinName() const {
2414 return "__clear_cache";
2417 /// Return the register ID of the name passed in. Used by named register
2418 /// global variables extension. There is no target-independent behaviour
2419 /// so the default action is to bail.
2420 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2421 report_fatal_error("Named registers not implemented for this target");
2424 /// Return the type that should be used to zero or sign extend a
2425 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2426 /// convention requires the return type to be promoted, but this is not true
2427 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2428 /// calling conventions. The frontend should handle this and include all of
2429 /// the necessary information.
2430 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2431 ISD::NodeType /*ExtendKind*/) const {
2432 EVT MinVT = getRegisterType(Context, MVT::i32);
2433 return VT.bitsLT(MinVT) ? MinVT : VT;
2436 /// For some targets, an LLVM struct type must be broken down into multiple
2437 /// simple types, but the calling convention specifies that the entire struct
2438 /// must be passed in a block of consecutive registers.
2440 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2441 bool isVarArg) const {
2445 /// Returns a 0 terminated array of registers that can be safely used as
2446 /// scratch registers.
2447 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2451 /// This callback is used to prepare for a volatile or atomic load.
2452 /// It takes a chain node as input and returns the chain for the load itself.
2454 /// Having a callback like this is necessary for targets like SystemZ,
2455 /// which allows a CPU to reuse the result of a previous load indefinitely,
2456 /// even if a cache-coherent store is performed by another CPU. The default
2457 /// implementation does nothing.
2458 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2459 SelectionDAG &DAG) const {
2463 /// This callback is invoked by the type legalizer to legalize nodes with an
2464 /// illegal operand type but legal result types. It replaces the
2465 /// LowerOperation callback in the type Legalizer. The reason we can not do
2466 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2467 /// use this callback.
2469 /// TODO: Consider merging with ReplaceNodeResults.
2471 /// The target places new result values for the node in Results (their number
2472 /// and types must exactly match those of the original return values of
2473 /// the node), or leaves Results empty, which indicates that the node is not
2474 /// to be custom lowered after all.
2475 /// The default implementation calls LowerOperation.
2476 virtual void LowerOperationWrapper(SDNode *N,
2477 SmallVectorImpl<SDValue> &Results,
2478 SelectionDAG &DAG) const;
2480 /// This callback is invoked for operations that are unsupported by the
2481 /// target, which are registered to use 'custom' lowering, and whose defined
2482 /// values are all legal. If the target has no operations that require custom
2483 /// lowering, it need not implement this. The default implementation of this
2485 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2487 /// This callback is invoked when a node result type is illegal for the
2488 /// target, and the operation was registered to use 'custom' lowering for that
2489 /// result type. The target places new result values for the node in Results
2490 /// (their number and types must exactly match those of the original return
2491 /// values of the node), or leaves Results empty, which indicates that the
2492 /// node is not to be custom lowered after all.
2494 /// If the target has no operations that require custom lowering, it need not
2495 /// implement this. The default implementation aborts.
2496 virtual void ReplaceNodeResults(SDNode * /*N*/,
2497 SmallVectorImpl<SDValue> &/*Results*/,
2498 SelectionDAG &/*DAG*/) const {
2499 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2502 /// This method returns the name of a target specific DAG node.
2503 virtual const char *getTargetNodeName(unsigned Opcode) const;
2505 /// This method returns a target specific FastISel object, or null if the
2506 /// target does not support "fast" ISel.
2507 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2508 const TargetLibraryInfo *) const {
2513 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2514 SelectionDAG &DAG) const;
2516 //===--------------------------------------------------------------------===//
2517 // Inline Asm Support hooks
2520 /// This hook allows the target to expand an inline asm call to be explicit
2521 /// llvm code if it wants to. This is useful for turning simple inline asms
2522 /// into LLVM intrinsics, which gives the compiler more information about the
2523 /// behavior of the code.
2524 virtual bool ExpandInlineAsm(CallInst *) const {
2528 enum ConstraintType {
2529 C_Register, // Constraint represents specific register(s).
2530 C_RegisterClass, // Constraint represents any of register(s) in class.
2531 C_Memory, // Memory constraint.
2532 C_Other, // Something else.
2533 C_Unknown // Unsupported constraint.
2536 enum ConstraintWeight {
2538 CW_Invalid = -1, // No match.
2539 CW_Okay = 0, // Acceptable.
2540 CW_Good = 1, // Good weight.
2541 CW_Better = 2, // Better weight.
2542 CW_Best = 3, // Best weight.
2544 // Well-known weights.
2545 CW_SpecificReg = CW_Okay, // Specific register operands.
2546 CW_Register = CW_Good, // Register operands.
2547 CW_Memory = CW_Better, // Memory operands.
2548 CW_Constant = CW_Best, // Constant operand.
2549 CW_Default = CW_Okay // Default or don't know type.
2552 /// This contains information for each constraint that we are lowering.
2553 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2554 /// This contains the actual string for the code, like "m". TargetLowering
2555 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2556 /// matches the operand.
2557 std::string ConstraintCode;
2559 /// Information about the constraint code, e.g. Register, RegisterClass,
2560 /// Memory, Other, Unknown.
2561 TargetLowering::ConstraintType ConstraintType;
2563 /// If this is the result output operand or a clobber, this is null,
2564 /// otherwise it is the incoming operand to the CallInst. This gets
2565 /// modified as the asm is processed.
2566 Value *CallOperandVal;
2568 /// The ValueType for the operand value.
2571 /// Return true of this is an input operand that is a matching constraint
2573 bool isMatchingInputConstraint() const;
2575 /// If this is an input matching constraint, this method returns the output
2576 /// operand it matches.
2577 unsigned getMatchedOperand() const;
2579 /// Copy constructor for copying from a ConstraintInfo.
2580 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2581 : InlineAsm::ConstraintInfo(std::move(Info)),
2582 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2583 ConstraintVT(MVT::Other) {}
2586 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2588 /// Split up the constraint string from the inline assembly value into the
2589 /// specific constraints and their prefixes, and also tie in the associated
2590 /// operand values. If this returns an empty vector, and if the constraint
2591 /// string itself isn't empty, there was an error parsing.
2592 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2594 /// Examine constraint type and operand type and determine a weight value.
2595 /// The operand object must already have been set up with the operand type.
2596 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2597 AsmOperandInfo &info, int maIndex) const;
2599 /// Examine constraint string and operand type and determine a weight value.
2600 /// The operand object must already have been set up with the operand type.
2601 virtual ConstraintWeight getSingleConstraintMatchWeight(
2602 AsmOperandInfo &info, const char *constraint) const;
2604 /// Determines the constraint code and constraint type to use for the specific
2605 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2606 /// If the actual operand being passed in is available, it can be passed in as
2607 /// Op, otherwise an empty SDValue can be passed.
2608 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2610 SelectionDAG *DAG = nullptr) const;
2612 /// Given a constraint, return the type of constraint it is for this target.
2613 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2615 /// Given a physical register constraint (e.g. {edx}), return the register
2616 /// number and the register class for the register.
2618 /// Given a register class constraint, like 'r', if this corresponds directly
2619 /// to an LLVM register class, return a register of 0 and the register class
2622 /// This should only be used for C_Register constraints. On error, this
2623 /// returns a register number of 0 and a null register class pointer..
2624 virtual std::pair<unsigned, const TargetRegisterClass*>
2625 getRegForInlineAsmConstraint(const std::string &Constraint,
2628 /// Try to replace an X constraint, which matches anything, with another that
2629 /// has more specific requirements based on the type of the corresponding
2630 /// operand. This returns null if there is no replacement to make.
2631 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2633 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2634 /// add anything to Ops.
2635 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2636 std::vector<SDValue> &Ops,
2637 SelectionDAG &DAG) const;
2639 //===--------------------------------------------------------------------===//
2640 // Div utility functions
2642 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2643 SelectionDAG &DAG) const;
2644 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2645 bool IsAfterLegalization,
2646 std::vector<SDNode *> *Created) const;
2647 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2648 bool IsAfterLegalization,
2649 std::vector<SDNode *> *Created) const;
2650 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2652 std::vector<SDNode *> *Created) const {
2656 /// Hooks for building estimates in place of slower divisions and square
2659 /// Return a reciprocal square root estimate value for the input operand.
2660 /// The RefinementSteps output is the number of Newton-Raphson refinement
2661 /// iterations required to generate a sufficient (though not necessarily
2662 /// IEEE-754 compliant) estimate for the value type.
2663 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2664 /// algorithm implementation that uses one constant or two constants.
2665 /// A target may choose to implement its own refinement within this function.
2666 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2667 /// any further refinement of the estimate.
2668 /// An empty SDValue return means no estimate sequence can be created.
2669 virtual SDValue getRsqrtEstimate(SDValue Operand,
2670 DAGCombinerInfo &DCI,
2671 unsigned &RefinementSteps,
2672 bool &UseOneConstNR) const {
2676 /// Return a reciprocal estimate value for the input operand.
2677 /// The RefinementSteps output is the number of Newton-Raphson refinement
2678 /// iterations required to generate a sufficient (though not necessarily
2679 /// IEEE-754 compliant) estimate for the value type.
2680 /// A target may choose to implement its own refinement within this function.
2681 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2682 /// any further refinement of the estimate.
2683 /// An empty SDValue return means no estimate sequence can be created.
2684 virtual SDValue getRecipEstimate(SDValue Operand,
2685 DAGCombinerInfo &DCI,
2686 unsigned &RefinementSteps) const {
2690 //===--------------------------------------------------------------------===//
2691 // Legalization utility functions
2694 /// Expand a MUL into two nodes. One that computes the high bits of
2695 /// the result and one that computes the low bits.
2696 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2697 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2698 /// if you want to control how low bits are extracted from the LHS.
2699 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2700 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2701 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2702 /// \returns true if the node has been expanded. false if it has not
2703 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2704 SelectionDAG &DAG, SDValue LL = SDValue(),
2705 SDValue LH = SDValue(), SDValue RL = SDValue(),
2706 SDValue RH = SDValue()) const;
2708 /// Expand float(f32) to SINT(i64) conversion
2709 /// \param N Node to expand
2710 /// \param Result output after conversion
2711 /// \returns True, if the expansion was successful, false otherwise
2712 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2714 //===--------------------------------------------------------------------===//
2715 // Instruction Emitting Hooks
2718 /// This method should be implemented by targets that mark instructions with
2719 /// the 'usesCustomInserter' flag. These instructions are special in various
2720 /// ways, which require special support to insert. The specified MachineInstr
2721 /// is created but not inserted into any basic blocks, and this method is
2722 /// called to expand it into a sequence of instructions, potentially also
2723 /// creating new basic blocks and control flow.
2724 virtual MachineBasicBlock *
2725 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2727 /// This method should be implemented by targets that mark instructions with
2728 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2729 /// instruction selection by target hooks. e.g. To fill in optional defs for
2730 /// ARM 's' setting instructions.
2732 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2734 /// If this function returns true, SelectionDAGBuilder emits a
2735 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2736 virtual bool useLoadStackGuardNode() const {
2741 /// Given an LLVM IR type and return type attributes, compute the return value
2742 /// EVTs and flags, and optionally also the offsets, if the return value is
2743 /// being lowered to memory.
2744 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2745 SmallVectorImpl<ISD::OutputArg> &Outs,
2746 const TargetLowering &TLI);
2748 } // end llvm namespace