1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // Register - You should define one instance of this class for each register
30 // in the target machine. String n will become the "name" of the register.
31 class Register<string n> {
32 string Namespace = "";
35 // Aliases - A list of registers that this register overlaps with. A read or
36 // modification of this register can potentially read or modify the aliased
38 list<Register> Aliases = [];
40 // SubRegs - A list of registers that are parts of this register. Note these
41 // are "immediate" sub-registers and the registers within the list do not
42 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
44 list<Register> SubRegs = [];
46 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
47 // to address it. Sub-sub-register indices are automatically inherited from
49 list<SubRegIndex> SubRegIndices = [];
51 // CompositeIndices - Specify subreg indices that don't correspond directly to
52 // a register in SubRegs and are not inherited. The following formats are
55 // (a) Identity - Reg:a == Reg
56 // (a b) Alias - Reg:a == Reg:b
57 // (a b,c) Composite - Reg:a == (Reg:b):c
59 // This can be used to disambiguate a sub-sub-register that exists in more
60 // than one subregister and other weird stuff.
61 list<dag> CompositeIndices = [];
63 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
64 // These values can be determined by locating the <target>.h file in the
65 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
66 // order of these names correspond to the enumeration used by gcc. A value of
67 // -1 indicates that the gcc number is undefined and -2 that register number
68 // is invalid for this mode/flavour.
69 list<int> DwarfNumbers = [];
71 // CostPerUse - Additional cost of instructions using this register compared
72 // to other registers in its class. The register allocator will try to
73 // minimize the number of instructions using a register with a CostPerUse.
74 // This is used by the x86-64 and ARM Thumb targets where some registers
75 // require larger instruction encodings.
79 // RegisterWithSubRegs - This can be used to define instances of Register which
80 // need to specify sub-registers.
81 // List "subregs" specifies which registers are sub-registers to this one. This
82 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
83 // This allows the code generator to be careful not to put two values with
84 // overlapping live ranges into registers which alias.
85 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
86 let SubRegs = subregs;
89 // RegisterClass - Now that all of the registers are defined, and aliases
90 // between registers are defined, specify which registers belong to which
91 // register classes. This also defines the default allocation order of
92 // registers by register allocators.
94 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
96 string Namespace = namespace;
98 // RegType - Specify the list ValueType of the registers in this register
99 // class. Note that all registers in a register class must have the same
100 // ValueTypes. This is a list because some targets permit storing different
101 // types in same register, for example vector values with 128-bit total size,
102 // but different count/size of items, like SSE on x86.
104 list<ValueType> RegTypes = regTypes;
106 // Size - Specify the spill size in bits of the registers. A default value of
107 // zero lets tablgen pick an appropriate size.
110 // Alignment - Specify the alignment required of the registers when they are
111 // stored or loaded to memory.
113 int Alignment = alignment;
115 // CopyCost - This value is used to specify the cost of copying a value
116 // between two registers in this register class. The default value is one
117 // meaning it takes a single instruction to perform the copying. A negative
118 // value means copying is extremely expensive or impossible.
121 // MemberList - Specify which registers are in this class. If the
122 // allocation_order_* method are not specified, this also defines the order of
123 // allocation used by the register allocator.
125 dag MemberList = regList;
127 // SubRegClasses - Specify the register class of subregisters as a list of
128 // dags: (RegClass SubRegIndex, SubRegindex, ...)
129 list<dag> SubRegClasses = [];
131 // isAllocatable - Specify that the register class can be used for virtual
132 // registers and register allocation. Some register classes are only used to
133 // model instruction operand constraints, and should have isAllocatable = 0.
134 bit isAllocatable = 1;
136 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
137 // code into a generated register class. The normal usage of this is to
138 // overload virtual methods.
139 code MethodProtos = [{}];
140 code MethodBodies = [{}];
142 // AltOrders - List of alternative allocation orders. The default order is
143 // MemberList itself, and that is good enough for most targets since the
144 // register allocators automatically remove reserved registers and move
145 // callee-saved registers to the end.
146 list<dag> AltOrders = [];
148 // AltOrderSelect - The body of a function that selects the allocation order
149 // to use in a given machine function. The code will be inserted in a
150 // function like this:
152 // static inline unsigned f(const MachineFunction &MF) { ... }
154 // The function should return 0 to select the default order defined by
155 // MemberList, 1 to select the first AltOrders entry and so on.
156 code AltOrderSelect = [{}];
159 // The memberList in a RegisterClass is a dag of set operations. TableGen
160 // evaluates these set operations and expand them into register lists. These
161 // are the most common operation, see test/TableGen/SetTheory.td for more
162 // examples of what is possible:
164 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
165 // register class, or a sub-expression. This is also the way to simply list
168 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
170 // (and GPR, CSR) - Set intersection. All registers from the first set that are
171 // also in the second set.
173 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
174 // numbered registers.
176 // (shl GPR, 4) - Remove the first N elements.
178 // (trunc GPR, 4) - Truncate after the first N elements.
180 // (rotl GPR, 1) - Rotate N places to the left.
182 // (rotr GPR, 1) - Rotate N places to the right.
184 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
186 // All of these operators work on ordered sets, not lists. That means
187 // duplicates are removed from sub-expressions.
189 // Set operators. The rest is defined in TargetSelectionDAG.td.
193 //===----------------------------------------------------------------------===//
194 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
195 // to the register numbering used by gcc and gdb. These values are used by a
196 // debug information writer to describe where values may be located during
198 class DwarfRegNum<list<int> Numbers> {
199 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
200 // These values can be determined by locating the <target>.h file in the
201 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
202 // order of these names correspond to the enumeration used by gcc. A value of
203 // -1 indicates that the gcc number is undefined and -2 that register number
204 // is invalid for this mode/flavour.
205 list<int> DwarfNumbers = Numbers;
208 // DwarfRegAlias - This class declares that a given register uses the same dwarf
209 // numbers as another one. This is useful for making it clear that the two
210 // registers do have the same number. It also lets us build a mapping
211 // from dwarf register number to llvm register.
212 class DwarfRegAlias<Register reg> {
213 Register DwarfAlias = reg;
216 //===----------------------------------------------------------------------===//
217 // Pull in the common support for scheduling
219 include "llvm/Target/TargetSchedule.td"
221 class Predicate; // Forward def
223 //===----------------------------------------------------------------------===//
224 // Instruction set description - These classes correspond to the C++ classes in
225 // the Target/TargetInstrInfo.h file.
228 string Namespace = "";
230 dag OutOperandList; // An dag containing the MI def operand list.
231 dag InOperandList; // An dag containing the MI use operand list.
232 string AsmString = ""; // The .s format to print the instruction with.
234 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
235 // otherwise, uninitialized.
238 // The follow state will eventually be inferred automatically from the
239 // instruction pattern.
241 list<Register> Uses = []; // Default to using no non-operand registers
242 list<Register> Defs = []; // Default to modifying no non-operand registers
244 // Predicates - List of predicates which will be turned into isel matching
246 list<Predicate> Predicates = [];
251 // Added complexity passed onto matching pattern.
252 int AddedComplexity = 0;
254 // These bits capture information about the high-level semantics of the
256 bit isReturn = 0; // Is this instruction a return instruction?
257 bit isBranch = 0; // Is this instruction a branch instruction?
258 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
259 bit isCompare = 0; // Is this instruction a comparison instruction?
260 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
261 bit isBitcast = 0; // Is this instruction a bitcast instruction?
262 bit isBarrier = 0; // Can control flow fall through this instruction?
263 bit isCall = 0; // Is this instruction a call instruction?
264 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
265 bit mayLoad = 0; // Is it possible for this inst to read memory?
266 bit mayStore = 0; // Is it possible for this inst to write memory?
267 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
268 bit isCommutable = 0; // Is this 3 operand instruction commutable?
269 bit isTerminator = 0; // Is this part of the terminator for a basic block?
270 bit isReMaterializable = 0; // Is this instruction re-materializable?
271 bit isPredicable = 0; // Is this instruction predicable?
272 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
273 bit usesCustomInserter = 0; // Pseudo instr needing special help.
274 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
275 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
276 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
277 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
278 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
280 // Side effect flags - When set, the flags have these meanings:
282 // hasSideEffects - The instruction has side effects that are not
283 // captured by any operands of the instruction or other flags.
285 // neverHasSideEffects - Set on an instruction with no pattern if it has no
287 bit hasSideEffects = 0;
288 bit neverHasSideEffects = 0;
290 // Is this instruction a "real" instruction (with a distinct machine
291 // encoding), or is it a pseudo instruction used for codegen modeling
293 bit isCodeGenOnly = 0;
295 // Is this instruction a pseudo instruction for use by the assembler parser.
296 bit isAsmParserOnly = 0;
298 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
300 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
302 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
303 /// be encoded into the output machineinstr.
304 string DisableEncoding = "";
306 string PostEncoderMethod = "";
307 string DecoderMethod = "";
309 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
310 bits<64> TSFlags = 0;
312 ///@name Assembler Parser Support
315 string AsmMatchConverter = "";
320 /// Predicates - These are extra conditionals which are turned into instruction
321 /// selector matching code. Currently each predicate is just a string.
322 class Predicate<string cond> {
323 string CondString = cond;
325 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
326 /// matcher, this is true. Targets should set this by inheriting their
327 /// feature from the AssemblerPredicate class in addition to Predicate.
328 bit AssemblerMatcherPredicate = 0;
331 /// NoHonorSignDependentRounding - This predicate is true if support for
332 /// sign-dependent-rounding is not enabled.
333 def NoHonorSignDependentRounding
334 : Predicate<"!HonorSignDependentRoundingFPMath()">;
336 class Requires<list<Predicate> preds> {
337 list<Predicate> Predicates = preds;
340 /// ops definition - This is just a simple marker used to identify the operand
341 /// list for an instruction. outs and ins are identical both syntactically and
342 /// semanticallyr; they are used to define def operands and use operands to
343 /// improve readibility. This should be used like this:
344 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
349 /// variable_ops definition - Mark this instruction as taking a variable number
354 /// PointerLikeRegClass - Values that are designed to have pointer width are
355 /// derived from this. TableGen treats the register class as having a symbolic
356 /// type that it doesn't know, and resolves the actual regclass to use by using
357 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
358 class PointerLikeRegClass<int Kind> {
359 int RegClassKind = Kind;
363 /// ptr_rc definition - Mark this operand as being a pointer value whose
364 /// register class is resolved dynamically via a callback to TargetInstrInfo.
365 /// FIXME: We should probably change this to a class which contain a list of
366 /// flags. But currently we have but one flag.
367 def ptr_rc : PointerLikeRegClass<0>;
369 /// unknown definition - Mark this operand as being of unknown type, causing
370 /// it to be resolved by inference in the context it is used.
373 /// AsmOperandClass - Representation for the kinds of operands which the target
374 /// specific parser can create and the assembly matcher may need to distinguish.
376 /// Operand classes are used to define the order in which instructions are
377 /// matched, to ensure that the instruction which gets matched for any
378 /// particular list of operands is deterministic.
380 /// The target specific parser must be able to classify a parsed operand into a
381 /// unique class which does not partially overlap with any other classes. It can
382 /// match a subset of some other class, in which case the super class field
383 /// should be defined.
384 class AsmOperandClass {
385 /// The name to use for this class, which should be usable as an enum value.
388 /// The super classes of this operand.
389 list<AsmOperandClass> SuperClasses = [];
391 /// The name of the method on the target specific operand to call to test
392 /// whether the operand is an instance of this class. If not set, this will
393 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
394 /// signature should be:
395 /// bool isFoo() const;
396 string PredicateMethod = ?;
398 /// The name of the method on the target specific operand to call to add the
399 /// target specific operand to an MCInst. If not set, this will default to
400 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
401 /// signature should be:
402 /// void addFooOperands(MCInst &Inst, unsigned N) const;
403 string RenderMethod = ?;
405 /// The name of the method on the target specific operand to call to custom
406 /// handle the operand parsing. This is useful when the operands do not relate
407 /// to immediates or registers and are very instruction specific (as flags to
408 /// set in a processor register, coprocessor number, ...).
409 string ParserMethod = ?;
412 def ImmAsmOperand : AsmOperandClass {
416 /// Operand Types - These provide the built-in operand types that may be used
417 /// by a target. Targets can optionally provide their own operand types as
418 /// needed, though this should not be needed for RISC targets.
419 class Operand<ValueType ty> {
421 string PrintMethod = "printOperand";
422 string EncoderMethod = "";
423 string DecoderMethod = "";
424 string AsmOperandLowerMethod = ?;
425 dag MIOperandInfo = (ops);
427 // ParserMatchClass - The "match class" that operands of this type fit
428 // in. Match classes are used to define the order in which instructions are
429 // match, to ensure that which instructions gets matched is deterministic.
431 // The target specific parser must be able to classify an parsed operand into
432 // a unique class, which does not partially overlap with any other classes. It
433 // can match a subset of some other class, in which case the AsmOperandClass
434 // should declare the other operand as one of its super classes.
435 AsmOperandClass ParserMatchClass = ImmAsmOperand;
438 def i1imm : Operand<i1>;
439 def i8imm : Operand<i8>;
440 def i16imm : Operand<i16>;
441 def i32imm : Operand<i32>;
442 def i64imm : Operand<i64>;
444 def f32imm : Operand<f32>;
445 def f64imm : Operand<f64>;
447 /// zero_reg definition - Special node to stand for the zero register.
451 /// PredicateOperand - This can be used to define a predicate operand for an
452 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
453 /// AlwaysVal specifies the value of this predicate when set to "always
455 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
457 let MIOperandInfo = OpTypes;
458 dag DefaultOps = AlwaysVal;
461 /// OptionalDefOperand - This is used to define a optional definition operand
462 /// for an instruction. DefaultOps is the register the operand represents if
463 /// none is supplied, e.g. zero_reg.
464 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
466 let MIOperandInfo = OpTypes;
467 dag DefaultOps = defaultops;
471 // InstrInfo - This class should only be instantiated once to provide parameters
472 // which are global to the target machine.
475 // Target can specify its instructions in either big or little-endian formats.
476 // For instance, while both Sparc and PowerPC are big-endian platforms, the
477 // Sparc manual specifies its instructions in the format [31..0] (big), while
478 // PowerPC specifies them using the format [0..31] (little).
479 bit isLittleEndianEncoding = 0;
482 // Standard Pseudo Instructions.
483 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
484 // Only these instructions are allowed in the TargetOpcode namespace.
485 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
486 def PHI : Instruction {
487 let OutOperandList = (outs);
488 let InOperandList = (ins variable_ops);
489 let AsmString = "PHINODE";
491 def INLINEASM : Instruction {
492 let OutOperandList = (outs);
493 let InOperandList = (ins variable_ops);
495 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
497 def PROLOG_LABEL : Instruction {
498 let OutOperandList = (outs);
499 let InOperandList = (ins i32imm:$id);
502 let isNotDuplicable = 1;
504 def EH_LABEL : Instruction {
505 let OutOperandList = (outs);
506 let InOperandList = (ins i32imm:$id);
509 let isNotDuplicable = 1;
511 def GC_LABEL : Instruction {
512 let OutOperandList = (outs);
513 let InOperandList = (ins i32imm:$id);
516 let isNotDuplicable = 1;
518 def KILL : Instruction {
519 let OutOperandList = (outs);
520 let InOperandList = (ins variable_ops);
522 let neverHasSideEffects = 1;
524 def EXTRACT_SUBREG : Instruction {
525 let OutOperandList = (outs unknown:$dst);
526 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
528 let neverHasSideEffects = 1;
530 def INSERT_SUBREG : Instruction {
531 let OutOperandList = (outs unknown:$dst);
532 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
534 let neverHasSideEffects = 1;
535 let Constraints = "$supersrc = $dst";
537 def IMPLICIT_DEF : Instruction {
538 let OutOperandList = (outs unknown:$dst);
539 let InOperandList = (ins);
541 let neverHasSideEffects = 1;
542 let isReMaterializable = 1;
543 let isAsCheapAsAMove = 1;
545 def SUBREG_TO_REG : Instruction {
546 let OutOperandList = (outs unknown:$dst);
547 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
549 let neverHasSideEffects = 1;
551 def COPY_TO_REGCLASS : Instruction {
552 let OutOperandList = (outs unknown:$dst);
553 let InOperandList = (ins unknown:$src, i32imm:$regclass);
555 let neverHasSideEffects = 1;
556 let isAsCheapAsAMove = 1;
558 def DBG_VALUE : Instruction {
559 let OutOperandList = (outs);
560 let InOperandList = (ins variable_ops);
561 let AsmString = "DBG_VALUE";
562 let neverHasSideEffects = 1;
564 def REG_SEQUENCE : Instruction {
565 let OutOperandList = (outs unknown:$dst);
566 let InOperandList = (ins variable_ops);
568 let neverHasSideEffects = 1;
569 let isAsCheapAsAMove = 1;
571 def COPY : Instruction {
572 let OutOperandList = (outs unknown:$dst);
573 let InOperandList = (ins unknown:$src);
575 let neverHasSideEffects = 1;
576 let isAsCheapAsAMove = 1;
580 //===----------------------------------------------------------------------===//
581 // AsmParser - This class can be implemented by targets that wish to implement
584 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
585 // syntax on X86 for example).
588 // AsmParserClassName - This specifies the suffix to use for the asmparser
589 // class. Generated AsmParser classes are always prefixed with the target
591 string AsmParserClassName = "AsmParser";
593 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
594 // function of the AsmParser class to call on every matched instruction.
595 // This can be used to perform target specific instruction post-processing.
596 string AsmParserInstCleanup = "";
598 // Variant - AsmParsers can be of multiple different variants. Variants are
599 // used to support targets that need to parser multiple formats for the
600 // assembly language.
603 // CommentDelimiter - If given, the delimiter string used to recognize
604 // comments which are hard coded in the .td assembler strings for individual
606 string CommentDelimiter = "";
608 // RegisterPrefix - If given, the token prefix which indicates a register
609 // token. This is used by the matcher to automatically recognize hard coded
610 // register tokens as constrained registers, instead of tokens, for the
611 // purposes of matching.
612 string RegisterPrefix = "";
614 def DefaultAsmParser : AsmParser;
616 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
617 /// matches instructions and aliases.
618 class AssemblerPredicate {
619 bit AssemblerMatcherPredicate = 1;
624 /// MnemonicAlias - This class allows targets to define assembler mnemonic
625 /// aliases. This should be used when all forms of one mnemonic are accepted
626 /// with a different mnemonic. For example, X86 allows:
627 /// sal %al, 1 -> shl %al, 1
628 /// sal %ax, %cl -> shl %ax, %cl
629 /// sal %eax, %cl -> shl %eax, %cl
630 /// etc. Though "sal" is accepted with many forms, all of them are directly
631 /// translated to a shl, so it can be handled with (in the case of X86, it
632 /// actually has one for each suffix as well):
633 /// def : MnemonicAlias<"sal", "shl">;
635 /// Mnemonic aliases are mapped before any other translation in the match phase,
636 /// and do allow Requires predicates, e.g.:
638 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
639 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
641 class MnemonicAlias<string From, string To> {
642 string FromMnemonic = From;
643 string ToMnemonic = To;
645 // Predicates - Predicates that must be true for this remapping to happen.
646 list<Predicate> Predicates = [];
649 /// InstAlias - This defines an alternate assembly syntax that is allowed to
650 /// match an instruction that has a different (more canonical) assembly
652 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
653 string AsmString = Asm; // The .s format to match the instruction with.
654 dag ResultInst = Result; // The MCInst to generate.
655 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
657 // Predicates - Predicates that must be true for this to match.
658 list<Predicate> Predicates = [];
661 //===----------------------------------------------------------------------===//
662 // AsmWriter - This class can be implemented by targets that need to customize
663 // the format of the .s file writer.
665 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
666 // on X86 for example).
669 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
670 // class. Generated AsmWriter classes are always prefixed with the target
672 string AsmWriterClassName = "AsmPrinter";
674 // Variant - AsmWriters can be of multiple different variants. Variants are
675 // used to support targets that need to emit assembly code in ways that are
676 // mostly the same for different targets, but have minor differences in
677 // syntax. If the asmstring contains {|} characters in them, this integer
678 // will specify which alternative to use. For example "{x|y|z}" with Variant
679 // == 1, will expand to "y".
683 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
684 // layout, the asmwriter can actually generate output in this columns (in
685 // verbose-asm mode). These two values indicate the width of the first column
686 // (the "opcode" area) and the width to reserve for subsequent operands. When
687 // verbose asm mode is enabled, operands will be indented to respect this.
688 int FirstOperandColumn = -1;
690 // OperandSpacing - Space between operand columns.
691 int OperandSpacing = -1;
693 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
694 // generation of the printInstruction() method. For MC printers, it takes
695 // an MCInstr* operand, otherwise it takes a MachineInstr*.
696 bit isMCAsmWriter = 0;
698 def DefaultAsmWriter : AsmWriter;
701 //===----------------------------------------------------------------------===//
702 // Target - This class contains the "global" target information
705 // InstructionSet - Instruction set description for this target.
706 InstrInfo InstructionSet;
708 // AssemblyParsers - The AsmParser instances available for this target.
709 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
711 // AssemblyWriters - The AsmWriter instances available for this target.
712 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
715 //===----------------------------------------------------------------------===//
716 // SubtargetFeature - A characteristic of the chip set.
718 class SubtargetFeature<string n, string a, string v, string d,
719 list<SubtargetFeature> i = []> {
720 // Name - Feature name. Used by command line (-mattr=) to determine the
721 // appropriate target chip.
725 // Attribute - Attribute to be set by feature.
727 string Attribute = a;
729 // Value - Value the attribute to be set to by feature.
733 // Desc - Feature description. Used by command line (-mattr=) to display help
738 // Implies - Features that this feature implies are present. If one of those
739 // features isn't set, then this one shouldn't be set either.
741 list<SubtargetFeature> Implies = i;
744 //===----------------------------------------------------------------------===//
745 // Processor chip sets - These values represent each of the chip sets supported
746 // by the scheduler. Each Processor definition requires corresponding
747 // instruction itineraries.
749 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
750 // Name - Chip set name. Used by command line (-mcpu=) to determine the
751 // appropriate target chip.
755 // ProcItin - The scheduling information for the target processor.
757 ProcessorItineraries ProcItin = pi;
759 // Features - list of
760 list<SubtargetFeature> Features = f;
763 //===----------------------------------------------------------------------===//
764 // Pull in the common support for calling conventions.
766 include "llvm/Target/TargetCallingConv.td"
768 //===----------------------------------------------------------------------===//
769 // Pull in the common support for DAG isel generation.
771 include "llvm/Target/TargetSelectionDAG.td"