include/llvm/CodeGen/SchedulerRegistry.h

   1 //===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the implementation for instruction scheduler function
  11 // pass registry (RegisterScheduler).
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
  16 #define LLVM_CODEGEN_SCHEDULERREGISTRY_H
  17
  18 #include "llvm/CodeGen/MachinePassRegistry.h"
  19 #include "llvm/Target/TargetMachine.h"
  20
  21 namespace llvm {
  22
  23 //===----------------------------------------------------------------------===//
  24 ///
  25 /// RegisterScheduler class - Track the registration of instruction schedulers.
  26 ///
  27 //===----------------------------------------------------------------------===//
  28
  29 class SelectionDAGISel;
  30 class ScheduleDAGSDNodes;
  31 class SelectionDAG;
  32 class MachineBasicBlock;
  33
  34 class RegisterScheduler : public MachinePassRegistryNode {
  35 public:
  36   typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
  37                                                   CodeGenOpt::Level);
  38
  39   static MachinePassRegistry Registry;
  40
  41   RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
  42   : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
  43   { Registry.Add(this); }
  44   ~RegisterScheduler() { Registry.Remove(this); }
  45
  46
  47   // Accessors.
  48   //
  49   RegisterScheduler *getNext() const {
  50     return (RegisterScheduler *)MachinePassRegistryNode::getNext();
  51   }
  52   static RegisterScheduler *getList() {
  53     return (RegisterScheduler *)Registry.getList();
  54   }
  55   static FunctionPassCtor getDefault() {
  56     return (FunctionPassCtor)Registry.getDefault();
  57   }
  58   static void setDefault(FunctionPassCtor C) {
  59     Registry.setDefault((MachinePassCtor)C);
  60   }
  61   static void setListener(MachinePassRegistryListener *L) {
  62     Registry.setListener(L);
  63   }
  64 };
  65
  66 /// createBURRListDAGScheduler - This creates a bottom up register usage
  67 /// reduction list scheduler.
  68 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
  69                                                CodeGenOpt::Level OptLevel);
  70
  71 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
  72 /// schedules nodes in source code order when possible.
  73 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
  74                                                  CodeGenOpt::Level OptLevel);
  75
  76 /// createHybridListDAGScheduler - This creates a bottom up register pressure
  77 /// aware list scheduler that make use of latency information to avoid stalls
  78 /// for long latency instructions in low register pressure mode. In high
  79 /// register pressure mode it schedules to reduce register pressure.
  80 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
  81                                                  CodeGenOpt::Level);
  82
  83 /// createILPListDAGScheduler - This creates a bottom up register pressure
  84 /// aware list scheduler that tries to increase instruction level parallelism
  85 /// in low register pressure mode. In high register pressure mode it schedules
  86 /// to reduce register pressure.
  87 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
  88                                               CodeGenOpt::Level);
  89
  90 /// createFastDAGScheduler - This creates a "fast" scheduler.
  91 ///
  92 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
  93                                            CodeGenOpt::Level OptLevel);
  94
  95 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
  96 /// DFA driven list scheduler with clustering heuristic to control
  97 /// register pressure.
  98 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
  99                                            CodeGenOpt::Level OptLevel);
 100 /// createDefaultScheduler - This creates an instruction scheduler appropriate
 101 /// for the target.
 102 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
 103                                            CodeGenOpt::Level OptLevel);
 104
 105 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
 106 /// linearize the DAG using topological order.
 107 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
 108                                         CodeGenOpt::Level OptLevel);
 109
 110 } // end namespace llvm
 111
 112 #endif