1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/Support/ArrayRecycler.h"
32 #include "llvm/Target/TargetOpcodes.h"
36 template <typename T> class SmallVectorImpl;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
44 //===----------------------------------------------------------------------===//
45 /// MachineInstr - Representation of each machine instruction.
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
51 class MachineInstr : public ilist_node<MachineInstr> {
53 typedef MachineMemOperand **mmo_iterator;
55 /// Flags to specify different kinds of comments to output in
56 /// assembly code. These flags carry semantic information not
57 /// otherwise easily derivable from the IR text.
65 FrameSetup = 1 << 0, // Instruction is used as a part of
66 // function frame setup code.
67 BundledPred = 1 << 1, // Instruction has bundled predecessors.
68 BundledSucc = 1 << 2 // Instruction has bundled successors.
71 const MCInstrDesc *MCID; // Instruction descriptor.
72 MachineBasicBlock *Parent; // Pointer to the owning basic block.
74 // Operands are allocated by an ArrayRecycler.
75 MachineOperand *Operands; // Pointer to the first operand.
76 unsigned NumOperands; // Number of operands on instruction.
77 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
78 OperandCapacity CapOperands; // Capacity of the Operands array.
80 uint8_t Flags; // Various bits of additional
81 // information about machine
84 uint8_t AsmPrinterFlags; // Various bits of information used by
85 // the AsmPrinter to emit helpful
86 // comments. This is *not* semantic
87 // information. Do not use this for
88 // anything other than to convey comment
89 // information to AsmPrinter.
91 uint8_t NumMemRefs; // Information on memory references.
94 DebugLoc debugLoc; // Source line information.
96 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
97 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
98 // Use MachineFunction::DeleteMachineInstr() instead.
99 ~MachineInstr() LLVM_DELETED_FUNCTION;
101 // Intrusive list support
102 friend struct ilist_traits<MachineInstr>;
103 friend struct ilist_traits<MachineBasicBlock>;
104 void setParent(MachineBasicBlock *P) { Parent = P; }
106 /// MachineInstr ctor - This constructor creates a copy of the given
107 /// MachineInstr in the given MachineFunction.
108 MachineInstr(MachineFunction &, const MachineInstr &);
110 /// MachineInstr ctor - This constructor create a MachineInstr and add the
111 /// implicit operands. It reserves space for number of operands specified by
112 /// MCInstrDesc. An explicit DebugLoc is supplied.
113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
114 const DebugLoc dl, bool NoImp = false);
116 // MachineInstrs are pool-allocated and owned by MachineFunction.
117 friend class MachineFunction;
120 const MachineBasicBlock* getParent() const { return Parent; }
121 MachineBasicBlock* getParent() { return Parent; }
123 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
125 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
127 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
129 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
131 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
133 bool getAsmPrinterFlag(CommentFlag Flag) const {
134 return AsmPrinterFlags & Flag;
137 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
139 void setAsmPrinterFlag(CommentFlag Flag) {
140 AsmPrinterFlags |= (uint8_t)Flag;
143 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
145 void clearAsmPrinterFlag(CommentFlag Flag) {
146 AsmPrinterFlags &= ~Flag;
149 /// getFlags - Return the MI flags bitvector.
150 uint8_t getFlags() const {
154 /// getFlag - Return whether an MI flag is set.
155 bool getFlag(MIFlag Flag) const {
159 /// setFlag - Set a MI flag.
160 void setFlag(MIFlag Flag) {
161 Flags |= (uint8_t)Flag;
164 void setFlags(unsigned flags) {
165 // Filter out the automatically maintained flags.
166 unsigned Mask = BundledPred | BundledSucc;
167 Flags = (Flags & Mask) | (flags & ~Mask);
170 /// clearFlag - Clear a MI flag.
171 void clearFlag(MIFlag Flag) {
172 Flags &= ~((uint8_t)Flag);
175 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
178 /// A bundle looks like this before it's finalized:
190 /// In this case, the first MI starts a bundle but is not inside a bundle, the
191 /// next 2 MIs are considered "inside" the bundle.
193 /// After a bundle is finalized, it looks like this:
209 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
210 /// a bundle, but the next three MIs are.
211 bool isInsideBundle() const {
212 return getFlag(BundledPred);
215 /// isBundled - Return true if this instruction part of a bundle. This is true
216 /// if either itself or its following instruction is marked "InsideBundle".
217 bool isBundled() const {
218 return isBundledWithPred() || isBundledWithSucc();
221 /// Return true if this instruction is part of a bundle, and it is not the
222 /// first instruction in the bundle.
223 bool isBundledWithPred() const { return getFlag(BundledPred); }
225 /// Return true if this instruction is part of a bundle, and it is not the
226 /// last instruction in the bundle.
227 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
229 /// Bundle this instruction with its predecessor. This can be an unbundled
230 /// instruction, or it can be the first instruction in a bundle.
231 void bundleWithPred();
233 /// Bundle this instruction with its successor. This can be an unbundled
234 /// instruction, or it can be the last instruction in a bundle.
235 void bundleWithSucc();
237 /// Break bundle above this instruction.
238 void unbundleFromPred();
240 /// Break bundle below this instruction.
241 void unbundleFromSucc();
243 /// getDebugLoc - Returns the debug location id of this MachineInstr.
245 DebugLoc getDebugLoc() const { return debugLoc; }
247 /// getDebugVariable() - Return the debug variable referenced by
248 /// this DBG_VALUE instruction.
249 DIVariable getDebugVariable() const {
250 assert(isDebugValue() && "not a DBG_VALUE");
251 const MDNode *Var = getOperand(getNumOperands() - 1).getMetadata();
252 return DIVariable(Var);
255 /// emitError - Emit an error referring to the source location of this
256 /// instruction. This should only be used for inline assembly that is somehow
257 /// impossible to compile. Other errors should have been handled much
260 /// If this method returns, the caller should try to recover from the error.
262 void emitError(StringRef Msg) const;
264 /// getDesc - Returns the target instruction descriptor of this
266 const MCInstrDesc &getDesc() const { return *MCID; }
268 /// getOpcode - Returns the opcode of this MachineInstr.
270 int getOpcode() const { return MCID->Opcode; }
272 /// Access to explicit operands of the instruction.
274 unsigned getNumOperands() const { return NumOperands; }
276 const MachineOperand& getOperand(unsigned i) const {
277 assert(i < getNumOperands() && "getOperand() out of range!");
280 MachineOperand& getOperand(unsigned i) {
281 assert(i < getNumOperands() && "getOperand() out of range!");
285 /// getNumExplicitOperands - Returns the number of non-implicit operands.
287 unsigned getNumExplicitOperands() const;
289 /// iterator/begin/end - Iterate over all operands of a machine instruction.
290 typedef MachineOperand *mop_iterator;
291 typedef const MachineOperand *const_mop_iterator;
293 mop_iterator operands_begin() { return Operands; }
294 mop_iterator operands_end() { return Operands + NumOperands; }
296 const_mop_iterator operands_begin() const { return Operands; }
297 const_mop_iterator operands_end() const { return Operands + NumOperands; }
299 iterator_range<mop_iterator> operands() {
300 return iterator_range<mop_iterator>(operands_begin(), operands_end());
302 iterator_range<const_mop_iterator> operands() const {
303 return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
305 iterator_range<mop_iterator> explicit_operands() {
306 return iterator_range<mop_iterator>(
307 operands_begin(), operands_begin() + getNumExplicitOperands());
309 iterator_range<const_mop_iterator> explicit_operands() const {
310 return iterator_range<const_mop_iterator>(
311 operands_begin(), operands_begin() + getNumExplicitOperands());
313 iterator_range<mop_iterator> implicit_operands() {
314 return iterator_range<mop_iterator>(explicit_operands().end(),
317 iterator_range<const_mop_iterator> implicit_operands() const {
318 return iterator_range<const_mop_iterator>(explicit_operands().end(),
321 iterator_range<mop_iterator> defs() {
322 return iterator_range<mop_iterator>(
323 operands_begin(), operands_begin() + getDesc().getNumDefs());
325 iterator_range<const_mop_iterator> defs() const {
326 return iterator_range<const_mop_iterator>(
327 operands_begin(), operands_begin() + getDesc().getNumDefs());
329 iterator_range<mop_iterator> uses() {
330 return iterator_range<mop_iterator>(
331 operands_begin() + getDesc().getNumDefs(), operands_end());
333 iterator_range<const_mop_iterator> uses() const {
334 return iterator_range<const_mop_iterator>(
335 operands_begin() + getDesc().getNumDefs(), operands_end());
338 /// Access to memory operands of the instruction
339 mmo_iterator memoperands_begin() const { return MemRefs; }
340 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
341 bool memoperands_empty() const { return NumMemRefs == 0; }
343 iterator_range<mmo_iterator> memoperands() {
344 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
346 iterator_range<mmo_iterator> memoperands() const {
347 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
350 /// hasOneMemOperand - Return true if this instruction has exactly one
351 /// MachineMemOperand.
352 bool hasOneMemOperand() const {
353 return NumMemRefs == 1;
356 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
357 /// queries but they are bundle aware.
360 IgnoreBundle, // Ignore bundles
361 AnyInBundle, // Return true if any instruction in bundle has property
362 AllInBundle // Return true if all instructions in bundle have property
365 /// hasProperty - Return true if the instruction (or in the case of a bundle,
366 /// the instructions inside the bundle) has the specified property.
367 /// The first argument is the property being queried.
368 /// The second argument indicates whether the query should look inside
369 /// instruction bundles.
370 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
371 // Inline the fast path for unbundled or bundle-internal instructions.
372 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
373 return getDesc().getFlags() & (1 << MCFlag);
375 // If this is the first instruction in a bundle, take the slow path.
376 return hasPropertyInBundle(1 << MCFlag, Type);
379 /// isVariadic - Return true if this instruction can have a variable number of
380 /// operands. In this case, the variable operands will be after the normal
381 /// operands but before the implicit definitions and uses (if any are
383 bool isVariadic(QueryType Type = IgnoreBundle) const {
384 return hasProperty(MCID::Variadic, Type);
387 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
388 /// ARM instructions which can set condition code if 's' bit is set.
389 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
390 return hasProperty(MCID::HasOptionalDef, Type);
393 /// isPseudo - Return true if this is a pseudo instruction that doesn't
394 /// correspond to a real machine instruction.
396 bool isPseudo(QueryType Type = IgnoreBundle) const {
397 return hasProperty(MCID::Pseudo, Type);
400 bool isReturn(QueryType Type = AnyInBundle) const {
401 return hasProperty(MCID::Return, Type);
404 bool isCall(QueryType Type = AnyInBundle) const {
405 return hasProperty(MCID::Call, Type);
408 /// isBarrier - Returns true if the specified instruction stops control flow
409 /// from executing the instruction immediately following it. Examples include
410 /// unconditional branches and return instructions.
411 bool isBarrier(QueryType Type = AnyInBundle) const {
412 return hasProperty(MCID::Barrier, Type);
415 /// isTerminator - Returns true if this instruction part of the terminator for
416 /// a basic block. Typically this is things like return and branch
419 /// Various passes use this to insert code into the bottom of a basic block,
420 /// but before control flow occurs.
421 bool isTerminator(QueryType Type = AnyInBundle) const {
422 return hasProperty(MCID::Terminator, Type);
425 /// isBranch - Returns true if this is a conditional, unconditional, or
426 /// indirect branch. Predicates below can be used to discriminate between
427 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
428 /// get more information.
429 bool isBranch(QueryType Type = AnyInBundle) const {
430 return hasProperty(MCID::Branch, Type);
433 /// isIndirectBranch - Return true if this is an indirect branch, such as a
434 /// branch through a register.
435 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
436 return hasProperty(MCID::IndirectBranch, Type);
439 /// isConditionalBranch - Return true if this is a branch which may fall
440 /// through to the next instruction or may transfer control flow to some other
441 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
442 /// information about this branch.
443 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
444 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
447 /// isUnconditionalBranch - Return true if this is a branch which always
448 /// transfers control flow to some other block. The
449 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
450 /// about this branch.
451 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
452 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
455 /// Return true if this instruction has a predicate operand that
456 /// controls execution. It may be set to 'always', or may be set to other
457 /// values. There are various methods in TargetInstrInfo that can be used to
458 /// control and modify the predicate in this instruction.
459 bool isPredicable(QueryType Type = AllInBundle) const {
460 // If it's a bundle than all bundled instructions must be predicable for this
462 return hasProperty(MCID::Predicable, Type);
465 /// isCompare - Return true if this instruction is a comparison.
466 bool isCompare(QueryType Type = IgnoreBundle) const {
467 return hasProperty(MCID::Compare, Type);
470 /// isMoveImmediate - Return true if this instruction is a move immediate
471 /// (including conditional moves) instruction.
472 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
473 return hasProperty(MCID::MoveImm, Type);
476 /// isBitcast - Return true if this instruction is a bitcast instruction.
478 bool isBitcast(QueryType Type = IgnoreBundle) const {
479 return hasProperty(MCID::Bitcast, Type);
482 /// isSelect - Return true if this instruction is a select instruction.
484 bool isSelect(QueryType Type = IgnoreBundle) const {
485 return hasProperty(MCID::Select, Type);
488 /// isNotDuplicable - Return true if this instruction cannot be safely
489 /// duplicated. For example, if the instruction has a unique labels attached
490 /// to it, duplicating it would cause multiple definition errors.
491 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
492 return hasProperty(MCID::NotDuplicable, Type);
495 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
496 /// which must be filled by the code generator.
497 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
498 return hasProperty(MCID::DelaySlot, Type);
501 /// canFoldAsLoad - Return true for instructions that can be folded as
502 /// memory operands in other instructions. The most common use for this
503 /// is instructions that are simple loads from memory that don't modify
504 /// the loaded value in any way, but it can also be used for instructions
505 /// that can be expressed as constant-pool loads, such as V_SETALLONES
506 /// on x86, to allow them to be folded when it is beneficial.
507 /// This should only be set on instructions that return a value in their
508 /// only virtual register definition.
509 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
510 return hasProperty(MCID::FoldableAsLoad, Type);
513 /// \brief Return true if this instruction behaves
514 /// the same way as the generic REG_SEQUENCE instructions.
516 /// dX VMOVDRR rY, rZ
518 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
520 /// Note that for the optimizers to be able to take advantage of
521 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
522 /// override accordingly.
523 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
524 return hasProperty(MCID::RegSequence, Type);
527 /// \brief Return true if this instruction behaves
528 /// the same way as the generic EXTRACT_SUBREG instructions.
530 /// rX, rY VMOVRRD dZ
531 /// is equivalent to two EXTRACT_SUBREG:
532 /// rX = EXTRACT_SUBREG dZ, ssub_0
533 /// rY = EXTRACT_SUBREG dZ, ssub_1
535 /// Note that for the optimizers to be able to take advantage of
536 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
537 /// override accordingly.
538 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
539 return hasProperty(MCID::ExtractSubreg, Type);
542 /// \brief Return true if this instruction behaves
543 /// the same way as the generic INSERT_SUBREG instructions.
545 /// dX = VSETLNi32 dY, rZ, Imm
546 /// is equivalent to a INSERT_SUBREG:
547 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
549 /// Note that for the optimizers to be able to take advantage of
550 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
551 /// override accordingly.
552 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
553 return hasProperty(MCID::InsertSubreg, Type);
556 //===--------------------------------------------------------------------===//
557 // Side Effect Analysis
558 //===--------------------------------------------------------------------===//
560 /// mayLoad - Return true if this instruction could possibly read memory.
561 /// Instructions with this flag set are not necessarily simple load
562 /// instructions, they may load a value and modify it, for example.
563 bool mayLoad(QueryType Type = AnyInBundle) const {
565 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
566 if (ExtraInfo & InlineAsm::Extra_MayLoad)
569 return hasProperty(MCID::MayLoad, Type);
573 /// mayStore - Return true if this instruction could possibly modify memory.
574 /// Instructions with this flag set are not necessarily simple store
575 /// instructions, they may store a modified value based on their operands, or
576 /// may not actually modify anything, for example.
577 bool mayStore(QueryType Type = AnyInBundle) const {
579 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
580 if (ExtraInfo & InlineAsm::Extra_MayStore)
583 return hasProperty(MCID::MayStore, Type);
586 //===--------------------------------------------------------------------===//
587 // Flags that indicate whether an instruction can be modified by a method.
588 //===--------------------------------------------------------------------===//
590 /// isCommutable - Return true if this may be a 2- or 3-address
591 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
592 /// result if Y and Z are exchanged. If this flag is set, then the
593 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
596 /// Note that this flag may be set on instructions that are only commutable
597 /// sometimes. In these cases, the call to commuteInstruction will fail.
598 /// Also note that some instructions require non-trivial modification to
600 bool isCommutable(QueryType Type = IgnoreBundle) const {
601 return hasProperty(MCID::Commutable, Type);
604 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
605 /// which can be changed into a 3-address instruction if needed. Doing this
606 /// transformation can be profitable in the register allocator, because it
607 /// means that the instruction can use a 2-address form if possible, but
608 /// degrade into a less efficient form if the source and dest register cannot
609 /// be assigned to the same register. For example, this allows the x86
610 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
611 /// is the same speed as the shift but has bigger code size.
613 /// If this returns true, then the target must implement the
614 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
615 /// is allowed to fail if the transformation isn't valid for this specific
616 /// instruction (e.g. shl reg, 4 on x86).
618 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
619 return hasProperty(MCID::ConvertibleTo3Addr, Type);
622 /// usesCustomInsertionHook - Return true if this instruction requires
623 /// custom insertion support when the DAG scheduler is inserting it into a
624 /// machine basic block. If this is true for the instruction, it basically
625 /// means that it is a pseudo instruction used at SelectionDAG time that is
626 /// expanded out into magic code by the target when MachineInstrs are formed.
628 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
629 /// is used to insert this into the MachineBasicBlock.
630 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
631 return hasProperty(MCID::UsesCustomInserter, Type);
634 /// hasPostISelHook - Return true if this instruction requires *adjustment*
635 /// after instruction selection by calling a target hook. For example, this
636 /// can be used to fill in ARM 's' optional operand depending on whether
637 /// the conditional flag register is used.
638 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
639 return hasProperty(MCID::HasPostISelHook, Type);
642 /// isRematerializable - Returns true if this instruction is a candidate for
643 /// remat. This flag is deprecated, please don't use it anymore. If this
644 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
645 /// verify the instruction is really rematable.
646 bool isRematerializable(QueryType Type = AllInBundle) const {
647 // It's only possible to re-mat a bundle if all bundled instructions are
648 // re-materializable.
649 return hasProperty(MCID::Rematerializable, Type);
652 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
653 /// less) than a move instruction. This is useful during certain types of
654 /// optimizations (e.g., remat during two-address conversion or machine licm)
655 /// where we would like to remat or hoist the instruction, but not if it costs
656 /// more than moving the instruction into the appropriate register. Note, we
657 /// are not marking copies from and to the same register class with this flag.
658 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
659 // Only returns true for a bundle if all bundled instructions are cheap.
660 return hasProperty(MCID::CheapAsAMove, Type);
663 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
664 /// have special register allocation requirements that are not captured by the
665 /// operand register classes. e.g. ARM::STRD's two source registers must be an
666 /// even / odd pair, ARM::STM registers have to be in ascending order.
667 /// Post-register allocation passes should not attempt to change allocations
668 /// for sources of instructions with this flag.
669 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
670 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
673 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
674 /// have special register allocation requirements that are not captured by the
675 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
676 /// even / odd pair, ARM::LDM registers have to be in ascending order.
677 /// Post-register allocation passes should not attempt to change allocations
678 /// for definitions of instructions with this flag.
679 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
680 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
685 CheckDefs, // Check all operands for equality
686 CheckKillDead, // Check all operands including kill / dead markers
687 IgnoreDefs, // Ignore all definitions
688 IgnoreVRegDefs // Ignore virtual register definitions
691 /// isIdenticalTo - Return true if this instruction is identical to (same
692 /// opcode and same operands as) the specified instruction.
693 bool isIdenticalTo(const MachineInstr *Other,
694 MICheckType Check = CheckDefs) const;
696 /// Unlink 'this' from the containing basic block, and return it without
699 /// This function can not be used on bundled instructions, use
700 /// removeFromBundle() to remove individual instructions from a bundle.
701 MachineInstr *removeFromParent();
703 /// Unlink this instruction from its basic block and return it without
706 /// If the instruction is part of a bundle, the other instructions in the
707 /// bundle remain bundled.
708 MachineInstr *removeFromBundle();
710 /// Unlink 'this' from the containing basic block and delete it.
712 /// If this instruction is the header of a bundle, the whole bundle is erased.
713 /// This function can not be used for instructions inside a bundle, use
714 /// eraseFromBundle() to erase individual bundled instructions.
715 void eraseFromParent();
717 /// Unlink 'this' from the containing basic block and delete it.
719 /// For all definitions mark their uses in DBG_VALUE nodes
720 /// as undefined. Otherwise like eraseFromParent().
721 void eraseFromParentAndMarkDBGValuesForRemoval();
723 /// Unlink 'this' form its basic block and delete it.
725 /// If the instruction is part of a bundle, the other instructions in the
726 /// bundle remain bundled.
727 void eraseFromBundle();
729 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
730 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
732 /// isLabel - Returns true if the MachineInstr represents a label.
734 bool isLabel() const { return isEHLabel() || isGCLabel(); }
735 bool isCFIInstruction() const {
736 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
739 // True if the instruction represents a position in the function.
740 bool isPosition() const { return isLabel() || isCFIInstruction(); }
742 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
743 /// A DBG_VALUE is indirect iff the first operand is a register and
744 /// the second operand is an immediate.
745 bool isIndirectDebugValue() const {
746 return isDebugValue()
747 && getOperand(0).isReg()
748 && getOperand(1).isImm();
751 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
752 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
753 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
754 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
755 bool isMSInlineAsm() const {
756 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
758 bool isStackAligningInlineAsm() const;
759 InlineAsm::AsmDialect getInlineAsmDialect() const;
760 bool isInsertSubreg() const {
761 return getOpcode() == TargetOpcode::INSERT_SUBREG;
763 bool isSubregToReg() const {
764 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
766 bool isRegSequence() const {
767 return getOpcode() == TargetOpcode::REG_SEQUENCE;
769 bool isBundle() const {
770 return getOpcode() == TargetOpcode::BUNDLE;
772 bool isCopy() const {
773 return getOpcode() == TargetOpcode::COPY;
775 bool isFullCopy() const {
776 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
778 bool isExtractSubreg() const {
779 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
782 /// isCopyLike - Return true if the instruction behaves like a copy.
783 /// This does not include native copy instructions.
784 bool isCopyLike() const {
785 return isCopy() || isSubregToReg();
788 /// isIdentityCopy - Return true is the instruction is an identity copy.
789 bool isIdentityCopy() const {
790 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
791 getOperand(0).getSubReg() == getOperand(1).getSubReg();
794 /// isTransient - Return true if this is a transient instruction that is
795 /// either very likely to be eliminated during register allocation (such as
796 /// copy-like instructions), or if this instruction doesn't have an
797 /// execution-time cost.
798 bool isTransient() const {
799 switch(getOpcode()) {
800 default: return false;
801 // Copy-like instructions are usually eliminated during register allocation.
802 case TargetOpcode::PHI:
803 case TargetOpcode::COPY:
804 case TargetOpcode::INSERT_SUBREG:
805 case TargetOpcode::SUBREG_TO_REG:
806 case TargetOpcode::REG_SEQUENCE:
807 // Pseudo-instructions that don't produce any real output.
808 case TargetOpcode::IMPLICIT_DEF:
809 case TargetOpcode::KILL:
810 case TargetOpcode::CFI_INSTRUCTION:
811 case TargetOpcode::EH_LABEL:
812 case TargetOpcode::GC_LABEL:
813 case TargetOpcode::DBG_VALUE:
818 /// Return the number of instructions inside the MI bundle, excluding the
821 /// This is the number of instructions that MachineBasicBlock::iterator
822 /// skips, 0 for unbundled instructions.
823 unsigned getBundleSize() const;
825 /// readsRegister - Return true if the MachineInstr reads the specified
826 /// register. If TargetRegisterInfo is passed, then it also checks if there
827 /// is a read of a super-register.
828 /// This does not count partial redefines of virtual registers as reads:
830 bool readsRegister(unsigned Reg,
831 const TargetRegisterInfo *TRI = nullptr) const {
832 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
835 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
836 /// virtual register. Take into account that a partial define is a
837 /// read-modify-write operation.
838 bool readsVirtualRegister(unsigned Reg) const {
839 return readsWritesVirtualRegister(Reg).first;
842 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
843 /// indicating if this instruction reads or writes Reg. This also considers
845 /// If Ops is not null, all operand indices for Reg are added.
846 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
847 SmallVectorImpl<unsigned> *Ops = nullptr) const;
849 /// killsRegister - Return true if the MachineInstr kills the specified
850 /// register. If TargetRegisterInfo is passed, then it also checks if there is
851 /// a kill of a super-register.
852 bool killsRegister(unsigned Reg,
853 const TargetRegisterInfo *TRI = nullptr) const {
854 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
857 /// definesRegister - Return true if the MachineInstr fully defines the
858 /// specified register. If TargetRegisterInfo is passed, then it also checks
859 /// if there is a def of a super-register.
860 /// NOTE: It's ignoring subreg indices on virtual registers.
861 bool definesRegister(unsigned Reg,
862 const TargetRegisterInfo *TRI = nullptr) const {
863 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
866 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
867 /// or partially define) the specified register.
868 /// NOTE: It's ignoring subreg indices on virtual registers.
869 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
870 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
873 /// registerDefIsDead - Returns true if the register is dead in this machine
874 /// instruction. If TargetRegisterInfo is passed, then it also checks
875 /// if there is a dead def of a super-register.
876 bool registerDefIsDead(unsigned Reg,
877 const TargetRegisterInfo *TRI = nullptr) const {
878 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
881 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
882 /// the specific register or -1 if it is not found. It further tightens
883 /// the search criteria to a use that kills the register if isKill is true.
884 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
885 const TargetRegisterInfo *TRI = nullptr) const;
887 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
888 /// a pointer to the MachineOperand rather than an index.
889 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
890 const TargetRegisterInfo *TRI = nullptr) {
891 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
892 return (Idx == -1) ? nullptr : &getOperand(Idx);
895 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
896 /// the specified register or -1 if it is not found. If isDead is true, defs
897 /// that are not dead are skipped. If Overlap is true, then it also looks for
898 /// defs that merely overlap the specified register. If TargetRegisterInfo is
899 /// non-null, then it also checks if there is a def of a super-register.
900 /// This may also return a register mask operand when Overlap is true.
901 int findRegisterDefOperandIdx(unsigned Reg,
902 bool isDead = false, bool Overlap = false,
903 const TargetRegisterInfo *TRI = nullptr) const;
905 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
906 /// a pointer to the MachineOperand rather than an index.
907 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
908 const TargetRegisterInfo *TRI = nullptr) {
909 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
910 return (Idx == -1) ? nullptr : &getOperand(Idx);
913 /// findFirstPredOperandIdx() - Find the index of the first operand in the
914 /// operand list that is used to represent the predicate. It returns -1 if
916 int findFirstPredOperandIdx() const;
918 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
919 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
920 /// getOperand(OpIdx) does not belong to an inline asm operand group.
922 /// If GroupNo is not NULL, it will receive the number of the operand group
923 /// containing OpIdx.
925 /// The flag operand is an immediate that can be decoded with methods like
926 /// InlineAsm::hasRegClassConstraint().
928 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
930 /// getRegClassConstraint - Compute the static register class constraint for
931 /// operand OpIdx. For normal instructions, this is derived from the
932 /// MCInstrDesc. For inline assembly it is derived from the flag words.
934 /// Returns NULL if the static register classs constraint cannot be
937 const TargetRegisterClass*
938 getRegClassConstraint(unsigned OpIdx,
939 const TargetInstrInfo *TII,
940 const TargetRegisterInfo *TRI) const;
942 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
943 /// the given \p CurRC.
944 /// If \p ExploreBundle is set and MI is part of a bundle, all the
945 /// instructions inside the bundle will be taken into account. In other words,
946 /// this method accumulates all the constrains of the operand of this MI and
947 /// the related bundle if MI is a bundle or inside a bundle.
949 /// Returns the register class that statisfies both \p CurRC and the
950 /// constraints set by MI. Returns NULL if such a register class does not
953 /// \pre CurRC must not be NULL.
954 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
955 unsigned Reg, const TargetRegisterClass *CurRC,
956 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
957 bool ExploreBundle = false) const;
959 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
960 /// to the given \p CurRC.
962 /// Returns the register class that statisfies both \p CurRC and the
963 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
966 /// \pre CurRC must not be NULL.
967 /// \pre The operand at \p OpIdx must be a register.
968 const TargetRegisterClass *
969 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
970 const TargetInstrInfo *TII,
971 const TargetRegisterInfo *TRI) const;
973 /// tieOperands - Add a tie between the register operands at DefIdx and
974 /// UseIdx. The tie will cause the register allocator to ensure that the two
975 /// operands are assigned the same physical register.
977 /// Tied operands are managed automatically for explicit operands in the
978 /// MCInstrDesc. This method is for exceptional cases like inline asm.
979 void tieOperands(unsigned DefIdx, unsigned UseIdx);
981 /// findTiedOperandIdx - Given the index of a tied register operand, find the
982 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
983 /// index of the tied operand which must exist.
984 unsigned findTiedOperandIdx(unsigned OpIdx) const;
986 /// isRegTiedToUseOperand - Given the index of a register def operand,
987 /// check if the register def is tied to a source operand, due to either
988 /// two-address elimination or inline assembly constraints. Returns the
989 /// first tied use operand index by reference if UseOpIdx is not null.
990 bool isRegTiedToUseOperand(unsigned DefOpIdx,
991 unsigned *UseOpIdx = nullptr) const {
992 const MachineOperand &MO = getOperand(DefOpIdx);
993 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
996 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1000 /// isRegTiedToDefOperand - Return true if the use operand of the specified
1001 /// index is tied to a def operand. It also returns the def operand index by
1002 /// reference if DefOpIdx is not null.
1003 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1004 unsigned *DefOpIdx = nullptr) const {
1005 const MachineOperand &MO = getOperand(UseOpIdx);
1006 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1009 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1013 /// clearKillInfo - Clears kill flags on all operands.
1015 void clearKillInfo();
1017 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
1018 /// properly composing subreg indices where necessary.
1019 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1020 const TargetRegisterInfo &RegInfo);
1022 /// addRegisterKilled - We have determined MI kills a register. Look for the
1023 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1024 /// add a implicit operand if it's not found. Returns true if the operand
1025 /// exists / is added.
1026 bool addRegisterKilled(unsigned IncomingReg,
1027 const TargetRegisterInfo *RegInfo,
1028 bool AddIfNotFound = false);
1030 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
1031 /// provided, this includes super-register kills.
1032 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1034 /// addRegisterDead - We have determined MI defined a register without a use.
1035 /// Look for the operand that defines it and mark it as IsDead. If
1036 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1037 /// true if the operand exists / is added.
1038 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1039 bool AddIfNotFound = false);
1041 /// addRegisterDefined - We have determined MI defines a register. Make sure
1042 /// there is an operand defining Reg.
1043 void addRegisterDefined(unsigned Reg,
1044 const TargetRegisterInfo *RegInfo = nullptr);
1046 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
1047 /// dead except those in the UsedRegs list.
1049 /// On instructions with register mask operands, also add implicit-def
1050 /// operands for all registers in UsedRegs.
1051 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1052 const TargetRegisterInfo &TRI);
1054 /// isSafeToMove - Return true if it is safe to move this instruction. If
1055 /// SawStore is set to true, it means that there is a store (or call) between
1056 /// the instruction's location and its intended destination.
1057 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
1058 bool &SawStore) const;
1060 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1061 /// or volatile memory reference, or if the information describing the memory
1062 /// reference is not available. Return false if it is known to have no
1063 /// ordered or volatile memory references.
1064 bool hasOrderedMemoryRef() const;
1066 /// isInvariantLoad - Return true if this instruction is loading from a
1067 /// location whose value is invariant across the function. For example,
1068 /// loading a value from the constant pool or from the argument area of
1069 /// a function if it does not change. This should only return true of *all*
1070 /// loads the instruction does are invariant (if it does multiple loads).
1071 bool isInvariantLoad(AliasAnalysis *AA) const;
1073 /// isConstantValuePHI - If the specified instruction is a PHI that always
1074 /// merges together the same virtual register, return the register, otherwise
1076 unsigned isConstantValuePHI() const;
1078 /// hasUnmodeledSideEffects - Return true if this instruction has side
1079 /// effects that are not modeled by mayLoad / mayStore, etc.
1080 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1081 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1082 /// INLINEASM instruction, in which case the side effect property is encoded
1083 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1085 bool hasUnmodeledSideEffects() const;
1087 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1089 bool allDefsAreDead() const;
1091 /// copyImplicitOps - Copy implicit register operands from specified
1092 /// instruction to this instruction.
1093 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1096 // Debugging support
1098 void print(raw_ostream &OS, const TargetMachine *TM = nullptr,
1099 bool SkipOpers = false) const;
1102 //===--------------------------------------------------------------------===//
1103 // Accessors used to build up machine instructions.
1105 /// Add the specified operand to the instruction. If it is an implicit
1106 /// operand, it is added to the end of the operand list. If it is an
1107 /// explicit operand it is added at the end of the explicit operand list
1108 /// (before the first implicit operand).
1110 /// MF must be the machine function that was used to allocate this
1113 /// MachineInstrBuilder provides a more convenient interface for creating
1114 /// instructions and adding operands.
1115 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1117 /// Add an operand without providing an MF reference. This only works for
1118 /// instructions that are inserted in a basic block.
1120 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1122 void addOperand(const MachineOperand &Op);
1124 /// setDesc - Replace the instruction descriptor (thus opcode) of
1125 /// the current instruction with a new one.
1127 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1129 /// setDebugLoc - Replace current source information with new such.
1130 /// Avoid using this, the constructor argument is preferable.
1132 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
1134 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
1135 /// fewer operand than it started with.
1137 void RemoveOperand(unsigned i);
1139 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
1140 /// This function should be used only occasionally. The setMemRefs function
1141 /// is the primary method for setting up a MachineInstr's MemRefs list.
1142 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1144 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
1145 /// list. This does not transfer ownership.
1146 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1147 MemRefs = NewMemRefs;
1148 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1149 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1153 /// getRegInfo - If this instruction is embedded into a MachineFunction,
1154 /// return the MachineRegisterInfo object for the current function, otherwise
1156 MachineRegisterInfo *getRegInfo();
1158 /// untieRegOperand - Break any tie involving OpIdx.
1159 void untieRegOperand(unsigned OpIdx) {
1160 MachineOperand &MO = getOperand(OpIdx);
1161 if (MO.isReg() && MO.isTied()) {
1162 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1167 /// addImplicitDefUseOperands - Add all implicit def and use operands to
1168 /// this instruction.
1169 void addImplicitDefUseOperands(MachineFunction &MF);
1171 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
1172 /// this instruction from their respective use lists. This requires that the
1173 /// operands already be on their use lists.
1174 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1176 /// AddRegOperandsToUseLists - Add all of the register operands in
1177 /// this instruction from their respective use lists. This requires that the
1178 /// operands not be on their use lists yet.
1179 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1181 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
1183 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1185 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1186 /// this MI and the given operand index \p OpIdx.
1187 /// If the related operand does not constrained Reg, this returns CurRC.
1188 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1189 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1190 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1193 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1194 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1195 /// The hashing and equality testing functions ignore definitions so this is
1196 /// useful for CSE, etc.
1197 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1198 static inline MachineInstr *getEmptyKey() {
1202 static inline MachineInstr *getTombstoneKey() {
1203 return reinterpret_cast<MachineInstr*>(-1);
1206 static unsigned getHashValue(const MachineInstr* const &MI);
1208 static bool isEqual(const MachineInstr* const &LHS,
1209 const MachineInstr* const &RHS) {
1210 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1211 LHS == getEmptyKey() || LHS == getTombstoneKey())
1213 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1217 //===----------------------------------------------------------------------===//
1218 // Debugging Support
1220 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1225 } // End llvm namespace