1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/Support/ArrayRecycler.h"
32 #include "llvm/Target/TargetOpcodes.h"
36 template <typename T> class SmallVectorImpl;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
44 //===----------------------------------------------------------------------===//
45 /// MachineInstr - Representation of each machine instruction.
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
51 class MachineInstr : public ilist_node<MachineInstr> {
53 typedef MachineMemOperand **mmo_iterator;
55 /// Flags to specify different kinds of comments to output in
56 /// assembly code. These flags carry semantic information not
57 /// otherwise easily derivable from the IR text.
65 FrameSetup = 1 << 0, // Instruction is used as a part of
66 // function frame setup code.
67 BundledPred = 1 << 1, // Instruction has bundled predecessors.
68 BundledSucc = 1 << 2 // Instruction has bundled successors.
71 const MCInstrDesc *MCID; // Instruction descriptor.
72 MachineBasicBlock *Parent; // Pointer to the owning basic block.
74 // Operands are allocated by an ArrayRecycler.
75 MachineOperand *Operands; // Pointer to the first operand.
76 unsigned NumOperands; // Number of operands on instruction.
77 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
78 OperandCapacity CapOperands; // Capacity of the Operands array.
80 uint8_t Flags; // Various bits of additional
81 // information about machine
84 uint8_t AsmPrinterFlags; // Various bits of information used by
85 // the AsmPrinter to emit helpful
86 // comments. This is *not* semantic
87 // information. Do not use this for
88 // anything other than to convey comment
89 // information to AsmPrinter.
91 uint8_t NumMemRefs; // Information on memory references.
94 DebugLoc debugLoc; // Source line information.
96 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
97 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
98 // Use MachineFunction::DeleteMachineInstr() instead.
99 ~MachineInstr() LLVM_DELETED_FUNCTION;
101 // Intrusive list support
102 friend struct ilist_traits<MachineInstr>;
103 friend struct ilist_traits<MachineBasicBlock>;
104 void setParent(MachineBasicBlock *P) { Parent = P; }
106 /// MachineInstr ctor - This constructor creates a copy of the given
107 /// MachineInstr in the given MachineFunction.
108 MachineInstr(MachineFunction &, const MachineInstr &);
110 /// MachineInstr ctor - This constructor create a MachineInstr and add the
111 /// implicit operands. It reserves space for number of operands specified by
112 /// MCInstrDesc. An explicit DebugLoc is supplied.
113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
114 const DebugLoc dl, bool NoImp = false);
116 // MachineInstrs are pool-allocated and owned by MachineFunction.
117 friend class MachineFunction;
120 const MachineBasicBlock* getParent() const { return Parent; }
121 MachineBasicBlock* getParent() { return Parent; }
123 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
125 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
127 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
129 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
131 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
133 bool getAsmPrinterFlag(CommentFlag Flag) const {
134 return AsmPrinterFlags & Flag;
137 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
139 void setAsmPrinterFlag(CommentFlag Flag) {
140 AsmPrinterFlags |= (uint8_t)Flag;
143 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
145 void clearAsmPrinterFlag(CommentFlag Flag) {
146 AsmPrinterFlags &= ~Flag;
149 /// getFlags - Return the MI flags bitvector.
150 uint8_t getFlags() const {
154 /// getFlag - Return whether an MI flag is set.
155 bool getFlag(MIFlag Flag) const {
159 /// setFlag - Set a MI flag.
160 void setFlag(MIFlag Flag) {
161 Flags |= (uint8_t)Flag;
164 void setFlags(unsigned flags) {
165 // Filter out the automatically maintained flags.
166 unsigned Mask = BundledPred | BundledSucc;
167 Flags = (Flags & Mask) | (flags & ~Mask);
170 /// clearFlag - Clear a MI flag.
171 void clearFlag(MIFlag Flag) {
172 Flags &= ~((uint8_t)Flag);
175 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
178 /// A bundle looks like this before it's finalized:
190 /// In this case, the first MI starts a bundle but is not inside a bundle, the
191 /// next 2 MIs are considered "inside" the bundle.
193 /// After a bundle is finalized, it looks like this:
209 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
210 /// a bundle, but the next three MIs are.
211 bool isInsideBundle() const {
212 return getFlag(BundledPred);
215 /// isBundled - Return true if this instruction part of a bundle. This is true
216 /// if either itself or its following instruction is marked "InsideBundle".
217 bool isBundled() const {
218 return isBundledWithPred() || isBundledWithSucc();
221 /// Return true if this instruction is part of a bundle, and it is not the
222 /// first instruction in the bundle.
223 bool isBundledWithPred() const { return getFlag(BundledPred); }
225 /// Return true if this instruction is part of a bundle, and it is not the
226 /// last instruction in the bundle.
227 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
229 /// Bundle this instruction with its predecessor. This can be an unbundled
230 /// instruction, or it can be the first instruction in a bundle.
231 void bundleWithPred();
233 /// Bundle this instruction with its successor. This can be an unbundled
234 /// instruction, or it can be the last instruction in a bundle.
235 void bundleWithSucc();
237 /// Break bundle above this instruction.
238 void unbundleFromPred();
240 /// Break bundle below this instruction.
241 void unbundleFromSucc();
243 /// getDebugLoc - Returns the debug location id of this MachineInstr.
245 DebugLoc getDebugLoc() const { return debugLoc; }
247 /// getDebugVariable() - Return the debug variable referenced by
248 /// this DBG_VALUE instruction.
249 DIVariable getDebugVariable() const {
250 assert(isDebugValue() && "not a DBG_VALUE");
251 const MDNode *Var = getOperand(getNumOperands() - 1).getMetadata();
252 return DIVariable(Var);
255 /// emitError - Emit an error referring to the source location of this
256 /// instruction. This should only be used for inline assembly that is somehow
257 /// impossible to compile. Other errors should have been handled much
260 /// If this method returns, the caller should try to recover from the error.
262 void emitError(StringRef Msg) const;
264 /// getDesc - Returns the target instruction descriptor of this
266 const MCInstrDesc &getDesc() const { return *MCID; }
268 /// getOpcode - Returns the opcode of this MachineInstr.
270 int getOpcode() const { return MCID->Opcode; }
272 /// Access to explicit operands of the instruction.
274 unsigned getNumOperands() const { return NumOperands; }
276 const MachineOperand& getOperand(unsigned i) const {
277 assert(i < getNumOperands() && "getOperand() out of range!");
280 MachineOperand& getOperand(unsigned i) {
281 assert(i < getNumOperands() && "getOperand() out of range!");
285 /// getNumExplicitOperands - Returns the number of non-implicit operands.
287 unsigned getNumExplicitOperands() const;
289 /// iterator/begin/end - Iterate over all operands of a machine instruction.
290 typedef MachineOperand *mop_iterator;
291 typedef const MachineOperand *const_mop_iterator;
293 mop_iterator operands_begin() { return Operands; }
294 mop_iterator operands_end() { return Operands + NumOperands; }
296 const_mop_iterator operands_begin() const { return Operands; }
297 const_mop_iterator operands_end() const { return Operands + NumOperands; }
299 iterator_range<mop_iterator> operands() {
300 return iterator_range<mop_iterator>(operands_begin(), operands_end());
302 iterator_range<const_mop_iterator> operands() const {
303 return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
305 iterator_range<mop_iterator> explicit_operands() {
306 return iterator_range<mop_iterator>(
307 operands_begin(), operands_begin() + getNumExplicitOperands());
309 iterator_range<const_mop_iterator> explicit_operands() const {
310 return iterator_range<const_mop_iterator>(
311 operands_begin(), operands_begin() + getNumExplicitOperands());
313 iterator_range<mop_iterator> implicit_operands() {
314 return iterator_range<mop_iterator>(explicit_operands().end(),
317 iterator_range<const_mop_iterator> implicit_operands() const {
318 return iterator_range<const_mop_iterator>(explicit_operands().end(),
321 iterator_range<mop_iterator> defs() {
322 return iterator_range<mop_iterator>(
323 operands_begin(), operands_begin() + getDesc().getNumDefs());
325 iterator_range<const_mop_iterator> defs() const {
326 return iterator_range<const_mop_iterator>(
327 operands_begin(), operands_begin() + getDesc().getNumDefs());
329 iterator_range<mop_iterator> uses() {
330 return iterator_range<mop_iterator>(
331 operands_begin() + getDesc().getNumDefs(), operands_end());
333 iterator_range<const_mop_iterator> uses() const {
334 return iterator_range<const_mop_iterator>(
335 operands_begin() + getDesc().getNumDefs(), operands_end());
338 /// Access to memory operands of the instruction
339 mmo_iterator memoperands_begin() const { return MemRefs; }
340 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
341 bool memoperands_empty() const { return NumMemRefs == 0; }
343 iterator_range<mmo_iterator> memoperands() {
344 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
346 iterator_range<mmo_iterator> memoperands() const {
347 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
350 /// hasOneMemOperand - Return true if this instruction has exactly one
351 /// MachineMemOperand.
352 bool hasOneMemOperand() const {
353 return NumMemRefs == 1;
356 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
357 /// queries but they are bundle aware.
360 IgnoreBundle, // Ignore bundles
361 AnyInBundle, // Return true if any instruction in bundle has property
362 AllInBundle // Return true if all instructions in bundle have property
365 /// hasProperty - Return true if the instruction (or in the case of a bundle,
366 /// the instructions inside the bundle) has the specified property.
367 /// The first argument is the property being queried.
368 /// The second argument indicates whether the query should look inside
369 /// instruction bundles.
370 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
371 // Inline the fast path for unbundled or bundle-internal instructions.
372 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
373 return getDesc().getFlags() & (1 << MCFlag);
375 // If this is the first instruction in a bundle, take the slow path.
376 return hasPropertyInBundle(1 << MCFlag, Type);
379 /// isVariadic - Return true if this instruction can have a variable number of
380 /// operands. In this case, the variable operands will be after the normal
381 /// operands but before the implicit definitions and uses (if any are
383 bool isVariadic(QueryType Type = IgnoreBundle) const {
384 return hasProperty(MCID::Variadic, Type);
387 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
388 /// ARM instructions which can set condition code if 's' bit is set.
389 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
390 return hasProperty(MCID::HasOptionalDef, Type);
393 /// isPseudo - Return true if this is a pseudo instruction that doesn't
394 /// correspond to a real machine instruction.
396 bool isPseudo(QueryType Type = IgnoreBundle) const {
397 return hasProperty(MCID::Pseudo, Type);
400 bool isReturn(QueryType Type = AnyInBundle) const {
401 return hasProperty(MCID::Return, Type);
404 bool isCall(QueryType Type = AnyInBundle) const {
405 return hasProperty(MCID::Call, Type);
408 /// isBarrier - Returns true if the specified instruction stops control flow
409 /// from executing the instruction immediately following it. Examples include
410 /// unconditional branches and return instructions.
411 bool isBarrier(QueryType Type = AnyInBundle) const {
412 return hasProperty(MCID::Barrier, Type);
415 /// isTerminator - Returns true if this instruction part of the terminator for
416 /// a basic block. Typically this is things like return and branch
419 /// Various passes use this to insert code into the bottom of a basic block,
420 /// but before control flow occurs.
421 bool isTerminator(QueryType Type = AnyInBundle) const {
422 return hasProperty(MCID::Terminator, Type);
425 /// isBranch - Returns true if this is a conditional, unconditional, or
426 /// indirect branch. Predicates below can be used to discriminate between
427 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
428 /// get more information.
429 bool isBranch(QueryType Type = AnyInBundle) const {
430 return hasProperty(MCID::Branch, Type);
433 /// isIndirectBranch - Return true if this is an indirect branch, such as a
434 /// branch through a register.
435 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
436 return hasProperty(MCID::IndirectBranch, Type);
439 /// isConditionalBranch - Return true if this is a branch which may fall
440 /// through to the next instruction or may transfer control flow to some other
441 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
442 /// information about this branch.
443 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
444 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
447 /// isUnconditionalBranch - Return true if this is a branch which always
448 /// transfers control flow to some other block. The
449 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
450 /// about this branch.
451 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
452 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
455 /// Return true if this instruction has a predicate operand that
456 /// controls execution. It may be set to 'always', or may be set to other
457 /// values. There are various methods in TargetInstrInfo that can be used to
458 /// control and modify the predicate in this instruction.
459 bool isPredicable(QueryType Type = AllInBundle) const {
460 // If it's a bundle than all bundled instructions must be predicable for this
462 return hasProperty(MCID::Predicable, Type);
465 /// isCompare - Return true if this instruction is a comparison.
466 bool isCompare(QueryType Type = IgnoreBundle) const {
467 return hasProperty(MCID::Compare, Type);
470 /// isMoveImmediate - Return true if this instruction is a move immediate
471 /// (including conditional moves) instruction.
472 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
473 return hasProperty(MCID::MoveImm, Type);
476 /// isBitcast - Return true if this instruction is a bitcast instruction.
478 bool isBitcast(QueryType Type = IgnoreBundle) const {
479 return hasProperty(MCID::Bitcast, Type);
482 /// isSelect - Return true if this instruction is a select instruction.
484 bool isSelect(QueryType Type = IgnoreBundle) const {
485 return hasProperty(MCID::Select, Type);
488 /// isNotDuplicable - Return true if this instruction cannot be safely
489 /// duplicated. For example, if the instruction has a unique labels attached
490 /// to it, duplicating it would cause multiple definition errors.
491 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
492 return hasProperty(MCID::NotDuplicable, Type);
495 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
496 /// which must be filled by the code generator.
497 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
498 return hasProperty(MCID::DelaySlot, Type);
501 /// canFoldAsLoad - Return true for instructions that can be folded as
502 /// memory operands in other instructions. The most common use for this
503 /// is instructions that are simple loads from memory that don't modify
504 /// the loaded value in any way, but it can also be used for instructions
505 /// that can be expressed as constant-pool loads, such as V_SETALLONES
506 /// on x86, to allow them to be folded when it is beneficial.
507 /// This should only be set on instructions that return a value in their
508 /// only virtual register definition.
509 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
510 return hasProperty(MCID::FoldableAsLoad, Type);
513 /// \brief Return true if this instruction behaves
514 /// the same way as the generic REG_SEQUENCE instructions.
516 /// dX VMOVDRR rY, rZ
518 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
520 /// Note that for the optimizers to be able to take advantage of
521 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
522 /// override accordingly.
523 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
524 return hasProperty(MCID::RegSequence, Type);
527 /// \brief Return true if this instruction behaves
528 /// the same way as the generic EXTRACT_SUBREG instructions.
530 /// rX, rY VMOVRRD dZ
531 /// is equivalent to two EXTRACT_SUBREG:
532 /// rX = EXTRACT_SUBREG dZ, ssub_0
533 /// rY = EXTRACT_SUBREG dZ, ssub_1
535 /// Note that for the optimizers to be able to take advantage of
536 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
537 /// override accordingly.
538 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
539 return hasProperty(MCID::ExtractSubreg, Type);
542 //===--------------------------------------------------------------------===//
543 // Side Effect Analysis
544 //===--------------------------------------------------------------------===//
546 /// mayLoad - Return true if this instruction could possibly read memory.
547 /// Instructions with this flag set are not necessarily simple load
548 /// instructions, they may load a value and modify it, for example.
549 bool mayLoad(QueryType Type = AnyInBundle) const {
551 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
552 if (ExtraInfo & InlineAsm::Extra_MayLoad)
555 return hasProperty(MCID::MayLoad, Type);
559 /// mayStore - Return true if this instruction could possibly modify memory.
560 /// Instructions with this flag set are not necessarily simple store
561 /// instructions, they may store a modified value based on their operands, or
562 /// may not actually modify anything, for example.
563 bool mayStore(QueryType Type = AnyInBundle) const {
565 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
566 if (ExtraInfo & InlineAsm::Extra_MayStore)
569 return hasProperty(MCID::MayStore, Type);
572 //===--------------------------------------------------------------------===//
573 // Flags that indicate whether an instruction can be modified by a method.
574 //===--------------------------------------------------------------------===//
576 /// isCommutable - Return true if this may be a 2- or 3-address
577 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
578 /// result if Y and Z are exchanged. If this flag is set, then the
579 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
582 /// Note that this flag may be set on instructions that are only commutable
583 /// sometimes. In these cases, the call to commuteInstruction will fail.
584 /// Also note that some instructions require non-trivial modification to
586 bool isCommutable(QueryType Type = IgnoreBundle) const {
587 return hasProperty(MCID::Commutable, Type);
590 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
591 /// which can be changed into a 3-address instruction if needed. Doing this
592 /// transformation can be profitable in the register allocator, because it
593 /// means that the instruction can use a 2-address form if possible, but
594 /// degrade into a less efficient form if the source and dest register cannot
595 /// be assigned to the same register. For example, this allows the x86
596 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
597 /// is the same speed as the shift but has bigger code size.
599 /// If this returns true, then the target must implement the
600 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
601 /// is allowed to fail if the transformation isn't valid for this specific
602 /// instruction (e.g. shl reg, 4 on x86).
604 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
605 return hasProperty(MCID::ConvertibleTo3Addr, Type);
608 /// usesCustomInsertionHook - Return true if this instruction requires
609 /// custom insertion support when the DAG scheduler is inserting it into a
610 /// machine basic block. If this is true for the instruction, it basically
611 /// means that it is a pseudo instruction used at SelectionDAG time that is
612 /// expanded out into magic code by the target when MachineInstrs are formed.
614 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
615 /// is used to insert this into the MachineBasicBlock.
616 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
617 return hasProperty(MCID::UsesCustomInserter, Type);
620 /// hasPostISelHook - Return true if this instruction requires *adjustment*
621 /// after instruction selection by calling a target hook. For example, this
622 /// can be used to fill in ARM 's' optional operand depending on whether
623 /// the conditional flag register is used.
624 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
625 return hasProperty(MCID::HasPostISelHook, Type);
628 /// isRematerializable - Returns true if this instruction is a candidate for
629 /// remat. This flag is deprecated, please don't use it anymore. If this
630 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
631 /// verify the instruction is really rematable.
632 bool isRematerializable(QueryType Type = AllInBundle) const {
633 // It's only possible to re-mat a bundle if all bundled instructions are
634 // re-materializable.
635 return hasProperty(MCID::Rematerializable, Type);
638 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
639 /// less) than a move instruction. This is useful during certain types of
640 /// optimizations (e.g., remat during two-address conversion or machine licm)
641 /// where we would like to remat or hoist the instruction, but not if it costs
642 /// more than moving the instruction into the appropriate register. Note, we
643 /// are not marking copies from and to the same register class with this flag.
644 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
645 // Only returns true for a bundle if all bundled instructions are cheap.
646 return hasProperty(MCID::CheapAsAMove, Type);
649 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
650 /// have special register allocation requirements that are not captured by the
651 /// operand register classes. e.g. ARM::STRD's two source registers must be an
652 /// even / odd pair, ARM::STM registers have to be in ascending order.
653 /// Post-register allocation passes should not attempt to change allocations
654 /// for sources of instructions with this flag.
655 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
656 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
659 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
660 /// have special register allocation requirements that are not captured by the
661 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
662 /// even / odd pair, ARM::LDM registers have to be in ascending order.
663 /// Post-register allocation passes should not attempt to change allocations
664 /// for definitions of instructions with this flag.
665 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
666 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
671 CheckDefs, // Check all operands for equality
672 CheckKillDead, // Check all operands including kill / dead markers
673 IgnoreDefs, // Ignore all definitions
674 IgnoreVRegDefs // Ignore virtual register definitions
677 /// isIdenticalTo - Return true if this instruction is identical to (same
678 /// opcode and same operands as) the specified instruction.
679 bool isIdenticalTo(const MachineInstr *Other,
680 MICheckType Check = CheckDefs) const;
682 /// Unlink 'this' from the containing basic block, and return it without
685 /// This function can not be used on bundled instructions, use
686 /// removeFromBundle() to remove individual instructions from a bundle.
687 MachineInstr *removeFromParent();
689 /// Unlink this instruction from its basic block and return it without
692 /// If the instruction is part of a bundle, the other instructions in the
693 /// bundle remain bundled.
694 MachineInstr *removeFromBundle();
696 /// Unlink 'this' from the containing basic block and delete it.
698 /// If this instruction is the header of a bundle, the whole bundle is erased.
699 /// This function can not be used for instructions inside a bundle, use
700 /// eraseFromBundle() to erase individual bundled instructions.
701 void eraseFromParent();
703 /// Unlink 'this' from the containing basic block and delete it.
705 /// For all definitions mark their uses in DBG_VALUE nodes
706 /// as undefined. Otherwise like eraseFromParent().
707 void eraseFromParentAndMarkDBGValuesForRemoval();
709 /// Unlink 'this' form its basic block and delete it.
711 /// If the instruction is part of a bundle, the other instructions in the
712 /// bundle remain bundled.
713 void eraseFromBundle();
715 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
716 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
718 /// isLabel - Returns true if the MachineInstr represents a label.
720 bool isLabel() const { return isEHLabel() || isGCLabel(); }
721 bool isCFIInstruction() const {
722 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
725 // True if the instruction represents a position in the function.
726 bool isPosition() const { return isLabel() || isCFIInstruction(); }
728 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
729 /// A DBG_VALUE is indirect iff the first operand is a register and
730 /// the second operand is an immediate.
731 bool isIndirectDebugValue() const {
732 return isDebugValue()
733 && getOperand(0).isReg()
734 && getOperand(1).isImm();
737 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
738 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
739 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
740 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
741 bool isMSInlineAsm() const {
742 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
744 bool isStackAligningInlineAsm() const;
745 InlineAsm::AsmDialect getInlineAsmDialect() const;
746 bool isInsertSubreg() const {
747 return getOpcode() == TargetOpcode::INSERT_SUBREG;
749 bool isSubregToReg() const {
750 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
752 bool isRegSequence() const {
753 return getOpcode() == TargetOpcode::REG_SEQUENCE;
755 bool isBundle() const {
756 return getOpcode() == TargetOpcode::BUNDLE;
758 bool isCopy() const {
759 return getOpcode() == TargetOpcode::COPY;
761 bool isFullCopy() const {
762 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
764 bool isExtractSubreg() const {
765 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
768 /// isCopyLike - Return true if the instruction behaves like a copy.
769 /// This does not include native copy instructions.
770 bool isCopyLike() const {
771 return isCopy() || isSubregToReg();
774 /// isIdentityCopy - Return true is the instruction is an identity copy.
775 bool isIdentityCopy() const {
776 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
777 getOperand(0).getSubReg() == getOperand(1).getSubReg();
780 /// isTransient - Return true if this is a transient instruction that is
781 /// either very likely to be eliminated during register allocation (such as
782 /// copy-like instructions), or if this instruction doesn't have an
783 /// execution-time cost.
784 bool isTransient() const {
785 switch(getOpcode()) {
786 default: return false;
787 // Copy-like instructions are usually eliminated during register allocation.
788 case TargetOpcode::PHI:
789 case TargetOpcode::COPY:
790 case TargetOpcode::INSERT_SUBREG:
791 case TargetOpcode::SUBREG_TO_REG:
792 case TargetOpcode::REG_SEQUENCE:
793 // Pseudo-instructions that don't produce any real output.
794 case TargetOpcode::IMPLICIT_DEF:
795 case TargetOpcode::KILL:
796 case TargetOpcode::CFI_INSTRUCTION:
797 case TargetOpcode::EH_LABEL:
798 case TargetOpcode::GC_LABEL:
799 case TargetOpcode::DBG_VALUE:
804 /// Return the number of instructions inside the MI bundle, excluding the
807 /// This is the number of instructions that MachineBasicBlock::iterator
808 /// skips, 0 for unbundled instructions.
809 unsigned getBundleSize() const;
811 /// readsRegister - Return true if the MachineInstr reads the specified
812 /// register. If TargetRegisterInfo is passed, then it also checks if there
813 /// is a read of a super-register.
814 /// This does not count partial redefines of virtual registers as reads:
816 bool readsRegister(unsigned Reg,
817 const TargetRegisterInfo *TRI = nullptr) const {
818 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
821 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
822 /// virtual register. Take into account that a partial define is a
823 /// read-modify-write operation.
824 bool readsVirtualRegister(unsigned Reg) const {
825 return readsWritesVirtualRegister(Reg).first;
828 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
829 /// indicating if this instruction reads or writes Reg. This also considers
831 /// If Ops is not null, all operand indices for Reg are added.
832 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
833 SmallVectorImpl<unsigned> *Ops = nullptr) const;
835 /// killsRegister - Return true if the MachineInstr kills the specified
836 /// register. If TargetRegisterInfo is passed, then it also checks if there is
837 /// a kill of a super-register.
838 bool killsRegister(unsigned Reg,
839 const TargetRegisterInfo *TRI = nullptr) const {
840 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
843 /// definesRegister - Return true if the MachineInstr fully defines the
844 /// specified register. If TargetRegisterInfo is passed, then it also checks
845 /// if there is a def of a super-register.
846 /// NOTE: It's ignoring subreg indices on virtual registers.
847 bool definesRegister(unsigned Reg,
848 const TargetRegisterInfo *TRI = nullptr) const {
849 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
852 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
853 /// or partially define) the specified register.
854 /// NOTE: It's ignoring subreg indices on virtual registers.
855 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
856 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
859 /// registerDefIsDead - Returns true if the register is dead in this machine
860 /// instruction. If TargetRegisterInfo is passed, then it also checks
861 /// if there is a dead def of a super-register.
862 bool registerDefIsDead(unsigned Reg,
863 const TargetRegisterInfo *TRI = nullptr) const {
864 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
867 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
868 /// the specific register or -1 if it is not found. It further tightens
869 /// the search criteria to a use that kills the register if isKill is true.
870 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
871 const TargetRegisterInfo *TRI = nullptr) const;
873 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
874 /// a pointer to the MachineOperand rather than an index.
875 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
876 const TargetRegisterInfo *TRI = nullptr) {
877 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
878 return (Idx == -1) ? nullptr : &getOperand(Idx);
881 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
882 /// the specified register or -1 if it is not found. If isDead is true, defs
883 /// that are not dead are skipped. If Overlap is true, then it also looks for
884 /// defs that merely overlap the specified register. If TargetRegisterInfo is
885 /// non-null, then it also checks if there is a def of a super-register.
886 /// This may also return a register mask operand when Overlap is true.
887 int findRegisterDefOperandIdx(unsigned Reg,
888 bool isDead = false, bool Overlap = false,
889 const TargetRegisterInfo *TRI = nullptr) const;
891 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
892 /// a pointer to the MachineOperand rather than an index.
893 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
894 const TargetRegisterInfo *TRI = nullptr) {
895 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
896 return (Idx == -1) ? nullptr : &getOperand(Idx);
899 /// findFirstPredOperandIdx() - Find the index of the first operand in the
900 /// operand list that is used to represent the predicate. It returns -1 if
902 int findFirstPredOperandIdx() const;
904 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
905 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
906 /// getOperand(OpIdx) does not belong to an inline asm operand group.
908 /// If GroupNo is not NULL, it will receive the number of the operand group
909 /// containing OpIdx.
911 /// The flag operand is an immediate that can be decoded with methods like
912 /// InlineAsm::hasRegClassConstraint().
914 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
916 /// getRegClassConstraint - Compute the static register class constraint for
917 /// operand OpIdx. For normal instructions, this is derived from the
918 /// MCInstrDesc. For inline assembly it is derived from the flag words.
920 /// Returns NULL if the static register classs constraint cannot be
923 const TargetRegisterClass*
924 getRegClassConstraint(unsigned OpIdx,
925 const TargetInstrInfo *TII,
926 const TargetRegisterInfo *TRI) const;
928 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
929 /// the given \p CurRC.
930 /// If \p ExploreBundle is set and MI is part of a bundle, all the
931 /// instructions inside the bundle will be taken into account. In other words,
932 /// this method accumulates all the constrains of the operand of this MI and
933 /// the related bundle if MI is a bundle or inside a bundle.
935 /// Returns the register class that statisfies both \p CurRC and the
936 /// constraints set by MI. Returns NULL if such a register class does not
939 /// \pre CurRC must not be NULL.
940 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
941 unsigned Reg, const TargetRegisterClass *CurRC,
942 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
943 bool ExploreBundle = false) const;
945 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
946 /// to the given \p CurRC.
948 /// Returns the register class that statisfies both \p CurRC and the
949 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
952 /// \pre CurRC must not be NULL.
953 /// \pre The operand at \p OpIdx must be a register.
954 const TargetRegisterClass *
955 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
956 const TargetInstrInfo *TII,
957 const TargetRegisterInfo *TRI) const;
959 /// tieOperands - Add a tie between the register operands at DefIdx and
960 /// UseIdx. The tie will cause the register allocator to ensure that the two
961 /// operands are assigned the same physical register.
963 /// Tied operands are managed automatically for explicit operands in the
964 /// MCInstrDesc. This method is for exceptional cases like inline asm.
965 void tieOperands(unsigned DefIdx, unsigned UseIdx);
967 /// findTiedOperandIdx - Given the index of a tied register operand, find the
968 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
969 /// index of the tied operand which must exist.
970 unsigned findTiedOperandIdx(unsigned OpIdx) const;
972 /// isRegTiedToUseOperand - Given the index of a register def operand,
973 /// check if the register def is tied to a source operand, due to either
974 /// two-address elimination or inline assembly constraints. Returns the
975 /// first tied use operand index by reference if UseOpIdx is not null.
976 bool isRegTiedToUseOperand(unsigned DefOpIdx,
977 unsigned *UseOpIdx = nullptr) const {
978 const MachineOperand &MO = getOperand(DefOpIdx);
979 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
982 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
986 /// isRegTiedToDefOperand - Return true if the use operand of the specified
987 /// index is tied to a def operand. It also returns the def operand index by
988 /// reference if DefOpIdx is not null.
989 bool isRegTiedToDefOperand(unsigned UseOpIdx,
990 unsigned *DefOpIdx = nullptr) const {
991 const MachineOperand &MO = getOperand(UseOpIdx);
992 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
995 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
999 /// clearKillInfo - Clears kill flags on all operands.
1001 void clearKillInfo();
1003 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
1004 /// properly composing subreg indices where necessary.
1005 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1006 const TargetRegisterInfo &RegInfo);
1008 /// addRegisterKilled - We have determined MI kills a register. Look for the
1009 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1010 /// add a implicit operand if it's not found. Returns true if the operand
1011 /// exists / is added.
1012 bool addRegisterKilled(unsigned IncomingReg,
1013 const TargetRegisterInfo *RegInfo,
1014 bool AddIfNotFound = false);
1016 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
1017 /// provided, this includes super-register kills.
1018 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1020 /// addRegisterDead - We have determined MI defined a register without a use.
1021 /// Look for the operand that defines it and mark it as IsDead. If
1022 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1023 /// true if the operand exists / is added.
1024 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1025 bool AddIfNotFound = false);
1027 /// addRegisterDefined - We have determined MI defines a register. Make sure
1028 /// there is an operand defining Reg.
1029 void addRegisterDefined(unsigned Reg,
1030 const TargetRegisterInfo *RegInfo = nullptr);
1032 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
1033 /// dead except those in the UsedRegs list.
1035 /// On instructions with register mask operands, also add implicit-def
1036 /// operands for all registers in UsedRegs.
1037 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1038 const TargetRegisterInfo &TRI);
1040 /// isSafeToMove - Return true if it is safe to move this instruction. If
1041 /// SawStore is set to true, it means that there is a store (or call) between
1042 /// the instruction's location and its intended destination.
1043 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
1044 bool &SawStore) const;
1046 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1047 /// or volatile memory reference, or if the information describing the memory
1048 /// reference is not available. Return false if it is known to have no
1049 /// ordered or volatile memory references.
1050 bool hasOrderedMemoryRef() const;
1052 /// isInvariantLoad - Return true if this instruction is loading from a
1053 /// location whose value is invariant across the function. For example,
1054 /// loading a value from the constant pool or from the argument area of
1055 /// a function if it does not change. This should only return true of *all*
1056 /// loads the instruction does are invariant (if it does multiple loads).
1057 bool isInvariantLoad(AliasAnalysis *AA) const;
1059 /// isConstantValuePHI - If the specified instruction is a PHI that always
1060 /// merges together the same virtual register, return the register, otherwise
1062 unsigned isConstantValuePHI() const;
1064 /// hasUnmodeledSideEffects - Return true if this instruction has side
1065 /// effects that are not modeled by mayLoad / mayStore, etc.
1066 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1067 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1068 /// INLINEASM instruction, in which case the side effect property is encoded
1069 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1071 bool hasUnmodeledSideEffects() const;
1073 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1075 bool allDefsAreDead() const;
1077 /// copyImplicitOps - Copy implicit register operands from specified
1078 /// instruction to this instruction.
1079 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1082 // Debugging support
1084 void print(raw_ostream &OS, const TargetMachine *TM = nullptr,
1085 bool SkipOpers = false) const;
1088 //===--------------------------------------------------------------------===//
1089 // Accessors used to build up machine instructions.
1091 /// Add the specified operand to the instruction. If it is an implicit
1092 /// operand, it is added to the end of the operand list. If it is an
1093 /// explicit operand it is added at the end of the explicit operand list
1094 /// (before the first implicit operand).
1096 /// MF must be the machine function that was used to allocate this
1099 /// MachineInstrBuilder provides a more convenient interface for creating
1100 /// instructions and adding operands.
1101 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1103 /// Add an operand without providing an MF reference. This only works for
1104 /// instructions that are inserted in a basic block.
1106 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1108 void addOperand(const MachineOperand &Op);
1110 /// setDesc - Replace the instruction descriptor (thus opcode) of
1111 /// the current instruction with a new one.
1113 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1115 /// setDebugLoc - Replace current source information with new such.
1116 /// Avoid using this, the constructor argument is preferable.
1118 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
1120 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
1121 /// fewer operand than it started with.
1123 void RemoveOperand(unsigned i);
1125 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
1126 /// This function should be used only occasionally. The setMemRefs function
1127 /// is the primary method for setting up a MachineInstr's MemRefs list.
1128 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1130 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
1131 /// list. This does not transfer ownership.
1132 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1133 MemRefs = NewMemRefs;
1134 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1135 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1139 /// getRegInfo - If this instruction is embedded into a MachineFunction,
1140 /// return the MachineRegisterInfo object for the current function, otherwise
1142 MachineRegisterInfo *getRegInfo();
1144 /// untieRegOperand - Break any tie involving OpIdx.
1145 void untieRegOperand(unsigned OpIdx) {
1146 MachineOperand &MO = getOperand(OpIdx);
1147 if (MO.isReg() && MO.isTied()) {
1148 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1153 /// addImplicitDefUseOperands - Add all implicit def and use operands to
1154 /// this instruction.
1155 void addImplicitDefUseOperands(MachineFunction &MF);
1157 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
1158 /// this instruction from their respective use lists. This requires that the
1159 /// operands already be on their use lists.
1160 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1162 /// AddRegOperandsToUseLists - Add all of the register operands in
1163 /// this instruction from their respective use lists. This requires that the
1164 /// operands not be on their use lists yet.
1165 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1167 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
1169 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1171 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1172 /// this MI and the given operand index \p OpIdx.
1173 /// If the related operand does not constrained Reg, this returns CurRC.
1174 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1175 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1176 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1179 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1180 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1181 /// The hashing and equality testing functions ignore definitions so this is
1182 /// useful for CSE, etc.
1183 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1184 static inline MachineInstr *getEmptyKey() {
1188 static inline MachineInstr *getTombstoneKey() {
1189 return reinterpret_cast<MachineInstr*>(-1);
1192 static unsigned getHashValue(const MachineInstr* const &MI);
1194 static bool isEqual(const MachineInstr* const &LHS,
1195 const MachineInstr* const &RHS) {
1196 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1197 LHS == getEmptyKey() || LHS == getTombstoneKey())
1199 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1203 //===----------------------------------------------------------------------===//
1204 // Debugging Support
1206 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1211 } // End llvm namespace