[urcu] Replaced RMW atomics with atomic load/store in URCU read-side lock/unlock.
[libcds.git] / cds / urcu / details / gp.h
index 2bd7e3640dde6a5737eacf0b9de12ba9d33326c9..41287a7d4029381b0ccec7b55e9f3c7bba5567b4 100644 (file)
@@ -68,12 +68,14 @@ namespace cds { namespace urcu { namespace details {
         uint32_t tmp = pRec->m_nAccessControl.load( atomics::memory_order_relaxed );
         if ( (tmp & rcu_class::c_nNestMask) == 0 ) {
             pRec->m_nAccessControl.store( gp_singleton<RCUtag>::instance()->global_control_word(atomics::memory_order_relaxed),
-                atomics::memory_order_release );
-            atomics::atomic_thread_fence( atomics::memory_order_acquire );
-            CDS_COMPILER_RW_BARRIER;
+                atomics::memory_order_relaxed );
+
+            // acquire barrier
+            pRec->m_nAccessControl.load( atomics::memory_order_acquire );
         }
         else {
-            pRec->m_nAccessControl.fetch_add( 1, atomics::memory_order_relaxed );
+            // nested lock
+            pRec->m_nAccessControl.store( tmp + 1, atomics::memory_order_relaxed );
         }
     }
 
@@ -83,8 +85,10 @@ namespace cds { namespace urcu { namespace details {
         thread_record * pRec = get_thread_record();
         assert( pRec != nullptr );
 
-        CDS_COMPILER_RW_BARRIER;
-        pRec->m_nAccessControl.fetch_sub( 1, atomics::memory_order_release );
+        uint32_t tmp = pRec->m_nAccessControl.load( atomics::memory_order_relaxed );
+        assert( (tmp & rcu_class::c_nNestMask) > 0 );
+
+        pRec->m_nAccessControl.store( tmp - 1, atomics::memory_order_release );
     }
 
     template <typename RCUtag>