|| order == memory_order_release
|| order == memory_order_seq_cst
);
- assert( pDest != NULL );
+ assert( pDest );
if ( order != memory_order_seq_cst ) {
fence_before( order );
|| order == memory_order_acquire
|| order == memory_order_seq_cst
);
- assert( pSrc != NULL );
+ assert( pSrc );
T v = *pSrc;
fence_after_load( order );
|| order == memory_order_release
|| order == memory_order_seq_cst
);
- assert( pDest != NULL );
+ assert( pDest );
assert( cds::details::is_aligned( pDest, 2 ));
if ( order != memory_order_seq_cst ) {
|| order == memory_order_acquire
|| order == memory_order_seq_cst
);
- assert( pSrc != NULL );
+ assert( pSrc );
assert( cds::details::is_aligned( pSrc, 2 ));
T v = *pSrc;
|| order == memory_order_release
|| order == memory_order_seq_cst
);
- assert( pDest != NULL );
+ assert( pDest );
assert( cds::details::is_aligned( pDest, 4 ));
if ( order != memory_order_seq_cst ) {
|| order == memory_order_acquire
|| order == memory_order_seq_cst
);
- assert( pSrc != NULL );
+ assert( pSrc );
assert( cds::details::is_aligned( pSrc, 4 ));
T v( *pSrc );
|| order == memory_order_acquire
|| order == memory_order_seq_cst
);
- assert( pSrc != NULL );
+ assert( pSrc );
assert( cds::details::is_aligned( pSrc, 8 ));
// Atomically loads 64bit value by SSE intrinsics
|| order == memory_order_release
|| order == memory_order_seq_cst
);
- assert( pDest != NULL );
+ assert( pDest );
assert( cds::details::is_aligned( pDest, 8 ));
if ( order != memory_order_seq_cst ) {
|| order == memory_order_release
|| order == memory_order_seq_cst
);
- assert( pDest != NULL );
+ assert( pDest );
if ( order != memory_order_seq_cst ) {
fence_before( order );
|| order == memory_order_acquire
|| order == memory_order_seq_cst
);
- assert( pSrc != NULL );
+ assert( pSrc );
T * v = *pSrc;
fence_after_load( order );