From cc4eebc3eab648c3894efca309804fb0eb238280 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 9 Dec 2016 11:38:17 +0800 Subject: [PATCH] pinctrl: rockchip: Add rk3328 pinctrl support Change-Id: I3b5b69e46b555ab3578d611e5d480ced9c493666 Signed-off-by: David Wu --- .../bindings/pinctrl/rockchip,pinctrl.txt | 4 +- drivers/pinctrl/pinctrl-rockchip.c | 161 +++++++++++++++++- 2 files changed, 156 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 8a73937436b4..8885acfa2032 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -22,8 +22,8 @@ Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl" - "rockchip,rk3366-pinctrl", "rockchip,rk3368-pinctrl" - "rockchip,rk3399-pinctrl" + "rockchip,rk3328-pinctrl", "rockchip,rk3366-pinctrl" + "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl" - rockchip,grf: phandle referencing a syscon providing the "general register files" diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 583b450b177a..c48e5a7c2c08 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -75,6 +75,8 @@ enum rockchip_pinctrl_type { #define IOMUX_WIDTH_4BIT BIT(1) #define IOMUX_SOURCE_PMU BIT(2) #define IOMUX_UNROUTED BIT(3) +#define IOMUX_WIDTH_3BIT BIT(4) +#define IOMUX_RECALCED_FLAG BIT(5) /** * @type: iomux variant using IOMUX_* constants @@ -361,6 +363,8 @@ struct rockchip_pin_ctrl { struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); + void (*iomux_recalc)(u8 bank_num, int pin, int *reg, + int *mask, u8 *bit); }; struct rockchip_pin_config { @@ -412,6 +416,24 @@ struct rockchip_pinctrl { unsigned int nfunctions; }; +/** + * struct rockchip_mux_recalced_data: represent a pin iomux data. + * @num: bank num. + * @bit: index at register or used to calc index. + * @min_pin: the min pin. + * @max_pin: the max pin. + * @reg: the register offset. + * @mask: mask bit + */ +struct rockchip_mux_recalced_data { + u8 num; + u8 bit; + int min_pin; + int max_pin; + int reg; + int mask; +}; + static struct regmap_config rockchip_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -576,13 +598,83 @@ static const struct pinctrl_ops rockchip_pctrl_ops = { * Hardware access */ +static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { + { + .num = 2, + .bit = 0x2, + .min_pin = 8, + .max_pin = 14, + .reg = 0x24, + .mask = 0x3 + }, + { + .num = 2, + .bit = 0, + .min_pin = 15, + .max_pin = 15, + .reg = 0x28, + .mask = 0x7 + }, + { + .num = 2, + .bit = 14, + .min_pin = 23, + .max_pin = 23, + .reg = 0x30, + .mask = 0x3 + }, + { + .num = 3, + .bit = 0, + .min_pin = 8, + .max_pin = 8, + .reg = 0x40, + .mask = 0x7 + }, + { + .num = 3, + .bit = 0x2, + .min_pin = 9, + .max_pin = 15, + .reg = 0x44, + .mask = 0x3 + }, +}; + +static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg, + int *mask, u8 *bit) +{ + const struct rockchip_mux_recalced_data *data = NULL; + int i; + + for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++) + if (rk3328_mux_recalced_data[i].num == bank_num && + rk3328_mux_recalced_data[i].min_pin <= pin && + rk3328_mux_recalced_data[i].max_pin >= pin) { + data = &rk3328_mux_recalced_data[i]; + break; + } + + if (!data) + return; + + *reg = data->reg; + *mask = data->mask; + + if (data->min_pin == data->max_pin) + *bit = data->bit; + else + *bit = (pin % 8) * data->bit; +} + static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) { struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; int iomux_num = (pin / 8); struct regmap *regmap; unsigned int val; - int reg, ret, mask; + int reg, ret, mask, mux_type; u8 bit; if (iomux_num > 3) @@ -600,16 +692,29 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) ? info->regmap_pmu : info->regmap_base; /* get basic quadrupel of mux registers and the correct reg inside */ - mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; + mux_type = bank->iomux[iomux_num].type; reg = bank->iomux[iomux_num].offset; - if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { + if (mux_type & IOMUX_WIDTH_4BIT) { + mask = 0xf; if ((pin % 8) >= 4) reg += 0x4; bit = (pin % 4) * 4; + } else if (mux_type & IOMUX_WIDTH_3BIT) { + mask = 0x7; + if ((pin % 8) >= 5) { + reg += 0x4; + bit = ((pin % 8) % 5) * 3; + } else { + bit = (pin % 8) * 3; + } } else { + mask = 0x3; bit = (pin % 8) * 2; } + if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED_FLAG)) + ctrl->iomux_recalc(bank->bank_num, pin, ®, &mask, &bit); + ret = regmap_read(regmap, reg, &val); if (ret) return ret; @@ -633,9 +738,10 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; int iomux_num = (pin / 8); struct regmap *regmap; - int reg, ret, mask; + int reg, ret, mask, mux_type; unsigned long flags; u8 bit; u32 data, rmask; @@ -665,16 +771,29 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) ? info->regmap_pmu : info->regmap_base; /* get basic quadrupel of mux registers and the correct reg inside */ - mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; + mux_type = bank->iomux[iomux_num].type; reg = bank->iomux[iomux_num].offset; - if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { + if (mux_type & IOMUX_WIDTH_4BIT) { + mask = 0xf; if ((pin % 8) >= 4) reg += 0x4; bit = (pin % 4) * 4; + } else if (mux_type & IOMUX_WIDTH_3BIT) { + mask = 0x7; + if ((pin % 8) >= 5) { + reg += 0x4; + bit = ((pin % 8) % 5) * 3; + } else { + bit = (pin % 8) * 3; + } } else { + mask = 0x3; bit = (pin % 8) * 2; } + if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED_FLAG)) + ctrl->iomux_recalc(bank->bank_num, pin, ®, &mask, &bit); + spin_lock_irqsave(&bank->slock, flags); data = (mask << (bit + 16)); @@ -2626,7 +2745,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( * Increase offset according to iomux width. * 4bit iomux'es are spread over two registers. */ - inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; + inc = (iom->type & (IOMUX_WIDTH_4BIT | + IOMUX_WIDTH_3BIT)) ? 8 : 4; if (iom->type & IOMUX_SOURCE_PMU) pmu_offs += inc; else @@ -2925,6 +3045,31 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3328_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, + IOMUX_WIDTH_3BIT | IOMUX_RECALCED_FLAG, + IOMUX_WIDTH_3BIT | IOMUX_RECALCED_FLAG, + 0), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_3BIT, + IOMUX_WIDTH_3BIT | IOMUX_RECALCED_FLAG, + 0, + 0), +}; + +static struct rockchip_pin_ctrl rk3328_pin_ctrl = { + .pin_banks = rk3328_pin_banks, + .nr_banks = ARRAY_SIZE(rk3328_pin_banks), + .label = "RK3328-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, + .iomux_recalc = rk3328_recalc_mux, +}; + static struct rockchip_pin_bank rk3366_pin_banks[] = { PIN_BANK_IOMUX_DRV_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, @@ -3090,6 +3235,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3228_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", .data = (void *)&rk3288_pin_ctrl }, + { .compatible = "rockchip,rk3328-pinctrl", + .data = (void *)&rk3328_pin_ctrl }, { .compatible = "rockchip,rk3366-pinctrl", .data = (void *)&rk3366_pin_ctrl }, { .compatible = "rockchip,rk3368-pinctrl", -- 2.34.1