From b636c08934ba85ec36c6b534993e48871e275f6d Mon Sep 17 00:00:00 2001 From: Feng Xiao Date: Thu, 3 Mar 2016 14:35:03 +0800 Subject: [PATCH] clk: rockchip: rk3366: modify hdmi clk according to the latest cru document Change-Id: I815406cd8dfd94e8526b96a827df487fe5381620 Signed-off-by: Feng Xiao --- drivers/clk/rockchip/clk-rk3366.c | 17 ++++++++++------- include/dt-bindings/clock/rk3366-cru.h | 1 - 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3366.c b/drivers/clk/rockchip/clk-rk3366.c index 7bffddfbe2a2..4953ba01b2cf 100644 --- a/drivers/clk/rockchip/clk-rk3366.c +++ b/drivers/clk/rockchip/clk-rk3366.c @@ -92,7 +92,7 @@ PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m", PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" }; PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll", "usbphy_480m" }; -PNAME(mux_pll_src_cpll_gpll_npll_mpll_p) = { "cpll", "gpll", "npll", "mpll" }; +PNAME(mux_pll_src_cpll_gpll_npll_mpll_p) = { "cpll", "gpll", "npll", "mpll_src" }; PNAME(mux_vop_full_pwm_p) = { "xin24m", "cpll", "gpll", "npll" }; PNAME(mux_clk_32k_p) = { "xin32k", "clk_32k_inter" }; PNAME(mux_i2s_8ch_pre_p) = { "i2s_8ch_src", "i2s_8ch_frac", @@ -217,6 +217,13 @@ static struct rockchip_clk_branch rk3366_uart3_fracmux __initdata = RK3368_CLKSEL_CON(39), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = { + /* + * Clock-Architecture Diagram 1 + */ + + GATE(0, "mpll_src", "mpll", CLK_IGNORE_UNUSED, + RK3368_CLKGATE_CON(2), 11, GFLAGS), + /* * Clock-Architecture Diagram 2 */ @@ -392,9 +399,9 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = { RK3368_CLKSEL_CON(24), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3368_CLKGATE_CON(5), 6, GFLAGS), - COMPOSITE_NOMUX(DCLK_HDMIPHY, "dclk_hdmiphy", "mpll", 0, + COMPOSITE_NOMUX(DCLK_HDMIPHY, "dclk_hdmiphy", "mpll_src", 0, RK3368_CLKSEL_CON(16), 8, 8, DFLAGS, - RK3368_CLKGATE_CON(2), 11, GFLAGS), + RK3368_CLKGATE_CON(5), 7, GFLAGS), COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0, RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS, @@ -566,10 +573,6 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = { * Clock-Architecture Diagram 7 */ - COMPOSITE_NOMUX(PCLK_HDMI_PHY, "pclk_hdmi_phy", "mpll", 0, - RK3368_CLKSEL_CON(16), 8, 8, DFLAGS, - RK3368_CLKGATE_CON(5), 7, GFLAGS), - COMPOSITE_NODIV(0, "btclk520_pll", mux_pll_src_cpll_gpll_npll_npll_p, 0, RK3368_CLKSEL_CON(5), 13, 2, MFLAGS, RK3368_CLKGATE_CON(2), 10, GFLAGS), diff --git a/include/dt-bindings/clock/rk3366-cru.h b/include/dt-bindings/clock/rk3366-cru.h index c5569d5bfb28..8c7bf158fdcf 100644 --- a/include/dt-bindings/clock/rk3366-cru.h +++ b/include/dt-bindings/clock/rk3366-cru.h @@ -159,7 +159,6 @@ #define PCLK_HDMI_CTRL 357 #define PCLK_VIO_H2P 358 #define PCLK_WDT 359 -#define PCLK_HDMI_PHY 360 #define PCLK_BUS 361 #define PCLK_PERI0 362 #define PCLK_PERI1 363 -- 2.34.1