From 9e76a3ad71111d3401cea7eabbadfe509b4b8d2b Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Tue, 14 Jun 2016 17:49:15 +0800
Subject: [PATCH] ARM64: dts: rk3399: pd: add clk control when pd on/off

make sure the clk is enabled when read/write qos regs.

Change-Id: Ia88453504bcfd612a86537c4b12d3fd5b53f3d76
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 34f1239f35da..8d693cff4b4f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -867,19 +867,27 @@
 
 			pd_vdu {
 				reg = <RK3399_PD_VDU>;
+				clocks = <&cru ACLK_VDU>,
+					 <&cru HCLK_VDU>;
 				pm_qos = <&qos_video_m1_r>,
 					 <&qos_video_m1_w>;
 			};
 			pd_vcodec {
 				reg = <RK3399_PD_VCODEC>;
+				clocks = <&cru ACLK_VCODEC>,
+					 <&cru HCLK_VCODEC>;
 				pm_qos = <&qos_video_m0>;
 			};
 			pd_iep {
 				reg = <RK3399_PD_IEP>;
+				clocks = <&cru ACLK_IEP>,
+					 <&cru HCLK_IEP>;
 				pm_qos = <&qos_iep>;
 			};
 			pd_rga {
 				reg = <RK3399_PD_RGA>;
+				clocks = <&cru ACLK_RGA>,
+					 <&cru HCLK_RGA>;
 				pm_qos = <&qos_rga_r>,
 					 <&qos_rga_w>;
 			};
@@ -890,16 +898,23 @@
 
 				pd_isp0 {
 					reg = <RK3399_PD_ISP0>;
+					clocks = <&cru ACLK_ISP0>,
+						 <&cru HCLK_ISP0>;
 					pm_qos = <&qos_isp0_m0>,
 						 <&qos_isp0_m1>;
 				};
 				pd_isp1 {
 					reg = <RK3399_PD_ISP1>;
+					clocks = <&cru ACLK_ISP1>,
+						 <&cru HCLK_ISP1>;
 					pm_qos = <&qos_isp1_m0>,
 						 <&qos_isp1_m1>;
 				};
 				pd_hdcp {
 					reg = <RK3399_PD_HDCP>;
+					clocks = <&cru ACLK_HDCP>,
+						 <&cru HCLK_HDCP>,
+						 <&cru PCLK_HDCP>;
 					pm_qos = <&qos_hdcp>;
 				};
 				pd_vo {
@@ -909,17 +924,22 @@
 
 					pd_vopb {
 						reg = <RK3399_PD_VOPB>;
+						clocks = <&cru ACLK_VOP0>,
+							 <&cru HCLK_VOP0>;
 						pm_qos = <&qos_vop_big_r>,
 							 <&qos_vop_big_w>;
 					};
 					pd_vopl {
 						reg = <RK3399_PD_VOPL>;
+						clocks = <&cru ACLK_VOP1>,
+							 <&cru HCLK_VOP1>;
 						pm_qos = <&qos_vop_little>;
 					};
 				};
 			};
 			pd_gpu {
 				reg = <RK3399_PD_GPU>;
+				clocks = <&cru ACLK_GPU>;
 				pm_qos = <&qos_gpu>;
 			};
 		};
-- 
2.34.1