From 598b411c7ef1b1ba8cab20d5f9514e7ca7db0f40 Mon Sep 17 00:00:00 2001 From: lintao Date: Mon, 21 Jul 2014 18:55:12 +0800 Subject: [PATCH] mmc: rk_sdmmc: fix coding style of 312x.dtsi --- arch/arm/boot/dts/rk312x.dtsi | 93 ++++++++++++++++++----------------- 1 file changed, 47 insertions(+), 46 deletions(-) diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi index 3737686a6ec9..49779776fbaf 100755 --- a/arch/arm/boot/dts/rk312x.dtsi +++ b/arch/arm/boot/dts/rk312x.dtsi @@ -223,60 +223,61 @@ }; emmc: rksdmmc@1021c000 { compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc"; - reg = <0x1021c000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - //pinctrl-names = "default",,"suspend"; - //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>; - clocks = <&clk_emmc>, <&clk_gates7 0>; - clock-names = "clk_mmc", "hclk_mmc"; - dmas = <&pdma 12>; - dma-names = "dw_mci"; - num-slots = <1>; - fifo-depth = <0x100>; - bus-width = <8>; + reg = <0x1021c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default",,"suspend"; + //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>; + clocks = <&clk_emmc>, <&clk_gates7 0>; + clock-names = "clk_mmc", "hclk_mmc"; + dmas = <&pdma 12>; + dma-names = "dw_mci"; + num-slots = <1>; + fifo-depth = <0x100>; + bus-width = <8>; status = "disabled"; }; sdmmc: rksdmmc@10214000 { - compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc"; - reg = <0x10214000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - //pinctrl-names = "default", "idle"; - //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - //pinctrl-1 = <&sdmmc0_gpio>; - //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/ - clocks = <&clk_sdmmc0>, <&clk_gates5 10>; - clock-names = "clk_mmc", "hclk_mmc"; - dmas = <&pdma 10>; - dma-names = "dw_mci"; - num-slots = <1>; - fifo-depth = <0x100>; - bus-width = <4>; + compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc"; + reg = <0x10214000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default", "idle"; + //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + //pinctrl-1 = <&sdmmc0_gpio>; + //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/ + clocks = <&clk_sdmmc0>, <&clk_gates5 10>; + clock-names = "clk_mmc", "hclk_mmc"; + dmas = <&pdma 10>; + dma-names = "dw_mci"; + num-slots = <1>; + fifo-depth = <0x100>; + bus-width = <4>; status = "disabled"; - }; + }; + sdio: rksdmmc@10218000 { - compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc"; - reg = <0x10218000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - //pinctrl-names = "default","idle"; - //pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; - //pinctrl-1 = <&sdio0_gpio>; - clocks = <&clk_sdio>, <&clk_gates5 11>; - clock-names = "clk_mmc", "hclk_mmc"; - dmas = <&pdma 11>; - dma-names = "dw_mci"; - num-slots = <1>; - fifo-depth = <0x100>; - bus-width = <4>; + compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc"; + reg = <0x10218000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + //pinctrl-names = "default","idle"; + //pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; + //pinctrl-1 = <&sdio0_gpio>; + clocks = <&clk_sdio>, <&clk_gates5 11>; + clock-names = "clk_mmc", "hclk_mmc"; + dmas = <&pdma 11>; + dma-names = "dw_mci"; + num-slots = <1>; + fifo-depth = <0x100>; + bus-width = <4>; status = "disabled"; - }; + }; adc: adc@2006c000 { compatible = "rockchip,saradc"; -- 2.34.1