From 56173870ac91228300dca8ec39606cf064b2e3b0 Mon Sep 17 00:00:00 2001 From: Wu Liang feng Date: Tue, 23 Aug 2016 09:11:41 +0800 Subject: [PATCH] phy: phy-rockchip-typec: fix rx eq training fail When do Rx compliance test, PHY is in loopback mode, we observed that Rx test failed with long cable, and it was found that equalizer adaptation is not happening properly. With rx_eq_training forced from PMA, the equalizer adaptation working fine and Rx test can pass. The root cause is that the Rx REE component will be turned off when control data is being received by default PHY configuration. So we need to unmask REE control data by setting REE control data mask register, and with this patch, equalizer training will happen based on the signal coming from controller only. Change-Id: Ic4fca1045d92381470588c4afccff0cc7318ab4c Signed-off-by: Wu Liang feng --- drivers/phy/phy-rockchip-typec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/phy-rockchip-typec.c b/drivers/phy/phy-rockchip-typec.c index b09699b3a5e9..420cd13bcb7c 100644 --- a/drivers/phy/phy-rockchip-typec.c +++ b/drivers/phy/phy-rockchip-typec.c @@ -165,6 +165,7 @@ #define RX_SLC_QEN1_OVRD (0x8155 << 2) #define RX_SLC_EEN0_OVRD (0x8159 << 2) #define RX_SLC_EEN1_OVRD (0x815d << 2) +#define RX_REE_CTRL_DATA_MASK(n) ((0x81bb | ((n) << 9)) << 2) #define RX_DIAG_SIGDET_TUNE(n) ((0x81dc | ((n) << 9)) << 2) #define RX_DIAG_SC2C_DELAY (0x81e1 << 2) @@ -372,6 +373,7 @@ static void tcphy_rx_usb_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) writel(0x2410, tcphy->base + RX_PSC_A3(lane)); writel(0x23ff, tcphy->base + RX_PSC_CAL(lane)); writel(0x13, tcphy->base + RX_SIGDET_HL_FILT_TMR(lane)); + writel(0x03e7, tcphy->base + RX_REE_CTRL_DATA_MASK(lane)); writel(0x1004, tcphy->base + RX_DIAG_SIGDET_TUNE(lane)); writel(0x2010, tcphy->base + RX_PSC_RDY(lane)); writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); -- 2.34.1