From 29d37eb1952bb4a1a47606310c59741e67d70028 Mon Sep 17 00:00:00 2001
From: Frank Wang <frank.wang@rock-chips.com>
Date: Mon, 22 Feb 2016 16:07:45 +0800
Subject: [PATCH] ARM64: dts: add usb2.0 dwc otg configuration for RK3368 sheep
 board

Change-Id: I01fd9671f89d9e61e2a59ac2272569ce8ebfd092
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 .../boot/dts/rockchip/rk3368-tb-sheep.dts     | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts b/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
index ffd3a1e81f0c..da3ba72a5b35 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
@@ -46,6 +46,35 @@
 / {
 	model = "Rockchip Sheep board";
 	compatible = "rockchip,sheep", "rockchip,rk3368";
+
+	dwc_control_usb: dwc-control-usb {
+		compatible = "rockchip,rk3368-dwc-control-usb";
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "otg_id", "otg_bvalid",
+				  "otg_linestate", "host0_linestate";
+		clocks = <&cru HCLK_USB_PERI>, <&cru SCLK_USBPHY480M>;
+		clock-names = "hclk_usb_peri", "usbphy_480m";
+
+		usb_bc {
+			compatible = "inno,phy";
+			regbase = &dwc_control_usb;
+			rk_usb,bvalid     = <0x4bc 23 1>;
+			rk_usb,iddig      = <0x4bc 26 1>;
+			rk_usb,vdmsrcen   = <0x718 12 1>;
+			rk_usb,vdpsrcen   = <0x718 11 1>;
+			rk_usb,rdmpden    = <0x718 10 1>;
+			rk_usb,idpsrcen   = <0x718  9 1>;
+			rk_usb,idmsinken  = <0x718  8 1>;
+			rk_usb,idpsinken  = <0x718  7 1>;
+			rk_usb,dpattach   = <0x4b8 31 1>;
+			rk_usb,cpdet      = <0x4b8 30 1>;
+			rk_usb,dcpattach  = <0x4b8 29 1>;
+		};
+	};
 };
 
 &rt5640 {
@@ -88,3 +117,23 @@
 &gpu {
 	logic-supply = <&vdd_logic>;
 };
+
+&dwc_control_usb {
+	host_drv_gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
+	otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
+
+	rockchip,remote_wakeup;
+	rockchip,usb_irq_wakeup;
+};
+
+&usb_otg {
+	clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
+	clock-names = "sclk_otgphy0", "otg";
+	resets = <&cru SRST_USBOTG_AHB>,
+		 <&cru SRST_USBOTG_PHY>,
+		 <&cru SRST_USBOTG_CON>;
+	reset-names = "otg_ahb", "otg_phy", "otg_controller";
+	/* 0 - Normal, 1 - Force Host, 2 - Force Device */
+	rockchip,usb-mode = <0>;
+	status = "okay";
+};
-- 
2.34.1