From 15e1a8fff456e793654f6377d0c55c2168d45252 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 7 Apr 2017 17:35:28 +0800 Subject: [PATCH 1/1] clk: rockchip: rk3368: add aclk_cci_pre ID Change-Id: I855e79023a9e244c2db37af88a075a4ef4c36aec Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3368.c | 4 ++-- include/dt-bindings/clock/rk3368-cru.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index a5e5050e4ccf..89a9d0a78d6f 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -329,8 +329,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { RK3368_CLKSEL_CON(4), 8, 5, DFLAGS, RK3368_CLKGATE_CON(0), 13, GFLAGS), - COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS, + COMPOSITE(ACLK_CCI_PRE, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED, + RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3368_CLKGATE_CON(0), 12, GFLAGS), GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS), diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h index 24ba64ec9866..690800da96b0 100644 --- a/include/dt-bindings/clock/rk3368-cru.h +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -115,6 +115,7 @@ #define ACLK_VIDEO 208 #define ACLK_BUS 209 #define ACLK_PERI 210 +#define ACLK_CCI_PRE 211 /* pclk gates */ #define PCLK_GPIO0 320 -- 2.34.1