clk: rockchip: add basic infrastructure for clock branches
authorHeiko Stübner <heiko@sntech.de>
Wed, 2 Jul 2014 23:58:39 +0000 (01:58 +0200)
committerMike Turquette <mturquette@linaro.org>
Sun, 13 Jul 2014 19:17:06 +0000 (12:17 -0700)
commita245fecbb8064641d9cc317b347b5bdb2b7a4bb6
treed4573cc7258ecc18e9db839f809960062ee419b0
parent5a994e151f7c54a5fdeb07fe2fed4ed64b9321b8
clk: rockchip: add basic infrastructure for clock branches

This adds infrastructure for registering clock branches. On Rockchip SoCs
most clock branches are a combination of mux,divider and gate components,
thus a composite clock is used when appropriate.

Clock branches are supposed to be declared in an array using the COMPOSITE*
or MUX, etc makros defined in the header and then registered using
rockchip_clk_register_branches.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/rockchip/Makefile
drivers/clk/rockchip/clk.c [new file with mode: 0644]
drivers/clk/rockchip/clk.h [new file with mode: 0644]