ARM64: dts: rk3366: update gpu's opp table

Change-Id: I1c3ccc7b896b4fe95f834a957a4ebe2aef482806
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

ARM64: defconfig: add the basic config for 3399 ChromeOS

With this defconfig which inherits from rockchip_defconfig,
ChromeOS boots up to command line.

Change-Id: I646fea9b26d9c235da16d0d2b559290ee5029a12
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

ARM64: dts: rk3366-tb: add regulator-ramp-delay of vdd_arm

Change-Id: If4eb8f964592d2f6c0e418659b12f672dc9abb94
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

Documentation: bindings: add compatible entry for Rockchip USB2.0 PHY

1. Compatible "rockchip,rk3399-usb-phy" support to RK3399;
2. Add host_drv_gpio optional property for usb2.0 vbus control.

Change-Id: Idfc6898ca2c519c46dae66d396f501b38e8d73bd
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM64: rockchip_defconfig: enable dwc3 and xhci drivers

Change-Id: I3c3dae4bf999cb3e7141d88bdfa60e50ab46e2fd
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: rockchip: Add device tree binding

Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.

Change-Id: I116b66c3b417cfecc968414db9912813a0ef2c5d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: of-simple: add compatible for rk3399

Change-Id: I0a74fcd97c5be7887b4d14bb708a58a10f70e71c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3399: enable usbdrd3_0 and usbdrd3_1

Change-Id: I2321c1b0651a1a0ad1352e1409d8c9cef1428a67
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3399: add usbdrd3_0 and usbdrd3_1 nodes

Change-Id: I4b940966e3b054e072de90f6943ab20006848495
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3366: update cpu's opp table

Change-Id: Id0d722d90672f78941073a4ad7e45615893b1e90
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

ARM64: rockchip_defconfig: enable rk808 regulator

set CONFIG_REGULATOR_RK808=y

Change-Id: I9cfc60fc82a4cb7dc4056bd13f3d678d6a0f7faf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: fix pmu cru register name error

Change-Id: I4ab865326657dceaf8759b37d02d80de9e3071c0
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: add some clock IDs for reference

Change-Id: I8ce291b7145a56aea9d8f5b5742506a581f26912
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: fix PLL table and add pclk DFLAG for rk3399

Change-Id: Id89c7099b24fdcff967528a3741af2e84fa1a754
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

video: rockchip: fb: the default state of FBDC is closed

Change-Id: I6c1a4e47daa00089bfeb7b7316dbe6bac4409a5c
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: lcdc: 3368: update for FBDC

FBDC state |= win[i]->area[0]->fbdc_en;

Change-Id: I2ddfdea66061ad67b876369c130b8cfa6e3bda55
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: init saved_list

Change-Id: I2da026cfcef25c6ae44356d0c3869e482cb97e11
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: lcdc: 3366: add more format for gather

Change-Id: I5d20a52f1bd680af4083672b0607fa95332d7146
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

iommu: rk-iovmm: change compatible name to a unified name

To make android platform iommu work well, we need a unified compatible
name to match the new iommu definition in dtsi

Change-Id: Ied581653e1261fd0a21577f4e9ce3b915af135cd
Signed-off-by: Simon <xxm@rock-chips.com>

video: rockchip: mipi: remove the function of get dsi host id

The rk3288, rk3368 and rk3366 have the same physical dsi id 0x3133302A,
so do not need to get dsi host id.

Change-Id: I0de1e9b7c0250b37ffdc2c39155c5f16afb48956
Signed-off-by: xubilv <xbl@rock-chips.com>

ARM64: dts: rk3366: mipi: modify compatible

Change-Id: I05bb54c00019310fb57a0bc3fb0bd365aaed10dd
Signed-off-by: xubilv <xbl@rock-chips.com>

video: rockchip: rk3366: add mipi support

Change-Id: Ibf70a23ba2fe02cff5e66932bc802264768d05cf
Signed-off-by: xubilv <xbl@rock-chips.com>

ARM64: dts: rk3366: assign rates for aclk_bus and aclk_peri

Assign rates for aclk_bus and aclk_peri according to our original design.

Change-Id: Iab4961d485421151be5dbdacf6929800150ab342
Signed-off-by: Feng Xiao <xf@rock-chips.com>

clk: rockchip: rk3366: modify cpuclk_rate_table

add 1296MHz, 1104MHz and 216MHz to the cpuclk_rate_table list

Change-Id: I1ea7ee432b7c69b89cb3c11a74e67d9d6af1a5dd
Signed-off-by: Feng Xiao <xf@rock-chips.com>

clk: rockchip: fix big/LITTLE cores alternate parent failed

Change-Id: Iebe33903ad5a06f276454ffe12654866bd9567eb
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: fix pclk_pmu_src clock for rk3399

Change-Id: I1e9c04366af370664d864d2877fa87a385da44a6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: fix uart4_pmu and mipidphy_ref clock for rk3399

Change-Id: I307e4480cb4eb52c447b2db47643b478d4292500
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

video: rockchip: hdmi: v2: modify phy reg to pass CTS signal quality test

Change-Id: Ife9f9808dcc29320f628bf91005e16f22bbe3c50
Signed-off-by: xuhuicong <xhc@rock-chips.com>

ARM64: dts: rk3399-tb: enable emmc_phy and sdhci

Change-Id: I0693b5e3f194b3fb0aed73784d0242ebf89d4ebe
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3366: assigned parents for clk_32k

Change-Id: I1742823658aa46226e3112969d3eabc695921fb5
Signed-off-by: Feng Xiao <xf@rock-chips.com>

ARM64: dts: rk3366: assigned parents for vop dclks

For sheep board, we have decided to assign vop full for
use with HDMI. And we can also change it in the board
dts in the further.

Change-Id: Id966615c84cef50f0e8d849e3840434ba7f7b7ec
Signed-off-by: Feng Xiao <xf@rock-chips.com>

clk: rockchip: rk3366: leave npll for VOP only

We will need a pll to support all kinds of clock rate requirement
for HDMI which may change the rate at run time.

In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP(FULL or LITE) can
select npll as parent. Also add the ability for DCLK_VOP to set
the rate of its parent (which is now forced to NPLL).

Change-Id: I1e13ef1c4f1b9728f9c173454d5056780c47a95e
Signed-off-by: Feng Xiao <xf@rock-chips.com>

phy: rockchip-emmc: add init function

We need to init some signal related stuff
to make sure the SI meet the requirement.

Change-Id: I829203fb9cd2e93aa6acaa5288667f600370d781
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

arm64: dts: rockchip: add compatible for rk3399evb board

Coreboot choose dtb by its compatible string.
Add "google,rk3399evb-rev*" accordingly.

Support more versions for rk3399evb in the future.
If we later find we need to introduce differences between versions,
it's easy to change things.

Change-Id: I049b4f113b1694577a1f0be68f6b635ae13653c0
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

clk: rockchip: fix cci src clocks for rk3399

Change-Id: I9c22a270c64feaf52436117e47fb874000361100
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: add some critical clocks for rk3399

Change-Id: I1a04f11f881764929d9e5801626ce398bc3b193e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: update dt-binding header for rk3399 pmucru IDs

Change-Id: I302dc97a3ec5ef5cd7609ecff929c6fea25f005b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399: fix incorrect pmucru reference

Change-Id: I4e6743eecf14597cc3391fd4f80ad329ee7b5785
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: fix and add some critical clocks for rk3399

Change-Id: I1db9ab40ba9c25d5054a4011eee1ea14f1207443
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: update dt-binding header for rk3399 pmucru clock IDs

Change-Id: Ic19ea01466ab4d90210cedbbb1d0bce21e3800e1
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

iommu/rockchip: fix bool operation error and probe warning

Bool type true is exactly BIT(0), so
bool enable = true;
enable &= BIT(2);
enable will be false, which isn't the result we expected in this case.
Change bool type to u32.

The other fix is checking the res in probe() to skip the irq resource.

Change-Id: I2947c9f1e15cb92f03096d26a44759c107bfacd1
Reported-by: Simon <xxm@rock-chips.com>
Suggested-by: Simon <xxm@rock-chips.com>
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

ARM64: dts: rk3399-monkey: fix uart2 address error

Change-Id: Id857682e49063fb4d47253385b930acb59327046
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

rockchip: clk: rk3399: fix up clk tree assigned error

add some clk id.

Change-Id: Iffc3fbfa557e5d01f70ab0be2d84a85cff7ac34c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

video: rockchip: hdmi: v2: modify phy clock rate to reduce tdms clock jitter

set hdmi phy clock as 148.5Mhz when dclk rate over this frequency

Change-Id: I416b2b98fe42fafc45491b66252f245aed0f1364
Signed-off-by: xuhuicong <xhc@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time

It may caused a dead lock if we flush the hpd work in bridge disable time.

The normal flow would like:
  IN --> DRM IOCTL
        1. Acquire crtc_ww_class_mutex (DRM IOCTL)
  IN --> analogix_dp_bridge
        2. Acquire hpd work lock (Flush hpd work)
        3. HPD work already in idle, no need to run the work function.
  OUT <-- analogix_dp_bridge
  OUT <-- DRM IOCTL

The dead lock flow would like:
  IN --> DRM IOCTL
        1. Acquire crtc_ww_class_mutex (DRM IOCTL)
  IN --> analogix_dp_bridge
        2. Acquire hpd work lock (Flush hpd work)
  IN --> analogix_dp_hotplug
  IN --> drm_helper_hpd_irq_event
        3. Acquire mode_config lock (This lock already have been acquired in previous step 1)
** Dead Lock Now **

It's wrong to flush the hpd work in bridge->disable time, I guess the
original code just want to ensure the delay work must be finish before
encoder disabled.

The flush work in bridge disable time is try to ensure the HPD event
won't be missed before display card disabled, actually we can take a
fast respond way(interrupt thread) to update DRM HPD event to fix the
delay update and possible dead lock.

(am from https://patchwork.kernel.org/patch/8313001/)

Change-Id: Id7b357de0f497ff8c9f259fe31dc28be34f17083
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time

Turn off the panel power in suspend time would help to reduce
power waste.

(am from https://patchwork.kernel.org/patch/8312971/)

Change-Id: Iac01ac4041a2486e0347ed0377abcc094ab493ea
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: add edid modes parse in get_modes method

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase

But for now driver need to read edid message in .get_modes()
function, so controller must be inited in bind time, so we
need to add controller init back.

(am from https://patchwork.kernel.org/patch/8312921/)

Change-Id: I32abee21665a7e1470f2898b7fbc925108f9d768
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: move hpd detect to connector detect function

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase

But for now the connector status don't hardcode to connected,
need to operate dp phy in .detect function, so we need to revert
parts if Gustavo Padovan's changes, add phy poweron
function in bind time.

(am from https://patchwork.kernel.org/patch/8312901/)

Change-Id: I0ed1be541210f85883477f1b2a88bd8d57e390d6
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: try force hpd after plug in lookup failed

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

(am from https://patchwork.kernel.org/patch/8313081/)

Change-Id: If99d29936aafd996c98568d6e184aee6d9c8bc47
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

(am from https://patchwork.kernel.org/patch/8312881/)

Change-Id: Id1432af874eb0a6dec819d7b7e735c1040f4bf5c
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: add some rk3288 special registers setting

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

(am from https://patchwork.kernel.org/patch/8312861/)

Change-Id: I422216f58a18f2c2fee187b4f19de7b9d0fcd05a
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: dt-bindings: add document for rockchip variant of analogix_dp

Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.

(am from https://patchwork.kernel.org/patch/8312841/)

Change-Id: If7a422554ac09cd3ed40eac8191369df532c58bf
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: rockchip: dp: add rockchip platform dp driver

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

(am from https://patchwork.kernel.org/patch/8615371/)

Change-Id: Ibe22447ab881b7421e999479cbdfd529d183f6b4
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver

After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.

Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.

(am from https://patchwork.kernel.org/patch/8312821/)

Change-Id: I79adafdb4a086d4a357678282cc653a7e3432da9
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: dt-bindings: add document for analogix display port driver

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

(am from https://patchwork.kernel.org/patch/8312811/)

Change-Id: Ia1d47783b735868a4f56231660d8309cf9c75923
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

(am from https://patchwork.kernel.org/patch/8312791/)

Change-Id: Ia7f37daf40fa2d0516d5c44737ad36b5822c6015
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

(am from https://patchwork.kernel.org/patch/8312771/)

Change-Id: I8cbf7146d70143bb5d30b3fa971e19f034c30e62
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: fix some obvious code style

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

(am from https://patchwork.kernel.org/patch/8615381/)

Change-Id: I49198f28156ae5761ba0aa8e8479bbdc963d9b25
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: rename register constants

In the original split we kept the register constants intact to keep the
diff small. Still the constants are Analogix-specific, so rename them now.

(am from https://patchwork.kernel.org/patch/8312781/)

Change-Id: I714d60bc941b7a992dd34d4c0804576bd07ca84d
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: split exynos dp driver to bridge directory

Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.

Beside the new analogix_dp driver would export six hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_suspned()" and "analogix_dp_resume()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"

The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.

They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.

(am from https://patchwork.kernel.org/patch/8615401/)

Change-Id: Iad075ae92ba9fa08674fb3d36488f7691909fead
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: removed optional dummy encoder mode_fixup function.

mode_fixup function for encoder drivers became optional with patch
http://patchwork.freedesktop.org/patch/msgid/1455106522-32307-1-git-send-email-palminha@synopsys.com

This patch set nukes all the dummy mode_fixup implementations.

(made on top of Daniel topic/drm-misc branch)

(cherry picked from commit 586236251464a9fcf44757f8639e531d8af628f9)

Change-Id: I58ea3c6042f4ceca0bdf0cbac57175fdb53d05b2
Signed-off-by: Carlos Palminha <palminha@synopsys.com>
[danvet: Squash in 2nd exynos patch.]
Link: http://patchwork.freedesktop.org/patch/msgid/3768b670931572de51fca1102efa18d20dd770ee.1455540137.git.palminha@synopsys.com
Link: http://patchwork.freedesktop.org/patch/msgid/4906a9925eebbe55489b1005c449b426a61c09bd.1455540137.git.palminha@synopsys.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: dp: Fix panel and bridge lookup logic

Commit a9fa852886fd ("drm/exynos: dp: add of_graph dt binding support
for panel") made the Exynos DP DT binding more consistent since the OF
graph could be used to lookup either a panel or a bridge device node.

Before that commit, a panel would be looked up using a phandle and a
bridge using the OF graph which made the DT binding not consistent.

But the patch broke the later case since not finding a panel dev node
would cause the driver's to do a probe deferral instead of attempting
to lookup a bridge device node associated with the remote endpoint.

So instead of returning a -EPROBE_DEFER if a panel is not found, check
if there's a bridge and only do a probe deferral if both aren't found.

(cherry picked from commit 37e110625eeeaba83e8cb763ab7645f0678c6f8e)

Change-Id: If8b66d792447d4e3455f99dc38b04f334b8b65a6
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: Constify function pointer structs

Moves a bunch of junk to .rodata from .data.

 drivers/gpu/drm/exynos/exynosdrm.ko:
-.text                       125792
+.text                       125788
-.rodata                      10972
+.rodata                      11748
-.data                         6720
+.data                         5944

(cherry picked from commit 800ba2b58182e4b0e8dc826a27362d45499068b1)

Change-Id: I8261dbe53224b581a20102253b162cc3a2563b58
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1450178476-26284-19-git-send-email-boris.brezillon@free-electrons.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: dp: add of_graph dt binding support for panel

This patch adds of_graph dt binding support for panel device
and also keeps the backward compatibility.

i.e.,
The dts file for Exynos5800 based peach pi board
has a panel property so we need to keep the backward compatibility.

Changelog v3:
- bind only one of two nodes outbound - panel or bridge.

Changelog v2:
- return -EINVAL if getting a port node failed.

(cherry picked from commit a9fa852886fd5a7ccec3b7e9eff75f85072f009c)

Change-Id: Ie300bdc95027269f4a6b0d7fef8d6f0ca4017f06
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: add pm_runtime to DP

Let pm_runtime handle the enabling/disabling of the device with
proper refcnt instead of rely on specific flags to track the enabled
state.

Chnagelog v3:
- revive dpms_mode to keep current dpms mode.

Changelog v2:
- no change

(cherry picked from commit 613d3853c2aca6cfd990e8bd0b436833b6c76db6)

Change-Id: Ieac8db078030f9331135ff0bc43a3a41d56d3b62
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: do not start enabling DP at bind() phase

The DP device will be properly enabled at the enable() call just
after the bind call finishes.

Changelog v2:
- no change

(cherry picked from commit 07c42703029244fb4b82593b0362d3f99c4268a4)

Change-Id: Id606cf49e9027036d9c7681b23f39681a3db5e87
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

ARM: dts: rk3366-tb: add declaration of smart card reader controller

Change-Id: I6a70ffccabb326bc691fd304db4b9df869530ee0
Signed-off-by: Aiyoujun <ayj@rock-chips.com>

ARM: configs: rockchip_defconfig: add SOC smart card reader controller.

Change-Id: I505e9c4d23ab23d50e5d31a68b576771ac9dd3c7
Signed-off-by: Aiyoujun <ayj@rock-chips.com>

dt-bindings: rockchip-scr: add rockchip SOC smart card reader controller.

Change-Id: I735c86c164eef2ea119818abe8afa0dd8ee5647a
Signed-off-by: Aiyoujun <ayj@rock-chips.com>

ARM: dts: rk3366: add smart card reader controller's resource define.

Change-Id: Icb21dc6b529e2791414f19a915085437332736df
Signed-off-by: Aiyoujun <ayj@rock-chips.com>

misc: rockchip-scr: add rockchip SOC smart card reader controller driver.

Change-Id: I8d3ab66bc6fa7cbb4e8d9b2f2c5c2feee94a045b
Signed-off-by: Aiyoujun <ayj@rock-chips.com>

clk: rockchip: update clock controller for the RK3399

Fix some clock reference error.

Change-Id: I0505387160aa4b38753adfb82aabf7fb3b967ada
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: update dt-binding header for rk3399 some clock IDs

Add some clock IDs for driver reference them.

Change-Id: I43b2507a58f141f8e04a530b5e43db507097f301
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format

Add a helper that can be used to obtain the number of bits per pixel
corresponding to a given MIPI DSI pixel format. This is useful in
bandwidth calculations, for example.

Change-Id: I03b9f93044ed46a2b999ce82e5623396a6f4d2bc
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
[treding@nvidia.com: add kerneldoc comment and commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit ec26d9e9382f432225d76b3ff1c7f72e21192f7f)

UPSTREAM: iommu/rockchip: Reconstruct to support multi slaves

There are some IPs, such as video encoder/decoder, contains 2 slave iommus,
one for reading and the other for writing. They share the same irq and
clock with master.

This patch reconstructs to support this case by making them share the same
Page Directory, Page Tables and even the register operations.
That means every instruction to the reading MMU registers would be
duplicated to the writing MMU and vice versa.

Change-Id: I3fd473898274cffcfb46c907b34bd3a4adc29250
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Simon <xxm@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit cd6438c5f8446691afa4829fe1a9d7b656204f11)

FROMLIST: iommu: dma-iommu: use common implementation also on ARM architecture

This patch replaces ARM-specific IOMMU-based DMA-mapping implementation
with generic IOMMU DMA-mapping code shared with ARM64 architecture. The
side-effect of this change is a switch from bitmap-based IO address space
management to tree-based code. There should be no functional changes
for drivers, which rely on initialization from generic arch_setup_dna_ops()
interface. Code, which used old arm_iommu_* functions must be updated to
new interface.

To avoid build failed on ARCH arm,we mannually fix the following two files that
to use arch_set_dma_ops API

arch/arm/mach-highbank/highbank.c
arch/arm/mach-mvebu/coherency.c

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Conflicts:
arch/arm/mm/dma-mapping.c

Change-Id: Iffad16a7a511d50cc8e422bc61497f117279c66d
Signed-off-by: Simon <xxm@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.freedesktop.org/patch/74409/)

FROMLIST: iommu: dma-iommu: move IOMMU/DMA-mapping code from ARM64 arch to drivers

This patch moves all the IOMMU-based DMA-mapping code from arch/arm64/mm
to drivers/iommu/dma-iommu-ops.c. This way it can be easily shared with
ARM architecture, which will also use them.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Conflicts:
arch/arm64/mm/dma-mapping.c

Change-Id: I7d56fa5e6e6ef43ae6c9c76035fcf81ee5cb7069
Signed-off-by: Simon <xxm@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.freedesktop.org/patch/74408/)

ARM64: dts: rk3399-tb: add GMAC node for rk3399-tb

Change-Id: I31f984a40bf8e2c04243e47fed7435bd3e400c4c
Signed-off-by: Roger Chen <roger.chen@rock-chips.com>

UPSTREAM: dt-bindings: modify document of Rockchip power domains

Modify binding documentation for the power domains
found on Rockchip RK3368 SoCs.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
master commit 1f164bd5b7dd4a1903c274ca70bf1ab11684db99)

Change-Id: Id6ef1ecfb32ee92e3a339326c1354a60b9028a80
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399: add GMAC node for RK3399

Change-Id: I77eed48561b7ca16f77472aa4087e93497f6c010
Signed-off-by: Roger Chen <roger.chen@rock-chips.com>

net: stmmac: dwmac-rk: support RK3399 GMAC driver

Change-Id: Ib584d3526929fa37ae1e701c01971a61188d213b
Signed-off-by: Roger Chen <roger.chen@rock-chips.com>

video: rockchip: lcdc: 3366: 480i and 576i need sel dclk div2

Change-Id: Ibc27be643ae33a81d181d9398b362af0ce0c6f03
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop lite: fix lut config error

Change-Id: I201e3bb8a60650259e2de4f3973173039188fe34
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop lite: recover interlace config

Change-Id: I03171fd1546ead16f477cb255f2b1bbc1d20adf8
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: rename time line name for vop0 and vop1

Change-Id: Ifae7d4fc88dd41ecb659c886237a6d65026fded6
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rockchip: add clk_ignore_unused for rk3399

Change-Id: I2f6faf3807d5c3b347d8b6930cc8f29c56746b2a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

video: rockchip: vop: 3366: writeback function test ok

Change-Id: I560a714a86dad83f277d380c3650d4ed7827d80b
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop lite: add deal with BGR data format

Change-Id: I5cac5cfd6385c5a0aa4152c927053ecd55290031
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: add BGR data format support

Change-Id: Ia97a20b5ed1e3ab92e31136e0cb60a785b570a65
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

i2c: rk3x: add i2c support for rk3399 soc

- new method to caculate i2c timings for rk3399:
  There was an timing issue about "repeated start" time at the I2C
  controller of version0, controller appears to drop SDA at .875x (7/8)
  programmed clk high. On version 1 of the controller, the rule(.875x)
  isn't enough to meet tSU;STA
  requirements on 100k's Standard-mode. To resolve this issue,
  sda_update_config, start_setup_config and stop_setup_config for I2C
  timing information are added, new rules are designed to calculate
  the timing information at new v1.
- pclk and function clk are separated at rk3399.
- support i2c highspeed mode: 1.7MHz for rk3399

Change-Id: I413455cf94fe7486c40694059e2f0931433992bb
Signed-off-by: David Wu <david.wu@rock-chips.com>

i2c: rk3x: switch to i2c generic dt parsing

Switch to the new generic functions: i2c_parse_fw_timings().

Change-Id: I14c3bea8e696d0ba5467effba1a157cd86e376d6
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rk3399: add support clock assignment for PMUCRU/CRU

Change-Id: I8dc31880a232c1753c0fbfbeb4e3df0d09d7cdb3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: add clock controller for the RK3399

Add the clock tree definition for the new RK3399 SoC.

Change-Id: I1d8755eb7c89bdc56b79644a96a7d3fd8e7fbc4b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add rk3288 mipi_dsi nodes

Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.

Change-Id: I0181ec03b0c944a18391737ea6bb65c5b642a6ea
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit cab6f070ab53df0fa8a17e95ca7518a8c8e42e69)

UPSTREAM: Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver

add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver

Change-Id: Ie6774d527475889a6eab587e66eda607d1ea2c8b
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
(cherry picked from commit a20d86e7f96422d375dfa9ac0fe96ca4ce2aa647)

UPSTREAM: drm/panel: simple: Add support for BOE TV080WUM-NL0

The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel
connected using four DSI lanes. It can be supported by the simple-panel
driver.

Change-Id: I4fe03fc830332e60997e98b24550801827692501
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit c8521969dea2b8e10ecbba86e0221e4f63dce921)

UPSTREAM: dt-bindings: Add BOE TV080WUM-NL0 panel binding

The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel
connected using four DSI lanes.

Change-Id: I963cf860315f86ca64249c8f2064acbba62276b5
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit 86b81f3e17b34e245ee01cf2bd142d12fae125cc)

UPSTREAM: of: Add vendor prefix for BOE Technology Group

BOE Technology Group Co., Ltd. is a supplier of semiconductor display
technologies, products and services.

Change-Id: Id9a81512f6174770fc1d1282579da902fcdc89b0
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
[treding@nvidia.com: add commit message, fixup subject]
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit 27d23b30a561b752f1564d99cb6c8247c78f74f6)

UPSTREAM: clk: rockchip: add mipidsi clock on rk3288

sclk_mipidsi_24m is the gating of mipi dsi phy.

Change-Id: I15b3e7a17b06397eb825eb2faca37d77732c9a97
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit a2f4c560f18edd2ffe0f15d52ce2be55cff605d2)

UPSTREAM: clk: rockchip: add id for mipidsi sclk on rk3288

Adds a new id for the sclk supplying the mipidsi on rk3288 socs.

Change-Id: Ifc3b97e4feed01098b483162d6320240d4b44cb3
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c6d49fbcfcc44264c31f93866c9a713491e4a5fe)