From: Shawn Lin Date: Tue, 18 Oct 2016 01:41:29 +0000 (+0800) Subject: UPSTREAM: PCI: rockchip: fix wrong negotiated lanes calculation X-Git-Tag: firefly_0821_release~1237 X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=commitdiff_plain;h=c2b181bebf793b22009f97b17111b3099edca5b2 UPSTREAM: PCI: rockchip: fix wrong negotiated lanes calculation The calculation of negotiated lanes is wrong since it should be shifted by PCIE_CORE_PL_CONF_LANE_SHIFT, but it is shifted by PCIE_CORE_PL_CONF_LANE_MASK. Let's fix it. Change-Id: I164d07c86e944fdab7c1a3100c87fdd24ec0ee82 Fixes: commit e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Shawn Lin Signed-off-by: Bjorn Helgaas Signed-off-by: Shawn Lin (am from git.kernel.org/cgit/linux/kernel/git/next/linux-next.git commit 898a2301cf002e1d96c0d56e41131a0d57cacb65) --- diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index f204f8b60b00..fd8620f92cae 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -595,8 +595,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) /* Check the final link width from negotiated lane counter from MGMT */ status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL); - status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >> - PCIE_CORE_PL_CONF_LANE_MASK); + status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >> + PCIE_CORE_PL_CONF_LANE_SHIFT); dev_dbg(dev, "current link width is x%d\n", status); rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,