From: Chen Liang Date: Thu, 17 Sep 2015 06:50:29 +0000 (+0800) Subject: rk3228: initialize platform data X-Git-Tag: firefly_0821_release~3770 X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=commitdiff_plain;h=8446bec1954770379dd4cce0064f627ab78aecda rk3228: initialize platform data Change-Id: Id7fd0d98ef70641a62bd8520b72214141b5cf199 Signed-off-by: Chen Liang --- diff --git a/arch/arm/boot/dts/rk3228-clocks.dtsi b/arch/arm/boot/dts/rk3228-clocks.dtsi new file mode 100644 index 000000000000..b8da26ea235e --- /dev/null +++ b/arch/arm/boot/dts/rk3228-clocks.dtsi @@ -0,0 +1,2162 @@ +/* + * Copyright (C) 2014-2015 ROCKCHIP, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +/{ + clocks { + compatible = "rockchip,rk-clocks"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x110e0000 0x1000>; + + fixed_rate_cons { + compatible = "rockchip,rk-fixed-rate-cons"; + + xin24m: xin24m { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "xin24m"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + xin12m: xin12m { + compatible = "rockchip,rk-fixed-clock"; + clocks = <&xin24m>; + clock-output-names = "xin12m"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; + + hdmiphy_out: hdmiphy_out { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "hdmiphy_out"; + clock-frequency = <594000000>; + #clock-cells = <0>; + }; + + usbphy0_480m: usbphy0_480m { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "usbphy0_480m"; + clock-frequency = <480000000>; + #clock-cells = <0>; + }; + + usbphy1_480m: usbphy1_480m { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "usbphy1_480m"; + clock-frequency = <480000000>; + #clock-cells = <0>; + }; + + jtag_clkin: jtag_clkin { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "jtag_clkin"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + dummy: dummy { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "dummy"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + gmac_clkin: gmac_clkin { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "gmac_clkin"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + phy_50m_out: phy_50m_out { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "phy_50m_out"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + phy_rx_out: phy_rx_out { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "phy_rx_out"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + phy_tx_out: phy_tx_out { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "phy_tx_out"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + clkin_hsadc_tsp: clkin_hsadc_tsp { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "clkin_hsadc_tsp"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + i2s_clkin: i2s_clkin { + compatible = "rockchip,rk-fixed-clock"; + clock-output-names = "i2s_clkin"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + }; + + fixed_factor_cons { + compatible = "rockchip,rk-fixed-factor-cons"; + + hclk_rkvdec: hclk_rkvdec { + compatible = "rockchip,rk-fixed-factor-clock"; + clocks = <&aclk_rkvdec>; + clock-output-names = "hclk_rkvdec"; + clock-div = <4>; + clock-mult = <1>; + #clock-cells = <0>; + }; + + hclk_vpu: hclk_vpu { + compatible = "rockchip,rk-fixed-factor-clock"; + clocks = <&aclk_vpu>; + clock-output-names = "hclk_vpu"; + clock-div = <4>; + clock-mult = <1>; + #clock-cells = <0>; + }; + + xin32k_out: xin32k_out { + compatible = "rockchip,rk-fixed-clock"; + clocks = <&clk_hdmi_cec>; + clock-output-names = "xin32k_out"; + clock-div = <1>; + clock-mult = <1>; + #clock-cells = <0>; + }; + + }; + + clock_regs { + compatible = "rockchip,rk-clock-regs"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0000 0x1000>; + ranges; + + /* PLL control regs */ + pll_cons { + compatible = "rockchip,rk-pll-cons"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_apll: pll-clk@0000 { + compatible = "rockchip,rk3188-pll-clk"; + reg = <0x0000 0x10>; + mode-reg = <0x0040 0>; + status-reg = <0x04 10>; + clocks = <&xin24m>; + clock-output-names = "clk_apll"; + rockchip,pll-type = ; + #clock-cells = <0>; + }; + + clk_dpll: pll-clk@000c { + compatible = "rockchip,rk3188-pll-clk"; + reg = <0x000c 0x10>; + mode-reg = <0x0040 4>; + status-reg = <0x10 10>; + clocks = <&xin24m>; + clock-output-names = "clk_dpll"; + rockchip,pll-type = ; + #clock-cells = <0>; + }; + + + clk_cpll: pll-clk@0018 { + compatible = "rockchip,rk3188-pll-clk"; + reg = <0x0018 0x10>; + mode-reg = <0x0040 8>; + status-reg = <0x1c 10>; + clocks = <&xin24m>; + clock-output-names = "clk_cpll"; + rockchip,pll-type = ; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + clk_gpll: pll-clk@0024 { + compatible = "rockchip,rk3188-pll-clk"; + reg = <0x0024 0x10>; + mode-reg = <0x0040 12>; + status-reg = <0x28 10>; + clocks = <&xin24m>; + clock-output-names = "clk_gpll"; + rockchip,pll-type = ; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + }; + + /* Select control regs */ + clk_sel_cons { + compatible = "rockchip,rk-sel-cons"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_sel_con0: sel-con@0044 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0044 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_core_div: clk_core_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&clk_core>; + clock-output-names = "clk_core"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + rockchip,flags = <(CLK_GET_RATE_NOCACHE | + CLK_SET_RATE_NO_REPARENT)>; + }; + + /* 5 reserved */ + + clk_core: clk_core_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <6 2>; + clocks = <&clk_apll>, <&clk_gpll>, <&clk_dpll>; + clock-output-names = "clk_core"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + aclk_bus: aclk_bus_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&aclk_bus_mux>; + clock-output-names = "aclk_bus"; + rockchip,div-type = ; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + aclk_bus_mux: aclk_bus_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <13 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>; + clock-output-names = "aclk_bus"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15 reserved */ + + }; + + clk_sel_con1: sel-con@0048 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0048 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + pclk_dbg: pclk_dbg_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 4>; + clocks = <&clk_core>; + clock-output-names = "pclk_dbg"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + aclk_core: aclk_core_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <4 3>; + clocks = <&clk_core>; + clock-output-names = "aclk_core"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 7 reserved */ + + hclk_bus: hclk_bus_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 2>; + clocks = <&aclk_bus>; + clock-output-names = "hclk_bus"; + rockchip,div-type = ; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 11:10 reserved */ + + pclk_bus: pclk_bus_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <12 3>; + clocks = <&aclk_bus>; + clock-output-names = "pclk_bus"; + rockchip,div-type = ; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15 reserved */ + + }; + + clk_sel_con2: sel-con@004c { + compatible = "rockchip,rk3188-selcon"; + reg = <0x004c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + hclk_vio: hclk_vio_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&aclk_iep>; + clock-output-names = "hclk_vio"; + rockchip,div-type = ; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 7:5 reserved */ + + clk_nandc_div: clk_nandc_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&clk_nandc>; + clock-output-names = "clk_nandc"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + }; + + /* 13: reserved */ + + clk_nandc: clk_nandc_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <14 1>; + clocks = <&clk_cpll>, <&clk_gpll>; + clock-output-names = "clk_nandc"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15 reserved */ + + }; + + clk_sel_con3: sel-con@0050 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0050 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_i2s1_pll_div: clk_i2s1_pll_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 7>; + clocks = <&clk_i2s1_pll>; + clock-output-names = "clk_i2s1_pll"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 7: reserved */ + + clk_i2s1: clk_i2s1_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&clk_i2s1_pll_div>, <&i2s1_frac>, <&i2s_clkin>, <&xin12m>; + clock-output-names = "clk_i2s1"; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 11:10: reserved */ + + clk_i2s1_out: clk_i2s1_out_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <12 1>; + clocks = <&clk_i2s1>, <&xin12m>; + clock-output-names = "i2s_clkout"; + #clock-cells = <0>; + }; + + /* 14:13: reserved */ + + clk_i2s1_pll: i2s1_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <15 1>; + clocks = <&clk_cpll>,<&clk_gpll>; + clock-output-names = "clk_i2s1_pll"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + }; + + clk_sel_con4: sel-con@0054 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0054 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + testclk_div: testclk_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&testclk>; + clock-output-names = "testclk"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 7:5 reserved */ + + clk_24m_div: clk_24m_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&xin24m>; + clock-output-names = "clk_24m"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 15:13 reserved */ + + }; + + clk_sel_con5: sel-con@0058 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0058 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_mac_pll_div: clk_mac_pll_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&clk_mac_pll>; + clock-output-names = "clk_mac_pll"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + clk_mac: clk_mac_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <5 1>; + clocks = <&clk_mac_pll>, <&rmii_clkin>; + clock-output-names = "clk_mac"; + #clock-cells = <0>; + rockchip,flags = ; + #clock-init-cells = <1>; + }; + + /* 6 reserved */ + + clk_mac_pll: clk_mac_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <7 1>; + clocks = <&clk_cpll>, <&clk_gpll>; + clock-output-names = "clk_mac_pll"; + #clock-cells = <0>; + }; + + clk_gmac_div: clk_gmac_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&clk_gmac>; + clock-output-names = "clk_gmac"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + }; + + /* 14:13 reserved */ + + clk_gmac: clk_gmac_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <15 1>; + clocks = <&clk_cpll>, <&clk_gpll>; + clock-output-names = "clk_gmac"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + }; + + clk_sel_con6: sel-con@005c { + compatible = "rockchip,rk3188-selcon"; + reg = <0x005c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + spdif_div: spdif_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 7>; + clocks = <&clk_spdif_pll>; + clock-output-names = "clk_spdif_pll"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 7 reserved */ + + clk_spdif: spdif_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>; + clock-output-names = "clk_spdif"; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 14:10 reserved */ + + clk_spdif_pll: spdif_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <15 1>; + clocks = <&clk_cpll>,<&clk_gpll>; + clock-output-names = "clk_spdif_pll"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + }; + + clk_sel_con7: sel-con@0060 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0060 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + i2s1_frac: i2s1_frac { + compatible = "rockchip,rk3188-frac-con"; + clocks = <&clk_i2s1_pll_div>; + clock-output-names = "i2s1_frac"; + /* numerator denominator */ + rockchip,bits = <0 32>; + rockchip,clkops-idx = + ; + #clock-cells = <0>; + }; + + }; + + clk_sel_con8: sel-con@0064 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0064 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + i2s0_frac: i2s0_frac { + compatible = "rockchip,rk3188-frac-con"; + clocks = <&clk_i2s0_pll_div>; + clock-output-names = "i2s0_frac"; + /* numerator denominator */ + rockchip,bits = <0 32>; + rockchip,clkops-idx = + ; + #clock-cells = <0>; + }; + + }; + + clk_sel_con9: sel-con@0068 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0068 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_i2s0_pll_div: clk_i2s0_pll_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 7>; + clocks = <&clk_i2s0_pll>; + clock-output-names = "clk_i2s0_pll"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 7: reserved */ + + clk_i2s0: clk_i2s0_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&clk_i2s0_pll_div>, <&i2s0_frac>, <&i2s_clkin>, <&xin12m>; + clock-output-names = "clk_i2s0"; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 14:10: reserved */ + + clk_i2s0_pll: i2s0_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <15 1>; + clocks = <&clk_cpll>,<&clk_gpll>; + clock-output-names = "clk_i2s0_pll"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + }; + + clk_sel_con10: sel-con@006c { + compatible = "rockchip,rk3188-selcon"; + reg = <0x006c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + aclk_peri_div: aclk_peri_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&aclk_peri>; + clock-output-names = "aclk_peri"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 7:5: reserved */ + + hclk_peri: hclk_peri_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 2>; + clocks = <&aclk_peri>; + clock-output-names = "hclk_peri"; + rockchip,div-type = ; + rockchip,div-relations = + <0x0 1 + 0x1 2 + 0x2 4>; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + aclk_peri: aclk_peri_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <10 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>; + clock-output-names = "aclk_peri"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + pclk_peri: pclk_peri_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <12 2>; + clocks = <&aclk_peri>; + clock-output-names = "pclk_peri"; + rockchip,div-type = ; + rockchip,div-relations = + <0x0 1 + 0x1 2 + 0x2 4 + 0x3 8>; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15: reserved */ + + }; + + clk_sel_con11: sel-con@0070 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0070 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_sdmmc0_div: clk_sdmmc0_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 8>; + clocks = <&clk_sdmmc0>; + clock-output-names = "clk_sdmmc0"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + }; + + clk_sdmmc0: clk_sdmmc0_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>; + clock-output-names = "clk_sdmmc0"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + clk_sdio: clk_sdio_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <10 2>; + clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>; + clock-output-names = "clk_sdio"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + clk_emmc: clk_emmc_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <12 2>; + clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>; + clock-output-names = "clk_emmc"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15:14 reserved */ + + }; + + clk_sel_con12: sel-con@0074 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_sdio_div: clk_sdio_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 8>; + clocks = <&clk_sdio>; + clock-output-names = "clk_sdio"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + }; + + clk_emmc_div: clk_emmc_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 8>; + clocks = <&clk_emmc>; + clock-output-names = "clk_emmc"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + }; + + }; + + clk_sel_con13: sel-con@0078 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0078 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_uart0_pll_div: clk_uart0_pll_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 7>; + clocks = <&clk_uart0_pll>; + clock-output-names = "clk_uart0_pll"; + rockchip,div-type = ; + #clock-cells = <0>; + }; + + /* 7 reserved */ + + clk_uart0: clk_uart0_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&clk_uart0_pll_div>, <&uart0_frac>, <&xin24m>; + clock-output-names = "clk_uart0"; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 11:10 reserved */ + + clk_uart0_pll: clk_uart0_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <12 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>; + clock-output-names = "clk_uart0_pll"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15:14 reserved */ + + }; + + clk_sel_con14: sel-con@007c { + compatible = "rockchip,rk3188-selcon"; + reg = <0x007c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_uart1_pll_div: clk_uart1_pll_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 7>; + clocks = <&clk_uart1_pll>; + clock-output-names = "clk_uart1_pll"; + rockchip,div-type = ; + #clock-cells = <0>; + }; + + /* 7 reserved */ + + clk_uart1: clk_uart1_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&clk_uart1_pll_div>, <&uart1_frac>, <&xin24m>; + clock-output-names = "clk_uart1"; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 11:10 reserved */ + + clk_uart1_pll: clk_uart1_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <12 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>; + clock-output-names = "clk_uart1_pll"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15:14 reserved */ + }; + + clk_sel_con15: sel-con@0080 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0080 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_uart2_pll_div: clk_uart2_pll_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 7>; + clocks = <&clk_uart2_pll>; + clock-output-names = "clk_uart2_pll"; + rockchip,div-type = ; + #clock-cells = <0>; + }; + + /* 7 reserved */ + + clk_uart2: clk_uart2_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&clk_uart2_pll>, <&uart2_frac>, <&xin24m>; + clock-output-names = "clk_uart2"; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 11:10 reserved */ + + clk_uart2_pll: clk_uart2_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <12 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>; + clock-output-names = "clk_uart2_pll"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15:14 reserved */ + + }; + + clk_sel_con16: sel-con@0084 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0084 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + i2s2_pll_div: i2s2_pll_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 7>; + clocks = <&clk_i2s2_pll>; + clock-output-names = "clk_i2s2_pll"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 7: reserved */ + + clk_i2s2: clk_i2s2_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&i2s2_pll_div>, <&i2s2_frac>, <&i2s_clkin>, <&xin12m>; + clock-output-names = "clk_i2s2"; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + rockchip,flags = ; + }; + + /* 14:10: reserved */ + + clk_i2s2_pll: i2s2_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <15 1>; + clocks = <&clk_cpll>,<&clk_gpll>; + clock-output-names = "clk_i2s2_pll"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + }; + + clk_sel_con17: sel-con@0088 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0088 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + uart0_frac: uart0_frac { + compatible = "rockchip,rk3188-frac-con"; + clocks = <&clk_uart0_pll_div>; + clock-output-names = "uart0_frac"; + /* numerator denominator */ + rockchip,bits = <0 32>; + rockchip,clkops-idx = + ; + #clock-cells = <0>; + }; + + }; + + clk_sel_con18: sel-con@008c { + compatible = "rockchip,rk3188-selcon"; + reg = <0x008c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + uart1_frac: uart1_frac { + compatible = "rockchip,rk3188-frac-con"; + clocks = <&clk_uart1_pll_div>; + clock-output-names = "uart1_frac"; + /* numerator denominator */ + rockchip,bits = <0 32>; + rockchip,clkops-idx = + ; + #clock-cells = <0>; + }; + + }; + + clk_sel_con19: sel-con@0090 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0090 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + uart2_frac: uart2_frac { + compatible = "rockchip,rk3188-frac-con"; + clocks = <&clk_uart2_pll_div>; + clock-output-names = "uart2_frac"; + /* numerator denominator */ + rockchip,bits = <0 32>; + rockchip,clkops-idx = + ; + #clock-cells = <0>; + }; + + }; + + clk_sel_con20: sel-con@0094 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0094 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + spdif_frac: spdif_frac { + compatible = "rockchip,rk3188-frac-con"; + clocks = <&spdif_div>; + clock-output-names = "spdif_frac"; + /* numerator denominator */ + rockchip,bits = <0 32>; + rockchip,clkops-idx = + ; + #clock-cells = <0>; + }; + + }; + + clk_sel_con21: sel-con@0098 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0098 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_hdmi_cec: clk_hdmi_cec_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 14>; + clocks = <&xin24m>; + clock-output-names = "clk_hdmi_cec"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + /* + clk_hdmi_cec_div: clk_hdmi_cec_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 14>; + clocks = <&clk_hdmi_cec>; + clock-output-names = "clk_hdmi_cec"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + clk_hdmi_cec: clk_hdmi_cec_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <14 2>; + clocks = <&dummy>, <&dummy>, <&xin24m>; + clock-output-names = "clk_hdmi_cec"; + #clock-cells = <0>; + }; + */ + }; + + clk_sel_con22: sel-con@009c { + compatible = "rockchip,rk3188-selcon"; + reg = <0x009c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_rga: clk_rga_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&aclk_rga>; + clock-output-names = "clk_rga"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 7:0 reserved */ + + clk_tsp_div: clk_tsp_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&clk_tsp>; + clock-output-names = "clk_tsp"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 14:13 reserved */ + + clk_tsp: clk_tsp_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <15 1>; + clocks = <&clk_cpll>, <&clk_gpll>; + clock-output-names = "clk_tsp"; + #clock-cells = <0>; + }; + + }; + + clk_sel_con23: sel-con@00a0 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00a0 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_wifi_div: clk_wifi_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&clk_wifi>; + clock-output-names = "clk_wifi"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + clk_wifi: clk_wifi_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <5 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>; + clock-output-names = "clk_wifi"; + #clock-cells = <0>; + }; + + /* 7 reserved */ + + clk_hdcp_div: clk_hdcp_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 6>; + clocks = <&clk_hdcp>; + clock-output-names = "clk_hdcp"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + clk_hdcp: clk_hdcp_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <14 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>; + clock-output-names = "clk_hdcp"; + #clock-cells = <0>; + }; + + }; + + clk_sel_con24: sel-con@00a4 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00a4 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_crypto_div: clk_crypto_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&clk_crypto>; + clock-output-names = "clk_crypto"; + rockchip,div-type = ; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + clk_crypto: clk_crypto_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <5 1>; + clocks = <&clk_cpll>, <&clk_gpll>; + clock-output-names = "clk_crypto"; + #clock-cells = <0>; + }; + + clk_tsadc: clk_tsadc_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <6 10>; + clocks = <&xin24m>; + clock-output-names = "clk_tsadc"; + rockchip,div-type = ; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + }; + + clk_sel_con25: sel-con@00a8 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00a8 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_spi0_div: clk_spi0_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 7>; + clocks = <&clk_spi0>; + clock-output-names = "clk_spi0"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 7 reserved */ + + clk_spi0: clk_spi0_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 1>; + clocks = <&clk_cpll>, <&clk_gpll>; + clock-output-names = "clk_spi0"; + #clock-cells = <0>; + }; + + /* 15:9 reserved */ + + }; + + clk_sel_con26: sel-con@00ac { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00ac 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + clk_ddr_div: clk_ddr_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 2>; + clocks = <&clk_ddr>; + clock-output-names = "clk_ddr"; + rockchip,div-type = ; + rockchip,div-relations = + <0x0 1 + 0x1 2 + 0x3 4>; + #clock-cells = <0>; + rockchip,flags = <(CLK_GET_RATE_NOCACHE | + CLK_SET_RATE_NO_REPARENT)>; + rockchip,clkops-idx = ; + }; + + /* 7:2 reserved */ + + clk_ddr: clk_ddr_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 2>; + clocks = <&clk_dpll>, <&clk_gpll>, <&clk_apll>; + clock-output-names = "clk_ddr"; + #clock-cells = <0>; + }; + + /* 15:10 reserved */ + + }; + + clk_sel_con27: sel-con@00b0 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00b0 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + dclk_vop0_pll: dclk_vop0_pll_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <0 1>; + clocks = <&clk_gpll>, <&clk_cpll>; + clock-output-names = "dclk_vop0_pll"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + dclk_vop0: dclk_vop0_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <1 1>; + clocks = <&hdmi_phy_clk>, <&dummy>;/*dclk_vop0_div*/ + clock-output-names = "dclk_vop0"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 7:2 reserved */ + + dclk_vop0_div: dclk_vop0_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 8>; + clocks = <&dclk_vop0_pll>; + clock-output-names = "dclk_vop0"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + }; + + clk_sel_con28: sel-con@00b4 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00b4 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + aclk_rkvdec_div: aclk_rkvdec_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&aclk_rkvdec>; + clock-output-names = "aclk_rkvdec"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 5 reserved */ + + aclk_rkvdec: aclk_rkvdec_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <6 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "aclk_rkvdec"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + clk_vdec_cabac_div: clk_vdec_cabac_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&clk_vdec_cabac>; + clock-output-names = "clk_vdec_cabac"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 13 reserved */ + + clk_vdec_cabac: clk_vdec_cabac_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <14 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "clk_vdec_cabac"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + }; + + clk_sel_con29: sel-con@00b8 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00b8 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + dclk_hdmiphy_div: dclk_hdmiphy_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 3>; + clocks = <&dclk_vop0_pll>; + clock-output-names = "dclk_hdmiphy"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + /* 7:3 reserved */ + + clk_macphy_div: clk_macphy_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 3>; + clocks = <&clk_macphy>; + clock-output-names = "clk_macphy"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + rmii_clkin: rmii_clkin { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <10 1>; + clocks = <&gmac_clkin>, <&phy_50m_out>; + clock-output-names = "rmii_clkin"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + /* + clk_mac_tx: clk_mac_tx { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <11 1>; + clocks = <&clk_gates5 6>, <&phy_tx_out>; + clock-output-names = "clk_mac_tx"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + */ + clk_macphy: clk_macphy_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <12 1>; + clocks = <&clk_mac_pll_div>, <&gmac_clkin>; + clock-output-names = "clk_macphy"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15:13 reserved */ + + }; + + clk_sel_con30: sel-con@00bc { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00bc 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + i2s2_frac: i2s2_frac { + compatible = "rockchip,rk3188-frac-con"; + clocks = <&i2s2_pll_div>; + clock-output-names = "i2s2_frac"; + /* numerator denominator */ + rockchip,bits = <0 32>; + rockchip,clkops-idx = + ; + #clock-cells = <0>; + }; + }; + + clk_sel_con31: sel-con@00c0 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00c0 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + aclk_iep_div: aclk_iep_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&aclk_iep>; + clock-output-names = "aclk_iep"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + aclk_iep: aclk_iep_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <5 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "aclk_iep"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 7: reserved */ + + aclk_hdcp_div: aclk_hdcp_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&aclk_hdcp>; + clock-output-names = "aclk_hdcp"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + aclk_hdcp: aclk_hdcp_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <13 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "aclk_hdcp"; + #clock-cells = <0>; + }; + + /* 15: reserved */ + }; + + clk_sel_con32: sel-con@00c4 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00c4 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + aclk_vpu_div: aclk_vpu_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&aclk_vpu>; + clock-output-names = "aclk_vpu"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + aclk_vpu: aclk_vpu_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <5 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "aclk_vpu"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15:7 reserved */ + + }; + + clk_sel_con33: sel-con@00c8 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00c8 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + aclk_vop_div: aclk_vop_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&aclk_vop>; + clock-output-names = "aclk_vop"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + aclk_vop: aclk_vop_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <5 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "aclk_vop"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 7 reserved */ + + aclk_rga_div: aclk_rga_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&aclk_rga>; + clock-output-names = "aclk_rga"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + aclk_rga: aclk_rga_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <13 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "aclk_rga"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 15 reserved */ + + }; + + clk_sel_con34: sel-con@00cc { + compatible = "rockchip,rk3188-selcon"; + reg = <0x00cc 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + aclk_gpu_div: aclk_gpu_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <0 5>; + clocks = <&aclk_gpu>; + clock-output-names = "aclk_gpu"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + aclk_gpu: aclk_gpu_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <5 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "aclk_gpu"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 7 reserved */ + + clk_vdec_core_div: clk_vdec_core_div { + compatible = "rockchip,rk3188-div-con"; + rockchip,bits = <8 5>; + clocks = <&clk_vdec_core>; + clock-output-names = "clk_vdec_core"; + rockchip,div-type = ; + #clock-cells = <0>; + rockchip,clkops-idx = ; + }; + + clk_vdec_core: clk_vdec_core_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <13 2>; + clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; + clock-output-names = "clk_vdec_core"; + #clock-cells = <0>; + #clock-init-cells = <1>; + + }; + + /* 15 reserved */ + }; + + clk_sel_con35: sel-con@0134 { + compatible = "rockchip,rk3188-selcon"; + reg = <0x0134 0x4>; + #address-cells = <1>; + #size-cells = <1>; + + /* 7:0 reserved */ + + testclk: testclk_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <8 4>; + clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&aclk_gpu>, <&aclk_peri>, <&aclk_core>; + clock-output-names = "testclk"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + /* 12 reserved */ + + hdmi_phy_clk: hdmi_phy_clk_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <13 1>; + clocks = <&hdmiphy_out>, <&xin24m>; + clock-output-names = "hdmi_phy_clk"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + usb480m_phy: usb480m_phy_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <14 1>; + clocks = <&usbphy0_480m>, <&usbphy1_480m>; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + #clock-init-cells = <1>; + }; + + usb480m: usb480m_mux { + compatible = "rockchip,rk3188-mux-con"; + rockchip,bits = <15 1>; + clocks = <&usb480m_phy>, <&xin24m>; + clock-output-names = "usb480m"; + #clock-cells = <0>; + rockchip,clkops-idx = + ; + #clock-init-cells = <1>; + }; + }; + }; + /* Gate control regs */ + clk_gate_cons { + compatible = "rockchip,rk-gate-cons"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clk_gates0: gate-clk@00d0 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00d0 0x4>; + clocks = + <&dummy>, <&dummy>, + <&dummy>, <&clk_i2s0_pll>, + + <&i2s0_frac>, <&clk_i2s0>, + <&dummy>, <&clk_i2s2_pll>, + + <&i2s2_frac>, <&clk_i2s2>, + <&clk_i2s1_pll>, <&i2s1_frac>, + + <&dummy>, <&clk_i2s1_out>, + <&clk_i2s1>, <&testclk>; + + clock-output-names = + "reserved", "reserved", + "reserved", "clk_i2s0_pll", + + "i2s0_frac", "i2s0_8ch", + "reserved", "clk_i2s2_pll", + + "i2s2_frac", "i2s2_2ch", + "clk_i2s1_pll", "i2s1_frac", + + "reserved", "i2s_clkout", + "i2s1_8ch", "testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk@00d4 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00d4 0x4>; + clocks = + <&clk_nandc>, <&aclk_vop>, + <&aclk_rga>, <&jtag_clkin>, + + <&aclk_hdcp>, <&xin24m>, + <&xin24m>, <&clk_mac_pll>, + + <&clk_uart0_pll>, <&uart0_frac>, + <&clk_uart1_pll>, <&uart1_frac>, + + <&clk_uart2_pll>, <&uart2_frac>, + <&dummy>, <&dummy>; + + clock-output-names = + "clk_nandc", "aclk_vop", + "aclk_rga", "clk_jtag", + + "aclk_hdcp", "clk_otgphy0", + "clk_otgphy1", "clk_mac_pll", + + "clk_uart0_pll", "uart0_frac", + "clk_uart1_pll", "uart1_frac", + + "clk_uart2_pll", "uart2_frac", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates2: gate-clk@00d8 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00d8 0x4>; + clocks = + <&dummy>, <&dummy>, + <&clk_gmac>, <&dummy>, + + <&dummy>, <&dummy>, + <&clk_tsp>, <&clk_crypto>, + + <&clk_tsadc>, <&clk_spi0>, + <&clk_spdif_pll>, <&clk_sdmmc0>, + + <&spdif_frac>, <&clk_sdio>, + <&clk_emmc>, <&clk_wifi>; + + clock-output-names = + "reserved", "clk_ddrmon", + "clk_gmac", "reserved", + + "reserved", "reserved", + "clk_tsp", "clk_crypto", + + "clk_tsadc", "clk_spi0", + "clk_spdif_pll", "clk_sdmmc0", + + "spdif_frac", "clk_sdio", + "clk_emmc", "clk_wifi"; + + #clock-cells = <1>; + }; + + clk_gates3: gate-clk@00dc { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00dc 0x4>; + clocks = + <&aclk_iep>, <&dummy>, + <&aclk_rkvdec>, <&clk_vdec_cabac>, + + <&clk_vdec_core>, <&clk_hdcp>, + <&aclk_rga>, <&xin24m>, + + <&clk_hdmi_cec>, <&dummy>, + <&dummy>, <&aclk_vpu>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "aclk_iep", "dclk_vop0", + "aclk_rkvdec", "clk_vdec_cabac", + + "clk_vdec_core", "clk_hdcp", + "clk_rga", "clk_hdmi_hdcp", + + "clk_hdmi_cec", "reserved", + "reserved", "aclk_vpu", + + "reserved", "reserved", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates4: gate-clk@00e0 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00e0 0x4>; + clocks = + <&clk_core>, <&clk_core>, + <&aclk_core>, <&dummy>, + + <&aclk_vpu>, <&aclk_rkvdec>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "aclk_core", "pclk_dbg", + "aclk_gic400", "reserved", + + "hclk_vpu", "hclk_rkvdec", + "reserved", "reserved", + + "reserved", "reserved", + "reserved", "reserved", + + "reserved", "reserved", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates5: gate-clk@00e4 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00e4 0x4>; + clocks = + <&aclk_peri>, <&aclk_peri>, + <&aclk_peri>, <&clk_mac>, + + <&clk_mac>, <&clk_mac>, + <&clk_mac>, <&clk_macphy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "aclk_peri", "hclk_peri", + "pclk_peri", "clk_mac_ref", + + "clk_mac_refout", "clk_mac_rx", + "clk_mac_tx", "clk_macphy", + + "reserved", "reserved", + "reserved", "reserved", + + "reserved", "reserved", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates6: gate-clk@00e8 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00e8 0x4>; + clocks = + <&aclk_bus>, <&aclk_bus>, + <&aclk_bus>, <&pclk_bus>, + + <&pclk_bus>, <&xin24m>, + <&xin24m>, <&xin24m>, + + <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + + <&dummy>, <&pclk_bus>, + <&dummy>, <&dummy>; + + clock-output-names = + "aclk_bus", "hclk_bus", + "pclk_bus", "pclk_bus_pre", + + "pclk_phy", "clk_timer0", + "clk_timer1", "clk_timer2", + + "clk_timer3", "clk_timer4", + "clk_timer5", "reserved", + + "reserved", "pclk_ddr", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates7: gate-clk@00ec { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00ec 0x4>; + clocks = + <&clk_ddr_div>, <&clk_ddr_div>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&aclk_gpu>, <&aclk_gpu>; + + clock-output-names = + "clk_ddrphy", "clk4x_ddrphy", + "reserved", "reserved", + + "reserved", "reserved", + "reserved", "reserved", + + "reserved", "reserved", + "reserved", "reserved", + + "reserved", "reserved", + "g_aclk_gpu", "g_aclk_gpu_noc"; + + #clock-cells = <1>; + }; + + clk_gates8: gate-clk@00f0 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00f0 0x4>; + clocks = + <&aclk_bus>, <&aclk_bus>, + <&aclk_bus>, <&hclk_bus>, + + <&clk_gates6 13>, <&clk_gates7 0>, + <&clk_gates6 13>, <&hclk_bus>, + + <&hclk_bus>, <&hclk_bus>, + <&hclk_bus>, <&hclk_bus>, + + <&hclk_bus>, <&pclk_bus>, + <&pclk_bus>, <&pclk_bus>; + + clock-output-names = + "g_aclk_intmem", "g_intmem_mbist", + "g_aclk_dmac_bus", "g_hclk_rom", + + "g_p_ddrupctl", "g_clk_ddrupctl", + "g_p_ddrmon", "g_h_i2s0_8ch", + + "g_h_i2s1_8ch", "g_h_i2s2_2ch", + "g_h_spdif_8ch", "g_h_crypto_mst", + + "g_h_crypto_slv", "g_p_efuse_1024", + "g_p_efuse_256", "g_pclk_i2c0"; + + #clock-cells = <1>; + }; + + clk_gates9: gate-clk@00f4 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00f4 0x4>; + clocks = + <&pclk_bus>, <&pclk_bus>, + <&pclk_bus>, <&dummy>, + + <&pclk_bus>, <&pclk_bus>, + <&pclk_bus>, <&pclk_bus>, + + <&pclk_bus>, <&pclk_bus>, + <&pclk_bus>, <&pclk_bus>, + + <&pclk_bus>, <&pclk_bus>, + <&pclk_bus>, <&pclk_bus>; + + clock-output-names = + "g_pclk_i2c1", "g_pclk_i2c2", + "g_pclk_i2c3", "reserved", + + "g_pclk_timer0", "g_pclk_stimer", + "g_pclk_spi0", "g_pclk_rk_pwm", + + "g_pclk_gpio0", "g_pclk_gpio1", + "g_pclk_gpio2", "g_pclk_gpio3", + + "g_pclk_uart0", "g_pclk_uart1", + "g_pclk_uart2", "g_pclk_tsadc"; + + #clock-cells = <1>; + }; + + clk_gates10: gate-clk@00f8 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00f8 0x4>; + clocks = + <&pclk_bus>, <&aclk_bus>, + <&clk_gates6 13>, <&clk_gates6 4>, + + <&pclk_bus>, <&clk_gates6 4>, + <&pclk_bus>, <&clk_gates6 4>, + + <&clk_gates6 4>, <&clk_gates6 4>, + <&pclk_bus>, <&hclk_bus>, + + <&clkin_hsadc_tsp>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "g_pclk_grf", "g_aclk_bus", + "g_p_mschniu", "g_p_ddrphy", + + "g_pclk_cru", "g_p_acodecphy", + "g_pclk_sgrf", "g_p_hdmiphy", + + "g_p_vdacphy", "g_p_phy_noc", + "g_pclk_sim", "g_hclk_tsp", + + "clk_hsadc_tsp", "reserved", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates11: gate-clk@00fc { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x00fc 0x4>; + clocks = + <&hclk_peri>, <&hclk_peri>, + <&hclk_peri>, <&hclk_peri>, + + <&aclk_peri>, <&pclk_peri>, + <&hclk_peri>, <&hclk_peri>, + + <&hclk_peri>, <&hclk_peri>, + <&hclk_peri>, <&dummy>, + + <&hclk_peri>, <&hclk_peri>, + <&hclk_peri>, <&dummy>; + + clock-output-names = + "g_hclk_sdmmc", "g_hclk_sdio", + "g_clk_emmc", "g_clk_nandc", + + "g_aclk_gmac", "g_pclk_gmac", + "g_hclk_host0", "g_h_host0_arb", + + "g_hclk_host1", "g_h_host1_arb", + "g_hclk_host2", "reserved", + + "g_hclk_otg", "g_hclk_otg_pmu", + "g_h_host2_arb", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates12: gate-clk@0100 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x0100 0x4>; + clocks = + <&aclk_peri>, <&hclk_peri>, + <&pclk_peri>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "g_a_peri_noc", "g_h_peri_noc", + "g_p_peri_noc", "reserved", + + "reserved", "reserved", + "reserved", "reserved", + + "reserved", "reserved", + "reserved", "reserved", + + "reserved", "reserved", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates13: gate-clk@0104 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x0104 0x4>; + clocks = + <&aclk_rga>, <&hclk_vio>, + <&aclk_iep>, <&hclk_vio>, + + <&dummy>, <&aclk_vop>, + <&hclk_vio>, <&hclk_vio>, + + <&hclk_vio>, <&aclk_iep>, + <&aclk_hdcp>, <&aclk_rga>, + + <&aclk_vop>, <&hclk_vio>, + <&dummy>, <&dummy>; + + clock-output-names = + "g_aclk_rga", "g_hclk_rga", + "g_aclk_iep", "g_hclk_iep", + + "reserved", "g_aclk_vop", + "g_hclk_vop", "g_h_vio_ahbarbi", + + "g_h_vio_noc", "g_a_iep_noc", + "g_a_hdcp_noc", "g_a_rga_noc", + + "g_a_vop_noc", "g_h_vop_noc", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates14: gate-clk@0108 { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x0108 0x4>; + clocks = + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&hclk_vio>, <&hclk_vio>, + + <&dummy>, <&dummy>, + <&aclk_hdcp>, <&hclk_vio>, + + <&hclk_vio>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "reserved", "reserved", + "reserved", "reserved", + + "reserved", "reserved", + "g_p_hdmi_ctrl", "g_h_vio_h2p", + + "reserved", "reserved", + "g_aclk_hdcp", "g_pclk_hdcp", + + "g_h_hdcp_mmu", "reserved", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + + clk_gates15: gate-clk@010c { + compatible = "rockchip,rk3188-gate-clk"; + reg = <0x010c 0x4>; + clocks = + <&aclk_vpu>, <&hclk_vpu>, + <&aclk_rkvdec>, <&hclk_rkvdec>, + + <&aclk_vpu>, <&hclk_vpu>, + <&aclk_rkvdec>, <&hclk_rkvdec>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "g_aclk_vpu", "g_hclk_vpu", + "g_a_rkvdec", "g_h_rkvdec", + + "g_a_vpu_noc", "g_h_vpu_noc", + "g_a_rkvdec_noc", "g_h_rkvdec_noc", + + "reserved", "reserved", + "reserved", "reserved", + + "reserved", "reserved", + "reserved", "reserved"; + + #clock-cells = <1>; + }; + }; + }; +}; +}; diff --git a/arch/arm/boot/dts/rk3228-fpga.dts b/arch/arm/boot/dts/rk3228-fpga.dts new file mode 100644 index 000000000000..e99ed198a4b3 --- /dev/null +++ b/arch/arm/boot/dts/rk3228-fpga.dts @@ -0,0 +1,153 @@ +/dts-v1/; + +#include + +#include "skeleton.dtsi" +#include "rk3228-clocks.dtsi" + +/ { + compatible = "rockchip,rk3228"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x32011000 0x1000>, + <0x32012000 0x1000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + clock-frequency = <24000000>; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x10000000>; + }; + + chosen { + bootargs = "initrd=0x62000000,0x00180000 init=/init console=ttyFIQ0,115200 earlyprintk=uart8250-32bit,0x11030000"; + }; + + aliases { + serial2 = &uart_dbg; + }; + + uart_dbg: serial@11030000 { + compatible = "rockchip,serial"; + reg = <0x11030000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&xin24m>, <&xin24m>; + clock-names = "sclk_uart", "pclk_uart"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <159>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + //status = "disabled"; + }; + + rockchip_clocks_init: clocks-init{ + compatible = "rockchip,clocks-init"; + rockchip,clocks-init-parent = + <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>, + <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>, + <&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>, + <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>, + <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>, + <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>, + <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>; + rockchip,clocks-init-rate = + <&clk_gpll 600000000>, <&clk_core 700000000>, + <&clk_cpll 500000000>, <&aclk_bus 250000000>, + <&hclk_bus 125000000>, <&pclk_bus 62500000>, + <&aclk_peri 250000000>, <&hclk_peri 125000000>, + <&pclk_peri 62500000>, <&clk_mac 125000000>, + <&aclk_iep 250000000>, <&hclk_vio 125000000>, + <&aclk_rga 250000000>, <&aclk_gpu 250000000>, + <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>, + <&clk_vdec_cabac 250000000>; +/* + rockchip,clocks-uboot-has-init = + <&aclk_vio0>; +*/ + }; + + rockchip_clocks_enable: clocks-enable { + compatible = "rockchip,clocks-enable"; + clocks = + /*PLL*/ + <&clk_apll>, + <&clk_dpll>, + <&clk_gpll>, + <&clk_cpll>, + + /*PD_CORE*/ + <&clk_core>, + <&pclk_dbg>, + <&aclk_core>, + <&clk_gates4 2>, + + /*PD_BUS*/ + <&aclk_bus>, + <&hclk_bus>, + <&pclk_bus>, + <&clk_gates8 0>,/*aclk_intmem*/ + <&clk_gates8 1>,/*clk_intmem_mbist*/ + <&clk_gates8 3>,/*aclk_dmac_bus*/ + <&clk_gates10 1>,/*g_aclk_bus*/ + <&clk_gates13 9>,/*aclk_gic400*/ + <&clk_gates8 3>,/*hclk_rom*/ + <&clk_gates8 4>,/*pclk_ddrupctl*/ + <&clk_gates8 6>,/*pclk_ddrmon*/ + <&clk_gates9 4>,/*pclk_timer0*/ + <&clk_gates9 5>,/*pclk_stimer*/ + <&clk_gates10 0>,/*pclk_grf*/ + <&clk_gates10 4>,/*pclk_cru*/ + <&clk_gates10 6>,/*pclk_sgrf*/ + <&clk_gates10 3>,/*pclk_ddrphy*/ + <&clk_gates10 9>,/*pclk_phy_noc*/ + + /*PD_PERI*/ + <&aclk_peri>, + <&hclk_peri>, + <&pclk_peri>, + <&clk_gates12 0>,/*aclk_peri_noc*/ + <&clk_gates12 1>,/*hclk_peri_noc*/ + <&clk_gates12 2>,/*pclk_peri_noc*/ + + <&clk_gates6 5>, /* g_clk_timer0 */ + <&clk_gates6 6>, /* g_clk_timer1 */ + + <&clk_gates7 14>, /* g_aclk_gpu */ + <&clk_gates7 15>, /* g_aclk_gpu_noc */ + + <&clk_gates1 3>;/*clk_jtag*/ + }; +}; diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index d3e49d113acb..c175b1da10c2 100755 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -5,6 +5,7 @@ obj-y += rk312x.o obj-y += rk3126b.o obj-y += rk3188.o obj-y += rk3288.o +obj-y += rk3228.o ifneq ($(CONFIG_ARM_TRUSTZONE),y) obj-y += ddr_freq.o endif diff --git a/arch/arm/mach-rockchip/rk3228.c b/arch/arm/mach-rockchip/rk3228.c new file mode 100644 index 000000000000..91410376d461 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3228.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2015 ROCKCHIP, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "loader.h" +#define CPU 3228 +#include "sram.h" +#include + +#define RK3228_DEVICE(name) \ + { \ + .virtual = (unsigned long) RK_##name##_VIRT, \ + .pfn = __phys_to_pfn(RK3228_##name##_PHYS), \ + .length = RK3228_##name##_SIZE, \ + .type = MT_DEVICE, \ + } + +static const char * const rk3228_dt_compat[] __initconst = { + "rockchip,rk3228", + NULL, +}; + +static struct map_desc rk3228_io_desc[] __initdata = { + RK3228_DEVICE(CRU), + RK3228_DEVICE(GRF), + RK3228_DEVICE(TIMER), + RK3228_DEVICE(CPU_AXI_BUS), + RK_DEVICE(RK_DEBUG_UART_VIRT, RK3228_UART2_PHYS, RK3228_UART_SIZE), + RK_DEVICE(RK_DDR_VIRT, RK3228_DDR_PCTL_PHYS, RK3228_DDR_PCTL_SIZE), + RK_DEVICE(RK_DDR_VIRT + RK3228_DDR_PCTL_SIZE, RK3228_DDR_PHY_PHYS, + RK3228_DDR_PHY_SIZE), + RK_DEVICE(RK_GPIO_VIRT(0), RK3228_GPIO0_PHYS, RK3228_GPIO_SIZE), + RK_DEVICE(RK_GPIO_VIRT(1), RK3228_GPIO1_PHYS, RK3228_GPIO_SIZE), + RK_DEVICE(RK_GPIO_VIRT(2), RK3228_GPIO2_PHYS, RK3228_GPIO_SIZE), + RK_DEVICE(RK_GPIO_VIRT(3), RK3228_GPIO3_PHYS, RK3228_GPIO_SIZE), + RK_DEVICE(RK_GIC_VIRT, RK3228_GIC_DIST_PHYS, RK3228_GIC_DIST_SIZE), + RK_DEVICE(RK_GIC_VIRT + RK3228_GIC_DIST_SIZE, RK3228_GIC_CPU_PHYS, + RK3228_GIC_CPU_SIZE), + RK_DEVICE(RK_PWM_VIRT, RK3228_PWM_PHYS, RK3228_PWM_SIZE), +}; + +void __init rk3228_dt_map_io(void) +{ + rockchip_soc_id = ROCKCHIP_SOC_RK3228; + + iotable_init(rk3228_io_desc, ARRAY_SIZE(rk3228_io_desc)); + debug_ll_io_init(); +} + +static void __init rk3228_dt_init_timer(void) +{ + of_clk_init(NULL); + clocksource_of_init(); + of_dvfs_init(); +} + +static void __init rk3228_reserve(void) +{ + /* reserve memory for uboot */ + rockchip_uboot_mem_reserve(); + + /* reserve memory for ION */ + rockchip_ion_reserve(); +} + +static void __init rk3228_init_late(void) +{ + if (rockchip_jtag_enabled) + clk_prepare_enable(clk_get_sys(NULL, "clk_jtag")); +} + +static void rk3228_restart(char mode, const char *cmd) +{ +} + +DT_MACHINE_START(RK3228_DT, "Rockchip RK3228") + .smp = smp_ops(rockchip_smp_ops), + .map_io = rk3228_dt_map_io, + .init_time = rk3228_dt_init_timer, + .dt_compat = rk3228_dt_compat, + .init_late = rk3228_init_late, + .reserve = rk3228_reserve, + .restart = rk3228_restart, +MACHINE_END + diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index ebbd25c6a2b7..5943ca12f8c2 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -232,9 +232,10 @@ static const struct pll_clk_set rk3036plus_pll_com_table[] = { static const struct pll_clk_set rk312xplus_pll_com_table[] = { /*_RK3036_PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),*/ /*_RK3036_PLL_SET_CLKS(798000, 2, 133, 2, 1, 1, 0),*/ + _RK3036_PLL_SET_CLKS(1000000, 3, 125, 1, 1, 1, 0), _RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0), - _RK3036_PLL_SET_CLKS(500000, 6, 250, 2, 1, 1, 0), - _RK3036_PLL_SET_CLKS(400000, 6, 400, 2, 2, 1, 0), + _RK3036_PLL_SET_CLKS(500000, 3, 125, 2, 1, 1, 0), + _RK3036_PLL_SET_CLKS(400000, 3, 200, 2, 2, 1, 0), }; static const struct apll_clk_set rk3368_apllb_table[] = { @@ -1960,7 +1961,7 @@ static int clk_pll_set_rate_3036_apll(struct clk_hw *hw, unsigned long rate, /************select apll******************/ cru_writel(RK3036_CORE_SEL_PLL(0), RK3036_CRU_CLKSELS_CON(0)); /**************return slow mode***********/ - /*cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);*/ + cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset); cru_writel(RK3036_CLK_CORE_DIV(1), RK3036_CRU_CLKSELS_CON(0)); @@ -2054,7 +2055,7 @@ static int clk_cpll_set_rate_312xplus(struct clk_hw *hw, unsigned long rate, } if (clk_set->rate == rate) { - clk_debug("cpll get a rate\n"); + clk_debug("cpll get a rate %ld\n", rate); rk3036_pll_clk_set_rate(clk_set, hw); } else { diff --git a/include/dt-bindings/clock/rockchip,rk3228.h b/include/dt-bindings/clock/rockchip,rk3228.h new file mode 100644 index 000000000000..b86e44536722 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3228.h @@ -0,0 +1,167 @@ +#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H + +#include "rockchip.h" + +/* pll id */ +#define RK3228_APLL_ID 0 +#define RK3228_DPLL_ID 1 +#define RK3228_CPLL_ID 2 +#define RK3228_GPLL_ID 3 +#define RK3228_END_PLL_ID 4 + +/* reset id */ +#define RK3228_RST_CORE0_PO 0 +#define RK3228_RST_CORE1_PO 1 +#define RK3228_RST_CORE2_PO 2 +#define RK3228_RST_CORE3_PO 3 +#define RK3228_RST_CORE0 4 +#define RK3228_RST_CORE1 5 +#define RK3228_RST_CORE2 6 +#define RK3228_RST_CORE3 7 +#define RK3228_RST_CORE0_DBG 8 +#define RK3228_RST_CORE1_DBG 9 +#define RK3228_RST_CORE2_DBG 10 +#define RK3228_RST_CORE3_DBG 11 +#define RK3228_RST_TOPDBG 12 +#define RK3228_RST_ACLK_CORE 13 +#define RK3228_RST_NOC_A 14 +#define RK3228_RST_L2C 15 + +#define RK3228_RST_1RES0 16 +#define RK3228_RST_1RES1 17 +#define RK3228_RST_CPUSYS_H 18 +#define RK3228_RST_BUSSYS_H 19 +#define RK3228_RST_SPDIF 20 +#define RK3228_RST_INTMEM 21 +#define RK3228_RST_ROM 22 +#define RK3228_RST_OTG_ADP 23 +#define RK3228_RST_I2S0 24 +#define RK3228_RST_I2S1 25 +#define RK3228_RST_I2S2 26 +#define RK3228_RST_ACODEC_P 27 +#define RK3228_RST_DFIMON 28 +#define RK3228_RST_MSCH 29 +#define RK3228_RST_EFUSE_1024 30 +#define RK3228_RST_EFUSE_256 31 + +#define RK3228_RST_GPIO0 32 +#define RK3228_RST_GPIO1 33 +#define RK3228_RST_GPIO2 34 +#define RK3228_RST_GPIO3 35 +#define RK3228_RST_PERIPH_NOC_A 36 +#define RK3228_RST_PERIPH_NOC_H 37 +#define RK3228_RST_PERIPH_NOC_P 38 +#define RK3228_RST_UART0 39 +#define RK3228_RST_UART1 40 +#define RK3228_RST_UART2 41 +#define RK3228_RST_PHYNOC 42 +#define RK3228_RST_I2C0 43 +#define RK3228_RST_I2C1 44 +#define RK3228_RST_I2C2 45 +#define RK3228_RST_I2C3 46 +#define RK3228_RST_2RES15 47 + +#define RK3228_RST_PWM0 48 +#define RK3228_RST_A53_GIC 49 +#define RK3228_RST_3RES2 50 +#define RK3228_RST_DAP 51 +#define RK3228_RST_DAP_NOC 52 +#define RK3228_RST_CRYPTO 53 +#define RK3228_RST_SGRF 54 +#define RK3228_RST_GRF 55 +#define RK3228_RST_GMAC 56 +#define RK3228_RST_3RES9 57 +#define RK3228_RST_PERIPHSYS_A 58 +#define RK3228_RST_3RES11 59 +#define RK3228_RST_3RES12 60 +#define RK3228_RST_3RES13 61 +#define RK3228_RST_3RES14 62 +#define RK3228_RST_MACPHY 63 + +#define RK3228_RST_4RES0 64 +#define RK3228_RST_4RES1 65 +#define RK3228_RST_4RES2 66 +#define RK3228_RST_4RES3 67 +#define RK3228_RST_NANDC 68 +#define RK3228_RST_USBOTG0 69 +#define RK3228_RST_OTGC0 70 +#define RK3228_RST_USBHOST0 71 +#define RK3228_RST_HOST_CTRL0 72 +#define RK3228_RST_USBHOST1 73 +#define RK3228_RST_HOST_CTRL1 74 +#define RK3228_RST_USBHOST2 75 +#define RK3228_RST_HOST_CTRL2 76 +#define RK3228_RST_USBPOR0 77 +#define RK3228_RST_USBPOR1 78 +#define RK3228_RST_DDRMSCH 79 + +#define RK3228_RST_SMART_CARD 80 +#define RK3228_RST_SDMMC0 81 +#define RK3228_RST_SDIO 82 +#define RK3228_RST_EMMC 83 +#define RK3228_RST_SPI0 84 +#define RK3228_RST_TSP_H 85 +#define RK3228_RST_TSP 86 +#define RK3228_RST_TSADC 87 +#define RK3228_RST_DDRPHY 88 +#define RK3228_RST_DDRPHY_P 89 +#define RK3228_RST_DDRCTRL 90 +#define RK3228_RST_DDRCTRL_P 91 +#define RK3228_RST_HOST0_ECHI 92 +#define RK3228_RST_HOST1_ECHI 93 +#define RK3228_RST_HOST2_ECHI 94 +#define RK3228_RST_VOP 95 + +#define RK3228_RST_HDMI_P 96 +#define RK3228_RST_VIO_ARBI_H 97 +#define RK3228_RST_IEP_NOC_A 98 +#define RK3228_RST_VIO_NOC_H 99 +#define RK3228_RST_VOP_A 100 +#define RK3228_RST_VOP_H 101 +#define RK3228_RST_VOP_D 102 +#define RK3228_RST_UTMI0 103 +#define RK3228_RST_UTMI1 104 +#define RK3228_RST_UTMI2 105 +#define RK3228_RST_UTMI3 106 +#define RK3228_RST_RGA 107 +#define RK3228_RST_RGA_NOC_A 108 +#define RK3228_RST_RGA_A 109 +#define RK3228_RST_RGA_H 110 +#define RK3228_RST_HDCP_A 111 + +#define RK3228_RST_VPU_A 112 +#define RK3228_RST_VPU_H 113 +#define RK3228_RST_7RES2 114 +#define RK3228_RST_7RES3 115 +#define RK3228_RST_VPU_NOC_A 116 +#define RK3228_RST_VPU_NOC_H 117 +#define RK3228_RST_RKVDEC_A 118 +#define RK3228_RST_RKVDEC_NOC_A 119 +#define RK3228_RST_RKVDEC_H 120 +#define RK3228_RST_RKVDEC_NOC_H 121 +#define RK3228_RST_RKVDEC_CORE 122 +#define RK3228_RST_RKVDEC_CABAC 123 +#define RK3228_RST_IEP_A 124 +#define RK3228_RST_IEP_H 125 +#define RK3228_RST_GPU_A 126 +#define RK3228_RST_GPU_NOC_A 127 + +#define RK3228_RST_CORE_DBG 128 +#define RK3228_RST_DBG_P 129 +#define RK3228_RST_TIMER0 130 +#define RK3228_RST_TIMER1 131 +#define RK3228_RST_TIMER2 132 +#define RK3228_RST_TIMER3 133 +#define RK3228_RST_TIMER4 134 +#define RK3228_RST_TIMER5 135 +#define RK3228_RST_VIO_H2P 136 +#define RK3228_RST_8RES9 137 +#define RK3228_RST_8RES10 138 +#define RK3228_RST_HDMIPHY 139 +#define RK3228_RST_VDAC 140 +#define RK3228_RST_TIMER_6CH 141 +#define RK3228_RST_8RES14 142 +#define RK3228_RST_8RES15 143 + +#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H */ diff --git a/include/linux/rockchip/cpu.h b/include/linux/rockchip/cpu.h index 17f0d589b2eb..edc145550f55 100644 --- a/include/linux/rockchip/cpu.h +++ b/include/linux/rockchip/cpu.h @@ -34,6 +34,7 @@ static inline void rockchip_set_cpu_version(unsigned long ver) #define ROCKCHIP_CPU_RK3188 0x31880000 #define ROCKCHIP_CPU_RK319X 0x31900000 #define ROCKCHIP_CPU_RK3288 0x32880000 +#define ROCKCHIP_CPU_RK3228 0x32280000 #ifdef CONFIG_ARM #define ROCKCHIP_CPU(id, ID) \ @@ -55,6 +56,7 @@ ROCKCHIP_CPU(312x, 312X) ROCKCHIP_CPU(3188, 3188) ROCKCHIP_CPU(319x, 319X) ROCKCHIP_CPU(3288, 3288) +ROCKCHIP_CPU(3228, 3228) #define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff) #define ROCKCHIP_SOC_RK2926 (ROCKCHIP_CPU_RK2928 | 0x00) @@ -76,6 +78,7 @@ ROCKCHIP_CPU(3288, 3288) #define ROCKCHIP_SOC_RK3188PLUS (ROCKCHIP_CPU_RK3188 | 0x10) #define ROCKCHIP_SOC_RK3190 (ROCKCHIP_CPU_RK319X | 0x00) #define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00) +#define ROCKCHIP_SOC_RK3228 (ROCKCHIP_CPU_RK3228 | 0x00) #ifdef CONFIG_ARM #define ROCKCHIP_SOC(id, ID) \ @@ -107,5 +110,6 @@ ROCKCHIP_SOC(3188, 3188) ROCKCHIP_SOC(3188plus, 3188PLUS) ROCKCHIP_SOC(3190, 3190) ROCKCHIP_SOC(3288, 3288) +ROCKCHIP_SOC(3228, 3228) #endif diff --git a/include/linux/rockchip/iomap.h b/include/linux/rockchip/iomap.h index f8785fa69803..e6ffe50e78c3 100755 --- a/include/linux/rockchip/iomap.h +++ b/include/linux/rockchip/iomap.h @@ -187,4 +187,42 @@ #define RK312X_PWM_PHYS 0x20050000 #define RK312X_PWM_SIZE SZ_16K +#define RK3228_IMEM_PHYS RK3036_IMEM_PHYS +#define RK3228_IMEM_SIZE SZ_32K +#define RK3228_ROM_PHYS RK3036_ROM_PHYS +#define RK3228_ROM_SIZE RK3036_ROM_SIZE +#define RK3228_CPU_AXI_BUS_PHYS 0x31000000 +#define RK3228_CPU_AXI_BUS_SIZE SZ_32K +#define RK3228_GIC_DIST_PHYS 0x32011000 +#define RK3228_GIC_DIST_SIZE SZ_4K +#define RK3228_GIC_CPU_PHYS 0x32012000 +#define RK3228_GIC_CPU_SIZE SZ_4K +#define RK3228_CRU_PHYS 0x110e0000 +#define RK3228_CRU_SIZE SZ_4K +#define RK3228_DDR_PCTL_PHYS 0x11200000 +#define RK3228_DDR_PCTL_SIZE SZ_4K +#define RK3228_GRF_PHYS 0x11000000 +#define RK3228_GRF_SIZE SZ_4K +#define RK3228_SGRF_PHYS 0x10140000 +#define RK3228_SGRF_SIZE SZ_4K +#define RK3228_DDR_PHY_PHYS 0x12000000 +#define RK3228_DDR_PHY_SIZE SZ_4K +#define RK3228_TIMER_PHYS 0x110c0000 +#define RK3228_TIMER_SIZE SZ_4K +#define RK3228_STIMER_PHYS 0x110d0000 +#define RK3228_STIMER_SIZE SZ_4K +#define RK3228_UART0_PHYS 0x11010000 +#define RK3228_UART1_PHYS 0x11020000 +#define RK3228_UART2_PHYS 0x11030000 +#define RK3228_UART_SIZE SZ_4K +#define RK3228_GPIO0_PHYS 0x11110000 +#define RK3228_GPIO1_PHYS 0x11120000 +#define RK3228_GPIO2_PHYS 0x11130000 +#define RK3228_GPIO3_PHYS 0x11140000 +#define RK3228_GPIO_SIZE SZ_4K +#define RK3228_EFUSE_PHYS 0x11040000 +#define RK3228_EFUSE_SIZE SZ_4K +#define RK3228_PWM_PHYS 0x110b0000 +#define RK3228_PWM_SIZE SZ_16K + #endif