From: Shawn Lin Date: Mon, 14 Nov 2016 04:11:06 +0000 (+0800) Subject: UPSTREAM: PCI: rockchip: Add quirk to disable RC's ASPM L0s X-Git-Tag: firefly_0821_release~1229 X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=commitdiff_plain;h=6c71bcdab9b48258ab496218581d035afb65e0dd;hp=517105143888b4d8b861141f96a4bbc6e366aa0e UPSTREAM: PCI: rockchip: Add quirk to disable RC's ASPM L0s Rockchip's RC outputs 100MHz reference clock but there are two methods for PHY to generate it. (1)One of them is to use system PLL to generate 100MHz clock and the PHY will relock it and filter signal noise then outputs the reference clock. (2)Another way is to share Soc's 24MHZ crystal oscillator with PHY and force PHY's DLL to generate 100MHz internally. When using case(2), the exit from L0s doesn't work fine occasionally due to the broken design of RC receiver's logical circuit. So even if we use extended-synch, it still fails for PHY to relock the bits from FTS sometimes. This will hang the system. Maybe we could argue that why not use case(1) to avoid it? The reason is that as we could see the reference clock is derived from system PLL and the path from it to PHY isn't so clean which means there are some noise introduced by power-domain and other buses can't be filterd out by PHY and we could see noise from the frequency spectrum by oscilloscope. This makes the TX compatibility test a little difficult to pass the spec. So case(1) and case(2) are both used indeed now. If using case(2), we should disable RC's L0s support, and that is why we need this property to indicate this quirk. Also after checking quirk.c, I noticed there is already a quirk for disabling L0s unconditionally, quirk_disable_aspm_l0s. But obviously we shouldn't do that as mentioned above that case(1) could still works fine with L0s. Change-Id: Ia9506d55f34a24001c19d398a8ecb088558c0f7e Reported-by: Jeffy Chen Cc: Brian Norris Signed-off-by: Shawn Lin Signed-off-by: Bjorn Helgaas Signed-off-by: Shawn Lin (am from git.kernel.org/cgit/linux/kernel/git/next/linux-next.git commit c2af19ee1b5e0f0ef942d27b18f7e22e2ab43cba) --- diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt index 71aeda1ca055..5d23902863ed 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt @@ -45,6 +45,8 @@ Required properties: Optional Property: - ep-gpios: contain the entry for pre-reset gpio - num-lanes: number of lanes to use +- quirk,aspm-no-l0s: RC won't support ASPM L0s. This property is needed if + using 24MHz OSC for RC's PHY. - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe. diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 1fcd42a1589d..86f08f3ecabc 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -140,6 +140,8 @@ #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) +#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) @@ -648,6 +650,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP); + /* Clear L0s from RC's link cap */ + if (of_property_read_bool(dev->of_node, "quirk,apsm-no-l0s")) { + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); + status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); + } + rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF); rockchip_pcie_write(rockchip,