From: Finley Xiao Date: Sat, 25 Mar 2017 12:33:58 +0000 (+0800) Subject: clk: rockchip: rk3368: add ddrc clock support X-Git-Tag: firefly_0821_release~109 X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=commitdiff_plain;h=43509cca481019946ba7c76f08491f1036616399;hp=968ccb6e8330739448c9fb40a6ed08013b17cbc7 clk: rockchip: rk3368: add ddrc clock support Add a ddrc clock into clk branches, so we can do ddr frequency scaling on rk3368 platform in future. Change-Id: Ie7fd2e8d8bdf8b9ff843ca13e848f772adaa109a Signed-off-by: Finley Xiao --- diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index e4554a3ca525..a5e5050e4ccf 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -338,6 +338,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { RK3368_CLKGATE_CON(1), 8, GFLAGS), GATE(0, "gpll_ddr", "gpll", 0, RK3368_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, + RK3368_CLKSEL_CON(13), 4, 1, 0, 0, ROCKCHIP_DDRCLK_SCPI), + COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),