From: Linus Torvalds Date: Tue, 7 May 2013 18:22:14 +0000 (-0700) Subject: Merge tag 'cleanup-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git... X-Git-Tag: firefly_0821_release~3680^2~544 X-Git-Url: http://plrg.eecs.uci.edu/git/?p=firefly-linux-kernel-4.4.55.git;a=commitdiff_plain;h=1bf25e78af317e6d5d9b5594dfeb0036e0d589d6 Merge tag 'cleanup-for-linus-2' of git://git./linux/kernel/git/arm/arm-soc Pull ARM SoC late cleanups from Arnd Bergmann: "These are cleanups and smaller changes that either depend on earlier feature branches or came in late during the development cycle. We normally try to get all cleanups early, so these are the exceptions: - A follow-up on the clocksource reworks, hopefully the last time we need to merge clocksource subsystem changes through arm-soc. A first set of patches was part of the original 3.10 arm-soc cleanup series because of interdependencies with timer drivers now moved out of arch/arm. - Migrating the SPEAr13xx platform away from using auxdata for DMA channel descriptions towards using information in device tree, based on the earlier SPEAr multiplatform series - A few follow-ups on the Atmel SAMA5 support and other changes for Atmel at91 based on the larger at91 reworks. - Moving the armada irqchip implementation to drivers/irqchip - Several OMAP cleanups following up on the larger series already merged in 3.10." * tag 'cleanup-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) ARM: OMAP4: change the device names in usb_bind_phy ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a ARM: SPEAr: conditionalize SMP code ARM: arch_timer: Silence debug preempt warnings ARM: OMAP: remove unused variable serial: amba-pl011: fix !CONFIG_DMA_ENGINE case ata: arasan: remove the need for platform_data ARM: at91/sama5d34ek.dts: remove not needed compatibility string ARM: at91: dts: add MCI DMA support ARM: at91: dts: add i2c dma support ARM: at91: dts: set #dma-cells to the correct value ARM: at91: suspend both memory controllers on at91sam9263 irqchip: armada-370-xp: slightly cleanup irq controller driver irqchip: armada-370-xp: move IRQ handler to avoid forward declaration irqchip: move IRQ driver for Armada 370/XP ARM: mvebu: move L2 cache initialization in init_early() devtree: add binding documentation for sp804 ARM: integrator-cp: convert use CLKSRC_OF for timer init ARM: versatile: use OF init for sp804 timer ARM: versatile: add versatile dtbs to dtbs target ... --- 1bf25e78af317e6d5d9b5594dfeb0036e0d589d6 diff --cc arch/arm/Kconfig index 18bef301d6e6,38b5d5dad8e4..34ef016626ff --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@@ -1059,6 -1172,8 +1059,7 @@@ config PLAT_VERSATIL config ARM_TIMER_SP804 bool select CLKSRC_MMIO + select CLKSRC_OF if OF - select HAVE_SCHED_CLOCK source arch/arm/mm/Kconfig diff --cc arch/arm/boot/dts/at91sam9x5.dtsi index 640b3bbbb706,cbb94732786c..1145ac330fb7 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@@ -535,10 -475,11 +541,13 @@@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; interrupts = <9 4 6>; + dmas = <&dma0 1 7>, + <&dma0 1 8>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; status = "disabled"; }; @@@ -546,10 -487,11 +555,13 @@@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x100>; interrupts = <10 4 6>; + dmas = <&dma1 1 5>, + <&dma1 1 6>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; status = "disabled"; }; @@@ -557,10 -499,11 +569,13 @@@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8018000 0x100>; interrupts = <11 4 6>; + dmas = <&dma0 1 9>, + <&dma0 1 10>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; status = "disabled"; }; diff --cc arch/arm/mach-mvebu/Makefile index ba769e082ad4,c3be068f1c96..2d04f0e21870 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@@ -5,6 -5,6 +5,6 @@@ AFLAGS_coherency_ll.o := -Wa,-march=ar obj-y += system-controller.o obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o - obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o -obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o ++obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --cc arch/arm/mach-mvebu/armada-370-xp.c index 12d3655830d1,433e8c5343b2..42a4cb3087e2 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@@ -19,7 -19,8 +19,9 @@@ #include #include #include +#include + #include + #include #include #include #include @@@ -58,20 -57,9 +60,24 @@@ void __init armada_370_xp_init_early(vo */ init_dma_coherent_pool_size(SZ_1M); + /* + * This initialization will be replaced by a DT-based + * initialization once the mvebu-mbus driver gains DT support. + */ + if (of_machine_is_compatible("marvell,armada370")) + mbus_soc_name = "marvell,armada370-mbus"; + else + mbus_soc_name = "marvell,armadaxp-mbus"; + + mvebu_mbus_init(mbus_soc_name, + ARMADA_370_XP_MBUS_WINS_BASE, + ARMADA_370_XP_MBUS_WINS_SIZE, + ARMADA_370_XP_SDRAM_WINS_BASE, + ARMADA_370_XP_SDRAM_WINS_SIZE); ++ + #ifdef CONFIG_CACHE_L2X0 + l2x0_of_init(0, ~0UL); + #endif } static void __init armada_370_xp_dt_init(void) diff --cc arch/arm/mach-shmobile/setup-r8a7740.c index 228d7aba4a7c,104b474a2ccf..326a4ab0bd5f --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@@ -1029,8 -904,8 +1029,7 @@@ DT_MACHINE_START(R8A7740_DT, "Generic R .map_io = r8a7740_map_io, .init_early = r8a7740_add_early_devices_dt, .init_irq = r8a7740_init_irq, - .handle_irq = shmobile_handle_irq_intc, .init_machine = r8a7740_add_standard_devices_dt, - .init_time = shmobile_timer_init, .dt_compat = r8a7740_boards_compat_dt, MACHINE_END diff --cc arch/arm/mach-vexpress/v2m.c index 9366f37902d9,09e571ddc984..b6083bb1eb8c --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@@ -22,10 -23,7 +23,9 @@@ #include #include #include +#include +#include - #include #include #include #include @@@ -430,29 -428,11 +427,11 @@@ void __init v2m_dt_init_early(void static void __init v2m_dt_timer_init(void) { - struct device_node *node = NULL; - - vexpress_clk_of_init(); + of_clk_init(NULL); clocksource_of_init(); - do { - node = of_find_compatible_node(node, NULL, "arm,sp804"); - } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); - if (node) { - pr_info("Using SP804 '%s' as a clock & events source\n", - node->full_name); - WARN_ON(clk_register_clkdev(of_clk_get_by_name(node, - "timclken1"), "v2m-timer0", "sp804")); - WARN_ON(clk_register_clkdev(of_clk_get_by_name(node, - "timclken2"), "v2m-timer1", "sp804")); - v2m_sp804_init(of_iomap(node, 0), - irq_of_parse_and_map(node, 0)); - } - - arch_timer_of_register(); - if (arch_timer_sched_clock_init() != 0) - versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), + versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000); } diff --cc drivers/irqchip/Makefile index c28fcccf4a0d,154722aa26cb..cda4cb5f7327 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@@ -2,7 -2,7 +2,8 @@@ obj-$(CONFIG_IRQCHIP) += irqchip. obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o + obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o +obj-$(CONFIG_ARCH_MXS) += irq-mxs.o obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o diff --cc drivers/irqchip/irq-armada-370-xp.c index 000000000000,ad1e6422a732..bb328a366122 mode 000000,100644..100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@@ -1,0 -1,294 +1,288 @@@ + /* + * Marvell Armada 370 and Armada XP SoC IRQ handling + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * Ben Dooks + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + #include "irqchip.h" + + /* Interrupt Controller Registers Map */ + #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) + #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) + + #define ARMADA_370_XP_INT_CONTROL (0x00) + #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) + #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) + #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) + + #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) + + #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) + #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) + #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8) + + #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) + + #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) + + #define IPI_DOORBELL_START (0) + #define IPI_DOORBELL_END (8) + #define IPI_DOORBELL_MASK 0xFF + + static DEFINE_RAW_SPINLOCK(irq_controller_lock); + + static void __iomem *per_cpu_int_base; + static void __iomem *main_int_base; + static struct irq_domain *armada_370_xp_mpic_domain; + + /* + * In SMP mode: + * For shared global interrupts, mask/unmask global enable bit - * For CPU interrtups, mask/unmask the calling CPU's bit ++ * For CPU interrupts, mask/unmask the calling CPU's bit + */ + static void armada_370_xp_irq_mask(struct irq_data *d) + { -#ifdef CONFIG_SMP + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) + writel(hwirq, main_int_base + + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); + else + writel(hwirq, per_cpu_int_base + + ARMADA_370_XP_INT_SET_MASK_OFFS); -#else - writel(irqd_to_hwirq(d), - per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); -#endif + } + + static void armada_370_xp_irq_unmask(struct irq_data *d) + { -#ifdef CONFIG_SMP + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) + writel(hwirq, main_int_base + + ARMADA_370_XP_INT_SET_ENABLE_OFFS); + else + writel(hwirq, per_cpu_int_base + + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); -#else - writel(irqd_to_hwirq(d), - per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); -#endif + } + + #ifdef CONFIG_SMP + static int armada_xp_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) + { + unsigned long reg; + unsigned long new_mask = 0; + unsigned long online_mask = 0; + unsigned long count = 0; + irq_hw_number_t hwirq = irqd_to_hwirq(d); + int cpu; + + for_each_cpu(cpu, mask_val) { + new_mask |= 1 << cpu_logical_map(cpu); + count++; + } + + /* + * Forbid mutlicore interrupt affinity + * This is required since the MPIC HW doesn't limit + * several CPUs from acknowledging the same interrupt. + */ + if (count > 1) + return -EINVAL; + + for_each_cpu(cpu, cpu_online_mask) + online_mask |= 1 << cpu_logical_map(cpu); + + raw_spin_lock(&irq_controller_lock); + + reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); + reg = (reg & (~online_mask)) | new_mask; + writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); + + raw_spin_unlock(&irq_controller_lock); + + return 0; + } + #endif + + static struct irq_chip armada_370_xp_irq_chip = { + .name = "armada_370_xp_irq", + .irq_mask = armada_370_xp_irq_mask, + .irq_mask_ack = armada_370_xp_irq_mask, + .irq_unmask = armada_370_xp_irq_unmask, + #ifdef CONFIG_SMP + .irq_set_affinity = armada_xp_set_affinity, + #endif + }; + + static int armada_370_xp_mpic_irq_map(struct irq_domain *h, + unsigned int virq, irq_hw_number_t hw) + { + armada_370_xp_irq_mask(irq_get_irq_data(virq)); - writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); ++ if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) ++ writel(hw, per_cpu_int_base + ++ ARMADA_370_XP_INT_CLEAR_MASK_OFFS); ++ else ++ writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); + irq_set_status_flags(virq, IRQ_LEVEL); + + if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) { + irq_set_percpu_devid(virq); + irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, + handle_percpu_devid_irq); + + } else { + irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, + handle_level_irq); + } + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); + + return 0; + } + + #ifdef CONFIG_SMP + void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq) + { + int cpu; + unsigned long map = 0; + + /* Convert our logical CPU mask into a physical one. */ + for_each_cpu(cpu, mask) + map |= 1 << cpu_logical_map(cpu); + + /* + * Ensure that stores to Normal memory are visible to the + * other CPUs before issuing the IPI. + */ + dsb(); + + /* submit softirq */ + writel((map << 8) | irq, main_int_base + + ARMADA_370_XP_SW_TRIG_INT_OFFS); + } + + void armada_xp_mpic_smp_cpu_init(void) + { + /* Clear pending IPIs */ + writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); + + /* Enable first 8 IPIs */ + writel(IPI_DOORBELL_MASK, per_cpu_int_base + + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); + + /* Unmask IPI interrupt */ + writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); + } + #endif /* CONFIG_SMP */ + + static struct irq_domain_ops armada_370_xp_mpic_irq_ops = { + .map = armada_370_xp_mpic_irq_map, + .xlate = irq_domain_xlate_onecell, + }; + + static asmlinkage void __exception_irq_entry + armada_370_xp_handle_irq(struct pt_regs *regs) + { + u32 irqstat, irqnr; + + do { + irqstat = readl_relaxed(per_cpu_int_base + + ARMADA_370_XP_CPU_INTACK_OFFS); + irqnr = irqstat & 0x3FF; + + if (irqnr > 1022) + break; + + if (irqnr > 0) { + irqnr = irq_find_mapping(armada_370_xp_mpic_domain, + irqnr); + handle_IRQ(irqnr, regs); + continue; + } + #ifdef CONFIG_SMP + /* IPI Handling */ + if (irqnr == 0) { + u32 ipimask, ipinr; + + ipimask = readl_relaxed(per_cpu_int_base + + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) + & IPI_DOORBELL_MASK; + + writel(~IPI_DOORBELL_MASK, per_cpu_int_base + + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); + + /* Handle all pending doorbells */ + for (ipinr = IPI_DOORBELL_START; + ipinr < IPI_DOORBELL_END; ipinr++) { + if (ipimask & (0x1 << ipinr)) + handle_IPI(ipinr, regs); + } + continue; + } + #endif + + } while (1); + } + + static int __init armada_370_xp_mpic_of_init(struct device_node *node, + struct device_node *parent) + { + u32 control; + + main_int_base = of_iomap(node, 0); + per_cpu_int_base = of_iomap(node, 1); + + BUG_ON(!main_int_base); + BUG_ON(!per_cpu_int_base); + + control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); + + armada_370_xp_mpic_domain = + irq_domain_add_linear(node, (control >> 2) & 0x3ff, + &armada_370_xp_mpic_irq_ops, NULL); + + if (!armada_370_xp_mpic_domain) + panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n"); + + irq_set_default_host(armada_370_xp_mpic_domain); + + #ifdef CONFIG_SMP + armada_xp_mpic_smp_cpu_init(); + + /* + * Set the default affinity from all CPUs to the boot cpu. + * This is required since the MPIC doesn't limit several CPUs + * from acknowledging the same interrupt. + */ + cpumask_clear(irq_default_affinity); + cpumask_set_cpu(smp_processor_id(), irq_default_affinity); + + #endif + + set_handle_irq(armada_370_xp_handle_irq); + + return 0; + } + + IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init); diff --cc drivers/tty/serial/amba-pl011.c index b2e9e177a354,1c1942b5cee9..8ab70a620919 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@@ -1094,9 -988,10 +1106,9 @@@ static inline bool pl011_dma_rx_running return uap->using_rx_dma && uap->dmarx.running; } - #else /* Blank functions if the DMA engine is not available */ - static inline void pl011_dma_probe(struct uart_amba_port *uap) + static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) { }