arm64: dts: rockchip: add mmc dt-bindings for rk3328 and evb board
authorShawn Lin <shawn.lin@rock-chips.com>
Thu, 15 Dec 2016 01:06:23 +0000 (09:06 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Mon, 19 Dec 2016 10:41:21 +0000 (18:41 +0800)
Add dt-bindings for sdio/sdmmc(+ext)/emmc controllers

Change-Id: I1c52b803110c499c58c2c27a1c7488a98b0ca870
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
arch/arm64/boot/dts/rockchip/rk3328.dtsi

index 5fba8a5..3ee1cd4 100644 (file)
                status = "okay";
        };
 };
                status = "okay";
        };
 };
+
+&emmc {
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       supports-emmc;
+       disable-wp;
+       non-removable;
+       num-slots = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+       status = "okay";
+};
index c198895..6258e28 100644 (file)
                        <32768>, <32768>;
        };
 
                        <32768>, <32768>;
        };
 
+       sdmmc: rksdmmc@ff500000 {
+               compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xff500000 0x0 0x4000>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+               clock-names = "biu", "ciu";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       sdio: dwmmc@ff510000 {
+               compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xff510000 0x0 0x4000>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+                        <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       emmc: rksdmmc@ff520000 {
+               compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xff520000 0x0 0x4000>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
+               clock-names = "biu", "ciu";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       sdmmc_ext: rksdmmc@ff5f0000 {
+               compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xff5f0000 0x0 0x4000>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+               clock-names = "biu", "ciu";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
        gic: interrupt-controller@ff811000 {
                compatible = "arm,gic-400";
                #interrupt-cells = <3>;
        gic: interrupt-controller@ff811000 {
                compatible = "arm,gic-400";
                #interrupt-cells = <3>;