clk: rockchip: rk3366: include downstream muxes into fractional dividers

Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported RK3366 SoCs.

Change-Id: Idabfe85f269b8f15f85471daa50c3ef988b21297
Signed-off-by: Xiao Feng <xf@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3366.c b/drivers/clk/rockchip/clk-rk3366.c
index 30328d7a03a193df935a4d71f81e6b441cd57c5d..cead6899e6cb4c72af184f9d8889d3071a5ee515 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3366.c
+++ b/drivers/clk/rockchip/clk-rk3366.c
@@ -192,6 +192,26 @@ static struct rockchip_cpuclk_rate_table rk3366_cpuclk_rates[] __initdata = {
        RK3366_CPUCLK_RATE( 312000000, 1, 1, 1),
 };
 
+static struct rockchip_clk_branch rk3366_i2s_8ch_fracmux __initdata =
+       MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
+                       RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3366_spdif_8ch_fracmux __initdata =
+       MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
+                       RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3366_i2s_2ch_fracmux __initdata =
+       MUX(0, "i2s_2ch_mux", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
+                       RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3366_uart0_fracmux __initdata =
+       MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
+                       RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3366_uart3_fracmux __initdata =
+       MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
+                       RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
+
 static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
        /*
         * Clock-Architecture Diagram 2
@@ -265,11 +285,10 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
        COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3368_CLKGATE_CON(6), 1, GFLAGS),
-       COMPOSITE_FRAC(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(28), 0,
-                       RK3368_CLKGATE_CON(6), 2, GFLAGS),
-       MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
-                       RK3368_CLKSEL_CON(27), 8, 2, MFLAGS),
+                       RK3368_CLKGATE_CON(6), 2, GFLAGS,
+                       &rk3366_i2s_8ch_fracmux),
        COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
                        RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
                        RK3368_CLKGATE_CON(6), 0, GFLAGS),
@@ -279,21 +298,21 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
        COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3368_CLKGATE_CON(6), 4, GFLAGS),
-       COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(32), 0,
-                       RK3368_CLKGATE_CON(6), 5, GFLAGS),
-       COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
-                       RK3368_CLKSEL_CON(31), 8, 2, MFLAGS,
+                       RK3368_CLKGATE_CON(6), 5, GFLAGS,
+                       &rk3366_spdif_8ch_fracmux),
+       GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
                        RK3368_CLKGATE_CON(6), 6, GFLAGS),
 
        COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3368_CLKGATE_CON(5), 13, GFLAGS),
-       COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(54), 0,
-                       RK3368_CLKGATE_CON(5), 14, GFLAGS),
-       COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
-                       RK3368_CLKSEL_CON(53), 8, 2, MFLAGS,
+                       RK3368_CLKGATE_CON(5), 14, GFLAGS,
+                       &rk3366_i2s_2ch_fracmux),
+       GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_mux", CLK_SET_RATE_PARENT,
                        RK3368_CLKGATE_CON(5), 15, GFLAGS),
 
        /*
@@ -503,20 +522,18 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
        COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
                        RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
                        RK3368_CLKGATE_CON(2), 0, GFLAGS),
-       COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(34), 0,
-                       RK3368_CLKGATE_CON(2), 1, GFLAGS),
-       MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
-                       RK3368_CLKSEL_CON(33), 8, 2, MFLAGS),
+                       RK3368_CLKGATE_CON(2), 1, GFLAGS,
+                       &rk3366_uart0_fracmux),
 
        COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
                        RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
                        RK3368_CLKGATE_CON(2), 6, GFLAGS),
-       COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(40), 0,
-                       RK3368_CLKGATE_CON(2), 7, GFLAGS),
-       MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
-                       RK3368_CLKSEL_CON(39), 8, 2, MFLAGS),
+                       RK3368_CLKGATE_CON(2), 7, GFLAGS,
+                       &rk3366_uart3_fracmux),
 
        /*
         * Clock-Architecture Diagram 6