dt-bindings: add documentation of rk3366 clock controller

Add the devicetree binding for the cru on the rk3366 which quite
similar structured as previous clock controllers.

Change-Id: I109da26f88cd733b64d4c4339db63346dd9ffea6
Signed-off-by: Xiao Feng <xf@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3366-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3366-cru.txt
new file mode 100644 (file)
index 0000000..d9d7766
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3366-cru.txt
@@ -0,0 +1,58 @@
+* Rockchip RK3366 Clock and Reset Unit
+
+The RK3366 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3366-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3366-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+ - "ext_jtag" - external JTAG clock - optional
+ - "usbotg_out" - output clock of the pll in the otg phy
+
+Example: Clock controller node:
+
+       cru: clock-controller@ff760000 {
+               compatible = "rockchip,rk3366-cru";
+               reg = <0x0 0xff760000 0x0 0x1000>;
+               rockchip,grf = <&grf>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+       uart0: serial@10124000 {
+               compatible = "snps,dw-apb-uart";
+               reg = <0x10124000 0x400>;
+               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <1>;
+               clocks = <&cru SCLK_UART0>;
+       };