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8c7f8df)
RGA2_SYS_CTRL bit[6] a safe reset, it would be ensure all
axi write/read operation into completion
Change-Id: I39a5a6a9f10883d355c428e9dbaa89778682c49b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
- rga2_write((1 << 3) | (1 << 4), RGA2_SYS_CTRL); //RGA_SYS_CTRL
+ rga2_write((1 << 3) | (1 << 4) | (1 << 6), RGA2_SYS_CTRL);
for(i = 0; i < RGA2_RESET_TIMEOUT; i++)
{
for(i = 0; i < RGA2_RESET_TIMEOUT; i++)
{