pinctrl-0 = <&lcdc1_lcdc>;
pinctrl-1 = <&lcdc1_gpio>;
status = "disabled";
+ };
+ rga@10114000 {
+ compatible = "rockchip,rga";
+ reg = <0x10114000 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates6 10>, <&clk_gates6 11>;
+ clock-names = "hclk_rga", "aclk_rga";
+ status = "disabled";
};
adc: adc@2006c000 {
CONFIG_SECURITY_SELINUX=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_TWOFISH=y
+CONFIG_ROCKCHIP_RGA=y
+# CONFIG_ROCKCHIP_RGA2=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
source "drivers/video/rockchip/hdmi/Kconfig"
source "drivers/video/rockchip/tve/Kconfig"
source "drivers/video/rockchip/rga/Kconfig"
+source "drivers/video/rockchip/rga2/Kconfig"
obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o rkfb_sysfs.o lcdc/
obj-$(CONFIG_RK_TRSM) += transmitter/
-obj-$(CONFIG_RGA_RK30) += rga/
+obj-$(CONFIG_ROCKCHIP_RGA) += rga/
+obj-$(CONFIG_ROCKCHIP_RGA2) += rga2/
obj-$(CONFIG_RK_HDMI) += display-sys.o hdmi/
menu "RGA"
- depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK3188 || ARCH_RK3026
+ depends on ARCH_ROCKCHIP
-config RGA_RK30
- tristate "ROCKCHIP RK30 || RK2928 RGA"
+config ROCKCHIP_RGA
+ tristate "ROCKCHIP_RGA"
help
rk30 rga module.
rga-y := rga_drv.o rga_mmu_info.o rga_reg_info.o RGA_API.o
-obj-$(CONFIG_RGA_RK30) += rga.o
+obj-$(CONFIG_ROCKCHIP_RGA) += rga.o
#include <asm/io.h>\r
#include <linux/irq.h>\r
#include <linux/interrupt.h>\r
-#include <mach/io.h>\r
-#include <mach/irqs.h>\r
+//#include <mach/io.h>\r
+//#include <mach/irqs.h>\r
#include <linux/fs.h>\r
#include <asm/uaccess.h>\r
#include <linux/miscdevice.h>\r
void (*rga_irq_callback)(int rga_retval); //callback function used by aync call\r
struct wake_lock wake_lock;\r
\r
+ struct clk *pd_rga;\r
struct clk *aclk_rga;\r
- struct clk *hclk_rga;\r
- struct clk *pd_rga;\r
+ struct clk *hclk_rga;\r
};\r
\r
static struct rga_drvdata *drvdata;\r
.fops = &rga_fops,\r
};\r
\r
-static int __devinit rga_drv_probe(struct platform_device *pdev)\r
+\r
+\r
+static const struct of_device_id rockchip_rga_of_match[] = {\r
+ { .compatible = "rockchip,rga", .data = NULL, },\r
+ {},\r
+};\r
+\r
+static int rga_drv_probe(struct platform_device *pdev)\r
{\r
struct rga_drvdata *data;\r
+ struct resource *res;\r
+ struct device_node *np = pdev->dev.of_node;\r
int ret = 0;\r
\r
INIT_LIST_HEAD(&rga_service.waiting);\r
rga_service.last_prc_src_format = 1; /* default is yuv first*/\r
rga_service.enable = false;\r
\r
- data = kzalloc(sizeof(struct rga_drvdata), GFP_KERNEL);\r
- if(NULL == data)\r
- {\r
+ data = devm_kzalloc(&pdev->dev, sizeof(struct rga_drvdata), GFP_KERNEL);\r
+ if(! data) {\r
ERR("failed to allocate driver data.\n");\r
return -ENOMEM;\r
}\r
INIT_DELAYED_WORK(&data->power_off_work, rga_power_off_work);\r
wake_lock_init(&data->wake_lock, WAKE_LOCK_SUSPEND, "rga");\r
\r
- data->pd_rga = clk_get(NULL, "pd_rga");\r
- data->aclk_rga = clk_get(NULL, "aclk_rga");\r
- data->hclk_rga = clk_get(NULL, "hclk_rga");\r
+ //data->pd_rga = devm_clk_get(&pdev->dev, "pd_rga");\r
+ data->aclk_rga = devm_clk_get(&pdev->dev, "aclk_rga");\r
+ data->hclk_rga = devm_clk_get(&pdev->dev, "hclk_rga");\r
\r
- /* map the memory */\r
- if (!request_mem_region(RK30_RGA_PHYS, RK30_RGA_SIZE, "rga_io"))\r
- {\r
- pr_info("failed to reserve rga HW regs\n");\r
- return -EBUSY;\r
- }\r
+ clk_prepare_enable(data->aclk_rga);\r
+ clk_prepare_enable(data->hclk_rga);\r
\r
- data->rga_base = (void*)ioremap_nocache(RK30_RGA_PHYS, RK30_RGA_SIZE);\r
- if (data->rga_base == NULL)\r
- {\r
+ /* map the registers */\r
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
+ data->rga_base = devm_ioremap_resource(&pdev->dev, res);\r
+ if (!data->rga_base) {\r
ERR("rga ioremap failed\n");\r
ret = -ENOENT;\r
goto err_ioremap;\r
}\r
\r
/* get the IRQ */\r
- data->irq = platform_get_irq(pdev, 0);\r
- if (data->irq <= 0)\r
- {\r
+ data->irq = ret = platform_get_irq(pdev, 0);\r
+ if (ret <= 0) {\r
ERR("failed to get rga irq resource (%d).\n", data->irq);\r
ret = data->irq;\r
goto err_irq;\r
}\r
\r
/* request the IRQ */\r
- ret = request_threaded_irq(data->irq, rga_irq, rga_irq_thread, 0, "rga", pdev);\r
+ //ret = request_threaded_irq(data->irq, rga_irq, rga_irq_thread, 0, "rga", pdev);\r
+ ret = devm_request_threaded_irq(&pdev->dev, data->irq, rga_irq, rga_irq_thread, 0, "rga", data);\r
if (ret)\r
{\r
ERR("rga request_irq failed (%d).\n", ret);\r
free_irq(data->irq, &data->miscdev);\r
iounmap((void __iomem *)(data->rga_base));\r
\r
- clk_put(data->pd_rga);\r
+ clk_disable_unprepare(data->aclk_rga);\r
+ clk_disable_unprepare(data->hclk_rga);\r
+\r
+ //clk_put(data->pd_rga);\r
clk_put(data->aclk_rga);\r
clk_put(data->hclk_rga);\r
\r
- kfree(data);\r
+ //kfree(data);\r
return 0;\r
}\r
\r
static struct platform_driver rga_driver = {\r
.probe = rga_drv_probe,\r
- .remove = __devexit_p(rga_drv_remove),\r
+ .remove = rga_drv_remove,\r
.driver = {\r
.owner = THIS_MODULE,\r
.name = "rga",\r
#include <asm/io.h>\r
#include <linux/irq.h>\r
#include <linux/interrupt.h>\r
-#include <mach/io.h>\r
-#include <mach/irqs.h>\r
+//#include <mach/io.h>\r
+//#include <mach/irqs.h>\r
#include <linux/fs.h>\r
#include <asm/uaccess.h>\r
#include <linux/miscdevice.h>\r
#include "rga.h"\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_pixel_width_init \r
-Description: \r
- select pixel_width form data format \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ RGA_pixel_width_init\r
+Description:\r
+ select pixel_width form data format\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
unsigned char\r
RGA_pixel_width_init(unsigned int format)\r
case RK_FORMAT_RGBA_4444 : pixel_width = 2; break;\r
case RK_FORMAT_BGR_888 : pixel_width = 3; break;\r
\r
- /* YUV FORMAT */ \r
+ /* YUV FORMAT */\r
case RK_FORMAT_YCbCr_422_SP : pixel_width = 1; break;\r
case RK_FORMAT_YCbCr_422_P : pixel_width = 1; break;\r
case RK_FORMAT_YCbCr_420_SP : pixel_width = 1; break;\r
return pixel_width;\r
}\r
\r
-/************************************************************* \r
-Func: \r
- dst_ctrl_cal \r
-Description: \r
- calculate dst act window position / width / height \r
- and set the tile struct \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ dst_ctrl_cal\r
+Description:\r
+ calculate dst act window position / width / height\r
+ and set the tile struct\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
void\r
dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile)\r
{\r
pos[0] = xoff;\r
pos[1] = yoff;\r
- \r
+\r
pos[2] = xoff;\r
pos[3] = yoff + height - 1;\r
- \r
+\r
pos[4] = xoff + width - 1;\r
pos[5] = yoff + height - 1;\r
\r
\r
xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);\r
xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);\r
- \r
+\r
ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);\r
ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);\r
- \r
+\r
//printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax);\r
}\r
else if(msg->rotate_mode == 1)\r
{\r
if((sina == 0) || (cosa == 0))\r
- { \r
+ {\r
if((sina == 0) && (cosa == -65536))\r
{\r
/* 180 */\r
pos[5] = yoff;\r
\r
pos[6] = xoff + height - 1;\r
- pos[7] = yoff - width + 1; \r
+ pos[7] = yoff - width + 1;\r
}\r
else\r
{\r
\r
xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);\r
xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);\r
- \r
+\r
ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);\r
ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);\r
- } \r
+ }\r
else\r
{\r
xx = msg->cosa;\r
\r
x2 = width + xoff;\r
y2 = height + yoff;\r
- \r
+\r
pos[0] = xoff;\r
pos[1] = yoff;\r
\r
\r
//printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);\r
}\r
- } \r
- \r
- if ((xmax < xmin) || (ymax < ymin)) { \r
+ }\r
+\r
+ if ((xmax < xmin) || (ymax < ymin)) {\r
xmin = xmax;\r
ymin = ymax;\r
- } \r
- \r
- if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) { \r
+ }\r
+\r
+ if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) {\r
xmin = xmax = ymin = ymax = 0;\r
}\r
\r
//printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);\r
- \r
+\r
tile->dst_ctrl.w = (xmax - xmin);\r
tile->dst_ctrl.h = (ymax - ymin);\r
tile->dst_ctrl.x_off = xmin;\r
tile->dst_y_tmp = ymin - msg->dst.y_offset;\r
}\r
\r
-/************************************************************* \r
-Func: \r
- src_tile_info_cal \r
-Description: \r
- calculate src remap window position / width / height \r
- and set the tile struct \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ src_tile_info_cal\r
+Description:\r
+ calculate src remap window position / width / height\r
+ and set the tile struct\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
void\r
src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile)\r
{\r
- s32 x0, x1, x2, x3, y0, y1, y2, y3; \r
- \r
+ s32 x0, x1, x2, x3, y0, y1, y2, y3;\r
+\r
int64_t xx, xy, yx, yy;\r
\r
int64_t pos[8];\r
yy = tile->matrix[3]; /* 32.32 */\r
\r
if(msg->rotate_mode == 1)\r
- { \r
+ {\r
x0 = tile->dst_x_tmp;\r
y0 = tile->dst_y_tmp;\r
- \r
+\r
x1 = x0;\r
y1 = y0 + 8;\r
\r
\r
x3 = x0 + 8;\r
y3 = y0;\r
- \r
- pos[0] = (x0*xx + y0*yx); \r
+\r
+ pos[0] = (x0*xx + y0*yx);\r
pos[1] = (x0*xy + y0*yy);\r
\r
pos[2] = (x1*xx + y1*yx);\r
y_dx = pos[2] - pos[0];\r
y_dy = pos[3] - pos[1];\r
\r
- tile->x_dx = (s32)(x_dx >> 22 ); \r
- tile->x_dy = (s32)(x_dy >> 22 ); \r
- tile->y_dx = (s32)(y_dx >> 22 ); \r
- tile->y_dy = (s32)(y_dy >> 22 ); \r
- \r
+ tile->x_dx = (s32)(x_dx >> 22 );\r
+ tile->x_dy = (s32)(x_dy >> 22 );\r
+ tile->y_dx = (s32)(y_dx >> 22 );\r
+ tile->y_dy = (s32)(y_dy >> 22 );\r
+\r
x_temp_start = x0*xx + y0*yx;\r
y_temp_start = x0*xy + y0*yy;\r
- \r
- xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6])); \r
- xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6])); \r
+\r
+ xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6]));\r
+ xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6]));\r
\r
ymax = (MAX(MAX(MAX(epos[1], epos[3]), epos[5]), epos[7]));\r
ymin = (MIN(MIN(MIN(epos[1], epos[3]), epos[5]), epos[7]));\r
\r
t_xoff = (x_temp_start - xmin)>>18;\r
t_yoff = (y_temp_start - ymin)>>18;\r
- \r
+\r
tile->tile_xoff = (s32)t_xoff;\r
tile->tile_yoff = (s32)t_yoff;\r
- \r
+\r
tile->tile_w = (u16)((xmax - xmin)>>21); //.11\r
tile->tile_h = (u16)((ymax - ymin)>>21); //.11\r
\r
tile->tile_start_x_coor = (s16)(xmin>>29); //.3\r
- tile->tile_start_y_coor = (s16)(ymin>>29); //.3 \r
+ tile->tile_start_y_coor = (s16)(ymin>>29); //.3\r
}\r
else if (msg->rotate_mode == 2)\r
{\r
tile->x_dy = 0;\r
tile->y_dx = 0;\r
tile->y_dy = (s32)((8*yy)>>22);\r
- \r
+\r
tile->tile_w = ABS((s32)((7*xx)>>21));\r
tile->tile_h = ABS((s32)((7*yy)>>21));\r
\r
tile->tile_yoff = 0;\r
\r
tile->tile_start_x_coor = (((msg->src.act_w - 1)<<11) - (tile->tile_w))>>8;\r
- tile->tile_start_y_coor = 0; \r
+ tile->tile_start_y_coor = 0;\r
}\r
else if (msg->rotate_mode == 3)\r
{\r
tile->x_dy = 0;\r
tile->y_dx = 0;\r
tile->y_dy = (s32)((8*yy)>>22);\r
- \r
+\r
tile->tile_w = ABS((s32)((7*xx)>>21));\r
tile->tile_h = ABS((s32)((7*yy)>>21));\r
\r
\r
tile->tile_start_x_coor = 0;\r
tile->tile_start_y_coor = (((msg->src.act_h - 1)<<11) - (tile->tile_h))>>8;\r
- } \r
+ }\r
\r
if ((msg->scale_mode == 2)||(msg->alpha_rop_flag >> 7))\r
{\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_mode_ctrl \r
-Description: \r
- fill mode ctrl reg info \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ RGA_set_mode_ctrl\r
+Description:\r
+ fill mode ctrl reg info\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
-void \r
+void\r
RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg)\r
{\r
u32 *bRGA_MODE_CTL;\r
u32 reg = 0;\r
- \r
+\r
u8 src_rgb_pack = 0;\r
u8 src_format = 0;\r
u8 src_rb_swp = 0;\r
u8 dst_format = 0;\r
u8 dst_rb_swp = 0;\r
u8 dst_a_swp = 0;\r
- \r
+\r
bRGA_MODE_CTL = (u32 *)(base + RGA_MODE_CTRL_OFFSET);\r
- \r
- reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode))); \r
+\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode)));\r
\r
/* src info set */\r
- \r
+\r
if (msg->render_mode == color_palette_mode || msg->render_mode == update_palette_table_mode)\r
{\r
src_format = 0x10 | (msg->palette_mode & 3);\r
{\r
switch (msg->src.format)\r
{\r
- case RK_FORMAT_RGBA_8888 : src_format = 0x0; break; \r
- case RK_FORMAT_RGBA_4444 : src_format = 0x3; break; \r
- case RK_FORMAT_RGBA_5551 : src_format = 0x2; break; \r
- case RK_FORMAT_BGRA_8888 : src_format = 0x0; src_rb_swp = 0x1; break; \r
- case RK_FORMAT_RGBX_8888 : src_format = 0x0; break; \r
+ case RK_FORMAT_RGBA_8888 : src_format = 0x0; break;\r
+ case RK_FORMAT_RGBA_4444 : src_format = 0x3; break;\r
+ case RK_FORMAT_RGBA_5551 : src_format = 0x2; break;\r
+ case RK_FORMAT_BGRA_8888 : src_format = 0x0; src_rb_swp = 0x1; break;\r
+ case RK_FORMAT_RGBX_8888 : src_format = 0x0; break;\r
case RK_FORMAT_RGB_565 : src_format = 0x1; break;\r
case RK_FORMAT_RGB_888 : src_format = 0x0; src_rgb_pack = 1; break;\r
case RK_FORMAT_BGR_888 : src_format = 0x0; src_rgb_pack = 1; src_rb_swp = 1; break;\r
- \r
- case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break; \r
- case RK_FORMAT_YCbCr_422_P : src_format = 0x5; break; \r
- case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break; \r
+\r
+ case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break;\r
+ case RK_FORMAT_YCbCr_422_P : src_format = 0x5; break;\r
+ case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break;\r
case RK_FORMAT_YCbCr_420_P : src_format = 0x7; break;\r
\r
- case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break; \r
- case RK_FORMAT_YCrCb_422_P : src_format = 0x5; src_cbcr_swp = 1; break; \r
- case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break; \r
+ case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break;\r
+ case RK_FORMAT_YCrCb_422_P : src_format = 0x5; src_cbcr_swp = 1; break;\r
+ case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break;\r
case RK_FORMAT_YCrCb_420_P : src_format = 0x7; src_cbcr_swp = 1; break;\r
- } \r
+ }\r
}\r
\r
src_a_swp = msg->src.alpha_swap & 1;\r
\r
- reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK)) | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack))); \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK)) | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_SRC_FORMAT)) | (s_RGA_MODE_CTRL_SRC_FORMAT(src_format)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RB_SWAP)) | (s_RGA_MODE_CTRL_SRC_RB_SWAP(src_rb_swp)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_SRC_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(src_a_swp)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE )) | (s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE (src_cbcr_swp)));\r
- \r
- \r
- /* YUV2RGB MODE */ \r
+\r
+\r
+ /* YUV2RGB MODE */\r
reg = ((reg & (~m_RGA_MODE_CTRL_YUV2RGB_CON_MODE)) | (s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(msg->yuv2rgb_mode)));\r
\r
/* ROTATE MODE */\r
/* COLOR FILL MODE */\r
reg = ((reg & (~m_RGA_MODE_CTRL_PAT_SEL)) | (s_RGA_MODE_CTRL_PAT_SEL(msg->color_fill_mode)));\r
\r
- \r
+\r
if ((msg->render_mode == update_palette_table_mode)||(msg->render_mode == update_patten_buff_mode))\r
{\r
dst_format = msg->pat.format;\r
{\r
dst_format = (u8)msg->dst.format;\r
}\r
- \r
- /* dst info set */ \r
+\r
+ /* dst info set */\r
switch (dst_format)\r
{\r
case RK_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; break;\r
}\r
\r
dst_a_swp = msg->dst.alpha_swap & 1;\r
- \r
- reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT)) | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format))); \r
+\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT)) | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK)) | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP)) | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp)));\r
- reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1))); \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE)) | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5)));\r
\r
*bRGA_MODE_CTL = reg;\r
- \r
+\r
}\r
\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_src \r
-Description: \r
- fill src relate reg info \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ RGA_set_src\r
+Description:\r
+ fill src relate reg info\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
void\r
RGA_set_src(u8 *base, const struct rga_req *msg)\r
-{ \r
+{\r
u32 *bRGA_SRC_VIR_INFO;\r
u32 *bRGA_SRC_ACT_INFO;\r
u32 *bRGA_SRC_Y_MST;\r
u32 pixel_width;\r
\r
uv_x_off = uv_y_off = uv_stride = 0;\r
- \r
+\r
bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);\r
bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);\r
bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);\r
y_off = msg->src.y_offset;\r
\r
pixel_width = RGA_pixel_width_init(msg->src.format);\r
- \r
+\r
stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);\r
\r
switch(msg->src.format)\r
{\r
- case RK_FORMAT_YCbCr_422_SP : \r
- uv_stride = stride; \r
- uv_x_off = x_off; \r
- uv_y_off = y_off; \r
+ case RK_FORMAT_YCbCr_422_SP :\r
+ uv_stride = stride;\r
+ uv_x_off = x_off;\r
+ uv_y_off = y_off;\r
break;\r
case RK_FORMAT_YCbCr_422_P :\r
uv_stride = stride >> 1;\r
uv_stride = stride >> 1;\r
uv_x_off = x_off >> 1;\r
uv_y_off = y_off >> 1;\r
- break; \r
- } \r
+ break;\r
+ }\r
\r
\r
- /* src addr set */ \r
+ /* src addr set */\r
*bRGA_SRC_Y_MST = msg->src.yrgb_addr + (y_off * stride) + (x_off * pixel_width);\r
*bRGA_SRC_CB_MST = msg->src.uv_addr + uv_y_off * uv_stride + uv_x_off;\r
*bRGA_SRC_CR_MST = msg->src.v_addr + uv_y_off * uv_stride + uv_x_off;\r
\r
byte_num = sw >> shift;\r
stride = (byte_num + 3) & (~3);\r
- } \r
+ }\r
\r
- /* src act window / vir window set */ \r
+ /* src act window / vir window set */\r
*bRGA_SRC_VIR_INFO = ((stride >> 2) | (msg->src.vir_h)<<16);\r
*bRGA_SRC_ACT_INFO = ((msg->src.act_w-1) | (msg->src.act_h-1)<<16);\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_dst \r
-Description: \r
- fill dst relate reg info \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ RGA_set_dst\r
+Description:\r
+ fill dst relate reg info\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
s32 RGA_set_dst(u8 *base, const struct rga_req *msg)\r
{\r
switch(msg->dst.format)\r
{\r
- case RK_FORMAT_YCbCr_422_SP : \r
+ case RK_FORMAT_YCbCr_422_SP :\r
*bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
break;\r
case RK_FORMAT_YCbCr_422_P :\r
case RK_FORMAT_YCrCb_420_P :\r
*bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
*bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
- break; \r
- } \r
+ break;\r
+ }\r
}\r
\r
rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21\r
- \r
+\r
reg = (stride >> 2) & 0xffff;\r
reg = reg | ((rop_mask_stride>>2) << 16);\r
\r
if (msg->render_mode == line_point_drawing_mode)\r
{\r
reg &= 0xffff;\r
- reg = reg | (msg->dst.vir_h << 16); \r
+ reg = reg | (msg->dst.vir_h << 16);\r
}\r
\r
*bRGA_DST_VIR_INFO = reg;\r
*bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);\r
\r
- return 0; \r
+ return 0;\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_alpha_rop \r
-Description: \r
- fill alpha rop some relate reg bit \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ RGA_set_alpha_rop\r
+Description:\r
+ fill alpha rop some relate reg bit\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
void\r
RGA_set_alpha_rop(u8 *base, const struct rga_req *msg)\r
u32 *bRGA_ROP_CON1;\r
u32 reg = 0;\r
u32 rop_con0, rop_con1;\r
- \r
+\r
u8 rop_mode = (msg->alpha_rop_mode) & 3;\r
u8 alpha_mode = msg->alpha_rop_mode & 3;\r
\r
rop_con0 = rop_con1 = 0;\r
- \r
+\r
bRGA_ALPHA_CON = (u32 *)(base + RGA_ALPHA_CON_OFFSET);\r
\r
reg = ((reg & (~m_RGA_ALPHA_CON_ENABLE) )| (s_RGA_ALPHA_CON_ENABLE(msg->alpha_rop_flag & 1)));\r
reg = ((reg & (~m_RGA_ALPHA_CON_DITHER_ENABLE)) | (s_RGA_ALPHA_CON_DITHER_ENABLE(msg->alpha_rop_flag >> 5)));\r
reg = ((reg & (~m_RGA_ALPHA_CON_GRADIENT_CAL_MODE)) | (s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(msg->alpha_rop_flag >> 6)));\r
reg = ((reg & (~m_RGA_ALPHA_CON_AA_SEL)) | (s_RGA_ALPHA_CON_AA_SEL(msg->alpha_rop_flag >> 7)));\r
- \r
+\r
*bRGA_ALPHA_CON = reg;\r
\r
- if(rop_mode == 0) { \r
+ if(rop_mode == 0) {\r
rop_con0 = ROP3_code[(msg->rop_code & 0xff)];\r
}\r
else if(rop_mode == 1) {\r
rop_con0 = ROP3_code[(msg->rop_code & 0xff)];\r
rop_con1 = ROP3_code[(msg->rop_code & 0xff00)>>8];\r
}\r
- \r
+\r
bRGA_ROP_CON0 = (u32 *)(base + RGA_ROP_CON0_OFFSET);\r
bRGA_ROP_CON1 = (u32 *)(base + RGA_ROP_CON1_OFFSET);\r
\r
*bRGA_ROP_CON0 = (u32)rop_con0;\r
- *bRGA_ROP_CON1 = (u32)rop_con1; \r
+ *bRGA_ROP_CON1 = (u32)rop_con1;\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_color \r
-Description: \r
+/*************************************************************\r
+Func:\r
+ RGA_set_color\r
+Description:\r
fill color some relate reg bit\r
bg_color/fg_color\r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
void\r
u32 *bRGA_SRC_TR_COLOR1;\r
u32 *bRGA_SRC_BG_COLOR;\r
u32 *bRGA_SRC_FG_COLOR;\r
- \r
- \r
+\r
+\r
bRGA_SRC_BG_COLOR = (u32 *)(base + RGA_SRC_BG_COLOR_OFFSET);\r
bRGA_SRC_FG_COLOR = (u32 *)(base + RGA_SRC_FG_COLOR_OFFSET);\r
- \r
+\r
*bRGA_SRC_BG_COLOR = msg->bg_color; /* 1bpp 0 */\r
*bRGA_SRC_FG_COLOR = msg->fg_color; /* 1bpp 1 */\r
- \r
- bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET); \r
+\r
+ bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET);\r
bRGA_SRC_TR_COLOR1 = (u32 *)(base + RGA_SRC_TR_COLOR1_OFFSET);\r
\r
*bRGA_SRC_TR_COLOR0 = msg->color_key_min;\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_fading \r
-Description: \r
+/*************************************************************\r
+Func:\r
+ RGA_set_fading\r
+Description:\r
fill fading some relate reg bit\r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
s32\r
\r
reg = (r<<8) | (g<<16) | (b<<24) | reg;\r
\r
- *bRGA_FADING_CON = reg; \r
- \r
+ *bRGA_FADING_CON = reg;\r
+\r
return 0;\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_pat \r
-Description: \r
+/*************************************************************\r
+Func:\r
+ RGA_set_pat\r
+Description:\r
fill patten some relate reg bit\r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
s32\r
bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);\r
\r
bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);\r
- \r
+\r
*bRGA_PAT_START_POINT = (msg->pat.act_w * msg->pat.y_offset) + msg->pat.x_offset;\r
\r
reg = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);\r
\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_bitblt_reg_info \r
-Description: \r
+/*************************************************************\r
+Func:\r
+ RGA_set_bitblt_reg_info\r
+Description:\r
fill bitblt mode relate ren info\r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
-void \r
+void\r
RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile)\r
{\r
u32 *bRGA_SRC_Y_MST;\r
\r
bRGA_SRC_X_PARA = (u32 *)(base + RGA_SRC_X_PARA_OFFSET);\r
bRGA_SRC_Y_PARA = (u32 *)(base + RGA_SRC_Y_PARA_OFFSET);\r
- \r
+\r
bRGA_SRC_TILE_XINFO = (u32 *)(base + RGA_SRC_TILE_XINFO_OFFSET);\r
bRGA_SRC_TILE_YINFO = (u32 *)(base + RGA_SRC_TILE_YINFO_OFFSET);\r
bRGA_SRC_TILE_H_INCR = (u32 *)(base + RGA_SRC_TILE_H_INCR_OFFSET);\r
- bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET); \r
+ bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET);\r
bRGA_SRC_TILE_OFFSETX = (u32 *)(base + RGA_SRC_TILE_OFFSETX_OFFSET);\r
bRGA_SRC_TILE_OFFSETY = (u32 *)(base + RGA_SRC_TILE_OFFSETY_OFFSET);\r
\r
bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);\r
bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);\r
\r
- /* Matrix reg fill */ \r
+ /* Matrix reg fill */\r
m0 = (s32)(tile->matrix[0] >> 18);\r
m1 = (s32)(tile->matrix[1] >> 18);\r
m2 = (s32)(tile->matrix[2] >> 18);\r
\r
*bRGA_SRC_X_PARA = (m0 & 0xffff) | (m2 << 16);\r
*bRGA_SRC_Y_PARA = (m1 & 0xffff) | (m3 << 16);\r
- \r
- /* src tile information setting */ \r
+\r
+ /* src tile information setting */\r
if(msg->rotate_mode != 0)//add by hxx,2011.7.12,for rtl0707,when line scanning ,do not calc src tile info\r
{\r
*bRGA_SRC_TILE_XINFO = (tile->tile_start_x_coor & 0xffff) | (tile->tile_w << 16);\r
}\r
\r
pixel_width = RGA_pixel_width_init(msg->src.format);\r
- \r
+\r
stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);\r
\r
if ((msg->rotate_mode == 1)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))\r
pos[6] >>= 11;\r
pos[7] >>= 11;\r
\r
- xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1); \r
- xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6])); \r
+ xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1);\r
+ xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]));\r
\r
- ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1); \r
- ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7])); \r
+ ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1);\r
+ ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]));\r
\r
xp = xmin + msg->src.x_offset;\r
yp = ymin + msg->src.y_offset;\r
xp = CLIP(xp, msg->src.x_offset, msg->src.x_offset + msg->src.act_w - 1);\r
yp = CLIP(yp, msg->src.y_offset, msg->src.y_offset + msg->src.act_h - 1);\r
}\r
- \r
+\r
switch(msg->src.format)\r
- { \r
+ {\r
case RK_FORMAT_YCbCr_420_P :\r
y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);\r
break;\r
case RK_FORMAT_YCbCr_420_SP :\r
y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
- u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1); \r
+ u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);\r
break;\r
- case RK_FORMAT_YCbCr_422_P : \r
+ case RK_FORMAT_YCbCr_422_P :\r
y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);\r
v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1);\r
break;\r
case RK_FORMAT_YCrCb_420_SP :\r
y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
- u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1); \r
+ u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);\r
break;\r
- case RK_FORMAT_YCrCb_422_P : \r
+ case RK_FORMAT_YCrCb_422_P :\r
y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);\r
v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1);\r
case RK_FORMAT_YCrCb_422_SP:\r
y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
u_addr = msg->src.uv_addr + yp*stride + ((xp>>1)<<1);\r
- break; \r
+ break;\r
default :\r
y_addr = msg->src.yrgb_addr + yp*stride + xp*pixel_width;\r
break;\r
*bRGA_SRC_CB_MST = u_addr;\r
*bRGA_SRC_CR_MST = v_addr;\r
}\r
- \r
+\r
/*dst info*/\r
pixel_width = RGA_pixel_width_init(msg->dst.format);\r
stride = (msg->dst.vir_w * pixel_width + 3) & (~3);\r
*bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (tile->dst_ctrl.y_off * stride) + (tile->dst_ctrl.x_off * pixel_width);\r
*bRGA_DST_CTR_INFO = (tile->dst_ctrl.w) | ((tile->dst_ctrl.h) << 16);\r
- \r
+\r
*bRGA_DST_CTR_INFO |= ((1<<29) | (1<<28));\r
}\r
\r
\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_color_palette_reg_info \r
-Description: \r
+/*************************************************************\r
+Func:\r
+ RGA_set_color_palette_reg_info\r
+Description:\r
fill color palette process some relate reg bit\r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
void\r
y_off = msg->src.y_offset;\r
\r
sw = msg->src.vir_w;\r
- shift = 3 - (msg->palette_mode & 3); \r
+ shift = 3 - (msg->palette_mode & 3);\r
byte_num = sw >> shift;\r
src_stride = (byte_num + 3) & (~3);\r
- \r
- p = msg->src.yrgb_addr; \r
+\r
+ p = msg->src.yrgb_addr;\r
p = p + (x_off>>shift) + y_off*src_stride;\r
\r
- bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET); \r
- *bRGA_SRC_Y_MST = (u32)p; \r
+ bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);\r
+ *bRGA_SRC_Y_MST = (u32)p;\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_color_fill_reg_info \r
-Description: \r
+/*************************************************************\r
+Func:\r
+ RGA_set_color_fill_reg_info\r
+Description:\r
fill color fill process some relate reg bit\r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
void\r
RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg)\r
*bRGA_CP_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16);\r
\r
*bRGA_PAT_CON = (msg->pat.vir_w-1) | ((msg->pat.vir_h-1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);\r
- \r
+\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_line_drawing_reg_info \r
-Description: \r
+/*************************************************************\r
+Func:\r
+ RGA_set_line_drawing_reg_info\r
+Description:\r
fill line drawing process some relate reg bit\r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg)\r
u32 *bRGA_DST_VIR_INFO;\r
u32 *bRGA_LINE_DRAW_XY_INFO;\r
u32 *bRGA_LINE_DRAW_WIDTH;\r
- u32 *bRGA_LINE_DRAWING_COLOR; \r
+ u32 *bRGA_LINE_DRAWING_COLOR;\r
u32 *bRGA_LINE_DRAWING_MST;\r
- \r
+\r
u32 reg = 0;\r
\r
s16 x_width, y_width;\r
u32 start_addr;\r
u8 line_dir, dir_major, dir_semi_major;\r
u16 major_width;\r
- \r
+\r
bRGA_LINE_DRAW = (u32 *)(base + RGA_LINE_DRAW_OFFSET);\r
bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);\r
bRGA_LINE_DRAW_XY_INFO = (u32 *)(base + RGA_LINE_DRAW_XY_INFO_OFFSET);\r
\r
stride = (msg->dst.vir_w * pw + 3) & (~3);\r
\r
- start_addr = msg->dst.yrgb_addr \r
- + (msg->line_draw_info.start_point.y * stride) \r
+ start_addr = msg->dst.yrgb_addr\r
+ + (msg->line_draw_info.start_point.y * stride)\r
+ (msg->line_draw_info.start_point.x * pw);\r
\r
x_width = msg->line_draw_info.start_point.x - msg->line_draw_info.end_point.x;\r
y_width = msg->line_draw_info.start_point.y - msg->line_draw_info.end_point.y;\r
\r
abs_x = abs(x_width);\r
- abs_y = abs(y_width); \r
- \r
+ abs_y = abs(y_width);\r
+\r
if (abs_x >= abs_y)\r
{\r
if (y_width > 0)\r
else\r
dir_semi_major = 0;\r
\r
- if (x_width > 0) \r
- dir_major = 1; \r
+ if (x_width > 0)\r
+ dir_major = 1;\r
else\r
dir_major = 0;\r
\r
- if((abs_x == 0)||(abs_y == 0)) \r
- delta = 0; \r
- else \r
+ if((abs_x == 0)||(abs_y == 0))\r
+ delta = 0;\r
+ else\r
delta = (abs_y<<12)/abs_x;\r
\r
if (delta >> 12)\r
delta -= 1;\r
- \r
- major_width = abs_x; \r
+\r
+ major_width = abs_x;\r
line_dir = 0;\r
}\r
else\r
dir_major = 1;\r
else\r
dir_major = 0;\r
- \r
- delta = (abs_x<<12)/abs_y; \r
+\r
+ delta = (abs_x<<12)/abs_y;\r
major_width = abs_y;\r
line_dir = 1;\r
}\r
- \r
+\r
reg = (reg & (~m_RGA_LINE_DRAW_MAJOR_WIDTH)) | (s_RGA_LINE_DRAW_MAJOR_WIDTH(major_width));\r
reg = (reg & (~m_RGA_LINE_DRAW_LINE_DIRECTION)) | (s_RGA_LINE_DRAW_LINE_DIRECTION(line_dir));\r
reg = (reg & (~m_RGA_LINE_DRAW_LINE_WIDTH)) | (s_RGA_LINE_DRAW_LINE_WIDTH(msg->line_draw_info.line_width - 1));\r
- reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE)) | (s_RGA_LINE_DRAW_INCR_VALUE(delta)); \r
+ reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE)) | (s_RGA_LINE_DRAW_INCR_VALUE(delta));\r
reg = (reg & (~m_RGA_LINE_DRAW_DIR_SEMI_MAJOR)) | (s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(dir_semi_major));\r
reg = (reg & (~m_RGA_LINE_DRAW_DIR_MAJOR)) | (s_RGA_LINE_DRAW_DIR_MAJOR(dir_major));\r
reg = (reg & (~m_RGA_LINE_DRAW_LAST_POINT)) | (s_RGA_LINE_DRAW_LAST_POINT(msg->line_draw_info.flag >> 1));\r
- reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING)) | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag)); \r
+ reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING)) | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag));\r
\r
*bRGA_LINE_DRAW = reg;\r
- \r
+\r
reg = (msg->line_draw_info.start_point.x & 0xfff) | ((msg->line_draw_info.start_point.y & 0xfff) << 16);\r
*bRGA_LINE_DRAW_XY_INFO = reg;\r
- \r
+\r
*bRGA_LINE_DRAW_WIDTH = msg->dst.vir_w;\r
\r
*bRGA_LINE_DRAWING_COLOR = msg->line_draw_info.color;\r
\r
*bRGA_LINE_DRAWING_MST = (u32)start_addr;\r
- \r
+\r
return 0;\r
}\r
\r
/*full*/\r
s32\r
RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg)\r
-{ \r
+{\r
u32 *bRGA_BLUR_SHARP_INFO;\r
u32 reg = 0;\r
- \r
+\r
bRGA_BLUR_SHARP_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);\r
\r
reg = *bRGA_BLUR_SHARP_INFO;\r
reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_MODE)) | (s_RGA_BLUR_SHARP_FILTER_MODE(msg->bsfilter_flag >>2)));\r
\r
*bRGA_BLUR_SHARP_INFO = reg;\r
- \r
- return 0; \r
+\r
+ return 0;\r
}\r
\r
\r
s32\r
RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg)\r
{\r
- u32 *bRGA_PRE_SCALE_INFO; \r
+ u32 *bRGA_PRE_SCALE_INFO;\r
u32 reg = 0;\r
u32 h_ratio = 0;\r
u32 v_ratio = 0;\r
if((dst_width == 0) || (dst_height == 0))\r
{\r
printk("pre scale reg info error ratio is divide zero\n");\r
- return -EINVAL; \r
+ return -EINVAL;\r
}\r
\r
h_ratio = (src_width <<16) / dst_width;\r
v_ratio = (src_height<<16) / dst_height;\r
\r
- if (h_ratio <= (1<<16)) \r
+ if (h_ratio <= (1<<16))\r
h_ratio = 0;\r
else if (h_ratio <= (2<<16))\r
h_ratio = 1;\r
else if (h_ratio <= (8<<16))\r
h_ratio = 3;\r
\r
- if (v_ratio <= (1<<16)) \r
+ if (v_ratio <= (1<<16))\r
v_ratio = 0;\r
else if (v_ratio <= (2<<16))\r
v_ratio = 1;\r
v_ratio = 3;\r
\r
if(msg->src.format == msg->dst.format)\r
- ps_yuv_flag = 0; \r
- else \r
- ps_yuv_flag = 1; \r
+ ps_yuv_flag = 0;\r
+ else\r
+ ps_yuv_flag = 1;\r
\r
bRGA_PRE_SCALE_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);\r
- \r
+\r
reg = *bRGA_PRE_SCALE_INFO;\r
reg = ((reg & (~m_RGA_PRE_SCALE_HOR_RATIO)) | (s_RGA_PRE_SCALE_HOR_RATIO((u8)h_ratio)));\r
reg = ((reg & (~m_RGA_PRE_SCALE_VER_RATIO)) | (s_RGA_PRE_SCALE_VER_RATIO((u8)v_ratio)));\r
reg = ((reg & (~m_RGA_PRE_SCALE_OUTPUT_FORMAT)) | (s_RGA_PRE_SCALE_OUTPUT_FORMAT(ps_yuv_flag)));\r
\r
*bRGA_PRE_SCALE_INFO = reg;\r
- \r
- return 0; \r
+\r
+ return 0;\r
}\r
\r
\r
\r
/*full*/\r
-int \r
+int\r
RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg)\r
{\r
u32 *bRGA_LUT_MST;\r
\r
- if (!msg->LUT_addr) { \r
+ if (!msg->LUT_addr) {\r
return -1;\r
- } \r
+ }\r
\r
bRGA_LUT_MST = (u32 *)(base + RGA_LUT_MST_OFFSET);\r
- \r
- *bRGA_LUT_MST = (u32)msg->LUT_addr; \r
+\r
+ *bRGA_LUT_MST = (u32)msg->LUT_addr;\r
\r
return 0;\r
}\r
\r
if ( !pat->yrgb_addr ) {\r
return -1;\r
- } \r
+ }\r
*bRGA_PAT_MST = (u32)pat->yrgb_addr;\r
\r
if ((pat->vir_w > 256)||(pat->x_offset > 256)||(pat->y_offset > 256)) {\r
*bRGA_PAT_START_POINT = (pat->vir_w * pat->y_offset) + pat->x_offset;\r
\r
reg = (pat->vir_w-1) | ((pat->vir_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);\r
- *bRGA_PAT_CON = reg; \r
- \r
+ *bRGA_PAT_CON = reg;\r
+\r
return 0;\r
}\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_set_mmu_ctrl_reg_info \r
-Description: \r
- fill mmu relate some reg info \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ RGA_set_mmu_ctrl_reg_info\r
+Description:\r
+ fill mmu relate some reg info\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
\r
s32\r
mmu_addr = (u32)msg->mmu_info.base_addr;\r
TLB_size = (msg->mmu_info.mmu_flag >> 4) & 0x3;\r
mmu_enable = msg->mmu_info.mmu_flag & 0x1;\r
- \r
+\r
src_flag = (msg->mmu_info.mmu_flag >> 1) & 0x1;\r
dst_flag = (msg->mmu_info.mmu_flag >> 2) & 0x1;\r
CMD_flag = (msg->mmu_info.mmu_flag >> 3) & 0x1;\r
reg = ((reg & (~m_RGA_MMU_CTRL_TLB_ADDR)) | s_RGA_MMU_CTRL_TLB_ADDR(mmu_addr));\r
*RGA_MMU_TLB = reg;\r
\r
- reg = *RGA_MMU_CTRL_ADDR; \r
+ reg = *RGA_MMU_CTRL_ADDR;\r
reg = ((reg & (~m_RGA_MMU_CTRL_PAGE_TABLE_SIZE)) | s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(TLB_size));\r
reg = ((reg & (~m_RGA_MMU_CTRL_MMU_ENABLE)) | s_RGA_MMU_CTRL_MMU_ENABLE(mmu_enable));\r
reg = ((reg & (~m_RGA_MMU_CTRL_SRC_FLUSH)) | s_RGA_MMU_CTRL_SRC_FLUSH(1));\r
\r
\r
\r
-/************************************************************* \r
-Func: \r
- RGA_gen_reg_info \r
-Description: \r
- Generate RGA command reg list from rga_req struct. \r
-Author: \r
- ZhangShengqin \r
-Date: \r
- 20012-2-2 10:59:25 \r
+/*************************************************************\r
+Func:\r
+ RGA_gen_reg_info\r
+Description:\r
+ Generate RGA command reg list from rga_req struct.\r
+Author:\r
+ ZhangShengqin\r
+Date:\r
+ 20012-2-2 10:59:25\r
**************************************************************/\r
int\r
RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base)\r
{\r
TILE_INFO tile;\r
\r
- memset(base, 0x0, 28*4); \r
+ memset(base, 0x0, 28*4);\r
RGA_set_mode_ctrl(base, msg);\r
- \r
+\r
switch(msg->render_mode)\r
{\r
case bitblt_mode :\r
RGA_set_alpha_rop(base, msg);\r
RGA_set_src(base, msg);\r
- RGA_set_dst(base, msg); \r
+ RGA_set_dst(base, msg);\r
RGA_set_color(base, msg);\r
RGA_set_fading(base, msg);\r
- RGA_set_pat(base, msg); \r
+ RGA_set_pat(base, msg);\r
matrix_cal(msg, &tile);\r
dst_ctrl_cal(msg, &tile);\r
src_tile_info_cal(msg, &tile);\r
- RGA_set_bitblt_reg_info(base, msg, &tile); \r
+ RGA_set_bitblt_reg_info(base, msg, &tile);\r
break;\r
case color_palette_mode :\r
RGA_set_src(base, msg);\r
- RGA_set_dst(base, msg); \r
+ RGA_set_dst(base, msg);\r
RGA_set_color(base, msg);\r
RGA_set_color_palette_reg_info(base, msg);\r
break;\r
case color_fill_mode :\r
RGA_set_alpha_rop(base, msg);\r
- RGA_set_dst(base, msg); \r
+ RGA_set_dst(base, msg);\r
RGA_set_color(base, msg);\r
RGA_set_pat(base, msg);\r
RGA_set_color_fill_reg_info(base, msg);\r
break;\r
case pre_scaling_mode :\r
RGA_set_src(base, msg);\r
- RGA_set_dst(base, msg); \r
+ RGA_set_dst(base, msg);\r
if(RGA_set_pre_scale_reg_info(base, msg) == -EINVAL)\r
return -1;\r
break;\r
}\r
break;\r
case update_patten_buff_mode:\r
- if (RGA_set_update_patten_buff_reg_info(base, msg)){ \r
+ if (RGA_set_update_patten_buff_reg_info(base, msg)){\r
return -1;\r
}\r
- \r
+\r
break;\r
}\r
\r
--- /dev/null
+menu "RGA2"
+ depends on ARCH_ROCKCHIP
+
+config ROCKCHIP_RGA2
+ tristate "ROCKCHIP_RGA2"
+ help
+ rk32 rga2 module.
+
+endmenu
--- /dev/null
+rga2-y := rga2_drv.o rga2_mmu_info.o rga2_reg_info.o RGA2_API.o
+
+obj-$(CONFIG_ROCKCHIP_RGA2) += rga2.o
--- /dev/null
+\r
+#include <linux/memory.h>\r
+#include "RGA2_API.h"\r
+#include "rga2.h"\r
+//#include "rga_angle.h"\r
+\r
+#define IS_YUV_420(format) \\r
+ ((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \\r
+ (format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP))\r
+\r
+#define IS_YUV_422(format) \\r
+ ((format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \\r
+ (format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))\r
+\r
+#define IS_YUV(format) \\r
+ ((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \\r
+ (format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP) | \\r
+ (format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \\r
+ (format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))\r
+\r
+\r
+\r
--- /dev/null
+#ifndef __RGA_API_H__\r
+#define __RGA_API_H__\r
+\r
+#include "rga2_reg_info.h"\r
+#include "rga2.h"\r
+\r
+#define ENABLE 1\r
+#define DISABLE 0\r
+\r
+\r
+\r
+#endif\r
--- /dev/null
+#ifndef _RGA_DRIVER_H_\r
+#define _RGA_DRIVER_H_\r
+\r
+#include <linux/mutex.h>\r
+\r
+#define RGA_BLIT_SYNC 0x5017\r
+#define RGA_BLIT_ASYNC 0x5018\r
+#define RGA_FLUSH 0x5019\r
+#define RGA_GET_RESULT 0x501a\r
+#define RGA_GET_VERSION 0x501b\r
+\r
+#define RGA2_BLIT_SYNC 0x6017\r
+#define RGA2_BLIT_ASYNC 0x6018\r
+#define RGA2_FLUSH 0x6019\r
+#define RGA2_GET_RESULT 0x601a\r
+#define RGA2_GET_VERSION 0x601b\r
+\r
+\r
+#define RGA2_REG_CTRL_LEN 0x8 /* 8 */\r
+#define RGA2_REG_CMD_LEN 0x20 /* 32 */\r
+#define RGA2_CMD_BUF_SIZE 0x700 /* 16*28*4 */\r
+\r
+#define RGA2_OUT_OF_RESOURCES -10\r
+#define RGA2_MALLOC_ERROR -11\r
+\r
+#define SCALE_DOWN_LARGE 1\r
+\r
+#define rgaIS_ERROR(status) (status < 0)\r
+#define rgaNO_ERROR(status) (status >= 0)\r
+#define rgaIS_SUCCESS(status) (status == 0)\r
+\r
+/* RGA2 process mode enum */\r
+enum\r
+{\r
+ bitblt_mode = 0x0,\r
+ color_palette_mode = 0x1,\r
+ color_fill_mode = 0x2,\r
+ update_palette_table_mode = 0x3,\r
+ update_patten_buff_mode = 0x4,\r
+}; /*render mode*/\r
+\r
+enum\r
+{\r
+ A_B_B =0x0,\r
+ A_B_C =0x1,\r
+}; //bitblt_mode select\r
+\r
+enum\r
+{\r
+ rop_enable_mask = 0x2,\r
+ dither_enable_mask = 0x8,\r
+ fading_enable_mask = 0x10,\r
+ PD_enbale_mask = 0x20,\r
+};\r
+\r
+\r
+\r
+/*\r
+// Alpha Red Green Blue\r
+{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888\r
+{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888\r
+{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888\r
+{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888\r
+{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565\r
+{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551\r
+{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444\r
+{ 2, 16, {{ 0, 0, 5, 0 11, 5, 16,11}}, GGL_BGR }, // RK_FORMAT_BGR_565\r
+{ 2, 16, {{ 1, 0, 6, 1, 11, 6, 16,11}}, GGL_BGRA }, // RK_FORMAT_BGRA_5551\r
+{ 2, 16, {{ 4, 0, 8, 4, 12, 8, 16,12}}, GGL_BGRA }, // RK_FORMAT_BGRA_4444\r
+\r
+*/\r
+enum\r
+{\r
+ RGA2_FORMAT_RGBA_8888 = 0x0,\r
+ RGA2_FORMAT_RGBX_8888 = 0x1,\r
+ RGA2_FORMAT_RGB_888 = 0x2,\r
+ RGA2_FORMAT_BGRA_8888 = 0x3,\r
+ RGA2_FORMAT_BGRX_8888 = 0x4,\r
+ RGA2_FORMAT_BGR_888 = 0x5,\r
+ RGA2_FORMAT_RGB_565 = 0x6,\r
+ RGA2_FORMAT_RGBA_5551 = 0x7,\r
+ RGA2_FORMAT_RGBA_4444 = 0x8,\r
+ RGA2_FORMAT_BGR_565 = 0x9,\r
+ RGA2_FORMAT_BGRA_5551 = 0xa,\r
+ RGA2_FORMAT_BGRA_4444 = 0xb,\r
+\r
+ RGA2_FORMAT_YCbCr_422_SP = 0x10,\r
+ RGA2_FORMAT_YCbCr_422_P = 0x11,\r
+ RGA2_FORMAT_YCbCr_420_SP = 0x12,\r
+ RGA2_FORMAT_YCbCr_420_P = 0x13,\r
+ RGA2_FORMAT_YCrCb_422_SP = 0x14,\r
+ RGA2_FORMAT_YCrCb_422_P = 0x15,\r
+ RGA2_FORMAT_YCrCb_420_SP = 0x16,\r
+ RGA2_FORMAT_YCrCb_420_P = 0x17,\r
+};\r
+\r
+typedef struct mdp_img\r
+{\r
+ u16 width;\r
+ u16 height;\r
+ u32 format;\r
+ u32 mem_addr;\r
+}\r
+mdp_img;\r
+\r
+typedef struct mdp_img_act\r
+{\r
+ u16 width; // width\r
+ u16 height; // height\r
+ s16 x_off; // x offset for the vir\r
+ s16 y_off; // y offset for the vir\r
+ s16 uv_x_off;\r
+ s16 uv_y_off;\r
+}\r
+mdp_img_act;\r
+\r
+typedef struct mdp_img_vir\r
+{\r
+ u16 width;\r
+ u16 height;\r
+ u32 format;\r
+ u32 mem_addr;\r
+ u32 uv_addr;\r
+ u32 v_addr;\r
+}\r
+mdp_img_vir;\r
+\r
+\r
+typedef struct MMU_INFO\r
+{\r
+ u32 src0_base_addr;\r
+ u32 src1_base_addr;\r
+ u32 dst_base_addr;\r
+ u32 els_base_addr;\r
+\r
+ u8 src0_mmu_flag; /* [0] src0 mmu enable [1] src0_flush [2] src0_prefetch_en [3] src0_prefetch dir */\r
+ u8 src1_mmu_flag; /* [0] src1 mmu enable [1] src1_flush [2] src1_prefetch_en [3] src1_prefetch dir */\r
+ u8 dst_mmu_flag; /* [0] dst mmu enable [1] dst_flush [2] dst_prefetch_en [3] dst_prefetch dir */\r
+ u8 els_mmu_flag; /* [0] els mmu enable [1] els_flush [2] els_prefetch_en [3] els_prefetch dir */\r
+} MMU_INFO;\r
+\r
+\r
+enum\r
+{\r
+ MMU_DIS = 0x0,\r
+ MMU_EN = 0x1\r
+};\r
+enum\r
+{\r
+ MMU_FLUSH_DIS = 0x0,\r
+ MMU_FLUSH_EN = 0x2\r
+};\r
+enum\r
+{\r
+ MMU_PRE_DIS = 0x0,\r
+ MMU_PRE_EN = 0x4\r
+};\r
+enum\r
+{\r
+ MMU_PRE_DIR_FORW = 0x0,\r
+ MMU_PRE_DIR_BACK = 0x8\r
+};\r
+typedef struct COLOR_FILL\r
+{\r
+ s16 gr_x_a;\r
+ s16 gr_y_a;\r
+ s16 gr_x_b;\r
+ s16 gr_y_b;\r
+ s16 gr_x_g;\r
+ s16 gr_y_g;\r
+ s16 gr_x_r;\r
+ s16 gr_y_r;\r
+}\r
+COLOR_FILL;\r
+\r
+enum\r
+{\r
+ ALPHA_ORIGINAL = 0x0,\r
+ ALPHA_NO_128 = 0x1\r
+};\r
+\r
+enum\r
+{\r
+ R2_BLACK = 0x00,\r
+ R2_COPYPEN = 0xf0,\r
+ R2_MASKNOTPEN = 0x0a,\r
+ R2_MASKPEN = 0xa0,\r
+ R2_MASKPENNOT = 0x50,\r
+ R2_MERGENOTPEN = 0xaf,\r
+ R2_MERGEPEN = 0xfa,\r
+ R2_MERGEPENNOT = 0xf5,\r
+ R2_NOP = 0xaa,\r
+ R2_NOT = 0x55,\r
+ R2_NOTCOPYPEN = 0x0f,\r
+ R2_NOTMASKPEN = 0x5f,\r
+ R2_NOTMERGEPEN = 0x05,\r
+ R2_NOTXORPEN = 0xa5,\r
+ R2_WHITE = 0xff,\r
+ R2_XORPEN = 0x5a\r
+};\r
+\r
+\r
+/***************************************/\r
+/* porting from rga.h for msg convert */\r
+/***************************************/\r
+\r
+typedef struct FADING\r
+{\r
+ uint8_t b;\r
+ uint8_t g;\r
+ uint8_t r;\r
+ uint8_t res;\r
+}\r
+FADING;\r
+\r
+typedef struct MMU\r
+{\r
+ unsigned char mmu_en;\r
+ uint32_t base_addr;\r
+ uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/\r
+} MMU;\r
+\r
+\r
+typedef struct RECT\r
+{\r
+ unsigned short xmin;\r
+ unsigned short xmax; // width - 1\r
+ unsigned short ymin;\r
+ unsigned short ymax; // height - 1\r
+} RECT;\r
+\r
+typedef struct POINT\r
+{\r
+ unsigned short x;\r
+ unsigned short y;\r
+}\r
+POINT;\r
+\r
+typedef struct line_draw_t\r
+{\r
+ POINT start_point; /* LineDraw_start_point */\r
+ POINT end_point; /* LineDraw_end_point */\r
+ uint32_t color; /* LineDraw_color */\r
+ uint32_t flag; /* (enum) LineDrawing mode sel */\r
+ uint32_t line_width; /* range 1~16 */\r
+}\r
+line_draw_t;\r
+\r
+typedef struct rga_img_info_t\r
+{\r
+ unsigned int yrgb_addr; /* yrgb mem addr */\r
+ unsigned int uv_addr; /* cb/cr mem addr */\r
+ unsigned int v_addr; /* cr mem addr */\r
+ unsigned int format; //definition by RK_FORMAT\r
+\r
+ unsigned short act_w;\r
+ unsigned short act_h;\r
+ unsigned short x_offset;\r
+ unsigned short y_offset;\r
+\r
+ unsigned short vir_w;\r
+ unsigned short vir_h;\r
+\r
+ unsigned short endian_mode; //for BPP\r
+ unsigned short alpha_swap;\r
+\r
+ //unsigned short uv_x_off;\r
+ //unsigned short uv_y_off;\r
+}\r
+rga_img_info_t;\r
+\r
+struct rga_req {\r
+ uint8_t render_mode; /* (enum) process mode sel */\r
+\r
+ rga_img_info_t src; /* src image info */\r
+ rga_img_info_t dst; /* dst image info */\r
+ rga_img_info_t pat; /* patten image info */\r
+\r
+ uint32_t rop_mask_addr; /* rop4 mask addr */\r
+ uint32_t LUT_addr; /* LUT addr */\r
+\r
+ RECT clip; /* dst clip window default value is dst_vir */\r
+ /* value from [0, w-1] / [0, h-1]*/\r
+\r
+ int32_t sina; /* dst angle default value 0 16.16 scan from table */\r
+ int32_t cosa; /* dst angle default value 0 16.16 scan from table */\r
+\r
+ uint16_t alpha_rop_flag; /* alpha rop process flag */\r
+ /* ([0] = 1 alpha_rop_enable) */\r
+ /* ([1] = 1 rop enable) */\r
+ /* ([2] = 1 fading_enable) */\r
+ /* ([3] = 1 PD_enable) */\r
+ /* ([4] = 1 alpha cal_mode_sel) */\r
+ /* ([5] = 1 dither_enable) */\r
+ /* ([6] = 1 gradient fill mode sel) */\r
+ /* ([7] = 1 AA_enable) */\r
+\r
+ uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */\r
+\r
+ uint32_t color_key_max; /* color key max */\r
+ uint32_t color_key_min; /* color key min */\r
+\r
+ uint32_t fg_color; /* foreground color */\r
+ uint32_t bg_color; /* background color */\r
+\r
+ COLOR_FILL gr_color; /* color fill use gradient */\r
+\r
+ line_draw_t line_draw_info;\r
+\r
+ FADING fading;\r
+\r
+ uint8_t PD_mode; /* porter duff alpha mode sel */\r
+\r
+ uint8_t alpha_global_value; /* global alpha value */\r
+\r
+ uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/\r
+\r
+ uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/\r
+\r
+ uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/\r
+\r
+ uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */\r
+\r
+ uint8_t endian_mode; /* 0/big endian 1/little endian*/\r
+\r
+ uint8_t rotate_mode; /* (enum) rotate mode */\r
+ /* 0x0, no rotate */\r
+ /* 0x1, rotate */\r
+ /* 0x2, x_mirror */\r
+ /* 0x3, y_mirror */\r
+\r
+ uint8_t color_fill_mode; /* 0 solid color / 1 patten color */\r
+\r
+ MMU mmu_info; /* mmu information */\r
+\r
+ uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */\r
+ /* ([2~3] rop mode) */\r
+ /* ([4] zero mode en) */\r
+ /* ([5] dst alpha mode) */\r
+ /* ([6] alpha output mode sel) 0 src / 1 dst*/\r
+\r
+ uint8_t src_trans_mode;\r
+};\r
+\r
+\r
+\r
+struct rga2_req\r
+{\r
+ u8 render_mode; /* (enum) process mode sel */\r
+\r
+ rga_img_info_t src; // src active window\r
+ rga_img_info_t src1; // src1 active window\r
+ rga_img_info_t dst; // dst active window\r
+ rga_img_info_t pat; // patten active window\r
+\r
+ u32 rop_mask_addr; // rop4 mask addr\r
+ u32 LUT_addr; // LUT addr\r
+\r
+ u32 rop_mask_stride;\r
+\r
+ u8 bitblt_mode; /* 0: SRC + DST => DST */\r
+ /* 1: SRC + SRC1 => DST */\r
+\r
+ u8 rotate_mode; /* [1:0] */\r
+ /* 0 degree 0x0 */\r
+ /* 90 degree 0x1 */\r
+ /* 180 degree 0x2 */\r
+ /* 270 degree 0x3 */\r
+ /* [5:4] */\r
+ /* none 0x0 */\r
+ /* x_mirror 0x1 */\r
+ /* y_mirror 0x2 */\r
+ /* x_mirror + y_mirror 0x3 */\r
+\r
+ u16 alpha_rop_flag; /* alpha rop process flag */\r
+ /* ([0] = 1 alpha_rop_enable) */\r
+ /* ([1] = 1 rop enable) */\r
+ /* ([2] = 1 fading_enable) */\r
+ /* ([3] = 1 alpha cal_mode_sel) */\r
+ /* ([4] = 1 src_dither_up_enable) */\r
+ /* ([5] = 1 dst_dither_up_enable) */\r
+ /* ([6] = 1 dither_down_enable) */\r
+ /* ([7] = 1 gradient fill mode sel) */\r
+\r
+\r
+ u16 alpha_mode_0; /* [0] SrcAlphaMode0 */\r
+ /* [2:1] SrcGlobalAlphaMode0 */\r
+ /* [3] SrcAlphaSelectMode0 */\r
+ /* [6:4] SrcFactorMode0 */\r
+ /* [7] SrcColorMode */\r
+\r
+ /* [8] DstAlphaMode0 */\r
+ /* [10:9] DstGlobalAlphaMode0 */\r
+ /* [11] DstAlphaSelectMode0 */\r
+ /* [14:12] DstFactorMode0 */\r
+ /* [15] DstColorMode0 */\r
+\r
+ u16 alpha_mode_1; /* [0] SrcAlphaMode1 */\r
+ /* [2:1] SrcGlobalAlphaMode1 */\r
+ /* [3] SrcAlphaSelectMode1 */\r
+ /* [6:4] SrcFactorMode1 */\r
+\r
+ /* [8] DstAlphaMode1 */\r
+ /* [10:9] DstGlobalAlphaMode1 */\r
+ /* [11] DstAlphaSelectMode1 */\r
+ /* [14:12] DstFactorMode1 */\r
+\r
+ u8 scale_bicu_mode; /* 0 1 2 3 */\r
+\r
+ u32 color_key_max; /* color key max */\r
+ u32 color_key_min; /* color key min */\r
+\r
+ u32 fg_color; /* foreground color */\r
+ u32 bg_color; /* background color */\r
+\r
+ u8 color_fill_mode;\r
+ COLOR_FILL gr_color; /* color fill use gradient */\r
+\r
+ u8 fading_alpha_value; /* Fading value */\r
+ u8 fading_r_value;\r
+ u8 fading_g_value;\r
+ u8 fading_b_value;\r
+\r
+ u8 src_a_global_val; /* src global alpha value */\r
+ u8 dst_a_global_val; /* dst global alpha value */\r
+\r
+\r
+ u8 rop_mode;\r
+ u16 rop_code; /* rop2/3/4 code */\r
+\r
+ u8 palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/\r
+\r
+ u8 yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */\r
+\r
+ u8 endian_mode; /* 0/little endian 1/big endian */\r
+\r
+ u8 CMD_fin_int_enable;\r
+\r
+ MMU_INFO mmu_info; /* mmu infomation */\r
+\r
+ u8 alpha_zero_key;\r
+ u8 src_trans_mode;\r
+\r
+ u8 alpha_swp;\r
+ u8 dither_mode;\r
+\r
+ u8 rgb2yuv_mode;\r
+};\r
+\r
+struct rga2_mmu_buf_t {\r
+ int32_t front;\r
+ int32_t back;\r
+ int32_t size;\r
+ int32_t curr;\r
+ unsigned int *buf;\r
+ unsigned int *buf_virtual;\r
+};\r
+\r
+//add for FPGA test ,by hxx & luj\r
+\r
+enum\r
+{\r
+ BB_ROTATE_OFF = 0x0, /* no rotate */\r
+ BB_ROTATE_90 = 0x1, /* rotate 90 */\r
+ BB_ROTATE_180 = 0x2, /* rotate 180 */\r
+ BB_ROTATE_270 = 0x3, /* rotate 270 */\r
+}; /*rotate mode*/\r
+\r
+enum\r
+{\r
+ BB_MIRROR_OFF = (0x0 << 4), /* no mirror */\r
+ BB_MIRROR_X = (0x1 << 4), /* x mirror */\r
+ BB_MIRROR_Y = (0x2 << 4), /* y mirror */\r
+ BB_MIRROR_XY = (0x3 << 4), /* xy mirror */\r
+}; /*mirror mode*/\r
+\r
+enum\r
+{\r
+ BB_COPY_USE_TILE = (0x1 << 6), /* bitblt mode copy but use Tile mode */\r
+};\r
+\r
+enum\r
+{\r
+ //BYPASS = 0x0,\r
+ BT_601_RANGE0 = 0x1,\r
+ BT_601_RANGE1 = 0x2,\r
+ BT_709_RANGE0 = 0x3,\r
+}; /*yuv2rgb_mode*/\r
+\r
+enum\r
+{\r
+ BPP1 = 0x0, /* BPP1 */\r
+ BPP2 = 0x1, /* BPP2 */\r
+ BPP4 = 0x2, /* BPP4 */\r
+ BPP8 = 0x3 /* BPP8 */\r
+}; /*palette_mode*/\r
+\r
+enum\r
+{\r
+ SOLID_COLOR = 0x0, //color fill mode; ROP4: SOLID_rop4_mask_addr COLOR\r
+ PATTERN_COLOR = 0x1 //pattern_fill_mode;ROP4:PATTERN_COLOR\r
+}; /*color fill mode*/\r
+\r
+enum\r
+{\r
+ COLOR_FILL_CLIP = 0x0,\r
+ COLOR_FILL_NOT_CLIP = 0x1\r
+};\r
+\r
+enum\r
+{\r
+ CATROM = 0x0,\r
+ MITCHELL = 0x1,\r
+ HERMITE = 0x2,\r
+ B_SPLINE = 0x3,\r
+}; /*bicubic coefficient*/\r
+\r
+enum\r
+{\r
+ ROP2 = 0x0,\r
+ ROP3 = 0x1,\r
+ ROP4 = 0x2\r
+}; /*ROP mode*/\r
+\r
+enum\r
+{\r
+ BIG_ENDIAN = 0x0,\r
+ LITTLE_ENDIAN = 0x1\r
+}; /*endian mode*/\r
+\r
+enum\r
+{\r
+ MMU_TABLE_4KB = 0x0,\r
+ MMU_TABLE_64KB = 0x1,\r
+}; /*MMU table size*/\r
+\r
+enum\r
+{\r
+ RGB_2_666 = 0x0,\r
+ RGB_2_565 = 0x1,\r
+ RGB_2_555 = 0x2,\r
+ RGB_2_444 = 0x3,\r
+}; /*dither down mode*/\r
+\r
+\r
+\r
+/**\r
+ * struct for process session which connect to rga\r
+ *\r
+ * @author ZhangShengqin (2012-2-15)\r
+ */\r
+typedef struct rga2_session {\r
+ /* a linked list of data so we can access them for debugging */\r
+ struct list_head list_session;\r
+ /* a linked list of register data waiting for process */\r
+ struct list_head waiting;\r
+ /* a linked list of register data in processing */\r
+ struct list_head running;\r
+ /* all coommand this thread done */\r
+ atomic_t done;\r
+ wait_queue_head_t wait;\r
+ pid_t pid;\r
+ atomic_t task_running;\r
+ atomic_t num_done;\r
+} rga2_session;\r
+\r
+struct rga2_reg {\r
+ rga2_session *session;\r
+ struct list_head session_link; /* link to rga service session */\r
+ struct list_head status_link; /* link to register set list */\r
+ uint32_t sys_reg[8];\r
+ uint32_t cmd_reg[32];\r
+\r
+ uint32_t *MMU_base;\r
+ uint32_t MMU_len;\r
+ //atomic_t int_enable;\r
+\r
+ //struct rga_req req;\r
+};\r
+\r
+\r
+\r
+struct rga2_service_info {\r
+ struct mutex lock;\r
+ struct timer_list timer; /* timer for power off */\r
+ struct list_head waiting; /* link to link_reg in struct vpu_reg */\r
+ struct list_head running; /* link to link_reg in struct vpu_reg */\r
+ struct list_head done; /* link to link_reg in struct vpu_reg */\r
+ struct list_head session; /* link to list_session in struct vpu_session */\r
+ atomic_t total_running;\r
+\r
+ struct rga2_reg *reg;\r
+\r
+ uint32_t cmd_buff[32*8];/* cmd_buff for rga */\r
+ uint32_t *pre_scale_buf;\r
+ atomic_t int_disable; /* 0 int enable 1 int disable */\r
+ atomic_t cmd_num;\r
+ atomic_t src_format_swt;\r
+ int last_prc_src_format;\r
+ atomic_t rga_working;\r
+ bool enable;\r
+\r
+ //struct rga_req req[10];\r
+\r
+ struct mutex mutex; // mutex\r
+};\r
+\r
+#define RGA2_TEST_CASE 0\r
+#define RGA2_TEST 0\r
+#define RGA2_TEST_MSG 0\r
+#define RGA2_TEST_TIME 0\r
+\r
+\r
+#if defined(CONFIG_ARCH_RK3190)\r
+#define RGA2_BASE 0x1010c000\r
+#elif defined(CONFIG_ARCH_RK32)\r
+#define RGA2_BASE 0x10114000\r
+#endif\r
+\r
+//General Registers\r
+#define RGA2_SYS_CTRL 0x000\r
+#define RGA2_CMD_CTRL 0x004\r
+#define RGA2_CMD_BASE 0x008\r
+#define RGA2_STATUS 0x00c\r
+#define RGA2_INT 0x010\r
+#define RGA2_MMU_CTRL0 0x018\r
+#define RGA2_MMU_CMD_BASE 0x01c\r
+\r
+//Command code start\r
+#define RGA2_MODE_CTRL 0x100\r
+#define RGA_BLIT_COMPLETE_EVENT 1\r
+\r
+long rga2_ioctl_kernel(struct rga2_req *req);\r
+\r
+\r
+#endif /*_RK29_IPP_DRIVER_H_*/\r
--- /dev/null
+/*\r
+ * Copyright (C) 2012 ROCKCHIP, Inc.\r
+ *\r
+ * This software is licensed under the terms of the GNU General Public\r
+ * License version 2, as published by the Free Software Foundation, and\r
+ * may be copied, distributed, and modified under those terms.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ */\r
+\r
+#define pr_fmt(fmt) "rga: " fmt\r
+#include <linux/kernel.h>\r
+#include <linux/init.h>\r
+#include <linux/module.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/sched.h>\r
+#include <linux/mutex.h>\r
+#include <linux/err.h>\r
+#include <linux/clk.h>\r
+#include <asm/delay.h>\r
+#include <linux/dma-mapping.h>\r
+#include <linux/delay.h>\r
+#include <asm/io.h>\r
+#include <linux/irq.h>\r
+#include <linux/interrupt.h>\r
+#include <mach/io.h>\r
+#include <mach/irqs.h>\r
+#include <linux/fs.h>\r
+#include <asm/uaccess.h>\r
+#include <linux/miscdevice.h>\r
+#include <linux/poll.h>\r
+#include <linux/delay.h>\r
+#include <linux/wait.h>\r
+#include <linux/syscalls.h>\r
+#include <linux/timer.h>\r
+#include <linux/time.h>\r
+#include <asm/cacheflush.h>\r
+#include <linux/slab.h>\r
+#include <linux/fb.h>\r
+#include <linux/wakelock.h>\r
+\r
+#include "rga2.h"\r
+#include "rga2_reg_info.h"\r
+#include "rga2_mmu_info.h"\r
+#include "RGA2_API.h"\r
+\r
+\r
+#define RGA2_TEST_FLUSH_TIME 0\r
+#define RGA2_INFO_BUS_ERROR 1\r
+\r
+#define RGA2_POWER_OFF_DELAY 4*HZ /* 4s */\r
+#define RGA2_TIMEOUT_DELAY 2*HZ /* 2s */\r
+\r
+#define RGA2_MAJOR 255\r
+\r
+#if defined(CONFIG_ROCKCHIP_RGA2)\r
+#define RK32_RGA2_PHYS 0xFFC70000\r
+#define RK32_RGA2_SIZE 0x00001000\r
+#endif\r
+#define RGA2_RESET_TIMEOUT 1000\r
+\r
+/* Driver information */\r
+#define DRIVER_DESC "RGA2 Device Driver"\r
+#define DRIVER_NAME "rga2"\r
+\r
+#define RGA2_VERSION "2.000"\r
+\r
+ktime_t rga_start;\r
+ktime_t rga_end;\r
+\r
+int rga2_flag = 0;\r
+\r
+rga2_session rga2_session_global;\r
+\r
+struct rga2_drvdata_t {\r
+ struct miscdevice miscdev;\r
+ struct device dev;\r
+ void *rga_base;\r
+ int irq;\r
+\r
+ struct delayed_work power_off_work;\r
+ void (*rga_irq_callback)(int rga_retval); //callback function used by aync call\r
+ struct wake_lock wake_lock;\r
+\r
+ struct clk *aclk_rga2;\r
+ struct clk *hclk_rga2;\r
+ struct clk *pd_rga2;\r
+ struct clk *rga2;\r
+};\r
+\r
+struct rga2_drvdata_t *rga2_drvdata;\r
+\r
+struct rga2_service_info rga2_service;\r
+struct rga2_mmu_buf_t rga2_mmu_buf;\r
+\r
+static int rga2_blit_async(rga2_session *session, struct rga2_req *req);\r
+static void rga2_del_running_list(void);\r
+static void rga2_del_running_list_timeout(void);\r
+static void rga2_try_set_reg(void);\r
+\r
+\r
+/* Logging */\r
+#define RGA_DEBUG 0\r
+#if RGA_DEBUG\r
+#define DBG(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)\r
+#define ERR(format, args...) printk(KERN_ERR "%s: " format, DRIVER_NAME, ## args)\r
+#define WARNING(format, args...) printk(KERN_WARN "%s: " format, DRIVER_NAME, ## args)\r
+#define INFO(format, args...) printk(KERN_INFO "%s: " format, DRIVER_NAME, ## args)\r
+#else\r
+#define DBG(format, args...)\r
+#define ERR(format, args...)\r
+#define WARNING(format, args...)\r
+#define INFO(format, args...)\r
+#endif\r
+\r
+#if RGA2_TEST_MSG\r
+static void print_info(struct rga2_req *req)\r
+{\r
+ printk("render_mode=%d bitblt_mode=%d rotate_mode=%.8x\n",\r
+ req->render_mode, req->bitblt_mode, req->rotate_mode);\r
+ printk("src : y=%.8x uv=%.8x v=%.8x format=%d aw=%d ah=%d vw=%d vh=%d xoff=%d yoff=%d \n",\r
+ req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr, req->src.format,\r
+ req->src.act_w, req->src.act_h, req->src.vir_w, req->src.vir_h,\r
+ req->src.x_offset, req->src.y_offset);\r
+ printk("dst : y=%.8x uv=%.8x v=%.8x format=%d aw=%d ah=%d vw=%d vh=%d xoff=%d yoff=%d \n",\r
+ req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr, req->dst.format,\r
+ req->dst.act_w, req->dst.act_h, req->dst.vir_w, req->dst.vir_h,\r
+ req->dst.x_offset, req->dst.y_offset);\r
+ printk("mmu : src=%.2x src1=%.2x dst=%.2x els=%.2x\n",\r
+ req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,\r
+ req->mmu_info.dst_mmu_flag, req->mmu_info.els_mmu_flag);\r
+ printk("alpha : flag %.8x mode0=%.8x mode1=%.8x\n",\r
+ req->alpha_rop_flag, req->alpha_mode_0, req->alpha_mode_1);\r
+}\r
+#endif\r
+\r
+\r
+static inline void rga2_write(u32 b, u32 r)\r
+{\r
+ __raw_writel(b, rga2_drvdata->rga_base + r);\r
+}\r
+\r
+static inline u32 rga2_read(u32 r)\r
+{\r
+ return __raw_readl(rga2_drvdata->rga_base + r);\r
+}\r
+\r
+static void rga2_soft_reset(void)\r
+{\r
+ u32 i;\r
+ u32 reg;\r
+\r
+ rga2_write(1, RGA2_SYS_CTRL); //RGA_SYS_CTRL\r
+\r
+ for(i = 0; i < RGA2_RESET_TIMEOUT; i++)\r
+ {\r
+ reg = rga2_read(RGA2_SYS_CTRL) & 1; //RGA_SYS_CTRL\r
+\r
+ if(reg == 0)\r
+ break;\r
+\r
+ udelay(1);\r
+ }\r
+\r
+ if(i == RGA2_RESET_TIMEOUT)\r
+ ERR("soft reset timeout.\n");\r
+}\r
+\r
+static void rga2_dump(void)\r
+{\r
+ int running;\r
+ struct rga2_reg *reg, *reg_tmp;\r
+ rga2_session *session, *session_tmp;\r
+\r
+ running = atomic_read(&rga2_service.total_running);\r
+ printk("rga total_running %d\n", running);\r
+\r
+ #if 0\r
+\r
+ /* Dump waiting list info */\r
+ if (!list_empty(&rga_service.waiting))\r
+ {\r
+ list_head *next;\r
+\r
+ next = &rga_service.waiting;\r
+\r
+ printk("rga_service dump waiting list\n");\r
+\r
+ do\r
+ {\r
+ reg = list_entry(next->next, struct rga_reg, status_link);\r
+ running = atomic_read(®->session->task_running);\r
+ num_done = atomic_read(®->session->num_done);\r
+ printk("rga session pid %d, done %d, running %d\n", reg->session->pid, num_done, running);\r
+ next = next->next;\r
+ }\r
+ while(!list_empty(next));\r
+ }\r
+\r
+ /* Dump running list info */\r
+ if (!list_empty(&rga_service.running))\r
+ {\r
+ printk("rga_service dump running list\n");\r
+\r
+ list_head *next;\r
+\r
+ next = &rga_service.running;\r
+ do\r
+ {\r
+ reg = list_entry(next->next, struct rga_reg, status_link);\r
+ running = atomic_read(®->session->task_running);\r
+ num_done = atomic_read(®->session->num_done);\r
+ printk("rga session pid %d, done %d, running %d:\n", reg->session->pid, num_done, running);\r
+ next = next->next;\r
+ }\r
+ while(!list_empty(next));\r
+ }\r
+ #endif\r
+\r
+ list_for_each_entry_safe(session, session_tmp, &rga2_service.session, list_session)\r
+ {\r
+ printk("session pid %d:\n", session->pid);\r
+ running = atomic_read(&session->task_running);\r
+ printk("task_running %d\n", running);\r
+ list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link)\r
+ {\r
+ printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
+ }\r
+ list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link)\r
+ {\r
+ printk("running register set 0x%.8x\n", (unsigned int)reg);\r
+ }\r
+ }\r
+}\r
+\r
+static inline void rga2_queue_power_off_work(void)\r
+{\r
+ queue_delayed_work(system_nrt_wq, &rga2_drvdata->power_off_work, RGA2_POWER_OFF_DELAY);\r
+}\r
+\r
+/* Caller must hold rga_service.lock */\r
+static void rga2_power_on(void)\r
+{\r
+ static ktime_t last;\r
+ ktime_t now = ktime_get();\r
+\r
+ if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
+ cancel_delayed_work_sync(&rga2_drvdata->power_off_work);\r
+ rga2_queue_power_off_work();\r
+ last = now;\r
+ }\r
+ if (rga2_service.enable)\r
+ return;\r
+\r
+ clk_enable(rga2_drvdata->rga2);\r
+ clk_enable(rga2_drvdata->aclk_rga2);\r
+ clk_enable(rga2_drvdata->hclk_rga2);\r
+ clk_enable(rga2_drvdata->pd_rga2);\r
+ wake_lock(&rga2_drvdata->wake_lock);\r
+ rga2_service.enable = true;\r
+}\r
+\r
+/* Caller must hold rga_service.lock */\r
+static void rga2_power_off(void)\r
+{\r
+ int total_running;\r
+\r
+ if (!rga2_service.enable) {\r
+ return;\r
+ }\r
+\r
+ total_running = atomic_read(&rga2_service.total_running);\r
+ if (total_running) {\r
+ pr_err("power off when %d task running!!\n", total_running);\r
+ mdelay(50);\r
+ pr_err("delay 50 ms for running task\n");\r
+ rga2_dump();\r
+ }\r
+\r
+ clk_disable(rga2_drvdata->pd_rga2);\r
+ clk_disable(rga2_drvdata->rga2);\r
+ clk_disable(rga2_drvdata->aclk_rga2);\r
+ clk_disable(rga2_drvdata->hclk_rga2);\r
+ wake_unlock(&rga2_drvdata->wake_lock);\r
+ rga2_service.enable = false;\r
+}\r
+\r
+static void rga2_power_off_work(struct work_struct *work)\r
+{\r
+ if (mutex_trylock(&rga2_service.lock)) {\r
+ rga2_power_off();\r
+ mutex_unlock(&rga2_service.lock);\r
+ } else {\r
+ /* Come back later if the device is busy... */\r
+ rga2_queue_power_off_work();\r
+ }\r
+}\r
+\r
+static int rga2_flush(rga2_session *session, unsigned long arg)\r
+{\r
+ int ret = 0;\r
+ int ret_timeout;\r
+\r
+ #if RGA2_TEST_FLUSH_TIME\r
+ ktime_t start;\r
+ ktime_t end;\r
+ start = ktime_get();\r
+ #endif\r
+\r
+ ret_timeout = wait_event_timeout(session->wait, atomic_read(&session->done), RGA2_TIMEOUT_DELAY);\r
+\r
+ if (unlikely(ret_timeout < 0)) {\r
+ //pr_err("flush pid %d wait task ret %d\n", session->pid, ret);\r
+ mutex_lock(&rga2_service.lock);\r
+ rga2_del_running_list();\r
+ mutex_unlock(&rga2_service.lock);\r
+ ret = ret_timeout;\r
+ } else if (0 == ret_timeout) {\r
+ //pr_err("flush pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
+ //printk("bus = %.8x\n", rga_read(RGA_INT));\r
+ mutex_lock(&rga2_service.lock);\r
+ rga2_del_running_list_timeout();\r
+ rga2_try_set_reg();\r
+ mutex_unlock(&rga2_service.lock);\r
+ ret = -ETIMEDOUT;\r
+ }\r
+\r
+ #if RGA2_TEST_FLUSH_TIME\r
+ end = ktime_get();\r
+ end = ktime_sub(end, start);\r
+ printk("one flush wait time %d\n", (int)ktime_to_us(end));\r
+ #endif\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+static int rga2_get_result(rga2_session *session, unsigned long arg)\r
+{\r
+ //printk("rga_get_result %d\n",drvdata->rga_result);\r
+\r
+ int ret = 0;\r
+\r
+ int num_done;\r
+\r
+ num_done = atomic_read(&session->num_done);\r
+\r
+ if (unlikely(copy_to_user((void __user *)arg, &num_done, sizeof(int)))) {\r
+ printk("copy_to_user failed\n");\r
+ ret = -EFAULT;\r
+ }\r
+ return ret;\r
+}\r
+\r
+\r
+static int rga2_check_param(const struct rga2_req *req)\r
+{\r
+ /*RGA2 can support up to 8192*8192 resolution in RGB format,but we limit the image size to 8191*8191 here*/\r
+ //check src width and height\r
+\r
+ if(!((req->render_mode == color_fill_mode)))\r
+ {\r
+ if (unlikely((req->src.act_w <= 0) || (req->src.act_w > 8191) || (req->src.act_h <= 0) || (req->src.act_h > 8191)))\r
+ {\r
+ printk("invalid source resolution act_w = %d, act_h = %d\n", req->src.act_w, req->src.act_h);\r
+ return -EINVAL;\r
+ }\r
+ }\r
+\r
+ if(!((req->render_mode == color_fill_mode)))\r
+ {\r
+ if (unlikely((req->src.vir_w <= 0) || (req->src.vir_w > 8191) || (req->src.vir_h <= 0) || (req->src.vir_h > 8191)))\r
+ {\r
+ printk("invalid source resolution vir_w = %d, vir_h = %d\n", req->src.vir_w, req->src.vir_h);\r
+ return -EINVAL;\r
+ }\r
+ }\r
+\r
+ //check dst width and height\r
+ if (unlikely((req->dst.act_w <= 0) || (req->dst.act_w > 4096) || (req->dst.act_h <= 0) || (req->dst.act_h > 4096)))\r
+ {\r
+ printk("invalid destination resolution act_w = %d, act_h = %d\n", req->dst.act_w, req->dst.act_h);\r
+ return -EINVAL;\r
+ }\r
+\r
+ if (unlikely((req->dst.vir_w <= 0) || (req->dst.vir_w > 4096) || (req->dst.vir_h <= 0) || (req->dst.vir_h > 4096)))\r
+ {\r
+ printk("invalid destination resolution vir_w = %d, vir_h = %d\n", req->dst.vir_w, req->dst.vir_h);\r
+ return -EINVAL;\r
+ }\r
+\r
+ //check src_vir_w\r
+ if(unlikely(req->src.vir_w < req->src.act_w)){\r
+ printk("invalid src_vir_w act_w = %d, vir_w = %d\n", req->src.act_w, req->src.vir_w);\r
+ return -EINVAL;\r
+ }\r
+\r
+ //check dst_vir_w\r
+ if(unlikely(req->dst.vir_w < req->dst.act_w)){\r
+ if(req->rotate_mode != 1)\r
+ {\r
+ printk("invalid dst_vir_w act_h = %d, vir_h = %d\n", req->dst.act_w, req->dst.vir_w);\r
+ return -EINVAL;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static void rga2_copy_reg(struct rga2_reg *reg, uint32_t offset)\r
+{\r
+ uint32_t i;\r
+ uint32_t *cmd_buf;\r
+ uint32_t *reg_p;\r
+\r
+ if(atomic_read(®->session->task_running) != 0)\r
+ {\r
+ printk(KERN_ERR "task_running is no zero\n");\r
+ }\r
+\r
+ atomic_add(1, &rga2_service.cmd_num);\r
+ atomic_add(1, ®->session->task_running);\r
+\r
+ cmd_buf = (uint32_t *)rga2_service.cmd_buff + offset*32;\r
+ reg_p = (uint32_t *)reg->cmd_reg;\r
+\r
+ for(i=0; i<32; i++)\r
+ {\r
+ cmd_buf[i] = reg_p[i];\r
+ }\r
+\r
+ dsb();\r
+}\r
+\r
+\r
+static struct rga2_reg * rga2_reg_init(rga2_session *session, struct rga2_req *req)\r
+{\r
+ uint32_t ret;\r
+ struct rga2_reg *reg = kzalloc(sizeof(struct rga2_reg), GFP_KERNEL);\r
+ if (NULL == reg) {\r
+ pr_err("kmalloc fail in rga_reg_init\n");\r
+ return NULL;\r
+ }\r
+\r
+ reg->session = session;\r
+ INIT_LIST_HEAD(®->session_link);\r
+ INIT_LIST_HEAD(®->status_link);\r
+\r
+ reg->MMU_base = NULL;\r
+\r
+ if ((req->mmu_info.src0_mmu_flag & 1) || (req->mmu_info.src1_mmu_flag & 1)\r
+ || (req->mmu_info.dst_mmu_flag & 1) || (req->mmu_info.els_mmu_flag & 1))\r
+ {\r
+ ret = rga2_set_mmu_info(reg, req);\r
+ if(ret < 0)\r
+ {\r
+ printk("%s, [%d] set mmu info error \n", __FUNCTION__, __LINE__);\r
+ if(reg != NULL)\r
+ {\r
+ kfree(reg);\r
+ }\r
+ return NULL;\r
+ }\r
+ }\r
+\r
+ if(RGA2_gen_reg_info((uint8_t *)reg->cmd_reg, req) == -1)\r
+ {\r
+ printk("gen reg info error\n");\r
+ if(reg != NULL)\r
+ {\r
+ kfree(reg);\r
+ }\r
+ return NULL;\r
+ }\r
+\r
+ mutex_lock(&rga2_service.lock);\r
+ list_add_tail(®->status_link, &rga2_service.waiting);\r
+ list_add_tail(®->session_link, &session->waiting);\r
+ mutex_unlock(&rga2_service.lock);\r
+\r
+ return reg;\r
+}\r
+\r
+\r
+/* Caller must hold rga_service.lock */\r
+static void rga2_reg_deinit(struct rga2_reg *reg)\r
+{\r
+ list_del_init(®->session_link);\r
+ list_del_init(®->status_link);\r
+ kfree(reg);\r
+}\r
+\r
+/* Caller must hold rga_service.lock */\r
+static void rga2_reg_from_wait_to_run(struct rga2_reg *reg)\r
+{\r
+ list_del_init(®->status_link);\r
+ list_add_tail(®->status_link, &rga2_service.running);\r
+\r
+ list_del_init(®->session_link);\r
+ list_add_tail(®->session_link, ®->session->running);\r
+}\r
+\r
+/* Caller must hold rga_service.lock */\r
+static void rga2_service_session_clear(rga2_session *session)\r
+{\r
+ struct rga2_reg *reg, *n;\r
+\r
+ list_for_each_entry_safe(reg, n, &session->waiting, session_link)\r
+ {\r
+ rga2_reg_deinit(reg);\r
+ }\r
+\r
+ list_for_each_entry_safe(reg, n, &session->running, session_link)\r
+ {\r
+ rga2_reg_deinit(reg);\r
+ }\r
+}\r
+\r
+/* Caller must hold rga_service.lock */\r
+static void rga2_try_set_reg(void)\r
+{\r
+ struct rga2_reg *reg ;\r
+\r
+ if (list_empty(&rga2_service.running))\r
+ {\r
+ if (!list_empty(&rga2_service.waiting))\r
+ {\r
+ /* RGA is idle */\r
+ reg = list_entry(rga2_service.waiting.next, struct rga2_reg, status_link);\r
+\r
+ rga2_power_on();\r
+ udelay(1);\r
+\r
+ rga2_copy_reg(reg, 0);\r
+ rga2_reg_from_wait_to_run(reg);\r
+\r
+ dmac_flush_range(&rga2_service.cmd_buff[0], &rga2_service.cmd_buff[32]);\r
+ outer_flush_range(virt_to_phys(&rga2_service.cmd_buff[0]),virt_to_phys(&rga2_service.cmd_buff[32]));\r
+\r
+ #if defined(CONFIG_ARCH_RK30)\r
+ rga2_soft_reset();\r
+ #endif\r
+\r
+ rga2_write(0x0, RGA2_SYS_CTRL);\r
+ //rga2_write(0, RGA_MMU_CTRL);\r
+\r
+ /* CMD buff */\r
+ rga2_write(virt_to_phys(rga2_service.cmd_buff), RGA2_CMD_BASE);\r
+\r
+#if RGA2_TEST\r
+ if(rga2_flag)\r
+ {\r
+ //printk(KERN_DEBUG "cmd_addr = %.8x\n", rga_read(RGA_CMD_ADDR));\r
+ uint32_t i, *p;\r
+ p = rga2_service.cmd_buff;\r
+ printk("CMD_REG\n");\r
+ for (i=0; i<8; i++)\r
+ printk("%.8x %.8x %.8x %.8x\n", p[0 + i*4], p[1+i*4], p[2 + i*4], p[3 + i*4]);\r
+ }\r
+#endif\r
+\r
+ /* master mode */\r
+ rga2_write((0x1<<1)|(0x1<<2)|(0x1<<5)|(0x1<<6), RGA2_SYS_CTRL);\r
+\r
+ /* All CMD finish int */\r
+ rga2_write(rga2_read(RGA2_INT)|(0x1<<10)|(0x1<<8), RGA2_INT);\r
+\r
+ #if RGA2_TEST_TIME\r
+ rga_start = ktime_get();\r
+ #endif\r
+\r
+ /* Start proc */\r
+ atomic_set(®->session->done, 0);\r
+ rga2_write(0x1, RGA2_CMD_CTRL);\r
+#if RGA2_TEST\r
+ if(rga2_flag)\r
+ {\r
+ uint32_t i;\r
+ printk("CMD_READ_BACK_REG\n");\r
+ for (i=0; i<8; i++)\r
+ printk("%.8x %.8x %.8x %.8x\n", rga2_read(0x100 + i*16 + 0),\r
+ rga2_read(0x100 + i*16 + 4), rga2_read(0x100 + i*16 + 8), rga2_read(0x100 + i*16 + 12));\r
+ }\r
+#endif\r
+ }\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
+/* Caller must hold rga_service.lock */\r
+static void rga2_del_running_list(void)\r
+{\r
+ struct rga2_reg *reg;\r
+\r
+ while(!list_empty(&rga2_service.running))\r
+ {\r
+ reg = list_entry(rga2_service.running.next, struct rga2_reg, status_link);\r
+\r
+ if(reg->MMU_len != 0)\r
+ {\r
+ if (rga2_mmu_buf.back + reg->MMU_len > 2*rga2_mmu_buf.size)\r
+ rga2_mmu_buf.back = reg->MMU_len + rga2_mmu_buf.size;\r
+ else\r
+ rga2_mmu_buf.back += reg->MMU_len;\r
+ }\r
+ atomic_sub(1, ®->session->task_running);\r
+ atomic_sub(1, &rga2_service.total_running);\r
+\r
+ if(list_empty(®->session->waiting))\r
+ {\r
+ atomic_set(®->session->done, 1);\r
+ wake_up(®->session->wait);\r
+ }\r
+\r
+ rga2_reg_deinit(reg);\r
+ }\r
+}\r
+\r
+/* Caller must hold rga_service.lock */\r
+static void rga2_del_running_list_timeout(void)\r
+{\r
+ struct rga2_reg *reg;\r
+\r
+ while(!list_empty(&rga2_service.running))\r
+ {\r
+ reg = list_entry(rga2_service.running.next, struct rga2_reg, status_link);\r
+\r
+ if(reg->MMU_base != NULL)\r
+ {\r
+ kfree(reg->MMU_base);\r
+ }\r
+\r
+ atomic_sub(1, ®->session->task_running);\r
+ atomic_sub(1, &rga2_service.total_running);\r
+\r
+ //printk("RGA soft reset for timeout process\n");\r
+ rga2_soft_reset();\r
+\r
+\r
+ #if 0\r
+ printk("RGA_INT is %.8x\n", rga_read(RGA_INT));\r
+ printk("reg->session->task_running = %d\n", atomic_read(®->session->task_running));\r
+ printk("rga_service.total_running = %d\n", atomic_read(&rga_service.total_running));\r
+\r
+ print_info(®->req);\r
+\r
+ {\r
+ uint32_t *p, i;\r
+ p = reg->cmd_reg;\r
+ for (i=0; i<7; i++)\r
+ printk("%.8x %.8x %.8x %.8x\n", p[0 + i*4], p[1+i*4], p[2 + i*4], p[3 + i*4]);\r
+\r
+ }\r
+ #endif\r
+\r
+ if(list_empty(®->session->waiting))\r
+ {\r
+ atomic_set(®->session->done, 1);\r
+ wake_up(®->session->wait);\r
+ }\r
+\r
+ rga2_reg_deinit(reg);\r
+ }\r
+}\r
+\r
+\r
+static void rga2_mem_addr_sel(struct rga2_req *req)\r
+{\r
+}\r
+\r
+\r
+static int rga2_blit(rga2_session *session, struct rga2_req *req)\r
+{\r
+ int ret = -1;\r
+ int num = 0;\r
+ struct rga2_reg *reg;\r
+\r
+ do\r
+ {\r
+ /* check value if legal */\r
+ ret = rga2_check_param(req);\r
+ if(ret == -EINVAL) {\r
+ printk("req argument is inval\n");\r
+ break;\r
+ }\r
+\r
+ reg = rga2_reg_init(session, req);\r
+ if(reg == NULL) {\r
+ break;\r
+ }\r
+ num = 1;\r
+\r
+ mutex_lock(&rga2_service.lock);\r
+ atomic_add(num, &rga2_service.total_running);\r
+ rga2_try_set_reg();\r
+ mutex_unlock(&rga2_service.lock);\r
+\r
+ return 0;\r
+ }\r
+ while(0);\r
+\r
+ return -EFAULT;\r
+}\r
+\r
+static int rga2_blit_async(rga2_session *session, struct rga2_req *req)\r
+{\r
+ int ret = -1;\r
+\r
+ #if RGA2_TEST_MSG\r
+ //printk("*** rga_blit_async proc ***\n");\r
+ if (req->src.format >= 0x10) {\r
+ print_info(req);\r
+ rga2_flag = 1;\r
+ printk("*** rga_blit_async proc ***\n");\r
+ }\r
+ else\r
+ rga2_flag = 0;\r
+ #endif\r
+ atomic_set(&session->done, 0);\r
+ ret = rga2_blit(session, req);\r
+\r
+ return ret;\r
+}\r
+\r
+static int rga2_blit_sync(rga2_session *session, struct rga2_req *req)\r
+{\r
+ int ret = -1;\r
+ int ret_timeout = 0;\r
+\r
+ #if RGA2_TEST_MSG\r
+ if (req->src.format >= 0x10) {\r
+ print_info(req);\r
+ rga2_flag = 1;\r
+ printk("*** rga2_blit_sync proc ***\n");\r
+ }\r
+ else\r
+ rga2_flag = 0;\r
+ #endif\r
+\r
+ atomic_set(&session->done, 0);\r
+\r
+ ret = rga2_blit(session, req);\r
+ if(ret < 0)\r
+ {\r
+ return ret;\r
+ }\r
+\r
+ ret_timeout = wait_event_timeout(session->wait, atomic_read(&session->done), RGA2_TIMEOUT_DELAY);\r
+\r
+ if (unlikely(ret_timeout< 0))\r
+ {\r
+ //pr_err("sync pid %d wait task ret %d\n", session->pid, ret_timeout);\r
+ mutex_lock(&rga2_service.lock);\r
+ rga2_del_running_list();\r
+ mutex_unlock(&rga2_service.lock);\r
+ ret = ret_timeout;\r
+ }\r
+ else if (0 == ret_timeout)\r
+ {\r
+ //pr_err("sync pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
+ mutex_lock(&rga2_service.lock);\r
+ rga2_del_running_list_timeout();\r
+ rga2_try_set_reg();\r
+ mutex_unlock(&rga2_service.lock);\r
+ ret = -ETIMEDOUT;\r
+ }\r
+\r
+ #if RGA2_TEST_TIME\r
+ rga_end = ktime_get();\r
+ rga_end = ktime_sub(rga_end, rga_start);\r
+ printk("sync one cmd end time %d\n", (int)ktime_to_us(rga_end));\r
+ #endif\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)\r
+{\r
+ struct rga2_req req;\r
+ struct rga_req req_rga;\r
+ int ret = 0;\r
+ rga2_session *session;\r
+\r
+ mutex_lock(&rga2_service.mutex);\r
+\r
+ session = (rga2_session *)file->private_data;\r
+\r
+ if (NULL == session)\r
+ {\r
+ printk("%s [%d] rga thread session is null\n",__FUNCTION__,__LINE__);\r
+ mutex_unlock(&rga2_service.mutex);\r
+ return -EINVAL;\r
+ }\r
+\r
+ memset(&req, 0x0, sizeof(req));\r
+\r
+ switch (cmd)\r
+ {\r
+ case RGA_BLIT_SYNC:\r
+\r
+ if (unlikely(copy_from_user(&req_rga, (struct rga_req*)arg, sizeof(struct rga_req))))\r
+ {\r
+ ERR("copy_from_user failed\n");\r
+ ret = -EFAULT;\r
+ break;\r
+ }\r
+ RGA_MSG_2_RGA2_MSG(&req_rga, &req);\r
+\r
+ ret = rga2_blit_sync(session, &req);\r
+ break;\r
+ case RGA_BLIT_ASYNC:\r
+ if (unlikely(copy_from_user(&req_rga, (struct rga_req*)arg, sizeof(struct rga_req))))\r
+ {\r
+ ERR("copy_from_user failed\n");\r
+ ret = -EFAULT;\r
+ break;\r
+ }\r
+\r
+ RGA_MSG_2_RGA2_MSG(&req_rga, &req);\r
+\r
+ if((atomic_read(&rga2_service.total_running) > 8))\r
+ {\r
+ ret = rga2_blit_sync(session, &req);\r
+ }\r
+ else\r
+ {\r
+ ret = rga2_blit_async(session, &req);\r
+ }\r
+ break;\r
+ case RGA2_BLIT_SYNC:\r
+ if (unlikely(copy_from_user(&req, (struct rga2_req*)arg, sizeof(struct rga2_req))))\r
+ {\r
+ ERR("copy_from_user failed\n");\r
+ ret = -EFAULT;\r
+ break;\r
+ }\r
+ ret = rga2_blit_sync(session, &req);\r
+ break;\r
+ case RGA2_BLIT_ASYNC:\r
+ if (unlikely(copy_from_user(&req, (struct rga2_req*)arg, sizeof(struct rga2_req))))\r
+ {\r
+ ERR("copy_from_user failed\n");\r
+ ret = -EFAULT;\r
+ break;\r
+ }\r
+\r
+ if((atomic_read(&rga2_service.total_running) > 16))\r
+ {\r
+ ret = rga2_blit_sync(session, &req);\r
+ }\r
+ else\r
+ {\r
+ ret = rga2_blit_async(session, &req);\r
+ }\r
+ break;\r
+ case RGA_FLUSH:\r
+ case RGA2_FLUSH:\r
+ ret = rga2_flush(session, arg);\r
+ break;\r
+ case RGA_GET_RESULT:\r
+ case RGA2_GET_RESULT:\r
+ ret = rga2_get_result(session, arg);\r
+ break;\r
+ case RGA_GET_VERSION:\r
+ case RGA2_GET_VERSION:\r
+ ret = copy_to_user((void *)arg, RGA2_VERSION, sizeof(RGA2_VERSION));\r
+ //ret = 0;\r
+ break;\r
+ default:\r
+ ERR("unknown ioctl cmd!\n");\r
+ ret = -EINVAL;\r
+ break;\r
+ }\r
+\r
+ mutex_unlock(&rga2_service.mutex);\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+long rga_ioctl_kernel(struct rga_req *req)\r
+{\r
+ int ret = 0;\r
+ rga2_session *session;\r
+ struct rga2_req req_rga2;\r
+\r
+ mutex_lock(&rga2_service.mutex);\r
+\r
+ session = &rga2_session_global;\r
+\r
+ if (NULL == session)\r
+ {\r
+ printk("%s [%d] rga thread session is null\n",__FUNCTION__,__LINE__);\r
+ mutex_unlock(&rga2_service.mutex);\r
+ return -EINVAL;\r
+ }\r
+\r
+ RGA_MSG_2_RGA2_MSG(req, &req_rga2);\r
+ ret = rga2_blit_sync(session, &req_rga2);\r
+\r
+ mutex_unlock(&rga2_service.mutex);\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+static int rga2_open(struct inode *inode, struct file *file)\r
+{\r
+ rga2_session *session = kzalloc(sizeof(rga2_session), GFP_KERNEL);\r
+ if (NULL == session) {\r
+ pr_err("unable to allocate memory for rga_session.");\r
+ return -ENOMEM;\r
+ }\r
+\r
+ session->pid = current->pid;\r
+ //printk(KERN_DEBUG "+");\r
+\r
+ INIT_LIST_HEAD(&session->waiting);\r
+ INIT_LIST_HEAD(&session->running);\r
+ INIT_LIST_HEAD(&session->list_session);\r
+ init_waitqueue_head(&session->wait);\r
+ mutex_lock(&rga2_service.lock);\r
+ list_add_tail(&session->list_session, &rga2_service.session);\r
+ mutex_unlock(&rga2_service.lock);\r
+ atomic_set(&session->task_running, 0);\r
+ atomic_set(&session->num_done, 0);\r
+\r
+ file->private_data = (void *)session;\r
+\r
+ //DBG("*** rga dev opened by pid %d *** \n", session->pid);\r
+ return nonseekable_open(inode, file);\r
+\r
+}\r
+\r
+static int rga2_release(struct inode *inode, struct file *file)\r
+{\r
+ int task_running;\r
+ rga2_session *session = (rga2_session *)file->private_data;\r
+ if (NULL == session)\r
+ return -EINVAL;\r
+ //printk(KERN_DEBUG "-");\r
+ task_running = atomic_read(&session->task_running);\r
+\r
+ if (task_running)\r
+ {\r
+ pr_err("rga2_service session %d still has %d task running when closing\n", session->pid, task_running);\r
+ msleep(100);\r
+ /*ͬ²½*/\r
+ }\r
+\r
+ wake_up(&session->wait);\r
+ mutex_lock(&rga2_service.lock);\r
+ list_del(&session->list_session);\r
+ rga2_service_session_clear(session);\r
+ kfree(session);\r
+ mutex_unlock(&rga2_service.lock);\r
+\r
+ //DBG("*** rga dev close ***\n");\r
+ return 0;\r
+}\r
+\r
+static irqreturn_t rga2_irq_thread(int irq, void *dev_id)\r
+{\r
+ mutex_lock(&rga2_service.lock);\r
+ if (rga2_service.enable) {\r
+ rga2_del_running_list();\r
+ rga2_try_set_reg();\r
+ }\r
+ mutex_unlock(&rga2_service.lock);\r
+\r
+ return IRQ_HANDLED;\r
+}\r
+\r
+static irqreturn_t rga2_irq(int irq, void *dev_id)\r
+{\r
+ /*clear INT */\r
+ rga2_write(rga2_read(RGA2_INT) | (0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7), RGA2_INT);\r
+\r
+ return IRQ_WAKE_THREAD;\r
+}\r
+\r
+struct file_operations rga2_fops = {\r
+ .owner = THIS_MODULE,\r
+ .open = rga2_open,\r
+ .release = rga2_release,\r
+ .unlocked_ioctl = rga_ioctl,\r
+};\r
+\r
+static struct miscdevice rga2_dev ={\r
+ .minor = RGA2_MAJOR,\r
+ .name = "rga",\r
+ .fops = &rga2_fops,\r
+};\r
+\r
+static int __devinit rga2_drv_probe(struct platform_device *pdev)\r
+{\r
+ struct rga2_drvdata_t *data;\r
+ int ret = 0;\r
+\r
+ INIT_LIST_HEAD(&rga2_service.waiting);\r
+ INIT_LIST_HEAD(&rga2_service.running);\r
+ INIT_LIST_HEAD(&rga2_service.done);\r
+ INIT_LIST_HEAD(&rga2_service.session);\r
+ mutex_init(&rga2_service.lock);\r
+ mutex_init(&rga2_service.mutex);\r
+ atomic_set(&rga2_service.total_running, 0);\r
+ atomic_set(&rga2_service.src_format_swt, 0);\r
+ rga2_service.last_prc_src_format = 1; /* default is yuv first*/\r
+ rga2_service.enable = false;\r
+\r
+ data = kzalloc(sizeof(struct rga2_drvdata_t), GFP_KERNEL);\r
+ if(NULL == data)\r
+ {\r
+ ERR("failed to allocate driver data.\n");\r
+ return -ENOMEM;\r
+ }\r
+\r
+ INIT_DELAYED_WORK(&data->power_off_work, rga2_power_off_work);\r
+ wake_lock_init(&data->wake_lock, WAKE_LOCK_SUSPEND, "rga");\r
+\r
+ data->pd_rga2 = clk_get(NULL, "pd_rga");\r
+ data->rga2 = clk_get(NULL, "rga");\r
+ data->aclk_rga2 = clk_get(NULL, "aclk_rga");\r
+ data->hclk_rga2 = clk_get(NULL, "hclk_rga");\r
+\r
+ /* map the memory */\r
+ if (!request_mem_region(RK32_RGA2_PHYS, RK32_RGA2_SIZE, "rga_io"))\r
+ {\r
+ pr_info("failed to reserve rga HW regs\n");\r
+ return -EBUSY;\r
+ }\r
+\r
+ data->rga_base = (void*)ioremap_nocache(RK32_RGA2_PHYS, RK32_RGA2_SIZE);\r
+ if (data->rga_base == NULL)\r
+ {\r
+ ERR("rga ioremap failed\n");\r
+ ret = -ENOENT;\r
+ goto err_ioremap;\r
+ }\r
+\r
+ /* get the IRQ */\r
+ data->irq = platform_get_irq(pdev, 0);\r
+ if (data->irq <= 0)\r
+ {\r
+ ERR("failed to get rga irq resource (%d).\n", data->irq);\r
+ ret = data->irq;\r
+ goto err_irq;\r
+ }\r
+\r
+ /* request the IRQ */\r
+ ret = request_threaded_irq(data->irq, rga2_irq, rga2_irq_thread, 0, "rga", pdev);\r
+ if (ret)\r
+ {\r
+ ERR("rga request_irq failed (%d).\n", ret);\r
+ goto err_irq;\r
+ }\r
+\r
+ platform_set_drvdata(pdev, data);\r
+ rga2_drvdata = data;\r
+\r
+ ret = misc_register(&rga2_dev);\r
+ if(ret)\r
+ {\r
+ ERR("cannot register miscdev (%d)\n", ret);\r
+ goto err_misc_register;\r
+ }\r
+\r
+ pr_info("Driver loaded succesfully\n");\r
+\r
+ return 0;\r
+\r
+err_misc_register:\r
+ free_irq(data->irq, pdev);\r
+err_irq:\r
+ iounmap(data->rga_base);\r
+err_ioremap:\r
+ wake_lock_destroy(&data->wake_lock);\r
+ kfree(data);\r
+\r
+ return ret;\r
+}\r
+\r
+static int rga2_drv_remove(struct platform_device *pdev)\r
+{\r
+ struct rga2_drvdata_t *data = platform_get_drvdata(pdev);\r
+ DBG("%s [%d]\n",__FUNCTION__,__LINE__);\r
+\r
+ wake_lock_destroy(&data->wake_lock);\r
+ misc_deregister(&(data->miscdev));\r
+ free_irq(data->irq, &data->miscdev);\r
+ iounmap((void __iomem *)(data->rga_base));\r
+\r
+ clk_put(data->pd_rga2);\r
+ clk_put(data->rga2);\r
+ clk_put(data->aclk_rga2);\r
+ clk_put(data->hclk_rga2);\r
+\r
+\r
+ kfree(data);\r
+ return 0;\r
+}\r
+\r
+static struct platform_driver rga2_driver = {\r
+ .probe = rga2_drv_probe,\r
+ .remove = __devexit_p(rga2_drv_remove),\r
+ .driver = {\r
+ .owner = THIS_MODULE,\r
+ .name = "rga",\r
+ },\r
+};\r
+\r
+\r
+void rga2_test_0(void);\r
+\r
+static int __init rga2_init(void)\r
+{\r
+ int ret;\r
+ uint32_t *buf_p;\r
+\r
+ /* malloc pre scale mid buf mmu table */\r
+ buf_p = kmalloc(1024*256, GFP_KERNEL);\r
+ rga2_mmu_buf.buf_virtual = buf_p;\r
+ rga2_mmu_buf.buf = (uint32_t *)virt_to_phys((void *)((uint32_t)buf_p));\r
+ rga2_mmu_buf.front = 0;\r
+ rga2_mmu_buf.back = 64*1024;\r
+ rga2_mmu_buf.size = 64*1024;\r
+\r
+ if ((ret = platform_driver_register(&rga2_driver)) != 0)\r
+ {\r
+ printk(KERN_ERR "Platform device register failed (%d).\n", ret);\r
+ return ret;\r
+ }\r
+\r
+ {\r
+ rga2_session_global.pid = 0x0000ffff;\r
+ INIT_LIST_HEAD(&rga2_session_global.waiting);\r
+ INIT_LIST_HEAD(&rga2_session_global.running);\r
+ INIT_LIST_HEAD(&rga2_session_global.list_session);\r
+ init_waitqueue_head(&rga2_session_global.wait);\r
+ //mutex_lock(&rga_service.lock);\r
+ list_add_tail(&rga2_session_global.list_session, &rga2_service.session);\r
+ //mutex_unlock(&rga_service.lock);\r
+ atomic_set(&rga2_session_global.task_running, 0);\r
+ atomic_set(&rga2_session_global.num_done, 0);\r
+ }\r
+\r
+ #if RGA2_TEST_CASE\r
+ rga2_test_0();\r
+ #endif\r
+\r
+ INFO("Module initialized.\n");\r
+\r
+ return 0;\r
+}\r
+\r
+static void __exit rga2_exit(void)\r
+{\r
+ rga2_power_off();\r
+\r
+ if (rga2_mmu_buf.buf_virtual)\r
+ kfree(rga2_mmu_buf.buf_virtual);\r
+\r
+ platform_driver_unregister(&rga2_driver);\r
+}\r
+\r
+\r
+#if RGA2_TEST_CASE\r
+\r
+extern struct fb_info * rk_get_fb(int fb_id);\r
+EXPORT_SYMBOL(rk_get_fb);\r
+\r
+extern void rk_direct_fb_show(struct fb_info * fbi);\r
+EXPORT_SYMBOL(rk_direct_fb_show);\r
+\r
+//unsigned int src_buf[1920*1080];\r
+//unsigned int dst_buf[1920*1080];\r
+//unsigned int tmp_buf[1920*1080 * 2];\r
+\r
+void rga2_test_0(void)\r
+{\r
+ struct rga2_req req;\r
+ rga2_session session;\r
+ unsigned int *src, *dst;\r
+ uint32_t i, j;\r
+ uint8_t *p;\r
+ uint8_t t;\r
+ uint32_t *dst0, *dst1, *dst2;\r
+\r
+ struct fb_info *fb;\r
+\r
+ session.pid = current->pid;\r
+ INIT_LIST_HEAD(&session.waiting);\r
+ INIT_LIST_HEAD(&session.running);\r
+ INIT_LIST_HEAD(&session.list_session);\r
+ init_waitqueue_head(&session.wait);\r
+ /* no need to protect */\r
+ list_add_tail(&session.list_session, &rga2_service.session);\r
+ atomic_set(&session.task_running, 0);\r
+ atomic_set(&session.num_done, 0);\r
+ //file->private_data = (void *)session;\r
+\r
+ fb = rk_get_fb(0);\r
+\r
+ memset(&req, 0, sizeof(struct rga2_req));\r
+ src = kmalloc(800*480*4, GFP_KERNEL);\r
+ dst = kmalloc(800*480*4, GFP_KERNEL);\r
+\r
+ memset(src, 0x80, 800*480*4);\r
+\r
+ dmac_flush_range(&src, &src[800*480*4]);\r
+ outer_flush_range(virt_to_phys(&src),virt_to_phys(&src[800*480*4]));\r
+\r
+\r
+ #if 0\r
+ memset(src_buf, 0x80, 800*480*4);\r
+ memset(dst_buf, 0xcc, 800*480*4);\r
+\r
+ dmac_flush_range(&dst_buf[0], &dst_buf[800*480]);\r
+ outer_flush_range(virt_to_phys(&dst_buf[0]),virt_to_phys(&dst_buf[800*480]));\r
+ #endif\r
+\r
+ dst0 = &dst;\r
+\r
+ i = j = 0;\r
+\r
+ printk("\n********************************\n");\r
+ printk("************ RGA2_TEST ************\n");\r
+ printk("********************************\n\n");\r
+\r
+ req.src.act_w = 320;\r
+ req.src.act_h = 240;\r
+\r
+ req.src.vir_w = 320;\r
+ req.src.vir_h = 240;\r
+ req.src.yrgb_addr = (uint32_t)virt_to_phys(src);\r
+ req.src.uv_addr = (uint32_t)(req.src.yrgb_addr + 800*480);\r
+ req.src.v_addr = (uint32_t)virt_to_phys(src);\r
+ req.src.format = RGA2_FORMAT_RGBA_8888;\r
+\r
+ req.dst.act_w = 320;\r
+ req.dst.act_h = 240;\r
+ req.dst.x_offset = 0;\r
+ req.dst.y_offset = 0;\r
+\r
+ req.dst.vir_w = 320;\r
+ req.dst.vir_h = 240;\r
+\r
+ req.dst.yrgb_addr = ((uint32_t)virt_to_phys(dst));\r
+ req.dst.format = RGA2_FORMAT_RGBA_8888;\r
+\r
+ //dst = dst0;\r
+\r
+ //req.render_mode = color_fill_mode;\r
+ //req.fg_color = 0x80ffffff;\r
+\r
+ req.rotate_mode = 1;\r
+ req.scale_bicu_mode = 2;\r
+\r
+ //req.alpha_rop_flag = 0;\r
+ //req.alpha_rop_mode = 0x19;\r
+ //req.PD_mode = 3;\r
+\r
+ req.rotate_mode = 0;\r
+\r
+ //req.mmu_info.mmu_flag = 0x21;\r
+ //req.mmu_info.mmu_en = 1;\r
+\r
+ //printk("src = %.8x\n", req.src.yrgb_addr);\r
+ //printk("src = %.8x\n", req.src.uv_addr);\r
+ //printk("dst = %.8x\n", req.dst.yrgb_addr);\r
+\r
+ rga2_blit_sync(&session, &req);\r
+\r
+ #if 0\r
+ fb->var.bits_per_pixel = 32;\r
+\r
+ fb->var.xres = 1280;\r
+ fb->var.yres = 800;\r
+\r
+ fb->var.red.length = 8;\r
+ fb->var.red.offset = 0;\r
+ fb->var.red.msb_right = 0;\r
+\r
+ fb->var.green.length = 8;\r
+ fb->var.green.offset = 8;\r
+ fb->var.green.msb_right = 0;\r
+\r
+ fb->var.blue.length = 8;\r
+\r
+ fb->var.blue.offset = 16;\r
+ fb->var.blue.msb_right = 0;\r
+\r
+ fb->var.transp.length = 8;\r
+ fb->var.transp.offset = 24;\r
+ fb->var.transp.msb_right = 0;\r
+\r
+ fb->var.nonstd &= (~0xff);\r
+ fb->var.nonstd |= 1;\r
+\r
+ fb->fix.smem_start = virt_to_phys(dst);\r
+\r
+ rk_direct_fb_show(fb);\r
+ #endif\r
+\r
+ if(src)\r
+ kfree(src);\r
+ if(dst)\r
+ kfree(dst);\r
+}\r
+\r
+#endif\r
+module_init(rga2_init);\r
+module_exit(rga2_exit);\r
+\r
+/* Module information */\r
+MODULE_AUTHOR("zsq@rock-chips.com");\r
+MODULE_DESCRIPTION("Driver for rga device");\r
+MODULE_LICENSE("GPL");\r
--- /dev/null
+\r
+\r
+#include <linux/version.h>\r
+#include <linux/init.h>\r
+#include <linux/module.h>\r
+#include <linux/fs.h>\r
+#include <linux/sched.h>\r
+#include <linux/signal.h>\r
+#include <linux/pagemap.h>\r
+#include <linux/seq_file.h>\r
+#include <linux/mm.h>\r
+#include <linux/mman.h>\r
+#include <linux/sched.h>\r
+#include <linux/slab.h>\r
+#include <linux/memory.h>\r
+#include <linux/dma-mapping.h>\r
+#include <asm/memory.h>\r
+#include <asm/atomic.h>\r
+#include <asm/cacheflush.h>\r
+#include "rga2_mmu_info.h"\r
+\r
+extern struct rga2_service_info rga2_service;\r
+extern struct rga2_mmu_buf_t rga2_mmu_buf;\r
+\r
+//extern int mmu_buff_temp[1024];\r
+\r
+#define KERNEL_SPACE_VALID 0xc0000000\r
+\r
+#define V7_VATOPA_SUCESS_MASK (0x1)\r
+#define V7_VATOPA_GET_PADDR(X) (X & 0xFFFFF000)\r
+#define V7_VATOPA_GET_INER(X) ((X>>4) & 7)\r
+#define V7_VATOPA_GET_OUTER(X) ((X>>2) & 3)\r
+#define V7_VATOPA_GET_SH(X) ((X>>7) & 1)\r
+#define V7_VATOPA_GET_NS(X) ((X>>9) & 1)\r
+#define V7_VATOPA_GET_SS(X) ((X>>1) & 1)\r
+\r
+#if 0\r
+static unsigned int armv7_va_to_pa(unsigned int v_addr)\r
+{\r
+ unsigned int p_addr;\r
+ __asm__ volatile ( "mcr p15, 0, %1, c7, c8, 0\n"\r
+ "isb\n"\r
+ "dsb\n"\r
+ "mrc p15, 0, %0, c7, c4, 0\n"\r
+ : "=r" (p_addr)\r
+ : "r" (v_addr)\r
+ : "cc");\r
+\r
+ if (p_addr & V7_VATOPA_SUCESS_MASK)\r
+ return 0xFFFFFFFF;\r
+ else\r
+ return (V7_VATOPA_GET_SS(p_addr) ? 0xFFFFFFFF : V7_VATOPA_GET_PADDR(p_addr));\r
+}\r
+#endif\r
+\r
+static int rga2_mmu_buf_get(struct rga2_mmu_buf_t *t, uint32_t size)\r
+{\r
+ mutex_lock(&rga2_service.lock);\r
+ t->front += size;\r
+ mutex_unlock(&rga2_service.lock);\r
+\r
+ return 0;\r
+}\r
+\r
+static int rga2_mmu_buf_get_try(struct rga2_mmu_buf_t *t, uint32_t size)\r
+{\r
+ mutex_lock(&rga2_service.lock);\r
+ if((t->back - t->front) > t->size) {\r
+ if(t->front + size > t->back - t->size)\r
+ return -1;\r
+ }\r
+ else {\r
+ if((t->front + size) > t->back)\r
+ return -1;\r
+\r
+ if(t->front + size > t->size) {\r
+ if (size > (t->back - t->size)) {\r
+ return -1;\r
+ }\r
+ t->front = 0;\r
+ }\r
+ }\r
+ mutex_unlock(&rga2_service.lock);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+static int rga2_mmu_buf_cal(struct rga2_mmu_buf_t *t, uint32_t size)\r
+{\r
+ if((t->front + size) > t->back) {\r
+ return -1;\r
+ }\r
+ else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+\r
+\r
+static int rga2_mem_size_cal(uint32_t Mem, uint32_t MemSize, uint32_t *StartAddr)\r
+{\r
+ uint32_t start, end;\r
+ uint32_t pageCount;\r
+\r
+ end = (Mem + (MemSize + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = Mem >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ *StartAddr = start;\r
+ return pageCount;\r
+}\r
+\r
+static int rga2_buf_size_cal(uint32_t yrgb_addr, uint32_t uv_addr, uint32_t v_addr,\r
+ int format, uint32_t w, uint32_t h, uint32_t *StartAddr )\r
+{\r
+ uint32_t size_yrgb = 0;\r
+ uint32_t size_uv = 0;\r
+ uint32_t size_v = 0;\r
+ uint32_t stride = 0;\r
+ uint32_t start, end;\r
+ uint32_t pageCount;\r
+\r
+ switch(format)\r
+ {\r
+ case RGA2_FORMAT_RGBA_8888 :\r
+ stride = (w * 4 + 3) & (~3);\r
+ size_yrgb = stride*h;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;\r
+ break;\r
+ case RGA2_FORMAT_RGBX_8888 :\r
+ stride = (w * 4 + 3) & (~3);\r
+ size_yrgb = stride*h;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;\r
+ break;\r
+ case RGA2_FORMAT_RGB_888 :\r
+ stride = (w * 3 + 3) & (~3);\r
+ size_yrgb = stride*h;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;\r
+ break;\r
+ case RGA2_FORMAT_BGRA_8888 :\r
+ size_yrgb = w*h*4;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;\r
+ break;\r
+ case RGA2_FORMAT_RGB_565 :\r
+ stride = (w*2 + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;\r
+ break;\r
+ case RGA2_FORMAT_RGBA_5551 :\r
+ stride = (w*2 + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;\r
+ break;\r
+ case RGA2_FORMAT_RGBA_4444 :\r
+ stride = (w*2 + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;\r
+ break;\r
+ case RGA2_FORMAT_BGR_888 :\r
+ stride = (w*3 + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;\r
+ break;\r
+\r
+ /* YUV FORMAT */\r
+ case RGA2_FORMAT_YCbCr_422_SP :\r
+ case RGA2_FORMAT_YCrCb_422_SP :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = stride * h;\r
+ start = MIN(yrgb_addr, uv_addr);\r
+\r
+ start >>= PAGE_SHIFT;\r
+ end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RGA2_FORMAT_YCbCr_422_P :\r
+ case RGA2_FORMAT_YCrCb_422_P :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = ((stride >> 1) * h);\r
+ size_v = ((stride >> 1) * h);\r
+ start = MIN(MIN(yrgb_addr, uv_addr), v_addr);\r
+ start = start >> PAGE_SHIFT;\r
+ end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RGA2_FORMAT_YCbCr_420_SP :\r
+ case RGA2_FORMAT_YCrCb_420_SP :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = (stride * (h >> 1));\r
+ start = MIN(yrgb_addr, uv_addr);\r
+ start >>= PAGE_SHIFT;\r
+ end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RGA2_FORMAT_YCbCr_420_P :\r
+ case RGA2_FORMAT_YCrCb_420_P :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = ((stride >> 1) * (h >> 1));\r
+ size_v = ((stride >> 1) * (h >> 1));\r
+ start = MIN(MIN(yrgb_addr, uv_addr), v_addr);\r
+ start >>= PAGE_SHIFT;\r
+ end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ #if 0\r
+ case RK_FORMAT_BPP1 :\r
+ break;\r
+ case RK_FORMAT_BPP2 :\r
+ break;\r
+ case RK_FORMAT_BPP4 :\r
+ break;\r
+ case RK_FORMAT_BPP8 :\r
+ break;\r
+ #endif\r
+ default :\r
+ pageCount = 0;\r
+ start = 0;\r
+ break;\r
+ }\r
+\r
+ *StartAddr = start;\r
+ return pageCount;\r
+}\r
+\r
+static int rga2_MapUserMemory(struct page **pages,\r
+ uint32_t *pageTable,\r
+ uint32_t Memory,\r
+ uint32_t pageCount)\r
+{\r
+ int32_t result;\r
+ uint32_t i;\r
+ uint32_t status;\r
+ uint32_t Address;\r
+ //uint32_t temp;\r
+\r
+ status = 0;\r
+ Address = 0;\r
+\r
+ do\r
+ {\r
+ down_read(¤t->mm->mmap_sem);\r
+ result = get_user_pages(current,\r
+ current->mm,\r
+ Memory << PAGE_SHIFT,\r
+ pageCount,\r
+ 1,\r
+ 0,\r
+ pages,\r
+ NULL\r
+ );\r
+ up_read(¤t->mm->mmap_sem);\r
+\r
+ #if 0\r
+ if(result <= 0 || result < pageCount)\r
+ {\r
+ status = 0;\r
+\r
+ for(i=0; i<pageCount; i++)\r
+ {\r
+ temp = armv7_va_to_pa((Memory + i) << PAGE_SHIFT);\r
+ if (temp == 0xffffffff)\r
+ {\r
+ printk("rga find mmu phy ddr error\n ");\r
+ status = RGA_OUT_OF_RESOURCES;\r
+ break;\r
+ }\r
+\r
+ pageTable[i] = temp;\r
+ }\r
+\r
+ return status;\r
+ }\r
+ #else\r
+ if(result <= 0 || result < pageCount)\r
+ {\r
+ struct vm_area_struct *vma;\r
+\r
+ for(i=0; i<pageCount; i++)\r
+ {\r
+ vma = find_vma(current->mm, (Memory + i) << PAGE_SHIFT);\r
+\r
+ if (vma)//&& (vma->vm_flags & VM_PFNMAP) )\r
+ {\r
+ #if 1\r
+ do\r
+ {\r
+ pte_t * pte;\r
+ spinlock_t * ptl;\r
+ unsigned long pfn;\r
+ pgd_t * pgd;\r
+ pud_t * pud;\r
+\r
+ pgd = pgd_offset(current->mm, (Memory + i) << PAGE_SHIFT);\r
+\r
+ if(pgd_val(*pgd) == 0)\r
+ {\r
+ //printk("rga pgd value is zero \n");\r
+ break;\r
+ }\r
+\r
+ pud = pud_offset(pgd, (Memory + i) << PAGE_SHIFT);\r
+ if (pud)\r
+ {\r
+ pmd_t * pmd = pmd_offset(pud, (Memory + i) << PAGE_SHIFT);\r
+ if (pmd)\r
+ {\r
+ pte = pte_offset_map_lock(current->mm, pmd, (Memory + i) << PAGE_SHIFT, &ptl);\r
+ if (!pte)\r
+ {\r
+ pte_unmap_unlock(pte, ptl);\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+\r
+ pfn = pte_pfn(*pte);\r
+ Address = ((pfn << PAGE_SHIFT) | (((unsigned long)((Memory + i) << PAGE_SHIFT)) & ~PAGE_MASK));\r
+ pte_unmap_unlock(pte, ptl);\r
+ }\r
+ while (0);\r
+\r
+ #else\r
+ do\r
+ {\r
+ pte_t * pte;\r
+ spinlock_t * ptl;\r
+ unsigned long pfn;\r
+ pgd_t * pgd;\r
+ pud_t * pud;\r
+ pmd_t * pmd;\r
+\r
+ pgd = pgd_offset(current->mm, (Memory + i) << PAGE_SHIFT);\r
+ pud = pud_offset(pgd, (Memory + i) << PAGE_SHIFT);\r
+ pmd = pmd_offset(pud, (Memory + i) << PAGE_SHIFT);\r
+ pte = pte_offset_map_lock(current->mm, pmd, (Memory + i) << PAGE_SHIFT, &ptl);\r
+\r
+ pfn = pte_pfn(*pte);\r
+ Address = ((pfn << PAGE_SHIFT) | (((unsigned long)((Memory + i) << PAGE_SHIFT)) & ~PAGE_MASK));\r
+ pte_unmap_unlock(pte, ptl);\r
+ }\r
+ while (0);\r
+ #endif\r
+\r
+ pageTable[i] = Address;\r
+ }\r
+ else\r
+ {\r
+ status = RGA2_OUT_OF_RESOURCES;\r
+ break;\r
+ }\r
+ }\r
+\r
+ return status;\r
+ }\r
+ #endif\r
+\r
+ /* Fill the page table. */\r
+ for(i=0; i<pageCount; i++)\r
+ {\r
+ /* Get the physical address from page struct. */\r
+ pageTable[i] = page_to_phys(pages[i]);\r
+ }\r
+\r
+ return 0;\r
+ }\r
+ while(0);\r
+\r
+ return status;\r
+}\r
+\r
+static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)\r
+{\r
+ int Src0MemSize, DstMemSize, Src1MemSize;\r
+ uint32_t Src0Start, Src1Start, DstStart;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base, *MMU_Base_phys;\r
+ int ret;\r
+ int status;\r
+ uint32_t uv_size, v_size;\r
+\r
+ struct page **pages = NULL;\r
+\r
+ MMU_Base = NULL;\r
+\r
+ Src0MemSize = 0;\r
+ Src1MemSize = 0;\r
+ DstMemSize = 0;\r
+\r
+ do\r
+ {\r
+ /* cal src0 buf mmu info */\r
+ if(req->mmu_info.src0_mmu_flag & 1) {\r
+ Src0MemSize = rga2_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,\r
+ req->src.format, req->src.vir_w,\r
+ (req->src.vir_h),\r
+ &Src0Start);\r
+ if (Src0MemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+ }\r
+\r
+ /* cal src1 buf mmu info */\r
+ if(req->mmu_info.src1_mmu_flag & 1) {\r
+ Src1MemSize = rga2_buf_size_cal(req->src1.yrgb_addr, req->src1.uv_addr, req->src1.v_addr,\r
+ req->src1.format, req->src1.vir_w,\r
+ (req->src1.vir_h),\r
+ &Src1Start);\r
+ Src0MemSize = (Src0MemSize + 3) & (~3);\r
+ if (Src1MemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+ }\r
+\r
+\r
+ /* cal dst buf mmu info */\r
+ if(req->mmu_info.dst_mmu_flag & 1) {\r
+ DstMemSize = rga2_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+ }\r
+\r
+ /* Cal out the needed mem size */\r
+ AllSize = ((Src0MemSize+3)&(~3)) + ((Src1MemSize+3)&(~3)) + ((DstMemSize+3)&(~3));\r
+\r
+ pages = kzalloc((AllSize)* sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed\n");\r
+ status = RGA2_MALLOC_ERROR;\r
+ break;\r
+ }\r
+\r
+ if (rga2_mmu_buf_get_try(&rga2_mmu_buf, AllSize)) {\r
+ pr_err("RGA2 Get MMU mem failed\n");\r
+ status = RGA2_MALLOC_ERROR;\r
+ break;\r
+ }\r
+\r
+ mutex_lock(&rga2_service.lock);\r
+ MMU_Base = rga2_mmu_buf.buf_virtual + (rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));\r
+ MMU_Base_phys = rga2_mmu_buf.buf + (rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));\r
+ mutex_unlock(&rga2_service.lock);\r
+\r
+ if(Src0MemSize) {\r
+ ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0], Src0Start, Src0MemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga2 map src0 memory failed\n");\r
+ status = ret;\r
+ break;\r
+ }\r
+\r
+ /* change the buf address in req struct */\r
+ req->mmu_info.src0_base_addr = (((uint32_t)MMU_Base_phys));\r
+ uv_size = (req->src.uv_addr - (Src0Start << PAGE_SHIFT)) >> PAGE_SHIFT;\r
+ v_size = (req->src.v_addr - (Src0Start << PAGE_SHIFT)) >> PAGE_SHIFT;\r
+\r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));\r
+ req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (uv_size << PAGE_SHIFT);\r
+ req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (v_size << PAGE_SHIFT);\r
+ }\r
+\r
+ Src0MemSize = (Src0MemSize + 3) & (~3);\r
+\r
+ if(Src1MemSize) {\r
+ ret = rga2_MapUserMemory(&pages[0], MMU_Base + Src0MemSize, Src1Start, Src1MemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga2 map src1 memory failed\n");\r
+ status = ret;\r
+ break;\r
+ }\r
+\r
+ /* change the buf address in req struct */\r
+ req->mmu_info.src1_base_addr = ((uint32_t)(MMU_Base_phys + Src0MemSize));\r
+ req->src1.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (Src1MemSize << PAGE_SHIFT);\r
+ }\r
+\r
+ Src1MemSize = (Src1MemSize + 3) & (~3);\r
+\r
+ if(DstMemSize) {\r
+ ret = rga2_MapUserMemory(&pages[0], MMU_Base + Src0MemSize + Src1MemSize, DstStart, DstMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga2 map dst memory failed\n");\r
+ status = ret;\r
+ break;\r
+ }\r
+\r
+ /* change the buf address in req struct */\r
+ req->mmu_info.dst_base_addr = ((uint32_t)(MMU_Base_phys + Src0MemSize + Src1MemSize));\r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((Src0MemSize + Src1MemSize) << PAGE_SHIFT);\r
+ uv_size = (req->dst.uv_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;\r
+ v_size = (req->dst.v_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;\r
+ req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) | ((Src0MemSize + Src1MemSize + uv_size) << PAGE_SHIFT);\r
+ req->dst.v_addr = (req->dst.v_addr & (~PAGE_MASK)) | ((Src0MemSize + Src1MemSize + v_size) << PAGE_SHIFT);\r
+ }\r
+\r
+ /* flush data to DDR */\r
+ dmac_flush_range(MMU_Base, (MMU_Base + AllSize));\r
+ outer_flush_range(virt_to_phys(MMU_Base),virt_to_phys(MMU_Base + AllSize));\r
+\r
+ rga2_mmu_buf_get(&rga2_mmu_buf, AllSize);\r
+ reg->MMU_len = AllSize;\r
+\r
+ status = 0;\r
+\r
+ /* Free the page table */\r
+ if (pages != NULL) {\r
+ kfree(pages);\r
+ }\r
+\r
+ return status;\r
+ }\r
+ while(0);\r
+\r
+\r
+ /* Free the page table */\r
+ if (pages != NULL) {\r
+ kfree(pages);\r
+ }\r
+\r
+ /* Free MMU table */\r
+ if(MMU_Base != NULL) {\r
+ kfree(MMU_Base);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_req *req)\r
+{\r
+ int SrcMemSize, DstMemSize, CMDMemSize;\r
+ uint32_t SrcStart, DstStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base = NULL;\r
+ uint32_t *MMU_p;\r
+ int ret, status;\r
+ uint32_t stride;\r
+\r
+ uint8_t shift;\r
+ uint16_t sw, byte_num;\r
+\r
+ shift = 3 - (req->palette_mode & 3);\r
+ sw = req->src.vir_w;\r
+ byte_num = sw >> shift;\r
+ stride = (byte_num + 3) & (~3);\r
+\r
+ do\r
+ {\r
+\r
+ SrcMemSize = rga2_mem_size_cal(req->src.yrgb_addr, stride, &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+\r
+ DstMemSize = rga2_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+\r
+ CMDMemSize = rga2_mem_size_cal((uint32_t)rga2_service.cmd_buff, RGA2_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+\r
+ AllSize = SrcMemSize + DstMemSize + CMDMemSize;\r
+\r
+ pages = kzalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed\n");\r
+ return -EINVAL;\r
+ }\r
+\r
+ MMU_Base = kzalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(MMU_Base == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed\n");\r
+ break;\r
+ }\r
+\r
+ /* map CMD addr */\r
+ for(i=0; i<CMDMemSize; i++)\r
+ {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i)<<PAGE_SHIFT));\r
+ }\r
+\r
+ /* map src addr */\r
+ if (req->src.yrgb_addr < KERNEL_SPACE_VALID)\r
+ {\r
+ ret = rga2_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0)\r
+ {\r
+ pr_err("rga map src memory failed\n");\r
+ status = ret;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ MMU_p = MMU_Base + CMDMemSize;\r
+\r
+ for(i=0; i<SrcMemSize; i++)\r
+ {\r
+ MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));\r
+ }\r
+ }\r
+\r
+ /* map dst addr */\r
+ if (req->src.yrgb_addr < KERNEL_SPACE_VALID)\r
+ {\r
+ ret = rga2_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);\r
+ if (ret < 0)\r
+ {\r
+ pr_err("rga map dst memory failed\n");\r
+ status = ret;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ MMU_p = MMU_Base + CMDMemSize + SrcMemSize;\r
+\r
+ for(i=0; i<DstMemSize; i++)\r
+ {\r
+ MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((DstStart + i) << PAGE_SHIFT));\r
+ }\r
+ }\r
+\r
+\r
+ /* zsq\r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU\r
+ */\r
+ req->mmu_info.src0_base_addr = (virt_to_phys(MMU_Base)>>2);\r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);\r
+\r
+\r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ /* flush data to DDR */\r
+ dmac_flush_range(MMU_Base, (MMU_Base + AllSize + 1));\r
+ outer_flush_range(virt_to_phys(MMU_Base),virt_to_phys(MMU_Base + AllSize + 1));\r
+\r
+ /* Free the page table */\r
+ if (pages != NULL) {\r
+ kfree(pages);\r
+ }\r
+\r
+ return status;\r
+\r
+ }\r
+ while(0);\r
+\r
+ /* Free the page table */\r
+ if (pages != NULL) {\r
+ kfree(pages);\r
+ }\r
+\r
+ /* Free mmu table */\r
+ if (MMU_Base != NULL) {\r
+ kfree(MMU_Base);\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static int rga2_mmu_info_color_fill_mode(struct rga2_reg *reg, struct rga2_req *req)\r
+{\r
+ int DstMemSize;\r
+ uint32_t DstStart;\r
+ struct page **pages = NULL;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base, *MMU_Base_phys;\r
+ int ret;\r
+ int status;\r
+\r
+ MMU_Base = NULL;\r
+\r
+ do\r
+ {\r
+ if(req->mmu_info.dst_mmu_flag & 1) {\r
+ DstMemSize = rga2_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+ }\r
+\r
+ AllSize = (DstMemSize + 3) & (~3);\r
+\r
+ pages = kzalloc((AllSize)* sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA2 MMU malloc pages mem failed\n");\r
+ status = RGA2_MALLOC_ERROR;\r
+ break;\r
+ }\r
+\r
+ if(rga2_mmu_buf_get_try(&rga2_mmu_buf, AllSize)) {\r
+ pr_err("RGA2 Get MMU mem failed\n");\r
+ status = RGA2_MALLOC_ERROR;\r
+ break;\r
+ }\r
+\r
+ mutex_lock(&rga2_service.lock);\r
+ MMU_Base_phys = rga2_mmu_buf.buf + (rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));\r
+ MMU_Base = rga2_mmu_buf.buf_virtual + (rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));\r
+ mutex_unlock(&rga2_service.lock);\r
+\r
+ if (DstMemSize)\r
+ {\r
+ ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0], DstStart, DstMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga2 map dst memory failed\n");\r
+ status = ret;\r
+ break;\r
+ }\r
+\r
+ /* change the buf address in req struct */\r
+ req->mmu_info.src0_base_addr = (((uint32_t)MMU_Base_phys)>>4);\r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK));\r
+ }\r
+\r
+ /* flush data to DDR */\r
+ dmac_flush_range(MMU_Base, (MMU_Base + AllSize + 1));\r
+ outer_flush_range(virt_to_phys(MMU_Base),virt_to_phys(MMU_Base + AllSize + 1));\r
+\r
+ rga2_mmu_buf_get_try(&rga2_mmu_buf, AllSize);\r
+\r
+ /* Free the page table */\r
+ if (pages != NULL)\r
+ kfree(pages);\r
+\r
+ return 0;\r
+ }\r
+ while(0);\r
+\r
+ if (pages != NULL)\r
+ kfree(pages);\r
+\r
+ if (MMU_Base != NULL)\r
+ kfree(MMU_Base);\r
+\r
+ return status;\r
+}\r
+\r
+\r
+static int rga2_mmu_info_update_palette_table_mode(struct rga2_reg *reg, struct rga2_req *req)\r
+{\r
+ int SrcMemSize, CMDMemSize;\r
+ uint32_t SrcStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base, *MMU_p;\r
+ int ret, status;\r
+\r
+ MMU_Base = NULL;\r
+\r
+ do\r
+ {\r
+ /* cal src buf mmu info */\r
+ SrcMemSize = rga2_mem_size_cal(req->src.yrgb_addr, req->src.vir_w * req->src.vir_h, &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+\r
+ /* cal cmd buf mmu info */\r
+ CMDMemSize = rga2_mem_size_cal((uint32_t)rga2_service.cmd_buff, RGA2_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+\r
+ AllSize = SrcMemSize + CMDMemSize;\r
+\r
+ pages = kzalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed\n");\r
+ status = RGA2_MALLOC_ERROR;\r
+ break;\r
+ }\r
+\r
+ MMU_Base = kzalloc((AllSize + 1)* sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed\n");\r
+ status = RGA2_MALLOC_ERROR;\r
+ break;\r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));\r
+ }\r
+\r
+ if (req->src.yrgb_addr < KERNEL_SPACE_VALID)\r
+ {\r
+ ret = rga2_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed\n");\r
+ return -EINVAL;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ MMU_p = MMU_Base + CMDMemSize;\r
+\r
+ for(i=0; i<SrcMemSize; i++)\r
+ {\r
+ MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));\r
+ }\r
+ }\r
+\r
+ /* zsq\r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU\r
+ */\r
+ req->mmu_info.src0_base_addr = (virt_to_phys(MMU_Base) >> 2);\r
+\r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+\r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ /* flush data to DDR */\r
+ dmac_flush_range(MMU_Base, (MMU_Base + AllSize));\r
+ outer_flush_range(virt_to_phys(MMU_Base),virt_to_phys(MMU_Base + AllSize));\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ }\r
+\r
+ return 0;\r
+ }\r
+ while(0);\r
+\r
+ if (pages != NULL)\r
+ kfree(pages);\r
+\r
+ if (MMU_Base != NULL)\r
+ kfree(MMU_Base);\r
+\r
+ return status;\r
+}\r
+\r
+static int rga2_mmu_info_update_patten_buff_mode(struct rga2_reg *reg, struct rga2_req *req)\r
+{\r
+ int SrcMemSize, CMDMemSize;\r
+ uint32_t SrcStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base, *MMU_p;\r
+ int ret, status;\r
+\r
+ MMU_Base = MMU_p = 0;\r
+\r
+ do\r
+ {\r
+\r
+ /* cal src buf mmu info */\r
+ SrcMemSize = rga2_mem_size_cal(req->pat.yrgb_addr, req->pat.act_w * req->pat.act_h * 4, &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+\r
+ /* cal cmd buf mmu info */\r
+ CMDMemSize = rga2_mem_size_cal((uint32_t)rga2_service.cmd_buff, RGA2_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL;\r
+ }\r
+\r
+ AllSize = SrcMemSize + CMDMemSize;\r
+\r
+ pages = kzalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed\n");\r
+ status = RGA2_MALLOC_ERROR;\r
+ break;\r
+ }\r
+\r
+ MMU_Base = kzalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed\n");\r
+ status = RGA2_MALLOC_ERROR;\r
+ break;\r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));\r
+ }\r
+\r
+ if (req->src.yrgb_addr < KERNEL_SPACE_VALID)\r
+ {\r
+ ret = rga2_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed\n");\r
+ status = ret;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ MMU_p = MMU_Base + CMDMemSize;\r
+\r
+ for(i=0; i<SrcMemSize; i++)\r
+ {\r
+ MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));\r
+ }\r
+ }\r
+\r
+ /* zsq\r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU\r
+ */\r
+ req->mmu_info.src0_base_addr = (virt_to_phys(MMU_Base) >> 2);\r
+\r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+\r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ /* flush data to DDR */\r
+ dmac_flush_range(MMU_Base, (MMU_Base + AllSize));\r
+ outer_flush_range(virt_to_phys(MMU_Base),virt_to_phys(MMU_Base + AllSize));\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ }\r
+\r
+ return 0;\r
+\r
+ }\r
+ while(0);\r
+\r
+ if (pages != NULL)\r
+ kfree(pages);\r
+\r
+ if (MMU_Base != NULL)\r
+ kfree(MMU_Base);\r
+\r
+ return status;\r
+}\r
+\r
+int rga2_set_mmu_info(struct rga2_reg *reg, struct rga2_req *req)\r
+{\r
+ int ret;\r
+\r
+ switch (req->render_mode) {\r
+ case bitblt_mode :\r
+ ret = rga2_mmu_info_BitBlt_mode(reg, req);\r
+ break;\r
+ case color_palette_mode :\r
+ ret = rga2_mmu_info_color_palette_mode(reg, req);\r
+ break;\r
+ case color_fill_mode :\r
+ ret = rga2_mmu_info_color_fill_mode(reg, req);\r
+ break;\r
+ case update_palette_table_mode :\r
+ ret = rga2_mmu_info_update_palette_table_mode(reg, req);\r
+ break;\r
+ case update_patten_buff_mode :\r
+ ret = rga2_mmu_info_update_patten_buff_mode(reg, req);\r
+ break;\r
+ default :\r
+ ret = -1;\r
+ break;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
--- /dev/null
+#ifndef __RGA_MMU_INFO_H__\r
+#define __RGA_MMU_INFO_H__\r
+\r
+#include "rga2.h"\r
+\r
+#ifndef MIN\r
+#define MIN(X, Y) ((X)<(Y)?(X):(Y))\r
+#endif\r
+\r
+#ifndef MAX\r
+#define MAX(X, Y) ((X)>(Y)?(X):(Y))\r
+#endif\r
+\r
+\r
+int rga2_set_mmu_info(struct rga2_reg *reg, struct rga2_req *req);\r
+\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+\r
+//#include <linux/kernel.h>\r
+#include <linux/memory.h>\r
+#include <linux/kernel.h>\r
+#include <linux/init.h>\r
+#include <linux/module.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/sched.h>\r
+#include <linux/mutex.h>\r
+#include <linux/err.h>\r
+#include <linux/clk.h>\r
+#include <asm/delay.h>\r
+#include <linux/dma-mapping.h>\r
+#include <linux/delay.h>\r
+#include <asm/io.h>\r
+#include <linux/irq.h>\r
+#include <linux/interrupt.h>\r
+#include <mach/io.h>\r
+#include <mach/irqs.h>\r
+#include <linux/fs.h>\r
+#include <asm/uaccess.h>\r
+#include <linux/miscdevice.h>\r
+#include <linux/poll.h>\r
+#include <linux/delay.h>\r
+#include <linux/wait.h>\r
+#include <linux/syscalls.h>\r
+#include <linux/timer.h>\r
+#include <linux/time.h>\r
+#include <asm/cacheflush.h>\r
+#include <linux/slab.h>\r
+#include <linux/fb.h>\r
+#include <linux/wakelock.h>\r
+\r
+#include "rga2_reg_info.h"\r
+#include "rga2_rop.h"\r
+#include "rga2.h"\r
+\r
+\r
+void\r
+RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_SRC_INFO;\r
+ RK_U32 *bRGA_SRC_X_FACTOR;\r
+ RK_U32 *bRGA_SRC_Y_FACTOR;\r
+ RK_U32 sw, sh;\r
+ RK_U32 dw, dh;\r
+ RK_U32 param_x, param_y;\r
+ RK_U8 x_flag, y_flag;\r
+\r
+ RK_U32 reg;\r
+\r
+ bRGA_SRC_INFO = (RK_U32 *)(base + RGA2_SRC_INFO_OFFSET);\r
+ reg = *bRGA_SRC_INFO;\r
+\r
+ bRGA_SRC_X_FACTOR = (RK_U32 *)(base + RGA2_SRC_X_FACTOR_OFFSET);\r
+ bRGA_SRC_Y_FACTOR = (RK_U32 *)(base + RGA2_SRC_Y_FACTOR_OFFSET);\r
+\r
+ x_flag = y_flag = 0;\r
+\r
+ if(((msg->rotate_mode & 0x3) == 1) || ((msg->rotate_mode & 0x3) == 3))\r
+ {\r
+ dw = msg->dst.act_h;\r
+ dh = msg->dst.act_w;\r
+ }\r
+ else\r
+ {\r
+ dw = msg->dst.act_w;\r
+ dh = msg->dst.act_h;\r
+ }\r
+\r
+ sw = msg->src.act_w;\r
+ sh = msg->src.act_h;\r
+\r
+ if (sw > dw)\r
+ {\r
+ x_flag = 1;\r
+ #if SCALE_DOWN_LARGE\r
+ param_x = ((dw) << 16) / (sw);\r
+ #else\r
+ param_x = ((dw) << 16) / (sw);\r
+ #endif\r
+ *bRGA_SRC_X_FACTOR |= ((param_x & 0xffff) << 0 );\r
+ }\r
+ else if (sw < dw)\r
+ {\r
+ x_flag = 2;\r
+ #if 1//SCALE_MINUS1\r
+ param_x = ((sw - 1) << 16) / (dw - 1);\r
+ #else\r
+ param_x = ((sw) << 16) / (dw);\r
+ #endif\r
+ *bRGA_SRC_X_FACTOR |= ((param_x & 0xffff) << 16);\r
+ }\r
+ else\r
+ {\r
+ *bRGA_SRC_X_FACTOR = 0;//((1 << 14) << 16) | (1 << 14);\r
+ }\r
+\r
+ if (sh > dh)\r
+ {\r
+ y_flag = 1;\r
+ #if SCALE_DOWN_LARGE\r
+ param_y = ((dh) << 16) / (sh);\r
+ #else\r
+ param_y = ((dh) << 16) / (sh);\r
+ #endif\r
+ *bRGA_SRC_Y_FACTOR |= ((param_y & 0xffff) << 0 );\r
+ }\r
+ else if (sh < dh)\r
+ {\r
+ y_flag = 2;\r
+ #if 1//SCALE_MINUS1\r
+ param_y = ((sh - 1) << 16) / (dh - 1);\r
+ #else\r
+ param_y = ((sh) << 16) / (dh);\r
+ #endif\r
+ *bRGA_SRC_Y_FACTOR |= ((param_y & 0xffff) << 16);\r
+ }\r
+ else\r
+ {\r
+ *bRGA_SRC_Y_FACTOR = 0;//((1 << 14) << 16) | (1 << 14);\r
+ }\r
+\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE(x_flag)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(y_flag)));\r
+}\r
+\r
+void\r
+RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_MODE_CTL;\r
+ RK_U32 reg = 0;\r
+ RK_U32 render_mode = msg->render_mode;\r
+\r
+ bRGA_MODE_CTL = (u32 *)(base + RGA2_MODE_CTRL_OFFSET);\r
+\r
+ if(msg->render_mode == 4)\r
+ {\r
+ render_mode = 3;\r
+ }\r
+\r
+ reg = ((reg & (~m_RGA2_MODE_CTRL_SW_RENDER_MODE)) | (s_RGA2_MODE_CTRL_SW_RENDER_MODE(render_mode)));\r
+ reg = ((reg & (~m_RGA2_MODE_CTRL_SW_BITBLT_MODE)) | (s_RGA2_MODE_CTRL_SW_BITBLT_MODE(msg->bitblt_mode)));\r
+ reg = ((reg & (~m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT)) | (s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(msg->color_fill_mode)));\r
+ reg = ((reg & (~m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET)) | (s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(msg->alpha_zero_key)));\r
+ reg = ((reg & (~m_RGA2_MODE_CTRL_SW_GRADIENT_SAT)) | (s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(msg->alpha_rop_flag >> 7)));\r
+ reg = ((reg & (~m_RGA2_MODE_CTRL_SW_INTR_CF_E)) | (s_RGA2_MODE_CTRL_SW_INTR_CF_E(msg->CMD_fin_int_enable)));\r
+\r
+ *bRGA_MODE_CTL = reg;\r
+}\r
+\r
+void\r
+RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_SRC_INFO;\r
+ RK_U32 *bRGA_SRC_BASE0, *bRGA_SRC_BASE1, *bRGA_SRC_BASE2;\r
+ RK_U32 *bRGA_SRC_VIR_INFO;\r
+ RK_U32 *bRGA_SRC_ACT_INFO;\r
+ RK_U32 *bRGA_MASK_ADDR;\r
+ RK_U32 *bRGA_SRC_TR_COLOR0, *bRGA_SRC_TR_COLOR1;\r
+\r
+ RK_U32 reg = 0;\r
+ RK_U8 src0_format = 0;\r
+\r
+ RK_U8 src0_rb_swp = 0;\r
+ RK_U8 src0_rgb_pack = 0;\r
+\r
+ RK_U8 src0_cbcr_swp = 0;\r
+ RK_U8 pixel_width = 1;\r
+ RK_U32 stride = 0;\r
+ RK_U32 uv_stride = 0;\r
+ RK_U32 mask_stride = 0;\r
+ RK_U32 ydiv = 1, xdiv = 2;\r
+\r
+ RK_U32 sw, sh;\r
+ RK_U32 dw, dh;\r
+ RK_U8 rotate_mode;\r
+ RK_U8 scale_w_flag, scale_h_flag;\r
+\r
+ bRGA_SRC_INFO = (RK_U32 *)(base + RGA2_SRC_INFO_OFFSET);\r
+\r
+ bRGA_SRC_BASE0 = (RK_U32 *)(base + RGA2_SRC_BASE0_OFFSET);\r
+ bRGA_SRC_BASE1 = (RK_U32 *)(base + RGA2_SRC_BASE1_OFFSET);\r
+ bRGA_SRC_BASE2 = (RK_U32 *)(base + RGA2_SRC_BASE2_OFFSET);\r
+\r
+ bRGA_SRC_VIR_INFO = (RK_U32 *)(base + RGA2_SRC_VIR_INFO_OFFSET);\r
+ bRGA_SRC_ACT_INFO = (RK_U32 *)(base + RGA2_SRC_ACT_INFO_OFFSET);\r
+\r
+ bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);\r
+\r
+ bRGA_SRC_TR_COLOR0 = (RK_U32 *)(base + RGA2_SRC_TR_COLOR0_OFFSET);\r
+ bRGA_SRC_TR_COLOR1 = (RK_U32 *)(base + RGA2_SRC_TR_COLOR1_OFFSET);\r
+\r
+ {\r
+ rotate_mode = msg->rotate_mode & 0x3;\r
+\r
+ sw = msg->src.act_w;\r
+ sh = msg->src.act_h;\r
+\r
+ if((rotate_mode == 1) | (rotate_mode == 3))\r
+ {\r
+ dw = msg->dst.act_h;\r
+ dh = msg->dst.act_w;\r
+ }\r
+ else\r
+ {\r
+ dw = msg->dst.act_w;\r
+ dh = msg->dst.act_h;\r
+ }\r
+\r
+ if(sw > dw)\r
+ scale_w_flag = 1;\r
+ else if (sw < dw)\r
+ scale_w_flag = 2;\r
+ else {\r
+ scale_w_flag = 0;\r
+ if(msg->rotate_mode >> 6)\r
+ scale_w_flag = 3;\r
+ }\r
+\r
+ if(sh > dh)\r
+ scale_h_flag = 1;\r
+ else if (sh < dh)\r
+ scale_h_flag = 2;\r
+ else\r
+ {\r
+ scale_h_flag = 0;\r
+ if(msg->rotate_mode >> 6)\r
+ scale_h_flag = 3;\r
+ }\r
+ }\r
+\r
+ switch (msg->src.format)\r
+ {\r
+ case RGA2_FORMAT_RGBA_8888 : src0_format = 0x0; pixel_width = 4; break;\r
+ case RGA2_FORMAT_BGRA_8888 : src0_format = 0x0; src0_rb_swp = 0x1; pixel_width = 4; break;\r
+ case RGA2_FORMAT_RGBX_8888 : src0_format = 0x1; pixel_width = 4; msg->src_trans_mode &= 0x07; break;\r
+ case RGA2_FORMAT_BGRX_8888 : src0_format = 0x1; src0_rb_swp = 0x1; pixel_width = 4; msg->src_trans_mode &= 0x07; break;\r
+ case RGA2_FORMAT_RGB_888 : src0_format = 0x2; src0_rgb_pack = 1; pixel_width = 3; msg->src_trans_mode &= 0x07; break;\r
+ case RGA2_FORMAT_BGR_888 : src0_format = 0x2; src0_rgb_pack = 1; src0_rb_swp = 1; pixel_width = 3; msg->src_trans_mode &= 0x07; break;\r
+ case RGA2_FORMAT_RGB_565 : src0_format = 0x4; pixel_width = 2; msg->src_trans_mode &= 0x07; src0_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_RGBA_5551 : src0_format = 0x5; pixel_width = 2; src0_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_RGBA_4444 : src0_format = 0x6; pixel_width = 2; src0_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_BGR_565 : src0_format = 0x4; pixel_width = 2; msg->src_trans_mode &= 0x07; break;\r
+ case RGA2_FORMAT_BGRA_5551 : src0_format = 0x5; pixel_width = 2; break;\r
+ case RGA2_FORMAT_BGRA_4444 : src0_format = 0x6; pixel_width = 2; break;\r
+\r
+ case RGA2_FORMAT_YCbCr_422_SP : src0_format = 0x8; xdiv = 1; ydiv = 1; break;\r
+ case RGA2_FORMAT_YCbCr_422_P : src0_format = 0x9; xdiv = 2; ydiv = 1; break;\r
+ case RGA2_FORMAT_YCbCr_420_SP : src0_format = 0xa; xdiv = 1; ydiv = 2; break;\r
+ case RGA2_FORMAT_YCbCr_420_P : src0_format = 0xb; xdiv = 2; ydiv = 2; break;\r
+ case RGA2_FORMAT_YCrCb_422_SP : src0_format = 0x8; xdiv = 1; ydiv = 1; src0_cbcr_swp = 1; break;\r
+ case RGA2_FORMAT_YCrCb_422_P : src0_format = 0x9; xdiv = 2; ydiv = 1; src0_cbcr_swp = 1; break;\r
+ case RGA2_FORMAT_YCrCb_420_SP : src0_format = 0xa; xdiv = 1; ydiv = 2; src0_cbcr_swp = 1; break;\r
+ case RGA2_FORMAT_YCrCb_420_P : src0_format = 0xb; xdiv = 2; ydiv = 2; src0_cbcr_swp = 1; break;\r
+ };\r
+\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) | (s_RGA2_SRC_INFO_SW_SRC_FMT(src0_format)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(src0_rb_swp)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(msg->alpha_swp)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(src0_cbcr_swp)));\r
+ if(msg->src.format <= RGA2_FORMAT_BGRA_4444)\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(0)));\r
+ else\r
+ if(msg->dst.format >= RGA2_FORMAT_YCbCr_422_SP)\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(0)));\r
+ else\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(msg->yuv2rgb_mode)));\r
+\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(msg->rotate_mode & 0x3)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE((msg->rotate_mode >> 4) & 0x3)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE((scale_w_flag))));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE((scale_h_flag))));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER)) | (s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER((msg->scale_bicu_mode))));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(msg->src_trans_mode)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E)) | (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(msg->src_trans_mode >> 1)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E)) | (s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E((msg->alpha_rop_flag >> 4) & 0x1)));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL)) | (s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL((msg->scale_bicu_mode>>4))));\r
+ RGA2_reg_get_param(base, msg);\r
+\r
+ stride = (((msg->src.vir_w * pixel_width) + 3) & ~3) >> 2;\r
+\r
+ uv_stride = ((msg->src.vir_w / xdiv + 3) & ~3);\r
+\r
+ *bRGA_SRC_BASE0 = (RK_U32)(msg->src.yrgb_addr + msg->src.y_offset * (stride<<2) + msg->src.x_offset * pixel_width);\r
+ *bRGA_SRC_BASE1 = (RK_U32)(msg->src.uv_addr + (msg->src.y_offset / ydiv) * uv_stride + (msg->src.x_offset / xdiv));\r
+ *bRGA_SRC_BASE2 = (RK_U32)(msg->src.v_addr + (msg->src.y_offset / ydiv) * uv_stride + (msg->src.x_offset / xdiv));\r
+\r
+ //mask_stride = ((msg->src0_act.width + 31) & ~31) >> 5;\r
+ mask_stride = msg->rop_mask_stride;\r
+\r
+ *bRGA_SRC_VIR_INFO = stride | (mask_stride << 16);\r
+\r
+ *bRGA_SRC_ACT_INFO = (msg->src.act_w - 1) | ((msg->src.act_h - 1) << 16);\r
+\r
+ *bRGA_MASK_ADDR = (RK_U32)msg->rop_mask_addr;\r
+\r
+ *bRGA_SRC_INFO = reg;\r
+\r
+ *bRGA_SRC_TR_COLOR0 = msg->color_key_min;\r
+ *bRGA_SRC_TR_COLOR1 = msg->color_key_max;\r
+}\r
+\r
+\r
+void\r
+RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_DST_INFO;\r
+ RK_U32 *bRGA_DST_BASE0, *bRGA_DST_BASE1, *bRGA_DST_BASE2, *bRGA_SRC_BASE3;\r
+ RK_U32 *bRGA_DST_VIR_INFO;\r
+ RK_U32 *bRGA_DST_ACT_INFO;\r
+\r
+ RK_U8 src1_format = 0;\r
+ RK_U8 src1_rb_swp = 0;\r
+ RK_U8 src1_rgb_pack = 0;\r
+ RK_U8 dst_format = 0;\r
+ RK_U8 dst_rb_swp = 0;\r
+ RK_U8 dst_rgb_pack = 0;\r
+ RK_U8 dst_cbcr_swp = 0;\r
+ RK_U32 reg = 0;\r
+ RK_U8 spw, dpw;\r
+ RK_U32 s_stride, d_stride;\r
+ RK_U32 x_mirr, y_mirr, rot_90_flag;\r
+ RK_U32 yrgb_addr, u_addr, v_addr, s_yrgb_addr;\r
+ RK_U32 d_uv_stride, x_div, y_div;\r
+ RK_U32 y_lt_addr, y_ld_addr, y_rt_addr, y_rd_addr;\r
+ RK_U32 u_lt_addr, u_ld_addr, u_rt_addr, u_rd_addr;\r
+ RK_U32 v_lt_addr, v_ld_addr, v_rt_addr, v_rd_addr;\r
+\r
+ RK_U32 s_y_lt_addr, s_y_ld_addr, s_y_rt_addr, s_y_rd_addr;\r
+\r
+ dpw = 1;\r
+ x_div = y_div = 1;\r
+\r
+ bRGA_DST_INFO = (RK_U32 *)(base + RGA2_DST_INFO_OFFSET);\r
+ bRGA_DST_BASE0 = (RK_U32 *)(base + RGA2_DST_BASE0_OFFSET);\r
+ bRGA_DST_BASE1 = (RK_U32 *)(base + RGA2_DST_BASE1_OFFSET);\r
+ bRGA_DST_BASE2 = (RK_U32 *)(base + RGA2_DST_BASE2_OFFSET);\r
+\r
+ bRGA_SRC_BASE3 = (RK_U32 *)(base + RGA2_SRC_BASE3_OFFSET);\r
+\r
+ bRGA_DST_VIR_INFO = (RK_U32 *)(base + RGA2_DST_VIR_INFO_OFFSET);\r
+ bRGA_DST_ACT_INFO = (RK_U32 *)(base + RGA2_DST_ACT_INFO_OFFSET);\r
+\r
+ switch (msg->src1.format)\r
+ {\r
+ case RGA2_FORMAT_RGBA_8888 : src1_format = 0x0; spw = 4; break;\r
+ case RGA2_FORMAT_BGRA_8888 : src1_format = 0x0; src1_rb_swp = 0x1; spw = 4; break;\r
+ case RGA2_FORMAT_RGBX_8888 : src1_format = 0x1; spw = 4; break;\r
+ case RGA2_FORMAT_BGRX_8888 : src1_format = 0x1; src1_rb_swp = 0x1; spw = 4; break;\r
+ case RGA2_FORMAT_RGB_888 : src1_format = 0x2; src1_rgb_pack = 1; spw = 3; break;\r
+ case RGA2_FORMAT_BGR_888 : src1_format = 0x2; src1_rgb_pack = 1; src1_rb_swp = 1; spw = 3; break;\r
+ case RGA2_FORMAT_RGB_565 : src1_format = 0x4; spw = 2; src1_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_RGBA_5551 : src1_format = 0x5; spw = 2; src1_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_RGBA_4444 : src1_format = 0x6; spw = 2; src1_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_BGR_565 : src1_format = 0x4; spw = 2; break;\r
+ case RGA2_FORMAT_BGRA_5551 : src1_format = 0x5; spw = 2; break;\r
+ case RGA2_FORMAT_BGRA_4444 : src1_format = 0x6; spw = 2; break;\r
+ default : spw = 4; break;\r
+ };\r
+\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_FMT)) | (s_RGA2_DST_INFO_SW_SRC1_FMT(src1_format)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_RB_SWP)) | (s_RGA2_DST_INFO_SW_SRC1_RB_SWP(src1_rb_swp)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP)) | (s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(msg->alpha_swp >> 1)));\r
+\r
+\r
+ switch (msg->dst.format)\r
+ {\r
+ case RGA2_FORMAT_RGBA_8888 : dst_format = 0x0; dpw = 4; break;\r
+ case RGA2_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; dpw = 4; break;\r
+ case RGA2_FORMAT_RGBX_8888 : dst_format = 0x1; dpw = 4; break;\r
+ case RGA2_FORMAT_BGRX_8888 : dst_format = 0x1; dst_rb_swp = 0x1; dpw = 4; break;\r
+ case RGA2_FORMAT_RGB_888 : dst_format = 0x2; dst_rgb_pack = 1; dpw = 3; break;\r
+ case RGA2_FORMAT_BGR_888 : dst_format = 0x2; dst_rgb_pack = 1; dst_rb_swp = 1; dpw = 3; break;\r
+ case RGA2_FORMAT_RGB_565 : dst_format = 0x4; dpw = 2; dst_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_RGBA_5551 : dst_format = 0x5; dpw = 2; dst_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_RGBA_4444 : dst_format = 0x6; dpw = 2; dst_rb_swp = 0x1; break;\r
+ case RGA2_FORMAT_BGR_565 : dst_format = 0x4; dpw = 2; break;\r
+ case RGA2_FORMAT_BGRA_5551 : dst_format = 0x5; dpw = 2; break;\r
+ case RGA2_FORMAT_BGRA_4444 : dst_format = 0x6; dpw = 2; break;\r
+\r
+ case RGA2_FORMAT_YCbCr_422_SP : dst_format = 0x8; x_div = 1; y_div = 1; break;\r
+ case RGA2_FORMAT_YCbCr_422_P : dst_format = 0x9; x_div = 2; y_div = 1; break;\r
+ case RGA2_FORMAT_YCbCr_420_SP : dst_format = 0xa; x_div = 1; y_div = 2; break;\r
+ case RGA2_FORMAT_YCbCr_420_P : dst_format = 0xb; x_div = 2; y_div = 2; break;\r
+ case RGA2_FORMAT_YCrCb_422_SP : dst_format = 0x8; dst_cbcr_swp = 1; x_div = 1; y_div = 1; break;\r
+ case RGA2_FORMAT_YCrCb_422_P : dst_format = 0x9; dst_cbcr_swp = 1; x_div = 2; y_div = 1; break;\r
+ case RGA2_FORMAT_YCrCb_420_SP : dst_format = 0xa; dst_cbcr_swp = 1; x_div = 1; y_div = 2; break;\r
+ case RGA2_FORMAT_YCrCb_420_P : dst_format = 0xb; dst_cbcr_swp = 1; x_div = 2; y_div = 2; break;\r
+ };\r
+\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT)) | (s_RGA2_DST_INFO_SW_DST_FMT(dst_format)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_RB_SWAP)) | (s_RGA2_DST_INFO_SW_DST_RB_SWAP(dst_rb_swp)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_ALPHA_SWAP)) | (s_RGA2_DST_INFO_SW_ALPHA_SWAP(msg->alpha_swp >> 2)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_UV_SWAP)) | (s_RGA2_DST_INFO_SW_DST_UV_SWAP(dst_cbcr_swp)));\r
+\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_UP_E)) | (s_RGA2_DST_INFO_SW_DITHER_UP_E(msg->alpha_rop_flag >> 5)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_DOWN_E)) | (s_RGA2_DST_INFO_SW_DITHER_DOWN_E(msg->alpha_rop_flag >> 6)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_MODE)) | (s_RGA2_DST_INFO_SW_DITHER_MODE(msg->dither_mode)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE)) | (s_RGA2_DST_INFO_SW_DST_CSC_MODE(msg->yuv2rgb_mode >> 4)));\r
+ reg = ((reg & (~m_RGA2_DST_INFO_SW_CSC_CLIP_MODE)) | (s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(msg->yuv2rgb_mode >> 6)));\r
+\r
+\r
+ *bRGA_DST_INFO = reg;\r
+\r
+ s_stride = ((msg->src1.vir_w * spw + 3) & ~3) >> 2;\r
+ d_stride = ((msg->dst.vir_w * dpw + 3) & ~3) >> 2;\r
+ d_uv_stride = (d_stride << 2) / x_div;\r
+\r
+ *bRGA_DST_VIR_INFO = d_stride | (s_stride << 16);\r
+ *bRGA_DST_ACT_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);\r
+ s_stride <<= 2;\r
+ d_stride <<= 2;\r
+\r
+ if(((msg->rotate_mode & 0xf) == 0) || ((msg->rotate_mode & 0xf) == 1))\r
+ {\r
+ x_mirr = 0;\r
+ y_mirr = 0;\r
+ }\r
+ else\r
+ {\r
+ x_mirr = 1;\r
+ y_mirr = 1;\r
+ }\r
+\r
+ rot_90_flag = msg->rotate_mode & 1;\r
+ x_mirr = (x_mirr + ((msg->rotate_mode >> 4) & 1)) & 1;\r
+ y_mirr = (y_mirr + ((msg->rotate_mode >> 5) & 1)) & 1;\r
+\r
+ yrgb_addr = (RK_U32)msg->src1.yrgb_addr + (msg->src1.y_offset * s_stride) + (msg->src1.x_offset * spw);\r
+\r
+ s_y_lt_addr = yrgb_addr;\r
+ s_y_ld_addr = yrgb_addr + (msg->src1.act_h - 1) * s_stride;\r
+ s_y_rt_addr = yrgb_addr + (msg->dst.act_w - 1) * spw;\r
+ s_y_rd_addr = s_y_ld_addr + (msg->dst.act_w - 1) * spw;\r
+\r
+ yrgb_addr = (RK_U32)msg->dst.yrgb_addr + (msg->dst.y_offset * d_stride) + (msg->dst.x_offset * dpw);\r
+ u_addr = (RK_U32)msg->dst.uv_addr + msg->dst.y_offset * d_uv_stride + msg->dst.x_offset / x_div;\r
+ v_addr = (RK_U32)msg->dst.v_addr + msg->dst.y_offset * d_uv_stride + msg->dst.x_offset / x_div;\r
+\r
+ y_lt_addr = yrgb_addr;\r
+ u_lt_addr = u_addr;\r
+ v_lt_addr = v_addr;\r
+\r
+ y_ld_addr = yrgb_addr + (msg->dst.act_h - 1) * (d_stride);\r
+ u_ld_addr = u_addr + ((msg->dst.act_h / y_div) - 1) * (d_uv_stride);\r
+ v_ld_addr = v_addr + ((msg->dst.act_h / y_div) - 1) * (d_uv_stride);\r
+\r
+ y_rt_addr = yrgb_addr + (msg->dst.act_w - 1) * dpw;\r
+ u_rt_addr = u_addr + (msg->dst.act_w / x_div) - 1;\r
+ v_rt_addr = v_addr + (msg->dst.act_w / x_div) - 1;\r
+\r
+ y_rd_addr = y_ld_addr + (msg->dst.act_w - 1) * dpw;\r
+ u_rd_addr = u_ld_addr + (msg->dst.act_w / x_div) - 1;\r
+ v_rd_addr = v_ld_addr + (msg->dst.act_w / x_div) - 1;\r
+\r
+ if(rot_90_flag == 0)\r
+ {\r
+ if(y_mirr == 1)\r
+ {\r
+ if(x_mirr == 1)\r
+ {\r
+ yrgb_addr = y_rd_addr;\r
+ u_addr = u_rd_addr;\r
+ v_addr = v_rd_addr;\r
+\r
+ s_yrgb_addr = s_y_rd_addr;\r
+ }\r
+ else\r
+ {\r
+ yrgb_addr = y_ld_addr;\r
+ u_addr = u_ld_addr;\r
+ v_addr = v_ld_addr;\r
+\r
+ s_yrgb_addr = s_y_ld_addr;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(x_mirr == 1)\r
+ {\r
+ yrgb_addr = y_rt_addr;\r
+ u_addr = u_rt_addr;\r
+ v_addr = v_rt_addr;\r
+\r
+ s_yrgb_addr = s_y_rt_addr;\r
+ }\r
+ else\r
+ {\r
+ yrgb_addr = y_lt_addr;\r
+ u_addr = u_lt_addr;\r
+ v_addr = v_lt_addr;\r
+\r
+ s_yrgb_addr = s_y_lt_addr;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(y_mirr == 1)\r
+ {\r
+ if(x_mirr == 1)\r
+ {\r
+ yrgb_addr = y_ld_addr;\r
+ u_addr = u_ld_addr;\r
+ v_addr = v_ld_addr;\r
+\r
+ s_yrgb_addr = s_y_ld_addr;\r
+ }\r
+ else\r
+ {\r
+ yrgb_addr = y_rd_addr;\r
+ u_addr = u_rd_addr;\r
+ v_addr = v_rd_addr;\r
+\r
+ s_yrgb_addr = s_y_rd_addr;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(x_mirr == 1)\r
+ {\r
+ yrgb_addr = y_lt_addr;\r
+ u_addr = u_lt_addr;\r
+ v_addr = v_lt_addr;\r
+\r
+ s_yrgb_addr = s_y_lt_addr;\r
+ }\r
+ else\r
+ {\r
+ yrgb_addr = y_rt_addr;\r
+ u_addr = u_rt_addr;\r
+ v_addr = v_rt_addr;\r
+\r
+ s_yrgb_addr = s_y_rt_addr;\r
+ }\r
+ }\r
+ }\r
+\r
+ *bRGA_DST_BASE0 = (RK_U32)yrgb_addr;\r
+ *bRGA_DST_BASE1 = (RK_U32)u_addr;\r
+ *bRGA_DST_BASE2 = (RK_U32)v_addr;\r
+ *bRGA_SRC_BASE3 = (RK_U32)s_y_lt_addr;\r
+}\r
+\r
+void\r
+RGA2_set_reg_alpha_info(u8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_ALPHA_CTRL0;\r
+ RK_U32 *bRGA_ALPHA_CTRL1;\r
+ RK_U32 *bRGA_FADING_CTRL;\r
+ RK_U32 reg0 = 0;\r
+ RK_U32 reg1 = 0;\r
+\r
+ bRGA_ALPHA_CTRL0 = (RK_U32 *)(base + RGA2_ALPHA_CTRL0_OFFSET);\r
+ bRGA_ALPHA_CTRL1 = (RK_U32 *)(base + RGA2_ALPHA_CTRL1_OFFSET);\r
+ bRGA_FADING_CTRL = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);\r
+\r
+ reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) | (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(msg->alpha_rop_flag)));\r
+ reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) | (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL(msg->alpha_rop_flag >> 1)));\r
+ reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) | (s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(msg->rop_mode)));\r
+ reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) | (s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA(msg->src_a_global_val)));\r
+ reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) | (s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA(msg->dst_a_global_val)));\r
+\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0(msg->alpha_mode_0 >> 15)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0(msg->alpha_mode_0 >> 7)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0(msg->alpha_mode_0 >> 12)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0(msg->alpha_mode_0 >> 4)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0(msg->alpha_mode_0 >> 11)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0(msg->alpha_mode_0 >> 3)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(msg->alpha_mode_0 >> 9)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0(msg->alpha_mode_0 >> 1)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0(msg->alpha_mode_0 >> 8)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0(msg->alpha_mode_0 >> 0)));\r
+\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1)) | (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1(msg->alpha_mode_1 >> 12)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1(msg->alpha_mode_1 >> 4)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1)) | (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1(msg->alpha_mode_1 >> 11)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1(msg->alpha_mode_1 >> 3)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1)) | (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(msg->alpha_mode_1 >> 9)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(msg->alpha_mode_1 >> 1)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1)) | (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(msg->alpha_mode_1 >> 8)));\r
+ reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(msg->alpha_mode_1 >> 0)));\r
+\r
+ *bRGA_ALPHA_CTRL0 = reg0;\r
+ *bRGA_ALPHA_CTRL1 = reg1;\r
+\r
+ if((msg->alpha_rop_flag>>2)&1)\r
+ {\r
+ *bRGA_FADING_CTRL = (1<<24) | (msg->fading_b_value<<16) | (msg->fading_g_value<<8) | (msg->fading_r_value);\r
+ }\r
+}\r
+\r
+void\r
+RGA2_set_reg_rop_info(u8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_ALPHA_CTRL0;\r
+ RK_U32 *bRGA_ROP_CTRL0;\r
+ RK_U32 *bRGA_ROP_CTRL1;\r
+ RK_U32 *bRGA_MASK_ADDR;\r
+ RK_U32 *bRGA_FG_COLOR;\r
+ RK_U32 *bRGA_PAT_CON;\r
+\r
+ RK_U32 rop_code0 = 0;\r
+ RK_U32 rop_code1 = 0;\r
+\r
+ bRGA_ALPHA_CTRL0 = (RK_U32 *)(base + RGA2_ALPHA_CTRL0_OFFSET);\r
+ bRGA_ROP_CTRL0 = (RK_U32 *)(base + RGA2_ROP_CTRL0_OFFSET);\r
+ bRGA_ROP_CTRL1 = (RK_U32 *)(base + RGA2_ROP_CTRL1_OFFSET);\r
+ bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);\r
+ bRGA_FG_COLOR = (RK_U32 *)(base + RGA2_SRC_FG_COLOR_OFFSET);\r
+ bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);\r
+\r
+ if(msg->rop_mode == 0) {\r
+ rop_code0 = ROP3_code[(msg->rop_code & 0xff)];\r
+ }\r
+ else if(msg->rop_mode == 1) {\r
+ rop_code0 = ROP3_code[(msg->rop_code & 0xff)];\r
+ }\r
+ else if(msg->rop_mode == 2) {\r
+ rop_code0 = ROP3_code[(msg->rop_code & 0xff)];\r
+ rop_code1 = ROP3_code[(msg->rop_code & 0xff00)>>8];\r
+ }\r
+\r
+ *bRGA_ROP_CTRL0 = rop_code0;\r
+ *bRGA_ROP_CTRL1 = rop_code1;\r
+ *bRGA_FG_COLOR = msg->fg_color;\r
+ *bRGA_MASK_ADDR = (RK_U32)msg->rop_mask_addr;\r
+ *bRGA_PAT_CON = (msg->pat.act_w-1) | ((msg->pat.act_h-1) << 8)\r
+ | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);\r
+ *bRGA_ALPHA_CTRL0 = *bRGA_ALPHA_CTRL0 | (((msg->endian_mode >> 1) & 1) << 20);\r
+\r
+}\r
+\r
+\r
+\r
+void\r
+RGA2_set_reg_color_palette(RK_U8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_SRC_BASE0, *bRGA_SRC_INFO, *bRGA_SRC_VIR_INFO, *bRGA_SRC_ACT_INFO, *bRGA_SRC_FG_COLOR, *bRGA_SRC_BG_COLOR;\r
+ RK_U32 *p;\r
+ RK_S16 x_off, y_off;\r
+ RK_U16 src_stride;\r
+ RK_U8 shift;\r
+ RK_U32 sw;\r
+ RK_U32 byte_num;\r
+ RK_U32 reg;\r
+\r
+ bRGA_SRC_BASE0 = (RK_U32 *)(base + RGA2_SRC_BASE0_OFFSET);\r
+ bRGA_SRC_INFO = (RK_U32 *)(base + RGA2_SRC_INFO_OFFSET);\r
+ bRGA_SRC_VIR_INFO = (RK_U32 *)(base + RGA2_SRC_VIR_INFO_OFFSET);\r
+ bRGA_SRC_ACT_INFO = (RK_U32 *)(base + RGA2_SRC_ACT_INFO_OFFSET);\r
+ bRGA_SRC_FG_COLOR = (RK_U32 *)(base + RGA2_SRC_FG_COLOR_OFFSET);\r
+ bRGA_SRC_BG_COLOR = (RK_U32 *)(base + RGA2_SRC_BG_COLOR_OFFSET);\r
+\r
+ reg = 0;\r
+\r
+ shift = 3 - msg->palette_mode;\r
+\r
+ x_off = msg->src.x_offset;\r
+ y_off = msg->src.y_offset;\r
+\r
+ sw = msg->src.vir_w;\r
+ byte_num = sw >> shift;\r
+\r
+ src_stride = (byte_num + 3) & (~3);\r
+\r
+ p = (RK_U32 *)msg->src.yrgb_addr;\r
+\r
+ #if 0\r
+ if(endian_mode)\r
+ {\r
+ p = p + (x_off>>shift) + y_off*src_stride;\r
+ }\r
+ else\r
+ {\r
+ p = p + (((x_off>>shift)>>2)<<2) + (3 - ((x_off>>shift) & 3)) + y_off*src_stride;\r
+ }\r
+ #endif\r
+\r
+ p = p + (x_off>>shift) + y_off*src_stride;\r
+\r
+\r
+ *bRGA_SRC_BASE0 = (RK_U32)p;\r
+\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) | (s_RGA2_SRC_INFO_SW_SRC_FMT((msg->palette_mode | 0xc))));\r
+ reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_CP_ENDAIN)) | (s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(msg->endian_mode & 1)));\r
+ *bRGA_SRC_VIR_INFO = src_stride >> 2;\r
+ *bRGA_SRC_ACT_INFO = (msg->src.act_w - 1) | ((msg->src.act_h - 1) << 16);\r
+ *bRGA_SRC_INFO = reg;\r
+\r
+ *bRGA_SRC_FG_COLOR = msg->fg_color;\r
+ *bRGA_SRC_BG_COLOR = msg->bg_color;\r
+\r
+}\r
+\r
+void\r
+RGA2_set_reg_color_fill(u8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_CF_GR_A;\r
+ RK_U32 *bRGA_CF_GR_B;\r
+ RK_U32 *bRGA_CF_GR_G;\r
+ RK_U32 *bRGA_CF_GR_R;\r
+ RK_U32 *bRGA_SRC_FG_COLOR;\r
+ RK_U32 *bRGA_MASK_ADDR;\r
+ RK_U32 *bRGA_PAT_CON;\r
+\r
+ RK_U32 mask_stride;\r
+ RK_U32 *bRGA_SRC_VIR_INFO;\r
+\r
+ bRGA_SRC_FG_COLOR = (RK_U32 *)(base + RGA2_SRC_FG_COLOR_OFFSET);\r
+\r
+ bRGA_CF_GR_A = (RK_U32 *)(base + RGA2_CF_GR_A_OFFSET);\r
+ bRGA_CF_GR_B = (RK_U32 *)(base + RGA2_CF_GR_B_OFFSET);\r
+ bRGA_CF_GR_G = (RK_U32 *)(base + RGA2_CF_GR_G_OFFSET);\r
+ bRGA_CF_GR_R = (RK_U32 *)(base + RGA2_CF_GR_R_OFFSET);\r
+\r
+ bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);\r
+ bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);\r
+\r
+ bRGA_SRC_VIR_INFO = (RK_U32 *)(base + RGA2_SRC_VIR_INFO_OFFSET);\r
+\r
+ mask_stride = msg->rop_mask_stride;\r
+\r
+ if(msg->color_fill_mode == 0)\r
+ {\r
+ /* solid color */\r
+ *bRGA_CF_GR_A = (msg->gr_color.gr_x_a & 0xffff) | (msg->gr_color.gr_y_a << 16);\r
+ *bRGA_CF_GR_B = (msg->gr_color.gr_x_b & 0xffff) | (msg->gr_color.gr_y_b << 16);\r
+ *bRGA_CF_GR_G = (msg->gr_color.gr_x_g & 0xffff) | (msg->gr_color.gr_y_g << 16);\r
+ *bRGA_CF_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16);\r
+\r
+ *bRGA_SRC_FG_COLOR = msg->fg_color;\r
+ }\r
+ else\r
+ {\r
+ /* patten color */\r
+ *bRGA_MASK_ADDR = (RK_U32)msg->pat.yrgb_addr;\r
+ *bRGA_PAT_CON = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8)\r
+ | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);\r
+ }\r
+ *bRGA_SRC_VIR_INFO = mask_stride << 16;\r
+}\r
+\r
+\r
+void\r
+RGA2_set_reg_update_palette_table(RK_U8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_MASK_BASE;\r
+ RK_U32 *bRGA_FADING_CTRL;\r
+\r
+ bRGA_MASK_BASE = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);\r
+ bRGA_FADING_CTRL = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);\r
+\r
+ *bRGA_FADING_CTRL = msg->fading_g_value << 8;\r
+ // *bRGA_MASK_BASE = (RK_U32)msg->LUT_addr;\r
+ *bRGA_MASK_BASE = (RK_U32)msg->pat.yrgb_addr;\r
+}\r
+\r
+\r
+void\r
+RGA2_set_reg_update_patten_buff(RK_U8 *base, struct rga2_req *msg)\r
+{\r
+ u32 *bRGA_PAT_MST;\r
+ u32 *bRGA_PAT_CON;\r
+ u32 *bRGA_PAT_START_POINT;\r
+ RK_U32 *bRGA_FADING_CTRL;\r
+ u32 reg = 0;\r
+ rga_img_info_t *pat;\r
+\r
+ RK_U32 num, offset;\r
+\r
+ pat = &msg->pat;\r
+\r
+ num = (pat->act_w * pat->act_h) - 1;\r
+\r
+ offset = pat->act_w * pat->y_offset + pat->x_offset;\r
+\r
+ bRGA_PAT_START_POINT = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);\r
+ bRGA_PAT_MST = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);\r
+ bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);\r
+ bRGA_FADING_CTRL = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);\r
+\r
+ *bRGA_PAT_MST = (RK_U32)msg->pat.yrgb_addr;\r
+ *bRGA_PAT_START_POINT = (pat->act_w * pat->y_offset) + pat->x_offset;\r
+\r
+ reg = (pat->act_w-1) | ((pat->act_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);\r
+ *bRGA_PAT_CON = reg;\r
+\r
+ *bRGA_FADING_CTRL = (num << 8) | offset;\r
+}\r
+\r
+\r
+void\r
+RGA2_set_pat_info(RK_U8 *base, struct rga2_req *msg)\r
+{\r
+ u32 *bRGA_PAT_CON;\r
+ u32 *bRGA_FADING_CTRL;\r
+ u32 reg = 0;\r
+ rga_img_info_t *pat;\r
+\r
+ RK_U32 num, offset;\r
+\r
+ pat = &msg->pat;\r
+\r
+ num = ((pat->act_w * pat->act_h) - 1) & 0xff;\r
+\r
+ offset = (pat->act_w * pat->y_offset) + pat->x_offset;\r
+\r
+ bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);\r
+ bRGA_FADING_CTRL = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);\r
+\r
+ reg = (pat->act_w-1) | ((pat->act_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);\r
+ *bRGA_PAT_CON = reg;\r
+\r
+ *bRGA_FADING_CTRL = (num << 8) | offset; //???pat_addr???\r
+}\r
+\r
+\r
+void\r
+RGA2_set_mmu_info(RK_U8 *base, struct rga2_req *msg)\r
+{\r
+ RK_U32 *bRGA_MMU_CTRL1;\r
+ RK_U32 *bRGA_MMU_SRC_BASE;\r
+ RK_U32 *bRGA_MMU_SRC1_BASE;\r
+ RK_U32 *bRGA_MMU_DST_BASE;\r
+ RK_U32 *bRGA_MMU_ELS_BASE;\r
+\r
+ RK_U32 reg;\r
+\r
+ bRGA_MMU_CTRL1 = (RK_U32 *)(base + RGA2_MMU_CTRL1_OFFSET);\r
+ bRGA_MMU_SRC_BASE = (RK_U32 *)(base + RGA2_MMU_SRC_BASE_OFFSET);\r
+ bRGA_MMU_SRC1_BASE = (RK_U32 *)(base + RGA2_MMU_SRC1_BASE_OFFSET);\r
+ bRGA_MMU_DST_BASE = (RK_U32 *)(base + RGA2_MMU_DST_BASE_OFFSET);\r
+ bRGA_MMU_ELS_BASE = (RK_U32 *)(base + RGA2_MMU_ELS_BASE_OFFSET);\r
+\r
+ reg = (msg->mmu_info.src0_mmu_flag & 0xf) | ((msg->mmu_info.src1_mmu_flag & 0xf) << 4)\r
+ | ((msg->mmu_info.dst_mmu_flag & 0xf) << 8) | ((msg->mmu_info.els_mmu_flag & 0x3) << 12);\r
+\r
+ *bRGA_MMU_CTRL1 = reg;\r
+ *bRGA_MMU_SRC_BASE = (RK_U32)(msg->mmu_info.src0_base_addr) >> 4;\r
+ *bRGA_MMU_SRC1_BASE = (RK_U32)(msg->mmu_info.src1_base_addr) >> 4;\r
+ *bRGA_MMU_DST_BASE = (RK_U32)(msg->mmu_info.dst_base_addr) >> 4;\r
+ *bRGA_MMU_ELS_BASE = (RK_U32)(msg->mmu_info.els_base_addr) >> 4;\r
+}\r
+\r
+\r
+int\r
+RGA2_gen_reg_info(RK_U8 *base , struct rga2_req *msg)\r
+{\r
+\r
+ RGA2_set_mode_ctrl(base, msg);\r
+\r
+ RGA2_set_pat_info(base, msg);\r
+\r
+ switch(msg->render_mode)\r
+ {\r
+ case bitblt_mode:\r
+ RGA2_set_reg_src_info(base, msg);\r
+ RGA2_set_reg_dst_info(base, msg);\r
+ RGA2_set_reg_alpha_info(base, msg);\r
+ RGA2_set_reg_rop_info(base, msg);\r
+ break;\r
+ case color_fill_mode :\r
+ RGA2_set_reg_color_fill(base, msg);\r
+ RGA2_set_reg_dst_info(base, msg);\r
+ RGA2_set_reg_alpha_info(base, msg);\r
+ break;\r
+ case color_palette_mode :\r
+ RGA2_set_reg_color_palette(base, msg);\r
+ RGA2_set_reg_dst_info(base, msg);\r
+ break;\r
+ case update_palette_table_mode :\r
+ RGA2_set_reg_update_palette_table(base, msg);\r
+ break;\r
+ case update_patten_buff_mode :\r
+ RGA2_set_reg_update_patten_buff(base, msg);\r
+ break;\r
+ default :\r
+ printk("RGA2 ERROR msg render mode %d \n", msg->render_mode);\r
+ break;\r
+\r
+ }\r
+\r
+ RGA2_set_mmu_info(base, msg);\r
+\r
+ return 0;\r
+\r
+}\r
+\r
+void format_name_convert(uint32_t *df, uint32_t sf)\r
+{\r
+ /*\r
+ RK_FORMAT_RGBA_8888 = 0x0,\r
+ RK_FORMAT_RGBX_8888 = 0x1,\r
+ RK_FORMAT_RGB_888 = 0x2,\r
+ RK_FORMAT_BGRA_8888 = 0x3,\r
+ RK_FORMAT_RGB_565 = 0x4,\r
+ RK_FORMAT_RGBA_5551 = 0x5,\r
+ RK_FORMAT_RGBA_4444 = 0x6,\r
+ RK_FORMAT_BGR_888 = 0x7,\r
+\r
+ RK_FORMAT_YCbCr_422_SP = 0x8,\r
+ RK_FORMAT_YCbCr_422_P = 0x9,\r
+ RK_FORMAT_YCbCr_420_SP = 0xa,\r
+ RK_FORMAT_YCbCr_420_P = 0xb,\r
+\r
+ RK_FORMAT_YCrCb_422_SP = 0xc,\r
+ RK_FORMAT_YCrCb_422_P = 0xd,\r
+ RK_FORMAT_YCrCb_420_SP = 0xe,\r
+ RK_FORMAT_YCrCb_420_P = 0xf,\r
+\r
+ RGA2_FORMAT_RGBA_8888 = 0x0,\r
+ RGA2_FORMAT_RGBX_8888 = 0x1,\r
+ RGA2_FORMAT_RGB_888 = 0x2,\r
+ RGA2_FORMAT_BGRA_8888 = 0x3,\r
+ RGA2_FORMAT_BGRX_8888 = 0x4,\r
+ RGA2_FORMAT_BGR_888 = 0x5,\r
+ RGA2_FORMAT_RGB_565 = 0x6,\r
+ RGA2_FORMAT_RGBA_5551 = 0x7,\r
+ RGA2_FORMAT_RGBA_4444 = 0x8,\r
+ RGA2_FORMAT_BGR_565 = 0x9,\r
+ RGA2_FORMAT_BGRA_5551 = 0xa,\r
+ RGA2_FORMAT_BGRA_4444 = 0xb,\r
+\r
+ RGA2_FORMAT_YCbCr_422_SP = 0x10,\r
+ RGA2_FORMAT_YCbCr_422_P = 0x11,\r
+ RGA2_FORMAT_YCbCr_420_SP = 0x12,\r
+ RGA2_FORMAT_YCbCr_420_P = 0x13,\r
+ RGA2_FORMAT_YCrCb_422_SP = 0x14,\r
+ RGA2_FORMAT_YCrCb_422_P = 0x15,\r
+ RGA2_FORMAT_YCrCb_420_SP = 0x16,\r
+ RGA2_FORMAT_YCrCb_420_P = 0x17,*/\r
+ switch(sf)\r
+ {\r
+ case 0x0: *df = RGA2_FORMAT_RGBA_8888; break;\r
+ case 0x1: *df = RGA2_FORMAT_RGBX_8888; break;\r
+ case 0x2: *df = RGA2_FORMAT_RGB_888; break;\r
+ case 0x3: *df = RGA2_FORMAT_BGRA_8888; break;\r
+ case 0x4: *df = RGA2_FORMAT_RGB_565; break;\r
+ case 0x5: *df = RGA2_FORMAT_RGBA_5551; break;\r
+ case 0x6: *df = RGA2_FORMAT_RGBA_4444; break;\r
+ case 0x7: *df = RGA2_FORMAT_BGR_888; break;\r
+ case 0x8: *df = RGA2_FORMAT_YCbCr_422_SP; break;\r
+ case 0x9: *df = RGA2_FORMAT_YCbCr_422_P; break;\r
+ case 0xa: *df = RGA2_FORMAT_YCbCr_420_SP; break;\r
+ case 0xb: *df = RGA2_FORMAT_YCbCr_420_P; break;\r
+ case 0xc: *df = RGA2_FORMAT_YCrCb_422_SP; break;\r
+ case 0xd: *df = RGA2_FORMAT_YCrCb_422_P; break;\r
+ case 0xe: *df = RGA2_FORMAT_YCrCb_420_SP; break;\r
+ case 0xf: *df = RGA2_FORMAT_YCrCb_420_P; break;\r
+ }\r
+}\r
+\r
+void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)\r
+{\r
+ u16 alpha_mode_0, alpha_mode_1;\r
+\r
+ if (req_rga->render_mode == 6)\r
+ req->render_mode = update_palette_table_mode;\r
+ else if (req_rga->render_mode == 7)\r
+ req->render_mode = update_patten_buff_mode;\r
+ else if (req_rga->render_mode == 5)\r
+ req->render_mode = bitblt_mode;\r
+\r
+ memcpy(&req->src, &req_rga->src, sizeof(req_rga->src));\r
+ memcpy(&req->dst, &req_rga->dst, sizeof(req_rga->dst));\r
+ memcpy(&req->pat, &req_rga->pat, sizeof(req_rga->pat));\r
+ memcpy(&req->src1,&req_rga->pat, sizeof(req_rga->pat));\r
+\r
+ format_name_convert(&req->src.format, req_rga->src.format);\r
+ format_name_convert(&req->dst.format, req_rga->dst.format);\r
+\r
+ if(req_rga->rotate_mode == 1) {\r
+ if(req_rga->sina == 0 && req_rga->cosa == 65536) {\r
+ /* rotate 0 */\r
+ req->rotate_mode = 0;\r
+ }\r
+ else if (req_rga->sina == 65536 && req_rga->cosa == 0) {\r
+ /* rotate 90 */\r
+ req->rotate_mode = 1;\r
+ req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_h + 1;\r
+ req->dst.act_w = req_rga->dst.act_h;\r
+ req->dst.act_h = req_rga->dst.act_w;\r
+ }\r
+ else if (req_rga->sina == 0 && req_rga->cosa == -65536) {\r
+ /* rotate 180 */\r
+ req->rotate_mode = 2;\r
+ req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_w + 1;\r
+ req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_h + 1;\r
+ }\r
+ else if (req_rga->sina == -65536 && req_rga->cosa == 0) {\r
+ /* totate 270 */\r
+ req->rotate_mode = 3;\r
+ req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_w + 1;\r
+ req->dst.act_w = req_rga->dst.act_h;\r
+ req->dst.act_h = req_rga->dst.act_w;\r
+ }\r
+ }\r
+ else if (req_rga->rotate_mode == 2)\r
+ {\r
+ //x_mirror\r
+ }\r
+ else if (req_rga->rotate_mode == 3)\r
+ {\r
+ //y_mirror\r
+ }\r
+ else {\r
+ req->rotate_mode = 0;\r
+ }\r
+\r
+ req->LUT_addr = req_rga->LUT_addr;\r
+ req->rop_mask_addr = req_rga->rop_mask_addr;\r
+\r
+ req->bitblt_mode = req_rga->bsfilter_flag;\r
+\r
+ req->src_a_global_val = req_rga->alpha_global_value;\r
+ req->dst_a_global_val = 0;\r
+ req->rop_code = req_rga->rop_code;\r
+ req->rop_mode = 0;\r
+\r
+ req->color_fill_mode = req_rga->color_fill_mode;\r
+ req->color_key_min = req_rga->color_key_min;\r
+ req->color_key_max = req_rga->color_key_max;\r
+\r
+ req->fg_color = req_rga->fg_color;\r
+ req->bg_color = req_rga->bg_color;\r
+ memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color));\r
+\r
+ req->palette_mode = req_rga->palette_mode;\r
+ req->yuv2rgb_mode = req_rga->yuv2rgb_mode + 1;\r
+ req->endian_mode = req_rga->endian_mode;\r
+ req->rgb2yuv_mode = 0;\r
+\r
+ req->fading_alpha_value = 0;\r
+ req->fading_r_value = req_rga->fading.r;\r
+ req->fading_g_value = req_rga->fading.g;\r
+ req->fading_b_value = req_rga->fading.b;\r
+\r
+ /* alpha mode set */\r
+ req->alpha_rop_flag = 0;\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag & 1))); // alpha_rop_enable\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 1) & 1) << 1); // rop_enable\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 2) & 1) << 2); // fading_enable\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 4) & 1) << 3); // alpha_cal_mode_sel\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6); // dst_dither_down\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7); // gradient fill mode sel\r
+\r
+ if(((req_rga->alpha_rop_flag) & 1)) {\r
+ if((req_rga->alpha_rop_flag >> 3) & 1) {\r
+ /* porter duff alpha enable */\r
+ switch(req_rga->PD_mode)\r
+ {\r
+ case 0: //dst = 0\r
+ break;\r
+ case 1: //dst = src\r
+ break;\r
+ case 2: //dst = dst\r
+ break;\r
+ case 3: //dst = (256*sc + (256 - sa)*dc) >> 8\r
+ if((req_rga->alpha_rop_mode & 3) == 0) {\r
+ alpha_mode_0 = 0x3818;\r
+ alpha_mode_1 = 0x3818;\r
+ }\r
+ else if ((req_rga->alpha_rop_mode & 3) == 1) {\r
+ alpha_mode_0 = 0x381A;\r
+ alpha_mode_1 = 0x381A;\r
+ }\r
+ else if ((req_rga->alpha_rop_mode & 3) == 2) {\r
+ alpha_mode_0 = 0x381C;\r
+ alpha_mode_1 = 0x381C;\r
+ }\r
+ else {\r
+ alpha_mode_0 = 0x381A;\r
+ alpha_mode_1 = 0x381A;\r
+ }\r
+ req->alpha_mode_0 = alpha_mode_0;\r
+ req->alpha_mode_1 = alpha_mode_1;\r
+ break;\r
+ case 4: //dst = (sc*(256-da) + 256*dc) >> 8\r
+ break;\r
+ case 5: //dst = (da*sc) >> 8\r
+ break;\r
+ case 6: //dst = (sa*dc) >> 8\r
+ break;\r
+ case 7: //dst = ((256-da)*sc) >> 8\r
+ break;\r
+ case 8: //dst = ((256-sa)*dc) >> 8\r
+ break;\r
+ case 9: //dst = (da*sc + (256-sa)*dc) >> 8\r
+ req->alpha_mode_0 = 0x3848;\r
+ req->alpha_mode_1 = 0x3848;\r
+ break;\r
+ case 10://dst = ((256-da)*sc + (sa*dc)) >> 8\r
+ break;\r
+ case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else {\r
+ if((req_rga->alpha_rop_mode & 3) == 0) {\r
+ req->alpha_mode_0 = 0x3848;\r
+ req->alpha_mode_1 = 0x3848;\r
+ }\r
+ else if ((req_rga->alpha_rop_mode & 3) == 1) {\r
+ req->alpha_mode_0 = 0x384A;\r
+ req->alpha_mode_1 = 0x384A;\r
+ }\r
+ else if ((req_rga->alpha_rop_mode & 3) == 2) {\r
+ req->alpha_mode_0 = 0x384C;\r
+ req->alpha_mode_1 = 0x384C;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (req_rga->mmu_info.mmu_en && (req_rga->mmu_info.mmu_flag & 1) == 1) {\r
+ req->mmu_info.src0_mmu_flag = 1;\r
+ req->mmu_info.dst_mmu_flag = 1;\r
+\r
+ if (req_rga->mmu_info.mmu_flag >> 31) {\r
+ req->mmu_info.src0_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 8) & 1);\r
+ req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 9) & 1);\r
+ req->mmu_info.dst_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 10) & 1);\r
+ req->mmu_info.els_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 11) & 1);\r
+ }\r
+ else {\r
+ if (req_rga->src.yrgb_addr >= 0xa0000000) {\r
+ req->mmu_info.src0_mmu_flag = 0;\r
+ req->src.yrgb_addr = req_rga->src.yrgb_addr - 0x60000000;\r
+ req->src.uv_addr = req_rga->src.uv_addr - 0x60000000;\r
+ req->src.v_addr = req_rga->src.v_addr - 0x60000000;\r
+ }\r
+\r
+ if (req_rga->dst.yrgb_addr >= 0xa0000000) {\r
+ req->mmu_info.dst_mmu_flag = 0;\r
+ req->dst.yrgb_addr = req_rga->dst.yrgb_addr - 0x60000000;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+#ifndef __REG2_INFO_H__\r
+#define __REG2_INFO_H__\r
+\r
+\r
+//#include "chip_register.h"\r
+\r
+//#include "rga_struct.h"\r
+#include "rga2.h"\r
+\r
+#ifndef MIN\r
+#define MIN(X, Y) ((X)<(Y)?(X):(Y))\r
+#endif\r
+\r
+#ifndef MAX\r
+#define MAX(X, Y) ((X)>(Y)?(X):(Y))\r
+#endif\r
+\r
+#ifndef ABS\r
+#define ABS(X) (((X) < 0) ? (-(X)) : (X))\r
+#endif\r
+\r
+#ifndef CLIP\r
+#define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))\r
+#endif\r
+\r
+#define rRGA_SYS_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_SYS_CTRL_OFFSET ))\r
+#define rRGA_CMD_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_CTRL_OFFSET ))\r
+#define rRGA_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_BASE_OFFSET ))\r
+#define rRGA_STATUS (*(volatile u32 *)(RGA2_BASE + RGA2_STATUS_OFFSET ))\r
+#define rRGA_INT (*(volatile u32 *)(RGA2_BASE + RGA2_INT_OFFSET ))\r
+#define rRGA_MMU_CTRL0 (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CTRL0_OFFSET ))\r
+#define rRGA_MMU_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CMD_BASE_OFFSET))\r
+#define rRGA_CMD_ADDR (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_ADDR))\r
+\r
+/*RGA_INT*/\r
+#define m_RGA2_INT_ALL_CMD_DONE_INT_EN ( 1<<10 )\r
+#define m_RGA2_INT_MMU_INT_EN ( 1<<9 )\r
+#define m_RGA2_INT_ERROR_INT_EN ( 1<<8 )\r
+#define m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 )\r
+#define m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 )\r
+#define m_RGA2_INT_MMU_INT_CLEAR ( 1<<5 )\r
+#define m_RGA2_INT_ERROR_INT_CLEAR ( 1<<4 )\r
+#define m_RGA2_INT_CUR_CMD_DONE_INT_FLAG ( 1<<3 )\r
+#define m_RGA2_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 )\r
+#define m_RGA2_INT_MMU_INT_FLAG ( 1<<1 )\r
+#define m_RGA2_INT_ERROR_INT_FLAG ( 1<<0 )\r
+\r
+#define s_RGA2_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 )\r
+#define s_RGA2_INT_MMU_INT_EN(x) ( (x&0x1)<<9 )\r
+#define s_RGA2_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 )\r
+#define s_RGA2_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 )\r
+#define s_RGA2_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 )\r
+#define s_RGA2_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 )\r
+#define s_RGA2_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 )\r
+\r
+\r
+\r
+/* RGA_MODE_CTRL */\r
+#define m_RGA2_MODE_CTRL_SW_RENDER_MODE ( 0x7<<0 )\r
+#define m_RGA2_MODE_CTRL_SW_BITBLT_MODE ( 0x1<<3 )\r
+#define m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT ( 0x1<<4 )\r
+#define m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET ( 0x1<<5 )\r
+#define m_RGA2_MODE_CTRL_SW_GRADIENT_SAT ( 0x1<<6 )\r
+#define m_RGA2_MODE_CTRL_SW_INTR_CF_E ( 0x1<<7 )\r
+\r
+#define s_RGA2_MODE_CTRL_SW_RENDER_MODE(x) ( (x&0x7)<<0 )\r
+#define s_RGA2_MODE_CTRL_SW_BITBLT_MODE(x) ( (x&0x1)<<3 )\r
+#define s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(x) ( (x&0x1)<<4 )\r
+#define s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(x) ( (x&0x1)<<5 )\r
+#define s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(x) ( (x&0x1)<<6 )\r
+#define s_RGA2_MODE_CTRL_SW_INTR_CF_E(x) ( (x&0x1)<<7 )\r
+\r
+/* RGA_SRC_INFO */\r
+#define m_RGA2_SRC_INFO_SW_SRC_FMT ( 0xf<<0 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP ( 0x1<<4 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP ( 0x1<<5 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP ( 0x1<<6 )\r
+#define m_RGA2_SRC_INFO_SW_SW_CP_ENDAIN ( 0x1<<7 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE ( 0x3<<8 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE ( 0x3<<10 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE ( 0x3<<12 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE ( 0x3<<14 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE ( 0x3<<16 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE ( 0x1<<18 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E ( 0xf<<19 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E ( 0x1<<23 )\r
+#define m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER ( 0x3<<24 )\r
+#define m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL ( 0x1<<26 )\r
+\r
+\r
+\r
+#define s_RGA2_SRC_INFO_SW_SRC_FMT(x) ( (x&0xf)<<0 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(x) ( (x&0x1)<<4 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(x) ( (x&0x1)<<5 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(x) ( (x&0x1)<<6 )\r
+#define s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(x) ( (x&0x1)<<7 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(x) ( (x&0x3)<<8 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(x) ( (x&0x3)<<10 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE(x) ( (x&0x3)<<12 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE(x) ( (x&0x3)<<14 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(x) ( (x&0x3)<<16 )\r
+\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(x) ( (x&0x1)<<18 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(x) ( (x&0xf)<<19 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E(x) ( (x&0x1)<<23 )\r
+#define s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER(x) ( (x&0x3)<<24 )\r
+#define s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL(x) ( (x&0x1)<<26 )\r
+\r
+\r
+/* RGA_SRC_VIR_INFO */\r
+#define m_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE ( 0x7fff<<0 ) //modify\r
+#define m_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE ( 0x3ff<<16 ) //modify\r
+\r
+#define s_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE(x) ( (x&0x7fff)<<0 ) //modify\r
+#define s_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE(x) ( (x&0x3ff)<<16 ) //modify\r
+\r
+\r
+/* RGA_SRC_ACT_INFO */\r
+#define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH ( 0x1fff<<0 )\r
+#define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT ( 0x1fff<<16 )\r
+\r
+#define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH(x) ( (x&0x1fff)<<0 )\r
+#define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT(x) ( (x&0x1fff<)<16 )\r
+\r
+\r
+/* RGA_DST_INFO */\r
+#define m_RGA2_DST_INFO_SW_DST_FMT ( 0xf<<0 )\r
+#define m_RGA2_DST_INFO_SW_DST_RB_SWAP ( 0x1<<4 )\r
+#define m_RGA2_DST_INFO_SW_ALPHA_SWAP ( 0x1<<5 )\r
+#define m_RGA2_DST_INFO_SW_DST_UV_SWAP ( 0x1<<6 )\r
+#define m_RGA2_DST_INFO_SW_SRC1_FMT ( 0x7<<7 )\r
+#define m_RGA2_DST_INFO_SW_SRC1_RB_SWP ( 0x1<<10)\r
+#define m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP ( 0x1<<11)\r
+#define m_RGA2_DST_INFO_SW_DITHER_UP_E ( 0x1<<12)\r
+#define m_RGA2_DST_INFO_SW_DITHER_DOWN_E ( 0x1<<13)\r
+#define m_RGA2_DST_INFO_SW_DITHER_MODE ( 0x3<<14)\r
+#define m_RGA2_DST_INFO_SW_DST_CSC_MODE ( 0x3<<16) //add\r
+#define m_RGA2_DST_INFO_SW_CSC_CLIP_MODE ( 0x1<<18)\r
+\r
+#define s_RGA2_DST_INFO_SW_DST_FMT(x) ( (x&0xf)<<0 )\r
+#define s_RGA2_DST_INFO_SW_DST_RB_SWAP(x) ( (x&0x1)<<4 )\r
+#define s_RGA2_DST_INFO_SW_ALPHA_SWAP(x) ( (x&0x1)<<5 )\r
+#define s_RGA2_DST_INFO_SW_DST_UV_SWAP(x) ( (x&0x1)<<6 )\r
+#define s_RGA2_DST_INFO_SW_SRC1_FMT(x) ( (x&0x7)<<7 )\r
+#define s_RGA2_DST_INFO_SW_SRC1_RB_SWP(x) ( (x&0x1)<<10)\r
+#define s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(x) ( (x&0x1)<<11)\r
+#define s_RGA2_DST_INFO_SW_DITHER_UP_E(x) ( (x&0x1)<<12)\r
+#define s_RGA2_DST_INFO_SW_DITHER_DOWN_E(x) ( (x&0x1)<<13)\r
+#define s_RGA2_DST_INFO_SW_DITHER_MODE(x) ( (x&0x3)<<14)\r
+#define s_RGA2_DST_INFO_SW_DST_CSC_MODE(x) ( (x&0x3)<<16) //add\r
+#define s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(x) ( (x&0x1)<<18)\r
+\r
+\r
+/* RGA_ALPHA_CTRL0 */\r
+#define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0 ( 0x1<<0 )\r
+#define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL ( 0x1<<1 )\r
+#define m_RGA2_ALPHA_CTRL0_SW_ROP_MODE ( 0x3<<2 )\r
+#define m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA ( 0xff<<4 )\r
+#define m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA ( 0xff<<12 )\r
+#define m_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN ( 0x1<<20 ) //add\r
+\r
+#define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(x) ( (x&0x1)<<0 )\r
+#define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL(x) ( (x&0x1)<<1 )\r
+#define s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(x) ( (x&0x3)<<2 )\r
+#define s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA(x) ( (x&0xff)<<4 )\r
+#define s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA(x) ( (x&0xff)<<12 )\r
+#define s_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN(x) ( (x&0x1)<<20 ) //add\r
+\r
+\r
+\r
+/* RGA_ALPHA_CTRL1 */\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0 ( 0x1<<0 )\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0 ( 0x1<<1 )\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0 ( 0x7<<2 )\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0 ( 0x7<<5 )\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0 ( 0x1<<8 )\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0 ( 0x1<<9 )\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0 ( 0x3<<10)\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0 ( 0x3<<12)\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0 ( 0x1<<14)\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0 ( 0x1<<15)\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1 ( 0x7<<16)\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1 ( 0x7<<19)\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1 ( 0x1<<22)\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1 ( 0x1<<23)\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1 ( 0x3<<24)\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1 ( 0x3<<26)\r
+#define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1 ( 0x1<<28)\r
+#define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1 ( 0x1<<29)\r
+\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0(x) ( (x&0x1)<<0 )\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0(x) ( (x&0x1)<<1 )\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0(x) ( (x&0x7)<<2 )\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0(x) ( (x&0x7)<<5 )\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0(x) ( (x&0x1)<<8 )\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0(x) ( (x&0x1)<<9 )\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(x) ( (x&0x3)<<10)\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0(x) ( (x&0x3)<<12)\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0(x) ( (x&0x1)<<14)\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0(x) ( (x&0x1)<<15)\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1(x) ( (x&0x7)<<16)\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1(x) ( (x&0x7)<<19)\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1(x) ( (x&0x1)<<22)\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1(x) ( (x&0x1)<<23)\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(x) ( (x&0x3)<<24)\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(x) ( (x&0x3)<<26)\r
+#define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(x) ( (x&0x1)<<28)\r
+#define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(x) ( (x&0x1)<<29)\r
+\r
+\r
+\r
+/* RGA_MMU_CTRL1 */\r
+#define m_RGA2_MMU_CTRL1_SW_SRC_MMU_EN ( 0x1<<0 )\r
+#define m_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH ( 0x1<<1 )\r
+#define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN ( 0x1<<2 )\r
+#define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR ( 0x1<<3 )\r
+#define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN ( 0x1<<4 )\r
+#define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH ( 0x1<<5 )\r
+#define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN ( 0x1<<6 )\r
+#define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR ( 0x1<<7 )\r
+#define m_RGA2_MMU_CTRL1_SW_DST_MMU_EN ( 0x1<<8 )\r
+#define m_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH ( 0x1<<9 )\r
+#define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN ( 0x1<<10 )\r
+#define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR ( 0x1<<11 )\r
+#define m_RGA2_MMU_CTRL1_SW_ELS_MMU_EN ( 0x1<<12 )\r
+#define m_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH ( 0x1<<13 )\r
+\r
+#define s_RGA2_MMU_CTRL1_SW_SRC_MMU_EN(x) ( (x&0x1)<<0 )\r
+#define s_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH(x) ( (x&0x1)<<1 )\r
+#define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN(x) ( (x&0x1)<<2 )\r
+#define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR(x) ( (x&0x1)<<3 )\r
+#define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN(x) ( (x&0x1)<<4 )\r
+#define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH(x) ( (x&0x1)<<5 )\r
+#define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN(x) ( (x&0x1)<<6 )\r
+#define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR(x) ( (x&0x1)<<7 )\r
+#define s_RGA2_MMU_CTRL1_SW_DST_MMU_EN(x) ( (x&0x1)<<8 )\r
+#define s_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH(x) ( (x&0x1)<<9 )\r
+#define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN(x) ( (x&0x1)<<10 )\r
+#define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR(x) ( (x&0x1)<<11 )\r
+#define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x) ( (x&0x1)<<12 )\r
+#define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ( (x&0x1)<<13 )\r
+\r
+\r
+#define RGA2_SYS_CTRL_OFFSET 0x0\r
+#define RGA2_CMD_CTRL_OFFSET 0x4\r
+#define RGA2_CMD_BASE_OFFSET 0x8\r
+#define RGA2_STATUS_OFFSET 0xc\r
+#define RGA2_INT_OFFSET 0x10\r
+#define RGA2_MMU_CTRL0_OFFSET 0x14\r
+#define RGA2_MMU_CMD_BASE_OFFSET 0x18\r
+\r
+#define RGA2_MODE_CTRL_OFFSET 0x00\r
+#define RGA2_SRC_INFO_OFFSET 0x04\r
+#define RGA2_SRC_BASE0_OFFSET 0x08\r
+#define RGA2_SRC_BASE1_OFFSET 0x0c\r
+#define RGA2_SRC_BASE2_OFFSET 0x10\r
+#define RGA2_SRC_BASE3_OFFSET 0x14\r
+#define RGA2_SRC_VIR_INFO_OFFSET 0x18\r
+#define RGA2_SRC_ACT_INFO_OFFSET 0x1c\r
+#define RGA2_SRC_X_FACTOR_OFFSET 0x20\r
+#define RGA2_SRC_Y_FACTOR_OFFSET 0x24\r
+#define RGA2_SRC_BG_COLOR_OFFSET 0x28\r
+#define RGA2_SRC_FG_COLOR_OFFSET 0x2c\r
+#define RGA2_SRC_TR_COLOR0_OFFSET 0x30\r
+#define RGA2_CF_GR_A_OFFSET 0x30 // repeat\r
+#define RGA2_SRC_TR_COLOR1_OFFSET 0x34\r
+#define RGA2_CF_GR_B_OFFSET 0x34 // repeat\r
+#define RGA2_DST_INFO_OFFSET 0x38\r
+#define RGA2_DST_BASE0_OFFSET 0x3c\r
+#define RGA2_DST_BASE1_OFFSET 0x40\r
+#define RGA2_DST_BASE2_OFFSET 0x44\r
+#define RGA2_DST_VIR_INFO_OFFSET 0x48\r
+#define RGA2_DST_ACT_INFO_OFFSET 0x4c\r
+#define RGA2_ALPHA_CTRL0_OFFSET 0x50\r
+#define RGA2_ALPHA_CTRL1_OFFSET 0x54\r
+#define RGA2_FADING_CTRL_OFFSET 0x58\r
+#define RGA2_PAT_CON_OFFSET 0x5c\r
+#define RGA2_ROP_CTRL0_OFFSET 0x60\r
+#define RGA2_CF_GR_G_OFFSET 0x60 // repeat\r
+#define RGA2_ROP_CTRL1_OFFSET 0x64\r
+#define RGA2_CF_GR_R_OFFSET 0x64 // repeat\r
+#define RGA2_MASK_BASE_OFFSET 0x68\r
+#define RGA2_MMU_CTRL1_OFFSET 0x6c\r
+#define RGA2_MMU_SRC_BASE_OFFSET 0x70\r
+#define RGA2_MMU_SRC1_BASE_OFFSET 0x74\r
+#define RGA2_MMU_DST_BASE_OFFSET 0x78\r
+#define RGA2_MMU_ELS_BASE_OFFSET 0x7c\r
+\r
+int RGA2_gen_reg_info(unsigned char *base, struct rga2_req *msg);\r
+void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req);\r
+\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+#ifndef __RGA_ROP_H__\r
+#define __RGA_ROP_H__\r
+\r
+#include "rga2_type.h"\r
+\r
+UWORD32 ROP3_code[256] =\r
+{\r
+ 0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0\r
+ 0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,\r
+\r
+ 0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1\r
+ 0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,\r
+\r
+ 0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2\r
+ 0x00800631, 0x0002b471, 0x00006071, 0x008037aa, 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,\r
+\r
+ 0x0000006e, 0x00000565, 0x00003451, 0x00800006, 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3\r
+ 0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c, 0x00000031, 0x00834850, 0x000034e6, 0x00800071,\r
+\r
+ 0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870, 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4\r
+ 0x00800728, 0x0002a561, 0x000026c2, 0x008002c6, 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,\r
+\r
+ 0x0000006c, 0x00000475, 0x000024e2, 0x008036b0, 0x00804051, 0x00800004, 0x00800251, 0x00000651,\r
+ 0x00002e4a, 0x0080024e, 0x00000028, 0x00824842, 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5\r
+\r
+ 0x008006b0, 0x000234f0, 0x00002741, 0x00800345, 0x00003651, 0x00800255, 0x00000030, 0x00834051,\r
+ 0x00a34842, 0x000002b0, 0x00800271, 0x0002b651, 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6\r
+\r
+ 0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,\r
+ 0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7\r
+\r
+ 0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,\r
+ 0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8\r
+\r
+ 0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,\r
+ 0x00034051, 0x00800030, 0x0080026e, 0x00803651, 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9\r
+\r
+ 0x00000068, 0x00802c75, 0x0080064e, 0x008024a2, 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,\r
+ 0x00800651, 0x00000251, 0x00800000, 0x00004051, 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a\r
+\r
+ 0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068, 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,\r
+ 0x00002f28, 0x00802561, 0x0080046e, 0x00000046, 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b\r
+\r
+ 0x00000071, 0x008034e6, 0x00034850, 0x00800031, 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,\r
+ 0x00800748, 0x00000341, 0x000026a2, 0x008034f0, 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c\r
+\r
+ 0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0, 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,\r
+ 0x00002e2a, 0x00803471, 0x00826862, 0x010007aa, 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d\r
+\r
+ 0x008006d0, 0x000002d0, 0x00002721, 0x00802d68, 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,\r
+ 0x010037aa, 0x00a36870, 0x00800471, 0x00004031, 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e\r
+\r
+ 0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,\r
+ 0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f\r
+};\r
+\r
+#endif\r
--- /dev/null
+#ifndef __RGA_TYPE_H__\r
+#define __RGA_TYPE_H__\r
+\r
+\r
+#ifdef __cplusplus\r
+#if __cplusplus\r
+}\r
+#endif\r
+#endif /* __cplusplus */\r
+\r
+typedef unsigned int UWORD32;\r
+typedef unsigned int uint32;\r
+typedef unsigned int RK_U32;\r
+\r
+typedef unsigned short UWORD16;\r
+typedef unsigned short RK_U16;\r
+\r
+typedef unsigned char UBYTE;\r
+typedef unsigned char RK_U8;\r
+\r
+typedef int WORD32;\r
+typedef int RK_S32;\r
+\r
+typedef short WORD16;\r
+typedef short RK_S16;\r
+\r
+typedef char BYTE;\r
+typedef char RK_S8;\r
+\r
+\r
+#ifndef NULL\r
+#define NULL 0L\r
+#endif\r
+\r
+#ifndef TRUE\r
+#define TRUE 1L\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+#if __cplusplus\r
+}\r
+#endif\r
+#endif /* __cplusplus */\r
+\r
+\r
+#endif /* __RGA_TYPR_H__ */\r
+\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff