nvmem: rockchip-efuse: Fix dependencies

Not every rockchip efuse depends on ROCKCHIP_SIP, so delete
dependencies in Kconfig. It is more appropriate to add
dependencies for sip_smc_secure_reg_read/write.

Change-Id: I7f551f9fe71ced847657531e3c3cf418766fa3a4
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index eaca3d20472ada85179e60c1e2780bfa6e932172..584f11a815e9f538a29fa8dacea4320505b2e7a9 100644 (file)
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -52,7 +52,6 @@ config ROCKCHIP_EFUSE
        tristate "Rockchip eFuse Support"
        depends on ARCH_ROCKCHIP || COMPILE_TEST
        depends on HAS_IOMEM
        tristate "Rockchip eFuse Support"
        depends on ARCH_ROCKCHIP || COMPILE_TEST
        depends on HAS_IOMEM

-       depends on ROCKCHIP_SIP

        help
          This is a simple drive to dump specified values of Rockchip SoC
          from eFuse, such as cpu-leakage.
        help
          This is a simple drive to dump specified values of Rockchip SoC
          from eFuse, such as cpu-leakage.

diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h
index 92a28c669e9736c10bc994d8576d97b9518a0e79..27b35463a604bb2f432fe343956cf2bc84e7d692 100644 (file)
--- a/include/linux/rockchip/rockchip_sip.h
+++ b/include/linux/rockchip/rockchip_sip.h
@@ -91,8 +91,13 @@ struct arm_smccc_res sip_smc_ddr_cfg(u32 arg0, u32 arg1,
                                     u32 arg2);
 struct arm_smccc_res sip_smc_get_share_mem_page(u32 page_num,
                                                share_page_type_t page_type);
                                     u32 arg2);
 struct arm_smccc_res sip_smc_get_share_mem_page(u32 page_num,
                                                share_page_type_t page_type);

+#ifdef CONFIG_ROCKCHIP_SIP

 u32 sip_smc_secure_reg_read(u32 addr_phy);
 int sip_smc_secure_reg_write(u32 addr_phy, u32 val);
 u32 sip_smc_secure_reg_read(u32 addr_phy);
 int sip_smc_secure_reg_write(u32 addr_phy, u32 val);

+#else
+u32 sip_smc_secure_reg_read(u32 addr_phy) { return 0; }
+int sip_smc_secure_reg_write(u32 addr_phy, u32 val) { return 0; }
+#endif

 
 void psci_enable_fiq(void);
 u32 rockchip_psci_smc_get_tf_ver(void);
 
 void psci_enable_fiq(void);
 u32 rockchip_psci_smc_get_tf_ver(void);