arm64: dts: rockchip: fix pcie and pcie-phy support for rk3399

Fix them for matching what the new drivers want.

Change-Id: I6ce43379ab9cf3d274b6b414ec014e431db588b7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 8f21aa78418d64f583837d473a920910e933a054..07e36f05c167a7c3a604019e1b9c8b75b64c061b 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1146,43 +1146,49 @@
                status = "disabled";
        };
 
                status = "disabled";
        };
 

+       pcie_phy: phy@e220 {
+               compatible = "rockchip,rk3399-pcie-phy";
+               #phy-cells = <0>;
+               rockchip,grf = <&grf>;
+               clocks = <&cru SCLK_PCIEPHY_REF>;
+               clock-names = "refclk";
+               resets = <&cru SRST_PCIEPHY>;
+               reset-names = "phy";
+               status = "disabled";
+       };
+

        pcie0: pcie@f8000000 {
                compatible = "rockchip,rk3399-pcie";
                #address-cells = <3>;
                #size-cells = <2>;
                clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
        pcie0: pcie@f8000000 {
                compatible = "rockchip,rk3399-pcie";
                #address-cells = <3>;
                #size-cells = <2>;
                clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,

-                        <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
-               clock-names = "aclk_pcie", "aclk_perf_pcie",
-                             "hclk_pcie", "clk_pciephy_ref";
+                        <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+               clock-names = "aclk", "aclk-perf",
+                             "hclk", "pm";

                bus-range = <0x0 0x1>;
                bus-range = <0x0 0x1>;

+               msi-map = <0x0 &its 0x0 0x1000>;

                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
                             <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
                             <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
                             <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
                             <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;

-               interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
-               ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
-                          0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
-               reg = < 0x0 0xf8000000 0x0 0x2000000 >,
-                     < 0x0 0xfd000000 0x0 0x1000000 >;
-               reg-name = "axi-base", "apb-base";
-               resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
-                        <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
-                        <&cru SRST_PCIE_PIPE>;
-               reset-names = "phy-rst", "core-rst", "mgmt-rst",
-                             "mgmt-sticky-rst", "pipe-rst";
-               rockchip,grf = <&grf>;
-               pcie-conf = <0xe220>;
-               pcie-status = <0xe2a4>;
-               pcie-laneoff = <0xe214>;
-               power-domains = <&power RK3399_PD_PERIHP>;
-               msi-parent = <&its>;
+               interrupt-names = "sys", "legacy", "client";

                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 0 7>;
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 0 7>;

-               interrupt-map = <0 0 0 1 &pcie0 1>,
-                               <0 0 0 2 &pcie0 2>,
-                               <0 0 0 3 &pcie0 3>,
-                               <0 0 0 4 &pcie0 4>;
+               interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+                               <0 0 0 2 &pcie0_intc 1>,
+                               <0 0 0 3 &pcie0_intc 2>,
+                               <0 0 0 4 &pcie0_intc 3>;
+               phys = <&pcie_phy>;
+               phy-names = "pcie-phy";
+               ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
+                         0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
+               reg = <0x0 0xf8000000 0x0 0x2000000>,
+                     <0x0 0xfd000000 0x0 0x1000000>;
+               reg-names = "axi-base", "apb-base";
+               resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+                        <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
+               reset-names = "core", "mgmt", "mgmt-sticky", "pipe";

                status = "disabled";
                status = "disabled";

-               pcie_intc: interrupt-controller {
+               pcie0_intc: interrupt-controller {

                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <1>;
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <1>;