printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
}
+static int ddr_init_resume(struct platform_device *pdev)
+{
+ ddr_init(DDR3_DEFAULT, 0);
+ return 0;
+}
+
static int __init rockchip_ddr_probe(struct platform_device *pdev)
{
struct device_node *np;
};
static struct platform_driver rockchip_ddr_driver = {
+#ifdef CONFIG_PM
+ .resume = ddr_init_resume,
+#endif /* CONFIG_PM */
.driver = {
.name = "rockchip_ddr",
.of_match_table = rockchip_ddr_of_match,
#include <linux/clk.h>
#include <linux/rockchip-mailbox.h>
+#include <linux/scpi_protocol.h>
#define MAILBOX_A2B_INTEN 0x00
#define MAILBOX_A2B_STATUS 0x04
};
MODULE_DEVICE_TABLE(of, rockchp_mbox_of_match);
+#ifdef CONFIG_PM
+static int rockchip_mbox_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ struct rockchip_mbox *mb = platform_get_drvdata(pdev);
+
+ if (scpi_sys_set_mcu_state_suspend())
+ dev_err(mb->mbox.dev, "scpi_sys_set_mcu_state_suspend timeout.\n");
+ return 0;
+}
+
+static int rockchip_mbox_resume(struct platform_device *pdev)
+{
+ struct rockchip_mbox *mb = platform_get_drvdata(pdev);
+
+ writel_relaxed((1 << mb->mbox.num_chans) - 1,
+ mb->mbox_base + MAILBOX_B2A_INTEN);
+
+ if (scpi_sys_set_mcu_state_resume())
+ dev_err(mb->mbox.dev, "scpi_sys_set_mcu_state_resume timeout.\n");
+ return 0;
+}
+#endif /* CONFIG_PM */
+
static int rockchip_mbox_probe(struct platform_device *pdev)
{
struct rockchip_mbox *mb;
static struct platform_driver rockchip_mbox_driver = {
.probe = rockchip_mbox_probe,
.remove = rockchip_mbox_remove,
+#ifdef CONFIG_PM
+ .suspend = rockchip_mbox_suspend,
+ .resume = rockchip_mbox_resume,
+#endif /* CONFIG_PM */
.driver = {
.name = "rockchip-mailbox",
.of_match_table = of_match_ptr(rockchip_mbox_of_match),
enum scpi_sys_cmd {
SCPI_SYS_GET_VERSION,
SCPI_SYS_REFRESH_MCU_FREQ,
+ SCPI_SYS_SET_MCU_STATE_SUSPEND,
+ SCPI_SYS_SET_MCU_STATE_RESUME,
};
enum scpi_std_cmd {
return ret;
}
+int scpi_sys_set_mcu_state_suspend(void)
+{
+ struct scpi_data_buf sdata;
+ struct rockchip_mbox_msg mdata;
+ struct __packed1 {
+ u32 status;
+ } tx_buf;
+ struct __packed2 {
+ u32 status;
+ } rx_buf;
+
+ tx_buf.status = 0;
+ SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_SYS,
+ SCPI_SYS_SET_MCU_STATE_SUSPEND, tx_buf, rx_buf);
+ return scpi_execute_cmd(&sdata);
+}
+EXPORT_SYMBOL_GPL(scpi_sys_set_mcu_state_suspend);
+
+int scpi_sys_set_mcu_state_resume(void)
+{
+ struct scpi_data_buf sdata;
+ struct rockchip_mbox_msg mdata;
+ struct __packed1 {
+ u32 status;
+ } tx_buf;
+ struct __packed2 {
+ u32 status;
+ } rx_buf;
+
+ tx_buf.status = 0;
+
+ SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_SYS,
+ SCPI_SYS_SET_MCU_STATE_RESUME, tx_buf, rx_buf);
+ return scpi_execute_cmd(&sdata);
+}
+EXPORT_SYMBOL_GPL(scpi_sys_set_mcu_state_resume);
+
int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type)
{
struct scpi_data_buf sdata;
int scpi_get_sensor(char *name);
int scpi_get_sensor_value(u16 sensor, u32 *val);
+int scpi_sys_set_mcu_state_suspend(void);
+int scpi_sys_set_mcu_state_resume(void);
+
int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type);
int scpi_ddr_set_clk_rate(u32 rate);
int scpi_ddr_round_rate(u32 m_hz);