clk: rockchip: add clock ids for i2s_src on RK3366

Set the newly added id for i2s_src, so that they can be called
in other parts.

Change-Id: Ie4ecc4d19e3ae64a07d1f2a80aa08d40f38d09ad
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3366.c b/drivers/clk/rockchip/clk-rk3366.c
index 1bb09e4dc5433c4b5e8be4cd1b5a747fbce931e8..2c44dc4312c9becacb9aca04738400c9a01208c7 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3366.c
+++ b/drivers/clk/rockchip/clk-rk3366.c
@@ -299,7 +299,7 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
                        RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
                        RK3368_CLKGATE_CON(1), 3, GFLAGS),
 
-       COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(SCLK_I2S_8CH_SRC, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3368_CLKGATE_CON(6), 1, GFLAGS),
        COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
@@ -312,7 +312,7 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
        GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
                        RK3368_CLKGATE_CON(6), 3, GFLAGS),
 
-       COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(SCLK_SPDIF_8CH_SRC, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3368_CLKGATE_CON(6), 4, GFLAGS),
        COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
@@ -322,7 +322,7 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
        GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
                        RK3368_CLKGATE_CON(6), 6, GFLAGS),
 
-       COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
+       COMPOSITE(SCLK_I2S_2CH_SRC, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
                        RK3368_CLKGATE_CON(5), 13, GFLAGS),
        COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,

diff --git a/include/dt-bindings/clock/rk3366-cru.h b/include/dt-bindings/clock/rk3366-cru.h
index 9facbd51c1e32c44a1179bfac144e25fbbc8be23..0ae354989c5086dda05181f5552fb1920ce35325 100644 (file)
--- a/include/dt-bindings/clock/rk3366-cru.h
+++ b/include/dt-bindings/clock/rk3366-cru.h
@@ -96,6 +96,9 @@
 #define SCLK_MPLL_SRC          130
 #define SCLK_32K_INTR          131
 #define SCLK_32K               132
+#define SCLK_I2S_8CH_SRC       133
+#define SCLK_I2S_2CH_SRC       134
+#define SCLK_SPDIF_8CH_SRC     135
 
 #define DCLK_VOP_FULL          170
 #define DCLK_VOP_LITE          171