+static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ u32 ret;
+ u32 lcdc_type = 7;
+
+ ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
+
+ return ret;
+}
+
+static unsigned long rockchip_ddrclk_scpi_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return (MHZ * scpi_ddr_get_clk_rate());
+}
+
+static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
+{
+ rate = rate / MHZ;
+ rate = (rate / 12) * 12;
+
+ return (rate * MHZ);
+}
+
+static const struct clk_ops rockchip_ddrclk_scpi_ops = {
+ .recalc_rate = rockchip_ddrclk_scpi_recalc_rate,
+ .set_rate = rockchip_ddrclk_scpi_set_rate,
+ .round_rate = rockchip_ddrclk_scpi_round_rate,
+ .get_parent = rockchip_ddrclk_get_parent,
+};
+